diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2021-07-29 20:15:26 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2021-07-29 20:15:26 +0000 |
| commit | 344a3780b2e33f6ca763666c380202b18aab72a3 (patch) | |
| tree | f0b203ee6eb71d7fdd792373e3c81eb18d6934dd /llvm/lib/Target/PowerPC/PPCFastISel.cpp | |
| parent | b60736ec1405bb0a8dd40989f67ef4c93da068ab (diff) | |
vendor/llvm-project/llvmorg-13-init-16847-g88e66fa60ae5vendor/llvm-project/llvmorg-12.0.1-rc2-0-ge7dac564cd0evendor/llvm-project/llvmorg-12.0.1-0-gfed41342a82f
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCFastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCFastISel.cpp | 28 |
1 files changed, 11 insertions, 17 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp index c181816e31c6..dfb2c1e5c0f5 100644 --- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp +++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp @@ -63,7 +63,7 @@ using namespace llvm; namespace { -typedef struct Address { +struct Address { enum { RegBase, FrameIndexBase @@ -81,7 +81,7 @@ typedef struct Address { : BaseType(RegBase), Offset(0) { Base.Reg = 0; } -} Address; +}; class PPCFastISel final : public FastISel { @@ -112,15 +112,12 @@ class PPCFastISel final : public FastISel { unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override; unsigned fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, bool Op0IsKill, - uint64_t Imm); + unsigned Op0, uint64_t Imm); unsigned fastEmitInst_r(unsigned MachineInstOpcode, - const TargetRegisterClass *RC, - unsigned Op0, bool Op0IsKill); + const TargetRegisterClass *RC, unsigned Op0); unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, bool Op0IsKill, - unsigned Op1, bool Op1IsKill); + unsigned Op0, unsigned Op1); bool fastLowerCall(CallLoweringInfo &CLI) override; @@ -2426,7 +2423,7 @@ unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) { // where those regs have another meaning. unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, bool Op0IsKill, + unsigned Op0, uint64_t Imm) { if (MachineInstOpcode == PPC::ADDI) MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); @@ -2437,8 +2434,7 @@ unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode, (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass : (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC)); - return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, - Op0, Op0IsKill, Imm); + return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, Op0, Imm); } // Override for instructions with one register operand to avoid use of @@ -2446,12 +2442,12 @@ unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode, // we must be conservative. unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass* RC, - unsigned Op0, bool Op0IsKill) { + unsigned Op0) { const TargetRegisterClass *UseRC = (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass : (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC)); - return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill); + return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0); } // Override for instructions with two register operands to avoid use @@ -2459,14 +2455,12 @@ unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode, // so we must be conservative. unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass* RC, - unsigned Op0, bool Op0IsKill, - unsigned Op1, bool Op1IsKill) { + unsigned Op0, unsigned Op1) { const TargetRegisterClass *UseRC = (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass : (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC)); - return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill, - Op1, Op1IsKill); + return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op1); } namespace llvm { |