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authorDimitry Andric <dim@FreeBSD.org>2025-12-06 19:56:45 +0000
committerDimitry Andric <dim@FreeBSD.org>2025-12-06 20:08:43 +0000
commit3f709e42e3be0f28a88ca3e77663a02b52c914f4 (patch)
tree948796bf3bf7e164373caf6c31f9f128ca85fd8c /llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
parent32a711e1c447004eb1fd015925f305ed1d8426de (diff)
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
index 75011ab3c872..a934853ff9f4 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
@@ -56,15 +56,15 @@ bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
- const DebugLoc &DL, MCRegister DestReg,
- MCRegister SrcReg, bool KillSrc,
+ const DebugLoc &DL, Register DestReg,
+ Register SrcReg, bool KillSrc,
bool RenamableDest,
bool RenamableSrc) const {
// This method is called by post-RA expansion, which expects only pregs to
// exist. However we need to handle both here.
auto &MRI = MBB.getParent()->getRegInfo();
const TargetRegisterClass *RC =
- Register::isVirtualRegister(DestReg)
+ DestReg.isVirtual()
? MRI.getRegClass(DestReg)
: MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);