diff options
author | Emmanuel Vadot <manu@FreeBSD.org> | 2024-04-19 16:04:55 +0000 |
---|---|---|
committer | Emmanuel Vadot <manu@FreeBSD.org> | 2024-04-19 16:04:55 +0000 |
commit | 48aa10e065908667e32e3aab09f1c787cd127470 (patch) | |
tree | 141762c42a29902f49f1d104ba845bff099f3c9f /src/arm64/marvell/ac5x-rd-carrier.dtsi | |
parent | 1fcc28bca1057f051708a8fc59129ea42c574693 (diff) | |
download | src-48aa10e065908667e32e3aab09f1c787cd127470.tar.gz src-48aa10e065908667e32e3aab09f1c787cd127470.zip |
Import device-tree files from Linux 6.8vendor/device-tree/6.8vendor/device-tree
Diffstat (limited to 'src/arm64/marvell/ac5x-rd-carrier.dtsi')
-rw-r--r-- | src/arm64/marvell/ac5x-rd-carrier.dtsi | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/arm64/marvell/ac5x-rd-carrier.dtsi b/src/arm64/marvell/ac5x-rd-carrier.dtsi new file mode 100644 index 000000000000..f98629abb58b --- /dev/null +++ b/src/arm64/marvell/ac5x-rd-carrier.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the AC5X RD Type 7 Com Express carrier board, + * This specific board in external mode (see below) only maintains + * a PCIe link with the COM Express CPU module, which does not + * require any special DTS definitions. + * + * AC5X RD can either work as you would expect, as a complete standalone + * box using the internal CPU, or you can move the switch on the back of + * the box to "external" mode, and connect via an external cable a kit + * which would allow it to use an external CPU COM Express module, + * mounted on top of an interposer kit. + * + * So in this case, once the switch is set to external mode as explained above, + * the AC5X RD becomes part of the carrier solution. + * This is a development/reference solution, not a full commercial solution, + * hence it was designed with the flexibility to be configured in different + * modes of operation. + * + * When the board boots in the external CPU mode, the internal CPU is disabled, + * and only the switch portion of the SOC acts as a PCIe end-point, Hence there + * is no need to describe this internal (disabled CPU) in the device tree. + * + * There is no CPU booting in this mode on the carrier, + * only on the COM Express CPU module. + */ + +/ { + model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board"; + compatible = "marvell,rd-ac5x-carrier"; + +}; |