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| author | Emmanuel Vadot <manu@FreeBSD.org> | 2024-04-19 16:03:26 +0000 |
|---|---|---|
| committer | Emmanuel Vadot <manu@FreeBSD.org> | 2024-04-19 16:03:26 +0000 |
| commit | 1fcc28bca1057f051708a8fc59129ea42c574693 (patch) | |
| tree | c56b72a227b6a1abcdd3c30a11439a8a595c4b9c /src/riscv/microchip/mpfs.dtsi | |
| parent | dbacf41c97755475589f64dd45ffa90febddf368 (diff) | |
| download | src-1fcc28bca1057f051708a8fc59129ea42c574693.tar.gz src-1fcc28bca1057f051708a8fc59129ea42c574693.zip | |
Import device-tree files from Linux 6.7vendor/device-tree/6.7
Diffstat (limited to 'src/riscv/microchip/mpfs.dtsi')
| -rw-r--r-- | src/riscv/microchip/mpfs.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/riscv/microchip/mpfs.dtsi b/src/riscv/microchip/mpfs.dtsi index 104504352e99..266489d43912 100644 --- a/src/riscv/microchip/mpfs.dtsi +++ b/src/riscv/microchip/mpfs.dtsi @@ -13,6 +13,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + timebase-frequency = <1000000>; cpu0: cpu@0 { compatible = "sifive,e51", "sifive,rocket0", "riscv"; @@ -22,6 +23,9 @@ i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; @@ -48,6 +52,9 @@ mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -76,6 +83,9 @@ mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -104,6 +114,9 @@ mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -132,6 +145,9 @@ mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; |