7 files changed, 0 insertions, 1025 deletions

diff --git a/sys/dev/ic/cd1400.h b/sys/dev/ic/cd1400.h
deleted file mode 100644
index 90672c4ee7e6..000000000000
--- a/sys/dev/ic/cd1400.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*-
- * cyclades cyclom-y serial driver
- *	Andrew Herbert <andrew@werple.apana.org.au>, 17 August 1993
- *
- * Copyright (c) 1993 Andrew Herbert.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name Andrew Herbert may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- * NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-/*
- * Definitions for Cirrus Logic CD1400 serial/parallel chips.
- */
-
-#define	CD1400_NO_OF_CHANNELS	4	/* 4 serial channels per chip */
-#define	CD1400_RX_FIFO_SIZE	12
-#define	CD1400_TX_FIFO_SIZE	12
-
-/*
- * Global registers.
- */
-#define	CD1400_GFRCR		0x40	/* global firmware revision code */
-#define	CD1400_CAR		0x68	/* channel access */
-#define	CD1400_CAR_CHAN			(3<<0)	/* channel select */
-#define	CD1400_GCR		0x4B	/* global configuration */
-#define	CD1400_GCR_PARALLEL		(1<<7)	/* channel 0 is parallel */
-#define	CD1400_SVRR		0x67	/* service request */
-#define	CD1400_SVRR_MDMCH		(1<<2)
-#define	CD1400_SVRR_TXRDY		(1<<1)
-#define	CD1400_SVRR_RXRDY		(1<<0)
-#define	CD1400_RICR		0x44	/* receive interrupting channel */
-#define	CD1400_TICR		0x45	/* transmit interrupting channel */
-#define	CD1400_MICR		0x46	/* modem interrupting channel */
-#define	CD1400_RIR		0x6B	/* receive interrupt status */
-#define	CD1400_RIR_RDIREQ		(1<<7)	/* rx service required */
-#define	CD1400_RIR_RBUSY		(1<<6)	/* rx service in progress */
-#define	CD1400_RIR_CHAN			(3<<0)	/* channel select */
-#define	CD1400_TIR		0x6A	/* transmit interrupt status */
-#define	CD1400_TIR_RDIREQ		(1<<7)	/* tx service required */
-#define	CD1400_TIR_RBUSY		(1<<6)	/* tx service in progress */
-#define	CD1400_TIR_CHAN			(3<<0)	/* channel select */
-#define	CD1400_MIR		0x69	/* modem interrupt status */
-#define	CD1400_MIR_RDIREQ		(1<<7)	/* modem service required */
-#define	CD1400_MIR_RBUSY		(1<<6)	/* modem service in progress */
-#define	CD1400_MIR_CHAN			(3<<0)	/* channel select */
-#define	CD1400_PPR		0x7E	/* prescaler period */
-#define	CD1400_PPR_PRESCALER		512
-
-/*
- * Virtual registers.
- */
-#define	CD1400_RIVR		0x43	/* receive interrupt vector */
-#define	CD1400_RIVR_EXCEPTION		(1<<2)	/* receive exception bit */
-#define	CD1400_TIVR		0x42	/* transmit interrupt vector */
-#define	CD1400_MIVR		0x41	/* modem interrupt vector */
-#define	CD1400_TDR		0x63	/* transmit data */
-#define	CD1400_RDSR		0x62	/* receive data/status */
-#define	CD1400_RDSR_TIMEOUT		(1<<7)	/* rx timeout */
-#define	CD1400_RDSR_SPECIAL_SHIFT	4	/* rx special char shift */
-#define	CD1400_RDSR_SPECIAL		(7<<4)	/* rx special char */
-#define	CD1400_RDSR_BREAK		(1<<3)	/* rx break */
-#define	CD1400_RDSR_PE			(1<<2)	/* rx parity error */
-#define	CD1400_RDSR_FE			(1<<1)	/* rx framing error */
-#define	CD1400_RDSR_OE			(1<<0)	/* rx overrun error */
-#define	CD1400_MISR		0x4C	/* modem interrupt status */
-#define	CD1400_MISR_DSRd		(1<<7)	/* DSR delta */
-#define	CD1400_MISR_CTSd		(1<<6)	/* CTS delta */
-#define	CD1400_MISR_RId			(1<<5)	/* RI delta */
-#define	CD1400_MISR_CDd			(1<<4)	/* CD delta */
-#define	CD1400_EOSRR		0x60	/* end of service request */
-
-/*
- * Channel registers.
- */
-#define	CD1400_LIVR		0x18	/* local interrupt vector */
-#define	CD1400_CCR		0x05	/* channel control */
-#define	CD1400_CCR_CMDRESET		(1<<7)	/* enables following: */
-#define	CD1400_CCR_FTF				(1<<1)	/* flush tx fifo */
-#define	CD1400_CCR_FULLRESET			(1<<0)	/* full reset */
-#define	CD1400_CCR_CHANRESET			0	/*  current channel */
-#define	CD1400_CCR_CMDCORCHG		(1<<6)	/* enables following: */
-#define	CD1400_CCR_COR3				(1<<3)	/* COR3 changed */
-#define	CD1400_CCR_COR2				(1<<2)	/* COR2 changed */
-#define	CD1400_CCR_COR1				(1<<1)	/* COR1 changed */
-#define	CD1400_CCR_CMDSENDSC		(1<<5)	/* enables following: */
-#define	CD1400_CCR_SC				(7<<0)	/* special char 1-4 */
-#define	CD1400_CCR_CMDCHANCTL		(1<<4)	/* enables following: */
-#define	CD1400_CCR_XMTEN			(1<<3)	/* tx enable */
-#define	CD1400_CCR_XMTDIS			(1<<2)	/* tx disable */
-#define	CD1400_CCR_RCVEN			(1<<1)	/* rx enable */
-#define	CD1400_CCR_RCVDIS			(1<<0)	/* rx disable */
-#define	CD1400_SRER		0x06	/* service request enable */
-#define	CD1400_SRER_MDMCH		(1<<7)	/* modem change */
-#define	CD1400_SRER_RXDATA		(1<<4)	/* rx data */
-#define	CD1400_SRER_TXRDY		(1<<2)	/* tx fifo empty */
-#define	CD1400_SRER_TXMPTY		(1<<1)	/* tx shift reg empty */
-#define	CD1400_SRER_NNDT		(1<<0)	/* no new data */
-#define	CD1400_COR1		0x08	/* channel option 1 */
-#define	CD1400_COR1_PARODD		(1<<7)
-#define	CD1400_COR1_PARNORMAL		(2<<5)
-#define	CD1400_COR1_PARFORCE		(1<<5)	/* odd/even = force 1/0 */
-#define	CD1400_COR1_PARNONE		(0<<5)
-#define	CD1400_COR1_NOINPCK		(1<<4)
-#define	CD1400_COR1_STOP2		(2<<2)
-#define	CD1400_COR1_STOP15		(1<<2)	/* 1.5 stop bits */
-#define	CD1400_COR1_STOP1		(0<<2)
-#define	CD1400_COR1_CS8			(3<<0)
-#define	CD1400_COR1_CS7			(2<<0)
-#define	CD1400_COR1_CS6			(1<<0)
-#define	CD1400_COR1_CS5			(0<<0)
-#define	CD1400_COR2		0x09	/* channel option 2 */
-#define	CD1400_COR2_IXANY		(1<<7)	/* implied XON mode */
-#define	CD1400_COR2_IXOFF		(1<<6)	/* in-band tx flow control */
-#define	CD1400_COR2_ETC			(1<<5)	/* embedded tx command */
-#define	CD1400_ETC_CMD				0x00	/* start an ETC */
-#define	CD1400_ETC_SENDBREAK			0x81
-#define	CD1400_ETC_INSERTDELAY			0x82
-#define	CD1400_ETC_STOPBREAK			0x83
-#define	CD1400_COR2_LLM			(1<<4)	/* local loopback mode */
-#define	CD1400_COR2_RLM			(1<<3)	/* remote loopback mode */
-#define	CD1400_COR2_RTSAO		(1<<2)	/* RTS auto output */
-#define	CD1400_COR2_CCTS_OFLOW		(1<<1)	/* CTS auto enable */
-#define	CD1400_COR2_CDSR_OFLOW		(1<<0)	/* DSR auto enable */
-#define	CD1400_COR3		0x0A	/* channel option 3 */
-#define	CD1400_COR3_SCDRNG		(1<<7)	/* special char detect range */
-#define	CD1400_COR3_SCD34		(1<<6)	/* special char detect 3-4 */
-#define	CD1400_COR3_FTC			(1<<5)	/* flow control transparency */
-#define	CD1400_COR3_SCD12		(1<<4)	/* special char detect 1-2 */
-#define	CD1400_COR3_RXTH		(15<<0)	/* rx fifo threshold */
-#define	CD1400_COR4		0x1E	/* channel option 4 */
-#define	CD1400_COR4_IGNCR		(1<<7)
-#define	CD1400_COR4_ICRNL		(1<<6)
-#define	CD1400_COR4_INLCR		(1<<5)
-#define	CD1400_COR4_IGNBRK		(1<<4)
-#define	CD1400_COR4_NOBRKINT		(1<<3)
-#define	CD1400_COR4_PFO_ESC		(4<<0)	/* parity/framing/overrun... */
-#define	CD1400_COR4_PFO_NUL		(3<<0)
-#define	CD1400_COR4_PFO_DISCARD		(2<<0)
-#define	CD1400_COR4_PFO_GOOD		(1<<0)
-#define	CD1400_COR4_PFO_EXCEPTION	(0<<0)
-#define	CD1400_COR5		0x1F	/* channel option 5 */
-#define	CD1400_COR5_ISTRIP		(1<<7)
-#define	CD1400_COR5_LNEXT		(1<<6)
-#define	CD1400_COR5_CMOE		(1<<5)	/* char matching on error */
-#define	CD1400_COR5_EBD			(1<<2)	/* end of break detected */
-#define	CD1400_COR5_ONLCR		(1<<1)
-#define	CD1400_COR5_OCRNL		(1<<0)
-#define	CD1400_CCSR		0x0B	/* channel control status */
-#define	CD1400_RDCR		0x0E	/* received data count */
-#define	CD1400_SCHR1		0x1A	/* special character 1 */
-#define	CD1400_SCHR2		0x1B	/* special character 2 */
-#define	CD1400_SCHR3		0x1C	/* special character 3 */
-#define	CD1400_SCHR4		0x1D	/* special character 4 */
-#define	CD1400_SCRL		0x22	/* special character range, low */
-#define	CD1400_SCRH		0x23	/* special character range, high */
-#define	CD1400_LNC		0x24	/* lnext character */
-#define	CD1400_MCOR1		0x15	/* modem change option 1 */
-#define	CD1400_MCOR1_DSRzd		(1<<7)	/* DSR one-to-zero delta */
-#define	CD1400_MCOR1_CTSzd		(1<<6)
-#define	CD1400_MCOR1_RIzd		(1<<5)
-#define	CD1400_MCOR1_CDzd		(1<<4)
-#define	CD1400_MCOR1_DTRth		(15<<0)	/* dtrflow threshold */
-#define	CD1400_MCOR2		0x16	/* modem change option 2 */
-#define	CD1400_MCOR2_DSRod		(1<<7)	/* DSR zero-to-one delta */
-#define	CD1400_MCOR2_CTSod		(1<<6)
-#define	CD1400_MCOR2_RIod		(1<<5)
-#define	CD1400_MCOR2_CDod		(1<<4)
-#define	CD1400_RTPR		0x21	/* receive timeout period */
-#define	CD1400_MSVR1		0x6C	/* modem signal value 1 */
-#define	CD1400_MSVR1_RTS		(1<<0)	/* RTS line (r/w) */
-#define	CD1400_MSVR2		0x6D	/* modem signal value 2 */
-#define	CD1400_MSVR2_DSR		(1<<7)	/* !DSR line (r) */
-#define	CD1400_MSVR2_CTS		(1<<6)	/* !CTS line (r) */
-#define	CD1400_MSVR2_RI			(1<<5)	/* !RI line (r) */
-#define	CD1400_MSVR2_CD			(1<<4)	/* !CD line (r) */
-#define	CD1400_MSVR2_DTR		(1<<1)	/* DTR line (r/w) */
-#define	CD1400_PSVR		0x6F	/* printer signal value */
-#define	CD1400_RBPR		0x78	/* receive baud rate period */
-#define	CD1400_RCOR		0x7C	/* receive clock option */
-#define	CD1400_TBPR		0x72	/* transmit baud rate period */
-#define	CD1400_TCOR		0x76	/* transmit clock option */
diff --git a/sys/dev/ic/cd180.h b/sys/dev/ic/cd180.h
deleted file mode 100644
index 5783ebd2db56..000000000000
--- a/sys/dev/ic/cd180.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
- * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-/*
- * Cirrus Logic CD180 registers
- */
-
-/* Global registers */
-#define CD180_GIVR      0x40    /* Global Interrupt Verctor Register      */
-#define CD180_GICR      0x41    /* Global Interrupting Channel Register   */
-#define CD180_PILR1     0x61    /* Priority Interrupt Level Register 1    */
-#define CD180_PILR2     0x62    /* Priority Interrupt Level Register 2    */
-#define CD180_PILR3     0x63    /* Priority Interrupt Level Register 3    */
-#define CD180_CAR       0x64    /* Channel Access Register                */
-#define CD180_GFRCR     0x6B    /* Global Firmware Revision Code Register */
-#define CD180_PPRH      0x70    /* Prescaler Period Register MSB          */
-#define CD180_PPRL      0x71    /* Prescaler Period Register LSB          */
-#define CD180_RDR       0x78    /* Receiver Data Register                 */
-#define CD180_RCSR      0x7A    /* Receiver Character Status Register     */
-#define CD180_TDR       0x7B    /* Transmit Data Register                 */
-#define CD180_EOIR      0x7F    /* End of Interrupt Register              */
-
-/* Channel Registers */
-#define CD180_CCR       0x01    /* Channel Command Register               */
-#define CD180_IER       0x02    /* Interrupt Enable Register              */
-#define CD180_COR1      0x03    /* Channel Option Register 1              */
-#define CD180_COR2      0x04    /* Channel Option Register 1              */
-#define CD180_COR3      0x05    /* Channel Option Register 1              */
-#define CD180_CCSR      0x06    /* Channel Control STatus Register        */
-#define CD180_RDCR      0x07    /* Receive Data Count Register            */
-#define CD180_SCHR1     0x09    /* Special Character Register 1           */
-#define CD180_SCHR2     0x0A    /* Special Character Register 2           */
-#define CD180_SCHR3     0x0B    /* Special Character Register 3           */
-#define CD180_SCHR4     0x0C    /* Special Character Register 4           */
-#define CD180_MCOR1     0x10    /* Modem Change Option 1 Register         */
-#define CD180_MCOR2     0x11    /* Modem Change Option 2 Register         */
-#define CD180_MCR       0x12    /* Modem Change Register                  */
-#define CD180_RTPR      0x18    /* Receive Timeout Period Register        */
-#define CD180_MSVR      0x28    /* Modem Signal Value Register            */
-#define CD180_RBPRH     0x31    /* Receive Baud Rate Period Register MSB  */
-#define CD180_RBPRL     0x32    /* Receive Baud Rate Period Register LSB  */
-#define CD180_TBPRH     0x39    /* Transmit Baud Rate Period Register MSB */
-#define CD180_TBPRL     0x3A    /* Transmit Baud Rate Period Register LSB */
-
-/** Register descritpions **/
-
-/* Global Interrupt Vector Register */
-#define GIVR_IT_MSCI    0x01    /* Modem Signal Change Interrupt          */
-#define GIVR_IT_TDI     0x02    /* Transmit Data Interrupt                */
-#define GIVR_IT_RGDI    0x03    /* Receive Good Data Interrupt            */
-#define GIVR_IT_REI     0x07    /* Receive Exception Interrupt            */
-
-/* Global Interrupt Channel Register */
-#define GICR_CHAN       0x1C    /* Channel Number Mask                    */
-#define GICR_LSH        2       /* Channel Number Shift                   */
-
-/* Channel Address Register */
-#define CAR_CHAN        0x07    /* Channel Number Mask                    */
-#define CAR_A7          0x08    /* Addres bit 7 (unused)                  */
-
-/* Receive Character Status Register */
-#define RCSR_OE         0x01    /* Overrun Error                          */
-#define RCSR_FE         0x02    /* Frame Error                            */
-#define RCSR_PE         0x04    /* Parity Error                           */
-#define RCSR_Break      0x08    /* Break detected                         */
-#define RCSR_Timeout    0x80    /* Rx Timeout                             */
-#define RCSR_SCMASK     0x70    /* Special Character Detected Mask        */
-#define RCSR_SC1        0x10    /* Special Char 1 (or 1 & 3 seq matched)  */
-#define RCSR_SC2        0x20    /* Special Char 2 (or 2 & 4 seq matched)  */
-#define RCSR_SC3        0x30    /* Special Char 3                         */
-#define RCSR_SC4        0x40    /* Special Char 4                         */
-
-/* Channel Command Register */
-#define CCR_ResetChan   0x80    /* Reset Channel                          */
-#define CCR_HWRESET     0x81    /* Hardware Reset (all channels)          */
-#define CCR_CORCHG1     0x42    /* Channel Option Register 1 Changed      */
-#define CCR_CORCHG2     0x44    /* Channel Option Register 2 Changed      */
-#define CCR_CORCHG3     0x48    /* Channel Option Register 3 Changed      */
-#define CCR_SENDSPCH1   0x21    /* Send Special Character 1               */
-#define CCR_SENDSPCH2   0x22    /* Send Special Character 2               */
-#define CCR_SENDSPCH3   0x23    /* Send Special Character 3               */
-#define CCR_SENDSPCH4   0x24    /* Send Special Character 4               */
-#define CCR_RCVRDIS     0x11    /* Receiver Disable                       */
-#define CCR_RCVREN      0x12    /* Receiver Enable                        */
-#define CCR_XMTRDIS     0x14    /* Transmitter Disable                    */
-#define CCR_XMTREN      0x18    /* Transmitter Enable                     */
-
-/* Interrupt Enable Register */
-#define IER_DSR         0x80    /* Enable interrupt on DSR change         */
-#define IER_CD          0x40    /* Enable interrupt on CD change          */
-#define IER_CTS         0x20    /* Enable interrupt on CTS change         */
-#define IER_RxData      0x10    /* Enable interrupt on Receive Data       */
-#define IER_RxSC        0x08    /* Enable interrupt on Receive Spec. Char */
-#define IER_TxRdy       0x04    /* Enable interrupt on TX FIFO empty      */
-#define IER_TxMpty      0x02    /* Enable interrupt on TX completely empty*/
-#define IER_RET         0x01    /* Enable interrupt on RX Except. Timeout */
-
-/* Channel Option Register 1 */
-#define COR1_ODDP       0x80    /* Odd Parity                             */
-#define COR1_ParMMASK   0x60    /* Parity Mode mask                       */
-#define COR1_NOPAR      0x02    /* No Parity                              */
-#define COR1_FORCEPAR   0x20    /* Force Parity                           */
-#define COR1_NORMPAR    0x40    /* Normal Parity                          */
-#define COR1_Ignore     0x10    /* Ignore Parity on RX                    */
-#define COR1_StopMASK   0x0C    /* Stop Bits mode mask                    */
-#define COR1_1SB        0x00    /* 1 Stop Bit                             */
-#define COR1_15SB       0x04    /* 1.5 Stop Bits                          */
-#define COR1_2SB        0x08    /* 2 Stop Bits                            */
-#define COR1_CHLMASK    0x03    /* Character Length mask                  */
-#define COR1_5BITS      0x00    /* 5 bits                                 */
-#define COR1_6BITS      0x01    /* 6 bits                                 */
-#define COR1_7BITS      0x02    /* 7 bits                                 */
-#define COR1_8BITS      0x03    /* 8 bits                                 */
-
-/* Channel Option Register 2 */
-#define COR2_IXM        0x80    /* Implied XON mode                       */
-#define COR2_TxIBE      0x40    /* Enable In-Band XON/XOFF Flow Control   */
-#define COR2_ETC        0x20    /* Embedded Tx Commands Enable            */
-#define COR2_LLM        0x10    /* Local Loopback Mode                    */
-#define COR2_RLM        0x08    /* Remote Loopback Mode                   */
-#define COR2_RtsAO      0x04    /* RTS Automatic Output Enable            */
-#define COR2_CtsAE      0x02    /* CTS Automatic Enable                   */
-#define COR2_DsrAE      0x01    /* DSR Automatic Enable                   */
-
-/* Channel Option Register 3 */
-#define COR3_XonCH      0x80    /* XON is a double seq (1 & 3)            */
-#define COR3_XoffCH     0x40    /* XOFF is a double seq (1 & 3)           */
-#define COR3_FCT        0x20    /* Flow-Control Transparency Mode         */
-#define COR3_SCDE       0x10    /* Special Character Detection Enable     */
-#define COR3_RxTHMASK   0x0F    /* RX FIFO Threshold value (1-8)          */
-
-/* Channel Control Status Register */
-#define CCSR_RxEn       0x80    /* Revceiver Enabled                      */
-#define CCSR_RxFloff    0x40    /* Receive Flow Off (XOFF sent)           */
-#define CCSR_RxFlon     0x20    /* Receive Flow On (XON sent)             */
-#define CCSR_TxEn       0x08    /* Transmitter Enabled                    */
-#define CCSR_TxFloff    0x04    /* Transmit Flow Off (got XOFF)           */
-#define CCSR_TxFlon     0x02    /* Transmit Flow On (got XON)             */
-
-/* Modem Change Option Register 1 */
-#define MCOR1_DSRzd     0x80    /* Detect 0->1 transition of DSR          */
-#define MCOR1_CDzd      0x40    /* Detect 0->1 transition of CD           */
-#define MCOR1_CTSzd     0x20    /* Detect 0->1 transition of CTS          */
-#define MCOR1_DTRthMASK 0x0F    /* Automatic DTR FC Threshold (1-8) chars */
-
-/* Modem Change Option Register 2 */
-#define MCOR2_DSRod     0x80    /* Detect 1->0 transition of DSR          */
-#define MCOR2_CDod      0x40    /* Detect 1->0 transition of CD           */
-#define MCOR2_CTSod     0x20    /* Detect 1->0 transition of CTS          */
-
-/* Modem Change Register */
-#define MCR_DSRchg      0x80    /* DSR Changed                            */
-#define MCR_CDchg       0x40    /* CD  Changed                            */
-#define MCR_CTSchg      0x20    /* CTS Changed                            */
-
-/* Modem Signal Value Register */
-#define MSVR_DSR        0x80    /* Current state of DSR input             */
-#define MSVR_CD         0x40    /* Current state of DSR input             */
-#define MSVR_CTS        0x20    /* Current state of CTS input             */
-#define MSVR_DTR        0x02    /* Current state of DTR output            */
-#define MSVR_RTS        0x01    /* Current state of RTS output            */
-
-/* Escape characters */
-#define CD180_C_ESC     0x00    /* Escape character                       */
-#define CD180_C_SBRK    0x81    /* Start sending BREAK                    */
-#define CD180_C_DELAY   0x82    /* Delay output                           */
-#define CD180_C_EBRK    0x83    /* Stop sending BREAK                     */
-
-/* Miscellaneous */
-#define CD180_NCHAN     8       /* 8 channels per chip                    */
-#define CD180_CTICKS    16      /* 16 ticks for character processing      */
-#define CD180_NFIFO     8       /* 8 bytes in FIFO                        */
diff --git a/sys/dev/ic/esp.h b/sys/dev/ic/esp.h
deleted file mode 100644
index a381ee7d22aa..000000000000
--- a/sys/dev/ic/esp.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*-
- * Copyright (c) 1995 Sean Eric Fagan.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of the author nor the names of contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _IC_ESP_H_
-#define	_IC_ESP_H_
-
-/*
- * Definitions for Hayes ESP serial cards.
- */
-
-/*
- * CMD1 and CMD2 are the command ports, offsets from <esp_iobase>.
- */
-#define	ESP_CMD1	4
-#define	ESP_CMD2	5
-
-/*
- * STAT1 and STAT2 are to get return values and status bytes;
- * they overload CMD1 and CMD2.
- */
-#define	ESP_STATUS1	ESP_CMD1
-#define	ESP_STATUS2	ESP_CMD2
-
-/*
- * Commands.  Commands are given by writing the command value to
- * ESP_CMD1 and then writing or reading some number of bytes from
- * ESP_CMD2 or ESP_STATUS2.
- */
-#define	ESP_GETTEST	0x01	/* self-test command (1 byte + extras) */
-#define	ESP_GETDIPS	0x02	/* get on-board DIP switches (1 byte) */
-#define	ESP_SETFLOWTYPE	0x08	/* set type of flow-control (2 bytes) */
-#define	ESP_SETRXFLOW	0x0a	/* set Rx FIFO flow control levels (4 bytes) */
-#define	ESP_SETMODE	0x10	/* set board mode (1 byte) */
-
-/* Mode bits (ESP_SETMODE). */
-#define	ESP_MODE_FIFO	0x02	/* act like a 16550 (compatibility mode) */
-#define	ESP_MODE_RTS	0x04	/* use RTS hardware flow control */
-#define	ESP_MODE_SCALE	0x80	/* scale FIFO trigger levels */
-
-/* Flow control type bits (ESP_SETFLOWTYPE). */
-#define	ESP_FLOW_RTS	0x04	/* cmd1: local Rx sends RTS flow control */
-#define	ESP_FLOW_CTS	0x10	/* cmd2: local transmitter responds to CTS */
-
-/* Used by ESP_SETRXFLOW. */
-#define	HIBYTE(w)	(((w) >> 8) & 0xff)
-#define	LOBYTE(w)	((w) & 0xff)
-
-#endif /* !_IC_ESP_H_ */
diff --git a/sys/dev/ic/i8237.h b/sys/dev/ic/i8237.h
deleted file mode 100644
index 2bc8a08317c6..000000000000
--- a/sys/dev/ic/i8237.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Intel 8237 DMA Controller
- *
- * $FreeBSD$
- */
-
-#define	DMA37MD_SINGLE	0x40	/* single pass mode */
-#define	DMA37MD_CASCADE	0xc0	/* cascade mode */
-#define	DMA37MD_AUTO	0x50	/* autoinitialise single pass mode */
-#define	DMA37MD_WRITE	0x04	/* read the device, write memory operation */
-#define	DMA37MD_READ	0x08	/* write the device, read memory operation */
-
diff --git a/sys/dev/ic/i82586.h b/sys/dev/ic/i82586.h
deleted file mode 100644
index 964621bd3677..000000000000
--- a/sys/dev/ic/i82586.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/*-
- * Copyright (c) 1992, University of Vermont and State Agricultural College.
- * Copyright (c) 1992, Garrett A. Wollman.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	Vermont and State Agricultural College and Garrett A. Wollman.
- * 4. Neither the name of the University nor the name of the author
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE UNIVERSITY OR AUTHOR BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-/*
- * Intel 82586 Ethernet chip
- * Register, bit, and structure definitions.
- *
- * Written by GAW with reference to the Clarkson Packet Driver code for this
- * chip written by Russ Nelson and others.
- */
-
-struct ie_en_addr {
-	u_char data[6];
-};
-
-/*
- * This is the master configuration block.  It tells the hardware where all
- * the rest of the stuff is.
- */
-struct ie_sys_conf_ptr {
-	u_short mbz;			/* must be zero */
-	u_char ie_bus_use;		/* true if 8-bit only */
-	u_char mbz2[5];			/* must be zero */
-	caddr_t ie_iscp_ptr;		/* 24-bit physaddr of ISCP */
-};
-
-/*
- * Note that this is wired in hardware; the SCP is always located here, no
- * matter what.
- */
-#define IE_SCP_ADDR 0xfffff4
-
-/*
- * The tells the hardware where all the rest of the stuff is, too.
- * FIXME: some of these should be re-commented after we figure out their
- * REAL function.
- */
-struct ie_int_sys_conf_ptr {
-	u_char ie_busy;			/* zeroed after init */
-	u_char mbz;
-	u_short ie_scb_offset;		/* 16-bit physaddr of next struct */
-	caddr_t ie_base;		/* 24-bit physaddr for all 16-bit vars */
-};
-
-/*
- * This FINALLY tells the hardware what to do and where to put it.
- */
-struct ie_sys_ctl_block {
-	u_short ie_status;		/* status word */
-	u_short ie_command;		/* command word */
-	u_short ie_command_list;	/* 16-pointer to command block list */
-	u_short ie_recv_list;		/* 16-pointer to receive frame list */
-	u_short ie_err_crc;		/* CRC errors */
-	u_short ie_err_align;		/* Alignment errors */
-	u_short ie_err_resource;	/* Resource errors */
-	u_short ie_err_overrun;		/* Overrun errors */
-};
-
-/* Command values */
-#define IE_RU_COMMAND	0x0070	/* mask for RU command */
-#define IE_RU_NOP	0	/* for completeness */
-#define IE_RU_START	0x0010	/* start receive unit command */
-#define IE_RU_ENABLE	0x0020	/* enable receiver command */
-#define IE_RU_DISABLE	0x0030	/* disable receiver command */
-#define IE_RU_ABORT	0x0040	/* abort current receive operation */
-
-#define IE_CU_COMMAND	0x0700	/* mask for CU command */
-#define IE_CU_NOP	0	/* included for completeness */
-#define IE_CU_START	0x0100	/* do-command command */
-#define IE_CU_RESUME	0x0200	/* resume a suspended cmd list */
-#define IE_CU_STOP	0x0300	/* SUSPEND was already taken */
-#define IE_CU_ABORT	0x0400	/* abort current command */
-
-#define IE_ACK_COMMAND	0xf000	/* mask for ACK command */
-#define IE_ACK_CX	0x8000	/* ack IE_ST_DONE */
-#define IE_ACK_FR	0x4000	/* ack IE_ST_RECV */
-#define IE_ACK_CNA	0x2000	/* ack IE_ST_ALLDONE */
-#define IE_ACK_RNR	0x1000	/* ack IE_ST_RNR */
-
-#define IE_ACTION_COMMAND(x) (((x) & IE_CU_COMMAND) == IE_CU_START)
-				/* is this command an action command? */
-
-/* Status values */
-#define IE_ST_WHENCE	0xf000	/* mask for cause of interrupt */
-#define IE_ST_DONE	0x8000	/* command with I bit completed */
-#define IE_ST_RECV	0x4000	/* frame received */
-#define IE_ST_ALLDONE	0x2000	/* all commands completed */
-#define IE_ST_RNR	0x1000	/* receive not ready */
-
-#define IE_CU_STATUS	0x700	/* mask for command unit status */
-#define IE_CU_ACTIVE	0x200	/* command unit is active */
-#define IE_CU_SUSPEND	0x100	/* command unit is suspended */
-
-#define IE_RU_STATUS	0x70	/* mask for receiver unit status */
-#define IE_RU_SUSPEND	0x10	/* receiver is suspended */
-#define IE_RU_NOSPACE	0x20	/* receiver has no resources */
-#define IE_RU_READY	0x40	/* reveiver is ready */
-
-/*
- * This is filled in partially by the chip, partially by us.
- */
-struct ie_recv_frame_desc {
-	u_short ie_fd_status;		/* status for this frame */
-	u_short ie_fd_last;		/* end of frame list flag */
-	u_short ie_fd_next;		/* 16-pointer to next RFD */
-	u_short ie_fd_buf_desc;		/* 16-pointer to list of buffer desc's */
-	struct ie_en_addr dest;		/* destination ether */
-	struct ie_en_addr src;		/* source ether */
-	u_short ie_length;		/* 802 length/Ether type */
-	u_short mbz;			/* must be zero */
-};
-
-#define IE_FD_LAST	0x8000	/* last rfd in list */
-#define IE_FD_SUSP	0x4000	/* suspend RU after receipt */
-
-#define IE_FD_COMPLETE	0x8000	/* frame is complete */
-#define IE_FD_BUSY	0x4000	/* frame is busy */
-#define IE_FD_OK	0x2000	/* frame is bad */
-#define IE_FD_RNR	0x0200	/* receiver out of resources here */
-
-/*
- * linked list of buffers...
- */
-struct ie_recv_buf_desc {
-	u_short ie_rbd_actual;		/* status for this buffer */
-	u_short ie_rbd_next;		/* 16-pointer to next RBD */
-	caddr_t ie_rbd_buffer;		/* 24-pointer to buffer for this RBD */
-	u_short ie_rbd_length;		/* length of the buffer */
-	u_short mbz;			/* must be zero */
-};
-
-#define IE_RBD_LAST	0x8000	/* last buffer */
-#define IE_RBD_USED	0x4000	/* this buffer has data */
-/*
- * All commands share this in common.
- */
-struct ie_cmd_common {
-	u_short ie_cmd_status;		/* status of this command */
-	u_short ie_cmd_cmd;		/* command word */
-	u_short ie_cmd_link;		/* link to next command */
-};
-
-#define IE_STAT_COMPL	0x8000	/* command is completed */
-#define IE_STAT_BUSY	0x4000	/* command is running now */
-#define IE_STAT_OK	0x2000	/* command completed successfully */
-
-#define IE_CMD_NOP	0x0000	/* NOP */
-#define IE_CMD_IASETUP	0x0001	/* initial address setup */
-#define IE_CMD_CONFIG	0x0002	/* configure command */
-#define IE_CMD_MCAST	0x0003	/* multicast setup command */
-#define IE_CMD_XMIT	0x0004	/* transmit command */
-#define IE_CMD_TDR	0x0005	/* time-domain reflectometer command */
-#define IE_CMD_DUMP	0x0006	/* dump command */
-#define IE_CMD_DIAGNOSE	0x0007	/* diagnostics command */
-
-#define IE_CMD_LAST	0x8000	/* this is the last command in the list */
-#define IE_CMD_SUSPEND	0x4000	/* suspend CU after this command */
-#define IE_CMD_INTR	0x2000	/* post an interrupt after completion */
-
-/*
- * This is the command to transmit a frame.
- */
-struct ie_xmit_cmd {
-	struct ie_cmd_common com;	/* common part */
-#define ie_xmit_status com.ie_cmd_status
-
-	u_short ie_xmit_desc;		/* 16-pointer to buffer descriptor */
-	struct ie_en_addr ie_xmit_addr; /* destination address */
-
-	u_short ie_xmit_length;		/* 802.3 length/Ether type field */
-};
-
-#define IE_XS_MAXCOLL  	0x000f	/* number of collisions during transmit */
-#define IE_XS_EXCMAX	0x0020	/* exceeded maximum number of collisions */
-#define IE_XS_SQE	0x0040	/* SQE positive */
-#define IE_XS_DEFERRED	0x0080	/* transmission deferred */
-#define IE_XS_UNDERRUN	0x0100	/* DMA underrun */
-#define IE_XS_LOSTCTS	0x0200	/* Lost CTS */
-#define IE_XS_NOCARRIER	0x0400	/* No Carrier */
-#define IE_XS_LATECOLL	0x0800	/* Late collision */
-
-/*
- * This is a buffer descriptor for a frame to be transmitted.
- */
-
-struct ie_xmit_buf {
-	u_short ie_xmit_flags;		/* see below */
-	u_short ie_xmit_next;		/* 16-pointer to next desc. */
-	caddr_t ie_xmit_buf;		/* 24-pointer to the actual buffer */
-};
-
-#define IE_XMIT_LAST 0x8000	/* this TBD is the last one */
-/* The rest of the `flags' word is actually the length. */
-
-/*
- * Multicast setup command.
- */
-
-#define MAXMCAST 50		/* must fit in transmit buffer */
-
-struct ie_mcast_cmd {
-	struct ie_cmd_common com;	/* common part */
-#define ie_mcast_status com.ie_cmd_status
-
-	u_short ie_mcast_bytes;	/* size (in bytes) of multicast addresses */
-	struct ie_en_addr ie_mcast_addrs[MAXMCAST + 1];	/* space for them */
-};
-
-/*
- * Time Domain Reflectometer command.
- */
-
-struct ie_tdr_cmd {
-	struct ie_cmd_common com;	/* common part */
-#define ie_tdr_status com.ie_cmd_status
-
-	u_short ie_tdr_time;		/* error bits and time */
-};
-
-#define IE_TDR_SUCCESS	0x8000	/* TDR succeeded without error */
-#define IE_TDR_XCVR	0x4000	/* detected a transceiver problem */
-#define IE_TDR_OPEN	0x2000	/* detected an open */
-#define IE_TDR_SHORT	0x1000	/* TDR detected a short */
-#define IE_TDR_TIME	0x07ff	/* mask for reflection time */
-
-/*
- * Initial Address Setup command
- */
-struct ie_iasetup_cmd {
-	struct ie_cmd_common com;
-#define ie_iasetup_status com.ie_cmd_status
-
-	struct ie_en_addr ie_address;
-};
-
-/*
- * Configuration command
- */
-struct ie_config_cmd {
-	struct ie_cmd_common com;	/* common part */
-#define ie_config_status com.ie_cmd_status
-
-	u_char ie_config_count;		/* byte count (0x0c) */
-	u_char ie_fifo;			/* fifo (8) */
-	u_char ie_save_bad;		/* save bad frames (0x40) */
-	u_char ie_addr_len;		/* address length (0x2e) (AL-LOC == 1) */
-	u_char ie_priority;		/* priority and backoff (0x0) */
-	u_char ie_ifs;			/* inter-frame spacing (0x60) */
-	u_char ie_slot_low;		/* slot time, LSB (0x0) */
-	u_char ie_slot_high;		/* slot time, MSN, and retries (0xf2) */
-	u_char ie_promisc;		/* 1 if promiscuous, else 0 */
-	u_char ie_crs_cdt;		/* CSMA/CD parameters (0x0) */
-	u_char ie_min_len;		/* min frame length (0x40) */
-	u_char ie_junk;			/* stuff for 82596 (0xff) */
-};
-
-/*
- * Here are a few useful functions.  We could have done these as macros,
- * but since we have the inline facility, it makes sense to use that
- * instead.
- */
-static __inline void
-ie_setup_config(volatile struct ie_config_cmd *cmd,
-		int promiscuous, int manchester) {
-	cmd->ie_config_count = 0x0c;
-	cmd->ie_fifo = 8;
-	cmd->ie_save_bad = 0x40;
-	cmd->ie_addr_len = 0x2e;
-	cmd->ie_priority = 0;
-	cmd->ie_ifs = 0x60;
-	cmd->ie_slot_low = 0;
-	cmd->ie_slot_high = 0xf2;
-	cmd->ie_promisc = !!promiscuous | manchester << 2;
-	cmd->ie_crs_cdt = 0;
-	cmd->ie_min_len = 64;
-	cmd->ie_junk = 0xff;
-}
-
-static __inline void *
-Align(void *ptr) {
-	uintptr_t l = (uintptr_t)ptr;
-	l = (l + 3) & ~3L;
-	return (void *)l;
-}
-
-static __inline volatile void *
-Alignvol(volatile void *ptr) {
-	uintptr_t l = (uintptr_t)ptr;
-	l = (l + 3) & ~3L;
-	return (volatile void *)l;
-}
-
-static __inline void
-ie_ack(volatile struct ie_sys_ctl_block *scb,
-				  u_int mask, int unit,
-				  void (*ca)(int)) {
-	scb->ie_command = scb->ie_status & mask;
-	(*ca)(unit);
-}
diff --git a/sys/dev/ic/nec765.h b/sys/dev/ic/nec765.h
deleted file mode 100644
index c08b73b7d600..000000000000
--- a/sys/dev/ic/nec765.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*-
- * Copyright (c) 1991 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	from: @(#)nec765.h	7.1 (Berkeley) 5/9/91
- * $FreeBSD$
- */
-
-/*
- * Nec 765 floppy disc controller definitions
- */
-
-/* Main status register */
-#define NE7_DAB	0x01	/* Diskette drive A is seeking, thus busy */
-#define NE7_DBB	0x02	/* Diskette drive B is seeking, thus busy */
-#define NE7_CB	0x10	/* Diskette Controller Busy */
-#define NE7_NDM	0x20	/* Diskette Controller in Non Dma Mode */
-#define NE7_DIO	0x40	/* Diskette Controller Data register I/O */
-#define NE7_RQM	0x80	/* Diskette Controller ReQuest for Master */
-
-/* Status register ST0 */
-#define NE7_ST0BITS	"\020\010invld\007abnrml\006seek_cmplt\005equ_chck\004drive_notrdy\003top_head"
-
-#define NE7_ST0_IC	0xc0	/* interrupt completion code */
-
-#define NE7_ST0_IC_RC	0xc0	/* terminated due to ready changed, n/a */
-#define NE7_ST0_IC_IV	0x80	/* invalid command; must reset FDC */
-#define NE7_ST0_IC_AT	0x40	/* abnormal termination, check error stat */
-#define NE7_ST0_IC_NT	0x00	/* normal termination */
-
-#define NE7_ST0_SE	0x20	/* seek end */
-#define NE7_ST0_EC	0x10	/* equipment check, recalibrated but no trk0 */
-#define NE7_ST0_NR	0x08	/* not ready (n/a) */
-#define NE7_ST0_HD	0x04	/* upper head selected */
-#define NE7_ST0_DR	0x03	/* drive code */
-
-/* Status register ST1 */
-#define NE7_ST1BITS	"\020\010end_of_cyl\006bad_crc\005data_overrun\003sec_not_fnd\002write_protect\001no_am"
-
-#define NE7_ST1_EN	0x80	/* end of cylinder, access past last record */
-#define NE7_ST1_DE	0x20	/* data error, CRC fail in ID or data */
-#define NE7_ST1_OR	0x10	/* DMA overrun, DMA failed to do i/o quickly */
-#define NE7_ST1_ND	0x04	/* no data, sector not found or CRC in ID f. */
-#define NE7_ST1_NW	0x02	/* not writeable, attempt to violate WP */
-#define NE7_ST1_MA	0x01	/* missing address mark (in ID or data field)*/
-
-/* Status register ST2 */
-#define NE7_ST2BITS	"\020\007ctrl_mrk\006bad_crc\005wrong_cyl\004scn_eq\003scn_not_fnd\002bad_cyl\001no_dam"
-
-#define NE7_ST2_CM	0x40	/* control mark; found deleted data */
-#define NE7_ST2_DD	0x20	/* data error in data field, CRC fail */
-#define NE7_ST2_WC	0x10	/* wrong cylinder, ID field mismatches cmd */
-#define NE7_ST2_SH	0x08	/* scan equal hit */
-#define NE7_ST2_SN	0x04	/* scan not satisfied */
-#define NE7_ST2_BC	0x02	/* bad cylinder, cylinder marked 0xff */
-#define NE7_ST2_MD	0x01	/* missing address mark in data field */
-
-/* Status register ST3 */
-#define NE7_ST3BITS	"\020\010fault\007write_protect\006drdy\005tk0\004two_side\003side_sel\002"
-
-#define NE7_ST3_FT	0x80	/* fault; PC: n/a */
-#define NE7_ST3_WP	0x40	/* write protected */
-#define NE7_ST3_RD	0x20	/* ready; PC: always true */
-#define NE7_ST3_T0	0x10	/* track 0 */
-#define NE7_ST3_TS	0x08	/* two-sided; PC: n/a */
-#define NE7_ST3_HD	0x04	/* upper head select */
-#define NE7_ST3_US	0x03	/* unit select */
-
-/* Commands */
-/*
- * the top three bits -- where appropriate -- are set as follows:
- *
- * 0x80 - MT  multi-track; allow both sides to be handled in single cmd
- * 0x40 - MFM modified frequency modulation; use MFM encoding
- * 0x20 - SK  skip; skip sectors marked as "deleted"
- */
-#define NE7CMD_READTRK	0x42	/*  read whole track */
-#define NE7CMD_SPECIFY	3	/*  specify drive parameters - requires unit
-					parameters byte */
-#define NE7CMD_SENSED	4	/*  sense drive - requires unit select byte */
-#define NE7CMD_WRITE	0xc5	/*  write - requires eight additional bytes */
-#define NE7CMD_READ	0xe6	/*  read - requires eight additional bytes */
-#define NE7CMD_RECAL	7	/*  recalibrate drive - requires
-					unit select byte */
-#define NE7CMD_SENSEI	8	/*  sense controller interrupt status */
-#define NE7CMD_WRITEDEL	0xc9	/*  write deleted data */
-#define NE7CMD_READID	0x4a	/*  read ID field */
-#define NE7CMD_READDEL	0xec	/*  read deleted data */
-#define NE7CMD_FORMAT	0x4d	/*  format - requires five additional bytes */
-#define NE7CMD_SEEK	0x0f	/*  seek drive - requires unit select byte
-					and new cyl byte */
-#define NE7CMD_SCNEQU	0xf1	/*  scan equal */
-#define NE7CMD_SCNLE	0xf9	/*  scan less or equal */
-#define NE7CMD_SCNGE	0xfd	/*  scan greater or equal */
-
-/*
- * Enhanced controller commands:
- */
-#define NE7CMD_VERSION	0x10	/*  version (ok for all controllers) */
-
-#define I8207X_CONFIGURE 0x13   /*  configure enhanced features */
-
-/*
- * "specify" definitions
- *
- * acronyms (times are relative to a FDC clock of 8 MHz):
- * srt - step rate; PC usually 3 ms
- * hut - head unload time; PC usually maximum of 240 ms
- * hlt - head load time; PC usually minimum of 2 ms
- * nd  - no DMA flag; PC usually not set (0)
- */
-
-#define NE7_SPEC_1(srt, hut) (((16 - (srt)) << 4) | (((hut) / 16)))
-#define NE7_SPEC_2(hlt, nd)  (((hlt) & 0xFE) | ((nd) & 1))
diff --git a/sys/dev/ic/ns16550.h b/sys/dev/ic/ns16550.h
deleted file mode 100644
index e8fad7da832e..000000000000
--- a/sys/dev/ic/ns16550.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*-
- * Copyright (c) 1991 The Regents of the University of California.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *	This product includes software developed by the University of
- *	California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- *	from: @(#)ns16550.h	7.1 (Berkeley) 5/9/91
- * $FreeBSD$
- */
-
-/*
- * NS16550 UART registers
- */
-#ifdef PC98
-#define	com_data	0x000	/* data register (R/W) */
-#define	com_dlbl	0x000	/* divisor latch low (W) */
-#define	com_dlbh	0x100	/* divisor latch high (W) */
-#define	com_ier		0x100	/* interrupt enable (W) */
-#define	com_iir		0x200	/* interrupt identification (R) */
-#define	com_fifo	0x200	/* FIFO control (W) */
-#define	com_lctl	0x300	/* line control register (R/W) */
-#define	com_cfcr	0x300	/* line control register (R/W) */
-#define	com_mcr		0x400	/* modem control register (R/W) */
-#define	com_lsr		0x500	/* line status register (R/W) */
-#define	com_msr		0x600	/* modem status register (R/W) */
-#else /* IBM-PC */
-#define	com_data	0	/* data register (R/W) */
-#define	com_dlbl	0	/* divisor latch low (W) */
-#define	com_dlbh	1	/* divisor latch high (W) */
-#define	com_ier		1	/* interrupt enable (W) */
-#define	com_iir		2	/* interrupt identification (R) */
-#define	com_fifo	2	/* FIFO control (W) */
-#define	com_lctl	3	/* line control register (R/W) */
-#define	com_cfcr	3	/* line control register (R/W) */
-#define	com_mcr		4	/* modem control register (R/W) */
-#define	com_lsr		5	/* line status register (R/W) */
-#define	com_msr		6	/* modem status register (R/W) */
-#endif /* PC98 */