diff options
| author | Pyun YongHyeon <yongari@FreeBSD.org> | 2010-05-06 18:43:00 +0000 |
|---|---|---|
| committer | Pyun YongHyeon <yongari@FreeBSD.org> | 2010-05-06 18:43:00 +0000 |
| commit | 6c3a42ef44f12e69086a579fcbc266f63a643924 (patch) | |
| tree | 39271c427231e0b202170833dbdd20a9895dd16e /sys/dev/msk | |
| parent | 0fcc3770ff3c578809412174383b4659a322beb4 (diff) | |
Notes
Diffstat (limited to 'sys/dev/msk')
| -rw-r--r-- | sys/dev/msk/if_msk.c | 9 | ||||
| -rw-r--r-- | sys/dev/msk/if_mskreg.h | 6 |
2 files changed, 11 insertions, 4 deletions
diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c index b6276a0d99aa..6da2bb853853 100644 --- a/sys/dev/msk/if_msk.c +++ b/sys/dev/msk/if_msk.c @@ -3673,9 +3673,9 @@ msk_init_locked(struct msk_if_softc *sc_if) if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { /* Set Rx Pause threshould. */ - CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), + CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), MSK_ECU_LLPP); - CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), + CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), MSK_ECU_ULPP); /* Configure store-and-forward for Tx. */ msk_set_tx_stfwd(sc_if); @@ -3763,6 +3763,11 @@ msk_init_locked(struct msk_if_softc *sc_if) msk_stop(sc_if); return; } + if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { + /* Disable flushing of non-ASF packets. */ + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), + GMF_RX_MACSEC_FLUSH_OFF); + } /* Configure interrupt handling. */ if (sc_if->msk_port == MSK_PORT_A) { diff --git a/sys/dev/msk/if_mskreg.h b/sys/dev/msk/if_mskreg.h index 9c18ba719867..3c1bdb0ef3a9 100644 --- a/sys/dev/msk/if_mskreg.h +++ b/sys/dev/msk/if_mskreg.h @@ -621,8 +621,8 @@ #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ -#define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ -#define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ +#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ +#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ @@ -1941,6 +1941,8 @@ #define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ #define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ #define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ +#define GMF_RX_MACSEC_FLUSH_ON BIT_23 +#define GMF_RX_MACSEC_FLUSH_OFF BIT_22 #define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ #define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ #define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ |