7 files changed, 4240 insertions, 0 deletions

diff --git a/sys/dev/utopia/idtphy.c b/sys/dev/utopia/idtphy.c
new file mode 100644
index 000000000000..5aaa576abb23
--- /dev/null
+++ b/sys/dev/utopia/idtphy.c
@@ -0,0 +1,494 @@
+/*-
+ * Copyright (c) 2003
+ *	Fraunhofer Institute for Open Communication Systems (FhG Fokus).
+ * 	All rights reserved.
+ *
+ * Author: Hartmut Brandt <harti@freebsd.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/unistd.h>
+#include <sys/kernel.h>
+#include <sys/kthread.h>
+#include <sys/proc.h>
+#include <sys/bus.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/sysctl.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_var.h>
+#include <net/if_media.h>
+#include <net/if_atm.h>
+
+#include <dev/utopia/idtphy.h>
+#include <dev/utopia/utopia.h>
+#include <dev/utopia/utopia_priv.h>
+
+/*
+ * Reset IDT77105. There is really no way to reset this thing by acessing
+ * the registers. Load the registers with default values.
+ */
+static int
+idt77105_reset(struct utopia *utp)
+{
+	int err = 0;
+	u_int n;
+	uint8_t val[2];
+
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_MCR, 0xff,
+	    IDTPHY_REGM_MCR_DRIC | IDTPHY_REGM_MCR_EI);
+	n = 1;
+	err |= UTP_READREGS(utp, IDTPHY_REGO_ISTAT, val, &n);
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_DIAG, 0xff, 0);
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_LHEC, 0xff, 0);
+
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_CNTS, 0xff, IDTPHY_REGM_CNTS_SEC);
+	n = 2;
+	err |= UTP_READREGS(utp, IDTPHY_REGO_CNT, val, &n);
+
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_CNTS, 0xff, IDTPHY_REGM_CNTS_TX);
+	n = 2;
+	err |= UTP_READREGS(utp, IDTPHY_REGO_CNT, val, &n);
+
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_CNTS, 0xff, IDTPHY_REGM_CNTS_RX);
+	n = 2;
+	err |= UTP_READREGS(utp, IDTPHY_REGO_CNT, val, &n);
+
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_CNTS, 0xff, IDTPHY_REGM_CNTS_HECE);
+	n = 2;
+	err |= UTP_READREGS(utp, IDTPHY_REGO_CNT, val, &n);
+
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_MCR, IDTPHY_REGM_MCR_DREC,
+	    IDTPHY_REGM_MCR_DREC);
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_DIAG, IDTPHY_REGM_DIAG_RFLUSH,
+	    IDTPHY_REGM_DIAG_RFLUSH);
+
+	/* loopback */
+	err |= utopia_set_loopback(utp, utp->loopback);
+
+	/* update carrier state */
+	err |= utopia_update_carrier(utp);
+
+	return (err ? EIO : 0);
+}
+
+static int
+idt77105_inval(struct utopia *utp, int what __unused)
+{
+
+	return (EINVAL);
+}
+
+static int
+idt77105_update_carrier(struct utopia *utp)
+{
+	int err;
+	uint8_t reg;
+	u_int n = 1;
+
+	if ((err = UTP_READREGS(utp, IDTPHY_REGO_ISTAT, &reg, &n)) != 0) {
+		utp->carrier = UTP_CARR_UNKNOWN;
+		return (err);
+	}
+	utopia_check_carrier(utp, reg & IDTPHY_REGM_ISTAT_GOOD);
+	return (0);
+}
+
+static int
+idt77105_set_loopback(struct utopia *utp, u_int mode)
+{
+	int err;
+
+	switch (mode) {
+	  case UTP_LOOP_NONE:
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_DIAG,
+		    IDTPHY_REGM_DIAG_LOOP, IDTPHY_REGM_DIAG_LOOP_NONE);
+		break;
+
+	  case UTP_LOOP_DIAG:
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_DIAG,
+		    IDTPHY_REGM_DIAG_LOOP, IDTPHY_REGM_DIAG_LOOP_PHY);
+		break;
+
+	  case UTP_LOOP_LINE:
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_DIAG,
+		    IDTPHY_REGM_DIAG_LOOP, IDTPHY_REGM_DIAG_LOOP_LINE);
+		break;
+
+	  default:
+		return (EINVAL);
+	}
+	if (err)
+		return (err);
+	utp->loopback = mode;
+	return (0);
+}
+
+/*
+ * Handle interrupt on IDT77105 chip
+ */
+static void
+idt77105_intr(struct utopia *utp)
+{
+	uint8_t reg;
+	u_int n = 1;
+	int err;
+
+	/* Interrupt status and ack the interrupt */
+	if ((err = UTP_READREGS(utp, IDTPHY_REGO_ISTAT, &reg, &n)) != 0) {
+		printf("IDT77105 read error %d\n", err);
+		return;
+	}
+	/* check for signal condition */
+	utopia_check_carrier(utp, reg & IDTPHY_REGM_ISTAT_GOOD);
+}
+
+static void
+idt77105_update_stats(struct utopia *utp)
+{
+	int err = 0;
+	uint8_t regs[2];
+	u_int n;
+
+#ifdef DIAGNOSTIC
+#define UDIAG(F,A,B)	printf(F, A, B)
+#else
+#define	UDIAG(F,A,B)	do { } while (0)
+#endif
+
+#define	UPD(FIELD, CODE, N, MASK)					\
+	err = UTP_WRITEREG(utp, IDTPHY_REGO_CNTS, 0xff, CODE);		\
+	if (err != 0) {							\
+		UDIAG("%s: cannot write CNTS: %d\n", __func__, err);	\
+		return;							\
+	}								\
+	n = N;								\
+	err = UTP_READREGS(utp, IDTPHY_REGO_CNT, regs, &n);		\
+	if (err != 0) {							\
+		UDIAG("%s: cannot read CNT: %d\n", __func__, err);	\
+		return;							\
+	}								\
+	if (n != N) {							\
+		UDIAG("%s: got only %u registers\n", __func__, n);	\
+		return;							\
+	}								\
+	if (N == 1)							\
+		utp->stats.FIELD += (regs[0] & MASK);			\
+	else								\
+		utp->stats.FIELD += (regs[0] | (regs[1] << 8)) & MASK;
+
+	UPD(rx_symerr, IDTPHY_REGM_CNTS_SEC, 1, 0xff);
+	UPD(tx_cells, IDTPHY_REGM_CNTS_TX, 2, 0xffff);
+	UPD(rx_cells, IDTPHY_REGM_CNTS_RX, 2, 0xffff);
+	UPD(rx_uncorr, IDTPHY_REGM_CNTS_HECE, 1, 0x1f);
+
+#undef	UDIAG
+#undef	UPD
+}
+
+struct utopia_chip utopia_chip_idt77105 = {
+	UTP_TYPE_IDT77105,
+	"IDT77105",
+	7,
+	idt77105_reset,
+	idt77105_inval,
+	idt77105_inval,
+	idt77105_inval,
+	idt77105_update_carrier,
+	idt77105_set_loopback,
+	idt77105_intr,
+	idt77105_update_stats,
+};
+
+/*
+ * Update the carrier status
+ */
+static int
+idt77155_update_carrier(struct utopia *utp)
+{
+	int err;
+	uint8_t reg;
+	u_int n = 1;
+
+	if ((err = UTP_READREGS(utp, IDTPHY_REGO_RSOS, &reg, &n)) != 0) {
+		utp->carrier = UTP_CARR_UNKNOWN;
+		return (err);
+	}
+	utopia_check_carrier(utp, !(reg & IDTPHY_REGM_RSOS_LOS));
+	return (0);
+}
+
+/*
+ * Handle interrupt on IDT77155 chip
+ */
+static void
+idt77155_intr(struct utopia *utp)
+{
+	uint8_t reg;
+	u_int n = 1;
+	int err;
+
+	if ((err = UTP_READREGS(utp, IDTPHY_REGO_RSOS, &reg, &n)) != 0) {
+		printf("IDT77105 read error %d\n", err);
+		return;
+	}
+	utopia_check_carrier(utp, !(reg & IDTPHY_REGM_RSOS_LOS));
+}
+
+/*
+ * set SONET/SDH mode
+ */
+static int
+idt77155_set_sdh(struct utopia *utp, int sdh)
+{
+	int err;
+
+	if (sdh)
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_PTRM,
+		    IDTPHY_REGM_PTRM_SS, IDTPHY_REGM_PTRM_SDH);
+	else
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_PTRM,
+		    IDTPHY_REGM_PTRM_SS, IDTPHY_REGM_PTRM_SONET);
+	if (err != 0)
+		return (err);
+
+	utp->state &= ~UTP_ST_SDH;
+	if (sdh)
+		utp->state |= UTP_ST_SDH;
+
+	return (0);
+}
+
+/*
+ * set idle/unassigned cells
+ */
+static int
+idt77155_set_unass(struct utopia *utp, int unass)
+{
+	int err;
+
+	if (unass)
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_TCHP, 0xff, 0);
+	else
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_TCHP, 0xff, 1);
+	if (err != 0)
+		return (err);
+
+	utp->state &= ~UTP_ST_UNASS;
+	if (unass)
+		utp->state |= UTP_ST_UNASS;
+
+	return (0);
+}
+
+/*
+ * enable/disable scrambling
+ */
+static int
+idt77155_set_noscramb(struct utopia *utp, int noscramb)
+{
+	int err;
+
+	if (noscramb) {
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_TCC,
+		    IDTPHY_REGM_TCC_DSCR, IDTPHY_REGM_TCC_DSCR);
+		if (err)
+			return (err);
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_RCC,
+		    IDTPHY_REGM_RCC_DSCR, IDTPHY_REGM_RCC_DSCR);
+		if (err)
+			return (err);
+		utp->state |= UTP_ST_NOSCRAMB;
+	} else {
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_TCC,
+		    IDTPHY_REGM_TCC_DSCR, 0);
+		if (err)
+			return (err);
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_RCC,
+		    IDTPHY_REGM_RCC_DSCR, 0);
+		if (err)
+			return (err);
+		utp->state &= ~UTP_ST_NOSCRAMB;
+	}
+	return (0);
+}
+
+/*
+ * Set loopback mode for the 77155
+ */
+static int
+idt77155_set_loopback(struct utopia *utp, u_int mode)
+{
+	int err;
+	uint32_t val;
+	u_int nmode;
+
+	val = 0;
+	nmode = mode;
+	if (mode & UTP_LOOP_TIME) {
+		nmode &= ~UTP_LOOP_TIME;
+		val |= IDTPHY_REGM_MCTL_TLOOP;
+	}
+	if (mode & UTP_LOOP_DIAG) {
+		nmode &= ~UTP_LOOP_DIAG;
+		val |= IDTPHY_REGM_MCTL_DLOOP;
+	}
+	if (mode & UTP_LOOP_LINE) {
+		nmode &= ~UTP_LOOP_LINE;
+		val |= IDTPHY_REGM_MCTL_LLOOP;
+	}
+	if (nmode != 0)
+		return (EINVAL);
+
+	err = UTP_WRITEREG(utp, IDTPHY_REGO_MCTL, IDTPHY_REGM_MCTL_TLOOP |
+	    IDTPHY_REGM_MCTL_DLOOP | IDTPHY_REGM_MCTL_LLOOP, val);
+	if (err)
+		return (err);
+	utp->loopback = mode;
+
+	return (0);
+}
+
+/*
+ * Set the chip to reflect the current state in utopia.
+ * Assume, that the chip has been reset.
+ */
+static int
+idt77155_set_chip(struct utopia *utp)
+{
+	int err = 0;
+
+	/* set sonet/sdh */
+	err |= idt77155_set_sdh(utp, utp->state & UTP_ST_SDH);
+
+	/* unassigned or idle cells */
+	err |= idt77155_set_unass(utp, utp->state & UTP_ST_UNASS);
+
+	/* loopback */
+	err |= idt77155_set_loopback(utp, utp->loopback);
+
+	/* update carrier state */
+	err |= idt77155_update_carrier(utp);
+
+	/* enable interrupts on LOS */
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_INT,
+	    IDTPHY_REGM_INT_RXSOHI, IDTPHY_REGM_INT_RXSOHI);
+	err |= UTP_WRITEREG(utp, IDTPHY_REGO_RSOC,
+	    IDTPHY_REGM_RSOC_LOSI, IDTPHY_REGM_RSOC_LOSI);
+
+	return (err ? EIO : 0);
+}
+
+/*
+ * Reset the chip to reflect the current state of utopia.
+ */
+static int
+idt77155_reset(struct utopia *utp)
+{
+	int err = 0;
+
+	if (!(utp->flags & UTP_FL_NORESET)) {
+		err |= UTP_WRITEREG(utp, IDTPHY_REGO_MRID,
+		    IDTPHY_REGM_MRID_RESET, IDTPHY_REGM_MRID_RESET);
+		err |= UTP_WRITEREG(utp, IDTPHY_REGO_MRID,
+		    IDTPHY_REGM_MRID_RESET, 0);
+	}
+
+	err |= idt77155_set_chip(utp);
+
+	return (err ? EIO : 0);
+}
+
+/*
+ * Update statistics from a IDT77155
+ * This appears to be the same as for the Suni/Lite and Ultra. IDT however
+ * makes no assessment about the transfer time. Assume 7us.
+ */
+static void
+idt77155_update_stats(struct utopia *utp)
+{
+	int err;
+
+	/* write to the master if we can */
+	if (!(utp->flags & UTP_FL_NORESET)) {
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_MRID, 0, 0);
+	} else {
+		err = UTP_WRITEREG(utp, IDTPHY_REGO_BIPC, 0, 0);
+		err |= UTP_WRITEREG(utp, IDTPHY_REGO_B2EC, 0, 0);
+		err |= UTP_WRITEREG(utp, IDTPHY_REGO_B3EC, 0, 0);
+		err |= UTP_WRITEREG(utp, IDTPHY_REGO_CEC, 0, 0);
+		err |= UTP_WRITEREG(utp, IDTPHY_REGO_TXCNT, 0, 0);
+
+	}
+	if (err) {
+#ifdef DIAGNOSTIC
+		printf("%s: register write error %s: %d\n", __func__,
+		    utp->chip->name, err);
+#endif
+		return;
+	}
+
+	DELAY(8);
+
+	utp->stats.rx_sbip += utopia_update(utp,
+	    IDTPHY_REGO_BIPC, 2, 0xffff);
+	utp->stats.rx_lbip += utopia_update(utp,
+	    IDTPHY_REGO_B2EC, 3, 0xfffff);
+	utp->stats.rx_lfebe += utopia_update(utp,
+	    IDTPHY_REGO_FEBEC, 3, 0xfffff);
+	utp->stats.rx_pbip += utopia_update(utp,
+	    IDTPHY_REGO_B3EC, 2, 0xffff);
+	utp->stats.rx_pfebe += utopia_update(utp,
+	    IDTPHY_REGO_PFEBEC, 2, 0xffff);
+	utp->stats.rx_corr += utopia_update(utp,
+	    IDTPHY_REGO_CEC, 1, 0xff);
+	utp->stats.rx_uncorr += utopia_update(utp,
+	    IDTPHY_REGO_UEC, 1, 0xff);
+	utp->stats.rx_cells += utopia_update(utp,
+	    IDTPHY_REGO_RCCNT, 3, 0x7ffff);
+	utp->stats.tx_cells += utopia_update(utp,
+	    IDTPHY_REGO_TXCNT, 3, 0x7ffff);
+}
+
+const struct utopia_chip utopia_chip_idt77155 = {
+	UTP_TYPE_IDT77155,
+	"IDT77155",
+	0x80,
+	idt77155_reset,
+	idt77155_set_sdh,
+	idt77155_set_unass,
+	idt77155_set_noscramb,
+	idt77155_update_carrier,
+	idt77155_set_loopback,
+	idt77155_intr,
+	idt77155_update_stats,
+};
diff --git a/sys/dev/utopia/idtphy.h b/sys/dev/utopia/idtphy.h
new file mode 100644
index 000000000000..1451d0561fa3
--- /dev/null
+++ b/sys/dev/utopia/idtphy.h
@@ -0,0 +1,761 @@
+/*-
+ * Copyright (c) 2003
+ *	Fraunhofer Institute for Open Communication Systems (FhG Fokus).
+ * 	All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Author: Hartmut Brandt <harti@freebsd.org>
+ *
+ * $FreeBSD$
+ *
+ * Register definitions for the following chips:
+ *	IDT 77105
+ *	IDT 77155
+ */
+#ifndef _DEV_UTOPIA_IDTPHY_H
+#define	_DEV_UTOPIA_IDTPHY_H
+
+#define	IDTPHY_REGO_MCR		0x00
+#define	IDTPHY_REGN_MCR		"Master Control Register"
+#define	IDTPHY_REGX_MCR		"\020\010UPLO\7DREC\6ECEI\5TDPC\4DRIC\3HALTTX\2BYTEM\1EI"
+#define	IDTPHY_REGM_MCR_UPL0	0x80
+#define	IDTPHY_REGM_MCR_DREC	0x40
+#define	IDTPHY_REGM_MCR_ECEI	0x20
+#define	IDTPHY_REGM_MCR_TDPC	0x10
+#define	IDTPHY_REGM_MCR_DRIC	0x08
+#define	IDTPHY_REGM_MCR_HALTTX	0x04
+#define	IDTPHY_REGM_MCR_BYTEM	0x02
+#define	IDTPHY_REGM_MCR_EI	0x01
+
+#define	IDTPHY_REGO_ISTAT	0x01
+#define	IDTPHY_REGN_ISTAT	"Interrupt Status"
+#define	IDTPHY_REGX_ISTAT	"\020\7GOOD\6HECE\5SCRE\4TPE\3RSCC\2RSE\1RFO"
+#define	IDTPHY_REGM_ISTAT_GOOD	0x40	/* good signal bit */
+#define	IDTPHY_REGM_ISTAT_HECE	0x20	/* HEC error */
+#define	IDTPHY_REGM_ISTAT_SCRE	0x10	/* short cell received error */
+#define	IDTPHY_REGM_ISTAT_TPE	0x08	/* transmit parity error */
+#define	IDTPHY_REGM_ISTAT_RSCC	0x04	/* receive signal condition change */
+#define	IDTPHY_REGM_ISTAT_RSE	0x02	/* receive symbol error */
+#define	IDTPHY_REGM_ISTAT_RFO	0x01	/* read FIFO overrun */
+
+#define	IDTPHY_REGO_DIAG	0x02
+#define	IDTPHY_REGN_DIAG	"Diagnostic Control"
+#define	IDTPHY_REGX_DIAG	"\020\010FTD\7ROS\6MULTI\5RFLUSH\4ITPE\3IHECE\11\3\0NORM\11\3\2PLOOP\11\3\3LLOOP"
+#define	IDTPHY_REGM_DIAG_FTD	0x80	/* Force TxClav Deassert */
+#define	IDTPHY_REGM_DIAG_ROS	0x40	/* RxClav Operation Select */
+#define	IDTPHY_REGM_DIAG_MULTI	0x20	/* Multi-phy operation */
+#define	IDTPHY_REGM_DIAG_RFLUSH	0x10	/* clear receive Fifo */
+#define	IDTPHY_REGM_DIAG_ITPE	0x08	/* insert transmit payload error */
+#define	IDTPHY_REGM_DIAG_IHECE	0x04	/* insert transmit HEC error */
+#define	IDTPHY_REGM_DIAG_LOOP	0x03	/* loopback mode */
+#define	IDTPHY_REGM_DIAG_LOOP_NONE	0x00	/* normal */
+#define	IDTPHY_REGM_DIAG_LOOP_PHY	0x02	/* PHY loopback */
+#define	IDTPHY_REGM_DIAG_LOOP_LINE	0x03	/* Line loopback */
+
+#define	IDTPHY_REGO_LHEC	0x03
+#define	IDTPHY_REGN_LHEC	"LED Driver and HEC Status/Control"
+#define	IDTPHY_REGX_LHEC	"\020\7DRHEC\6DTHEC\11\x18\0CYC1\11\x18\1CYC2\11\x18\2CYC4\11\x18\3CYC8\3FIFOE\2TXLED\1RXLED"
+#define	IDTPHY_REGM_LHEC_DRHEC	0x40	/* disable receive HEC */
+#define	IDTPHY_REGM_LHEC_DTHEC	0x20	/* disable transmit HEC */
+#define	IDTPHY_REGM_LHEC_RXREF	0x18	/* RxRef pulse width */
+#define	IDTPHY_REGM_LHEC_RXREF1	0x00	/* 1 pulse */
+#define	IDTPHY_REGM_LHEC_RXREF2	0x08	/* 2 pulse */
+#define	IDTPHY_REGM_LHEC_RXREF4	0x10	/* 4 pulse */
+#define	IDTPHY_REGM_LHEC_RXREF8	0x18	/* 8 pulse */
+#define	IDTPHY_REGM_LHEC_FIFOE	0x04	/* Fifo empty */
+#define	IDTPHY_REGM_LHEC_TXLED	0x02	/* Tx LED status */
+#define	IDTPHY_REGM_LHEC_RXLED	0x01	/* Rx LED status */
+
+#define	IDTPHY_REGO_CNT		0x04	/* +0x05 */
+#define	IDTPHY_REGN_CNT		"Counter"
+
+#define	IDTPHY_REGO_CNTS	0x06
+#define	IDTPHY_REGN_CNTS	"Counter select"
+#define	IDTPHY_REGX_CNTS	"\020\4SEC\3TX\2RX\1HECE"
+#define	IDTPHY_REGM_CNTS_SEC	0x08	/* symbol error counter */
+#define	IDTPHY_REGM_CNTS_TX	0x04	/* Tx cells */
+#define	IDTPHY_REGM_CNTS_RX	0x02	/* Rx cells */
+#define	IDTPHY_REGM_CNTS_HECE	0x01	/* HEC errors */
+
+#define	IDTPHY_PRINT_77105					\
+	{ /* 00 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_MCR,		\
+	  IDTPHY_REGN_MCR,	IDTPHY_REGX_MCR },		\
+	{ /* 01 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_ISTAT,		\
+	  IDTPHY_REGN_ISTAT,	IDTPHY_REGX_ISTAT },		\
+	{ /* 02 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_DIAG,		\
+	  IDTPHY_REGN_DIAG,	IDTPHY_REGX_DIAG },		\
+	{ /* 03 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_LHEC,		\
+	  IDTPHY_REGN_LHEC,	IDTPHY_REGX_LHEC },		\
+	{ /* 04, 05 */						\
+	  UTP_REGT_INT16,	IDTPHY_REGO_CNT,		\
+	  IDTPHY_REGN_CNT,	NULL },				\
+	{ /* 06 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_CNTS,		\
+	  IDTPHY_REGN_CNTS,	IDTPHY_REGX_CNTS }
+
+#define	IDTPHY_REGO_MRID	0x00
+#define	IDTPHY_REGN_MRID	"Master Reset & ID"
+#define	IDTPHY_REGM_MRID_RESET	0x80	/* software reset */
+#define	IDTPHY_REGM_MRID_TYPE	0x70	/* type */
+#define	IDTPHY_REGM_MRID_155	0x30	/* idt77155 type */
+#define	IDTPHY_REGM_MRID_ID	0x0f	/* revision */
+#define	IDTPHY_REGX_MRID	\
+	    "\020\010mstReset\12\x70\12type\12\xf\12id"
+
+#define	IDTPHY_REGO_CONF	0x01
+#define	IDTPHY_REGN_CONF	"Configuration"
+#define	IDTPHY_REGM_CONF_AFEBE	0x40	/* autoFEBE */
+#define	IDTPHY_REGM_CONF_ALRDI	0x20	/* autoLRDI */
+#define	IDTPHY_REGM_CONF_APRDI	0x10	/* autoPRDI */
+#define	IDTPHY_REGM_CONF_TCAIN	0x08	/* TCAInv */
+#define	IDTPHY_REGM_CONF_RCAIN	0x04	/* RCAInv */
+#define	IDTPHY_REGM_CONF_RXDIN	0x02	/* RXDInv */
+#define	IDTPHY_REGM_CONF_RESV	0x81
+#define	IDTPHY_REGX_CONF	\
+	    "\020\07autoFEBE\6autoLRDI\5autoPRDI\4TCAInv\3RCAInv\2RXDInv"
+
+#define	IDTPHY_REGO_INT		0x02
+#define	IDTPHY_REGN_INT		"Interrupt"
+#define	IDTPHY_REGM_INT_TXOOLI	0x80	/* txOOLInt */
+#define	IDTPHY_REGM_INT_RXLOCI	0x40	/* rxLOCInt */
+#define	IDTPHY_REGM_INT_RXOOLI	0x20	/* rxOOLInt */
+#define	IDTPHY_REGM_INT_TXCDI	0x10	/* txCDi */
+#define	IDTPHY_REGM_INT_RXCDI	0x08	/* rxCDi */
+#define	IDTPHY_REGM_INT_RXPOHI	0x04	/* rxPOHi */
+#define	IDTPHY_REGM_INT_RXLOHI	0x02	/* rxLOHi */
+#define	IDTPHY_REGM_INT_RXSOHI	0x01	/* rxSOHi */
+#define	IDTPHY_REGX_INT		\
+	    "\020\10txOOLInt\7rxLOCInt\6rxOOLInt\5txCDi\4rxCDi\3rxPOHi" \
+	    "\2rxLOHi\1rxSOHi"
+
+#define	IDTPHY_REGO_MCM		0x04
+#define	IDTPHY_REGN_MCM		"Master Clock Monitor"
+#define	IDTPHY_REGM_MCM_RRCLK	0x08	/* rrclkReg */
+#define	IDTPHY_REGM_MCM_TRCLK	0x04	/* trclkReg */
+#define	IDTPHY_REGM_MCM_RCLK	0x02	/* rclkReg */
+#define	IDTPHY_REGM_MCM_TCLK	0x01	/* tclkReg */
+#define	IDTPHY_REGM_MCM_RESV	0xf0
+#define	IDTPHY_REGX_MCM		\
+	    "\020\4rrclkReg\3trclkReg\2rclkReg\1tclkReg"
+
+#define	IDTPHY_REGO_MCTL	0x05
+#define	IDTPHY_REGN_MCTL	"Master Control"
+#define	IDTPHY_REGM_MCTL_LOCI	0x80	/* rxLOCIEn */
+#define	IDTPHY_REGM_MCTL_LOC	0x40	/* LOC */
+#define	IDTPHY_REGM_MCTL_FIXP	0x20	/* txFixptr */
+#define	IDTPHY_REGM_MCTL_LLOOP	0x04	/* txLLoop */
+#define	IDTPHY_REGM_MCTL_DLOOP	0x02	/* rxDLoop */
+#define	IDTPHY_REGM_MCTL_TLOOP	0x01	/* rxLoopT */
+#define	IDTPHY_REGM_MCTL_RESV	0x18
+#define	IDTPHY_REGX_MCTL	\
+	    "\020\10rxLOCIEn\7LOC\6txFixptr\3txLLoop\2rxDLoop\1rxLoopT"
+
+#define	IDTPHY_REGO_TXC		0x06
+#define	IDTPHY_REGN_TXC		"Transmit Clock Synthesis C/S"
+#define	IDTPHY_REGM_TXC_TXOOL	0x08	/* txOOL */
+#define	IDTPHY_REGM_TXC_TXOOLI	0x02	/* txOOLIEn */
+#define	IDTPHY_REGM_TXC_TXREF	0x01	/* txrefSel */
+#define	IDTPHY_REGM_TXC_RESV	0xf4
+#define	IDTPHY_REGX_TXC		\
+	    "\020\4txOOL\2txOOLIEn\1txrefSel"
+
+#define	IDTPHY_REGO_RXC		0x07
+#define	IDTPHY_REGN_RXC		"Receive Clock/Data Recovery C/S"
+#define	IDTPHY_REGM_RXC_RXOOL	0x08	/* rxOOL */
+#define	IDTPHY_REGM_RXC_RXOOLI	0x02	/* rxOOLIEn */
+#define	IDTPHY_REGM_RXC_RXREF	0x01	/* rxrefSel */
+#define	IDTPHY_REGM_RXC_RESV	0xf4
+#define	IDTPHY_REGX_RXC		\
+	    "\020\4rxOOL\2rxOOLIEn\1rxrefSel"
+
+#define	IDTPHY_REGO_RSOC	0x10
+#define	IDTPHY_REGN_RSOC	"Receive Overhead Control"
+#define	IDTPHY_REGM_RSOC_DSCR	0x40	/* scrDis */
+#define	IDTPHY_REGM_RSOC_FOOF	0x20	/* frcOOF */
+#define	IDTPHY_REGM_RSOC_B1IE	0x08	/* B1ErrIEn */
+#define	IDTPHY_REGM_RSOC_LOSI	0x04	/* LOSIEn */
+#define	IDTPHY_REGM_RSOC_LOFI	0x02	/* LOFIEn */
+#define	IDTPHY_REGM_RSOC_OOFI	0x01	/* OOFIEn */
+#define	IDTPHY_REGM_RSOC_RESV	0x90
+#define	IDTPHY_REGX_RSOC	\
+	    "\020\7scrDis\6frcOOF\4B1ErrIEn\3LOSIEn\2LOFIEn\1OOFIEn"
+
+#define	IDTPHY_REGO_RSOS	0x11
+#define	IDTPHY_REGN_RSOS	"Receive Overhead Status"
+#define	IDTPHY_REGM_RSOS_C1INT	0x80	/* C1Int */
+#define	IDTPHY_REGM_RSOS_B1INT	0x40	/* B1ErrInt */
+#define	IDTPHY_REGM_RSOS_LOSI	0x20	/* LOSInt */
+#define	IDTPHY_REGM_RSOS_LOFI	0x10	/* LOFInt */
+#define	IDTPHY_REGM_RSOS_OOFI	0x08	/* OOFInt */
+#define	IDTPHY_REGM_RSOS_LOS	0x04	/* LOS */
+#define	IDTPHY_REGM_RSOS_LOF	0x02	/* LOF */
+#define	IDTPHY_REGM_RSOS_OOF	0x01	/* OOF */
+#define	IDTPHY_REGX_RSOS	\
+	    "\020\10C1Int\7B1ErrInt\6LOSInt\5LOFInt\4OOFint\3LOS\2LOF\1OOF"
+
+#define	IDTPHY_REGO_BIPC	0x12	/* + 0x13 LE */
+#define	IDTPHY_REGN_BIPC	"Receive Section BIP Errors"
+
+#define	IDTPHY_REGO_TSOC	0x14
+#define	IDTPHY_REGN_TSOC	"Transmit Overhead Control"
+#define	IDTPHY_REGM_TSOC_DSCR	0x40	/* scrDis */
+#define	IDTPHY_REGM_TSOC_LAISI	0x01	/* LAISIns */
+#define	IDTPHY_REGM_TSOC_RESV	0xbe
+#define	IDTPHY_REGX_TSOC	\
+	    "\020\7scrDis\1LAISIns"
+
+#define	IDTPHY_REGO_TSOC2	0x15
+#define	IDTPHY_REGN_TSOC2	"Transmit Overhead Control 2"
+#define	IDTPHY_REGM_TSOC2_LOSI	0x04	/* LOSIns */
+#define	IDTPHY_REGM_TSOC2_B1INV	0x02	/* B1Inv */
+#define	IDTPHY_REGM_TSOC2_IFE	0x01	/* frErrIns */
+#define	IDTPHY_REGM_TSOC2_RESV	0xf8
+#define	IDTPHY_REGX_TSOC2	\
+	    "\020\3LOSIns\2B1Inv\1frErrIns"
+
+#define	IDTPHY_REGO_RLOS	0x18
+#define	IDTPHY_REGN_RLOS	"Receive Line Overhead Status"
+#define	IDTPHY_REGM_RLOS_B2W	0x80	/* B2Word */
+#define	IDTPHY_REGM_RLOS_LAIS	0x02	/* LAIS */
+#define	IDTPHY_REGM_RLOS_LRDI	0x01	/* LRDI */
+#define	IDTPHY_REGM_RLOS_RESV	0x7c
+#define	IDTPHY_REGX_RLOS	\
+	    "\020\10B2Word\2LAIS\1LRDI"
+
+#define	IDTPHY_REGO_RLOI	0x19
+#define	IDTPHY_REGN_RLOI	"Receive Line Overhead Interrupt"
+#define	IDTPHY_REGM_RLOI_LFEBEE	0x80	/* LFEBEIEn */
+#define	IDTPHY_REGM_RLOI_B2EE	0x40	/* B2ErrIEn */
+#define	IDTPHY_REGM_RLOI_LAISE	0x20	/* LAISIEn */
+#define	IDTPHY_REGM_RLOI_LRDIE	0x10	/* LRDIIEn */
+#define	IDTPHY_REGM_RLOI_LFEBEI	0x08	/* LFEBEInt */
+#define	IDTPHY_REGM_RLOI_B2EI	0x04	/* B2ErrInt */
+#define	IDTPHY_REGM_RLOI_LAISI	0x02	/* LAISInt */
+#define	IDTPHY_REGM_RLOI_LRDII	0x01	/* LRDIInt */
+#define	IDTPHY_REGX_RLOI	\
+	    "\020\10LFEBEIEn\7B2ErrIEn\6LAISIEn\5LRDIIEn\4LFEBEInt\3B2ErrInt" \
+	    "\2LAISInt\1LRDIInt"
+
+#define	IDTPHY_REGO_B2EC	0x1a	/* + 0x1b, 0x1c, 20bit LE */
+#define	IDTPHY_REGN_B2EC	"B2 Errors"
+
+#define	IDTPHY_REGO_FEBEC	0x1d	/* + 0x1e, 0x1f, 20bit LE */
+#define	IDTPHY_REGN_FEBEC	"Line FEBE Errors"
+
+#define	IDTPHY_REGO_TLOS	0x20
+#define	IDTPHY_REGN_TLOS	"Transmit Line Overhead Status"
+#define	IDTPHY_REGM_TLOS_LRDI	0x01	/* LRDI */
+#define	IDTPHY_REGM_TLOS_RESV	0xfe
+#define	IDTPHY_REGX_TLOS	\
+	    "\020\1LRDI"
+
+#define	IDTPHY_REGO_TLOC	0x21
+#define	IDTPHY_REGN_TLOC	"Transmit Line Overhead Control"
+#define	IDTPHY_REGM_TLOC_B2INV	0x01	/* B2Inv */
+#define	IDTPHY_REGM_TLOC_RESV	0xfe
+#define	IDTPHY_REGX_TLOC	\
+	    "\020\1B2Inv"
+
+#define	IDTPHY_REGO_TK1		0x24
+#define	IDTPHY_REGN_TK1		"Transmit K1"
+
+#define	IDTPHY_REGO_TK2		0x25
+#define	IDTPHY_REGN_TK2		"Transmit K2"
+
+#define	IDTPHY_REGO_RK1		0x26
+#define	IDTPHY_REGN_RK1		"Receive K1"
+
+#define	IDTPHY_REGO_RK2		0x27
+#define	IDTPHY_REGN_RK2		"Receive K2"
+
+#define	IDTPHY_REGO_RPOS	0x30
+#define	IDTPHY_REGN_RPOS	"Receive Path Overhead Status"
+#define	IDTPHY_REGM_RPOS_LOP	0x20	/* LOP */
+#define	IDTPHY_REGM_RPOS_PAIS	0x08	/* PAIS */
+#define	IDTPHY_REGM_RPOS_PRDI	0x04	/* PRDI */
+#define	IDTPHY_REGM_RPOS_RESV	0xd3
+#define	IDTPHY_REGX_RPOS	\
+	    "\020\6LOP\4PAIS\3PRDI"
+
+#define	IDTPHY_REGO_RPOI	0x31
+#define	IDTPHY_REGN_RPOI	"Receive Path Overhead Interrupt"
+#define	IDTPHY_REGM_RPOI_C2I	0x80	/* C2Int */
+#define	IDTPHY_REGM_RPOI_LOPI	0x20	/* LOPInt */
+#define	IDTPHY_REGM_RPOI_PAISI	0x08	/* PAISInt */
+#define	IDTPHY_REGM_RPOI_PRDII	0x04	/* PRDIInt */
+#define	IDTPHY_REGM_RPOI_B3EI	0x02	/* B3ErrInt */
+#define	IDTPHY_REGM_RPOI_PFEBEI	0x01	/* PFEBEInt */
+#define	IDTPHY_REGM_RPOI_RESV	0x50
+#define	IDTPHY_REGX_RPOI	\
+	    "\020\10C2Int\6LOPInt\4PAISInt\3PRDIInt\2B3ErrInt\1PFEBEInt"
+
+#define	IDTPHY_REGO_RPIE	0x33
+#define	IDTPHY_REGN_RPIE	"Receive Path Interrupt Enable"
+#define	IDTPHY_REGM_RPIE_C2E	0x80	/* C2IEn */
+#define	IDTPHY_REGM_RPIE_LOPE	0x20	/* LOPIEn */
+#define	IDTPHY_REGM_RPIE_PAISE	0x08	/* PAISIEn */
+#define	IDTPHY_REGM_RPIE_PRDIE	0x04	/* PRDIIEn */
+#define	IDTPHY_REGM_RPIE_B3EE	0x02	/* B3ErrIEn */
+#define	IDTPHY_REGM_RPIE_PFEBEE	0x01	/* PFEBEIEn */
+#define	IDTPHY_REGM_RPIE_RESV	0x50
+#define	IDTPHY_REGX_RPIE	\
+	    "\020\10CSIEn\6LOPIEn\4PAISIEn\3PRDIIEn\2B3ErrIEn\1PFEBEIEn"
+
+#define	IDTPHY_REGO_RC2		0x37
+#define	IDTPHY_REGN_RC2		"Receive C2"
+
+#define	IDTPHY_REGO_B3EC	0x38	/* + 0x39, LE, 16bit */
+#define	IDTPHY_REGN_B3EC	"B3 Errors"
+
+#define	IDTPHY_REGO_PFEBEC	0x3a	/* + 0x3b, LE, 16bit */
+#define	IDTPHY_REGN_PFEBEC	"Path FEBE Errors"
+
+#define	IDTPHY_REGO_RPEC	0x3d
+#define	IDTPHY_REGN_RPEC	"Receive Path BIP Error Control"
+#define	IDTPHY_REGM_RPEC_B3C	0x20	/* blkBIP */
+#define	IDTPHY_REGM_RPEC_RESV	0xdf
+#define	IDTPHY_REGX_RPEC	\
+	    "\020\6blkBIP"
+
+#define	IDTPHY_REGO_TPOC	0x40
+#define	IDTPHY_REGN_TPOC	"Transmit Path Control"
+#define	IDTPHY_REGM_TPOC_B3INV	0x02	/* B3Inv */
+#define	IDTPHY_REGM_TPOC_PAISI	0x01	/* PAISIns */
+#define	IDTPHY_REGM_TPOC_RESC	0xfc
+#define	IDTPHY_REGX_TPOC	\
+	   "\020\2B3Inv\1PAISIns"
+
+#define	IDTPHY_REGO_TPTC	0x41
+#define	IDTPHY_REGN_TPTC	"Transmit Pointer Control"
+#define	IDTPHY_REGM_TPTC_FPTR	0x40	/* frcPtr */
+#define	IDTPHY_REGM_TPTC_STUFF	0x20	/* stuffCtl */
+#define	IDTPHY_REGM_TPTC_PTR	0x10	/* Ptr */
+#define	IDTPHY_REGM_TPTC_NDF	0x08	/* NDF */
+#define	IDTPHY_REGM_TPTC_DECP	0x04	/* decPtr */
+#define	IDTPHY_REGM_TPTC_INCP	0x02	/* incPtr */
+#define	IDTPHY_REGM_TPTC_RESV	0x81
+#define	IDTPHY_REGX_TPTC	\
+	    "\020\7frcPtr\6stuffCtl\5Ptr\4NDF\3decPtr\2incPtr"
+
+#define	IDTPHY_REGO_PTRL	0x45
+#define	IDTPHY_REGN_PTRL	"Transmit Pointer LSB"
+#define	IDTPHY_REGX_PTRL	\
+	    "\020\12\xff\20arbPtr"
+
+#define	IDTPHY_REGO_PTRM	0x46
+#define	IDTPHY_REGN_PTRM	"Transmit Pointer MSB"
+#define	IDTPHY_REGM_PTRM_NDF	0xf0	/* NDFVal */
+#define	IDTPHY_REGS_PTRM_NDF	4
+#define	IDTPHY_REGM_PTRM_SS	0x0c	/* ssBit */
+#define	IDTPHY_REGM_PTRM_SONET	0x00
+#define	IDTPHY_REGM_PTRM_SDH	0x08
+#define	IDTPHY_REGM_PTRM_PTR	0x03
+#define	IDTPHY_REGX_PTRM	\
+	    "\020\12\xf0\20NDFVal\12\xc\20ssBit\12\x3\20arbPtr"
+
+#define	IDTPHY_REGO_TC2		0x48
+#define	IDTPHY_REGN_TC2		"Transmit C2"
+
+#define	IDTPHY_REGO_TPOC2	0x49
+#define	IDTPHY_REGN_TPOC2	"Transmit Path Control 2"
+#define	IDTPHY_REGM_TPOC2_FEBE	0xf0	/* PFEBEIns */
+#define	IDTPHY_REGS_TPOC2_FEBE	4
+#define	IDTPHY_REGM_TPOC2_PRDII	0x08	/* PRDIIns */
+#define	IDTPHY_REGM_TPOC2_G1	0x07	/* G1Ins */
+#define	IDTPHY_REGX_TPOC2	\
+	    "\020\12\xf0\20PFEBEIns\4PRDIIns\12\x7\20G1Ins"
+
+#define	IDTPHY_REGO_RCC		0x50
+#define	IDTPHY_REGN_RCC		"Receive Cell Control"
+#define	IDTPHY_REGM_RCC_OCD	0x80	/* OCD */
+#define	IDTPHY_REGM_RCC_PARTY	0x40	/* parity */
+#define	IDTPHY_REGM_RCC_PASS	0x20	/* pass */
+#define	IDTPHY_REGM_RCC_DCOR	0x10	/* corDis */
+#define	IDTPHY_REGM_RCC_DHEC	0x08	/* HECdis */
+#define	IDTPHY_REGM_RCC_ADD	0x04	/* csetAdd */
+#define	IDTPHY_REGM_RCC_DSCR	0x02	/* scrDis */
+#define	IDTPHY_REGM_RCC_RFIFO	0x01	/* rxFIFOrst */
+#define	IDTPHY_REGX_RCC		\
+	    "\020\10OCD\7parity\6pass\5corDis\4HECdis\3csetAdd" \
+	    "\2scrDis\1rxFIFOrst"
+
+#define	IDTPHY_REGO_RCI		0x51
+#define	IDTPHY_REGN_RCI		"Receive Cell Interrupt"
+#define	IDTPHY_REGM_RCI_OCDE	0x80	/* OCDIEn */
+#define	IDTPHY_REGM_RCI_HECE	0x40	/* HECIEn */
+#define	IDTPHY_REGM_RCI_OVFE	0x20	/* ovfIEn */
+#define	IDTPHY_REGM_RCI_OCDI	0x10	/* OCDInt */
+#define	IDTPHY_REGM_RCI_CORI	0x08	/* corInt */
+#define	IDTPHY_REGM_RCI_UCORI	0x04	/* uncorInt */
+#define	IDTPHY_REGM_RCI_OVFI	0x02	/* ovfInt */
+#define	IDTPHY_REGM_RCI_RESV	0x01
+#define	IDTPHY_REGX_RCI		\
+	    "\020\10OCDIEn\7HECIEn\6ovfIEn\5OCDInt\4corInt\3uncorInt\2ovfInt"
+
+#define	IDTPHY_REGO_CMH		0x52
+#define	IDTPHY_REGN_CMH		"Receive Cell Match Header"
+#define	IDTPHY_REGM_CMH_GFC	0xf0	/* GFC */
+#define	IDTPHY_REGS_CMH_GFC	4
+#define	IDTPHY_REGM_CMH_PTI	0x0e	/* PTI */
+#define	IDTPHY_REGS_CMH_PTI	1
+#define	IDTPHY_REGM_CMH_CLP	0x01	/* CLP */
+#define	IDTPHY_REGX_CMH		\
+	    "\020\12\xf0\20GFC\12\xe\20PTI\12\x1\20CLP"
+
+#define	IDTPHY_REGO_CMHM	0x53
+#define	IDTPHY_REGN_CMHM	"Receive Cell Match Header Mask"
+#define	IDTPHY_REGM_CMHM_GFC	0xf0	/* mskGFC */
+#define	IDTPHY_REGS_CMHM_GFC	4
+#define	IDTPHY_REGM_CMHM_PTI	0x0e	/* mskPTI */
+#define	IDTPHY_REGS_CMHM_PTI	1
+#define	IDTPHY_REGM_CMHM_CLP	0x01	/* mskCLP */
+#define	IDTPHY_REGX_CMHM	\
+	    "\020\12\xf0\20mskGFC\12\xe\20mskPTI\12\x1\20mskCLP"
+
+#define	IDTPHY_REGO_CEC		0x54
+#define	IDTPHY_REGN_CEC		"Correctable Errors"
+
+#define	IDTPHY_REGO_UEC		0x55
+#define	IDTPHY_REGN_UEC		"Uncorrectable Errors"
+
+#define	IDTPHY_REGO_RCCNT	0x56	/* +0x57, 0x58, LE, 19bit */
+#define	IDTPHY_REGN_RCCNT	"Receive Cells"
+
+#define	IDTPHY_REGO_RCCF	0x59
+#define	IDTPHY_REGN_RCCF	"Receive Cell Configuration"
+#define	IDTPHY_REGM_RCCF_GFCE	0xf0	/* GFCen */
+#define	IDTPHY_REGS_RCCF_GFCE	4
+#define	IDTPHY_REGM_RCCF_FIXS	0x08	/* FixSen */
+#define	IDTPHY_REGM_RCCF_RCAL	0x04	/* RCAlevel */
+#define	IDTPHY_REGM_RCCF_HECF	0x03	/* HECftr */
+#define	IDTPHY_REGX_RCCF	\
+	    "\020\12\xf0\20GFCen\4FixSen\3RCAlevel\12\x3\20HECftr"
+
+#define	IDTPHY_REGO_RXID	0x5a
+#define	IDTPHY_REGN_RXID	"Receive ID Address"
+#define	IDTPHY_REGM_RXID_ID	0x03	/* IDAddr */
+#define	IDTPHY_REGM_RXID_RESV	0xfc
+#define	IDTPHY_REGX_RXID	\
+	    "\020\12\x3\20IDAddr"
+
+#define	IDTPHY_REGO_TCC		0x60
+#define	IDTPHY_REGN_TCC		"Transmit Cell Control"
+#define	IDTPHY_REGM_TCC_FIFOE	0x80	/* fovrIEn */
+#define	IDTPHY_REGM_TCC_SOCI	0x40	/* socInt */
+#define	IDTPHY_REGM_TCC_FIFOI	0x20	/* fovrInt */
+#define	IDTPHY_REGM_TCC_HECINV	0x10	/* HECInv */
+#define	IDTPHY_REGM_TCC_HECDIS	0x08	/* HECDis */
+#define	IDTPHY_REGM_TCC_ADD	0x04	/* csetAdd */
+#define	IDTPHY_REGM_TCC_DSCR	0x02	/* scrDis */
+#define	IDTPHY_REGM_TCC_FIFOR	0x01	/* txFIFOrst */
+#define	IDTPHY_REGX_TCC		\
+	    "\020\10fovrIEn\7socInt\6fovrInt\5HECInv\4HECDis\3csetAdd" \
+	    "\2scrDis\1txFIFOrst"
+
+#define	IDTPHY_REGO_TCHP	0x61
+#define	IDTPHY_REGN_TCHP	"Transmit Idle Cell Header"
+#define	IDTPHY_REGM_TCHP_GFC	0xf0	/* GFCtx */
+#define	IDTPHY_REGS_TCHP_GFC	4
+#define	IDTPHY_REGM_TCHP_PTI	0x0e	/* PTItx */
+#define	IDTPHY_REGS_TCHP_PTI	1
+#define	IDTPHY_REGM_TCHP_CLP	0x01	/* CLPtx */
+#define	IDTPHY_REGX_TCHP	\
+	    "\020\12\xf0\20GFCtx\12\xe\20PTItx\12\x1\20CLPtx"
+
+#define	IDTPHY_REGO_TPLD	0x62
+#define	IDTPHY_REGN_TPLD	"Transmit Idle Cell Payload"
+
+#define	IDTPHY_REGO_TCC2	0x63
+#define	IDTPHY_REGN_TCC2	"Transmit Cell Configuration 2"
+#define	IDTPHY_REGM_TCC2_PARITY	0x80	/* parity */
+#define	IDTPHY_REGM_TCC2_PARE	0x40	/* parIEn */
+#define	IDTPHY_REGM_TCC2_PARI	0x10	/* parInt */
+#define	IDTPHY_REGM_TCC2_FIFO	0x0c	/* FIFOdpth */
+#define	IDTPHY_REGS_TCC2_FIFO	2
+#define	IDTPHY_REGM_TCC2_TCAL	0x02	/* TCAlevel */
+#define	IDTPHY_REGM_TCC2_RESV	0x01
+#define	IDTPHY_REGX_TCC2	\
+	    "\020\10parity\7parIEn\5parInt\12\xc\20FIFOdpth\2TCAlevel"
+
+#define	IDTPHY_REGO_TXCNT	0x64	/* +65,66 LE 19bit */
+#define	IDTPHY_REGN_TXCNT	"Transmit Cells"
+
+#define	IDTPHY_REGO_TCC3	0x67
+#define	IDTPHY_REGN_TCC3	"Transmit Cell Configuration 3"
+#define	IDTPHY_REGM_TCC3_GFCE	0xf0	/* txGFCen */
+#define	IDTPHY_REGS_TCC3_GFCE	4
+#define	IDTPHY_REGM_TCC3_FIXE	0x08	/* txFixSen */
+#define	IDTPHY_REGM_TCC3_H4ID	0x04	/* H4InsDis */
+#define	IDTPHY_REGM_TCC3_FIXB	0x03	/* fixByte */
+#define	IDTPHY_REGM_TCC3_FIX00	0x00	/* 0x00 */
+#define	IDTPHY_REGM_TCC3_FIX55	0x01	/* 0x55 */
+#define	IDTPHY_REGM_TCC3_FIXAA	0x02	/* 0xAA */
+#define	IDTPHY_REGM_TCC3_FIXFF	0x03	/* 0xFF */
+#define	IDTPHY_REGX_TCC3	\
+	    "\020\12\xf0\20txGFCen\4txFixSen\3H4InsDis" \
+	    "\11\x3\x0FIX00\11\x3\x1FIX55\11\x3\x2FIXAA\11\x3\x3FIXFF"
+
+#define	IDTPHY_REGO_TXID	0x68
+#define	IDTPHY_REGN_TXID	"Transmit ID Address"
+#define	IDTPHY_REGM_TXID_ID	0x03	/* txIDAddr */
+#define	IDTPHY_REGM_TXID_RESV	0xfc
+#define	IDTPHY_REGX_TXID	\
+	    "\020\12\x3\20txIDAddr"
+
+#define	IDTPHY_REGO_RBER	0x70
+#define	IDTPHY_REGN_RBER	"Receive BER S/C"
+#define	IDTPHY_REGM_RBER_FAILE	0x08	/* FailIEn */
+#define	IDTPHY_REGM_RBER_WARNE	0x04	/* WarnIEn */
+#define	IDTPHY_REGM_RBER_FAIL	0x02	/* BERfail */
+#define	IDTPHY_REGM_RBER_WARN	0x01	/* BERwarn */
+#define	IDTPHY_REGM_RBER_RESV	0xf0
+#define	IDTPHY_REGX_RBER	\
+	    "\020\4FailIEn\3WarnIEn\2BERfail\1BERwarn"
+
+#define	IDTPHY_REGO_BFTH	0x71
+#define	IDTPHY_REGN_BFTH	"Receive BER Fail Threshold"
+
+#define	IDTPHY_REGO_BFWIN	0x72
+#define	IDTPHY_REGN_BFWIN	"Receive BER Fail Window"
+
+#define	IDTPHY_REGO_BFDEN	0x73	/* +74, 16bit LE */
+#define	IDTPHY_REGN_BFDEN	"Receive BER Fail Denominator"
+
+#define	IDTPHY_REGO_BWTH	0x75
+#define	IDTPHY_REGN_BWTH	"Receive BER Warn Threshold"
+
+#define	IDTPHY_REGO_BWWIN	0x76
+#define	IDTPHY_REGN_BWWIN	"Receive BER Warn Window"
+
+#define	IDTPHY_REGO_BWDEN	0x77	/* +78, 16bit LE */
+#define	IDTPHY_REGN_BWDEN	"Receive BER Warn Denomiator"
+
+#define	IDTPHY_REGO_OPEC	0x7f
+#define	IDTPHY_REGN_OPEC	"Output PECL Control"
+#define	IDTPHY_REGM_OPEC_TXC	0x04	/* pcctl_tc */
+#define	IDTPHY_REGM_OPEC_TXD	0x02	/* pcctl_td */
+#define	IDTPHY_REGM_OPEC_RXDO	0x01	/* pcctl_r */
+#define	IDTPHY_REGM_OPEC_RESV	0xf8
+#define	IDTPHY_REGX_OPEC	\
+	    "\020\3pctl_tc\2pcctl_td\1pcctl_r"
+
+#define	IDTPHY_PRINT_77155					\
+	{ /* 00 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_MRID,		\
+	  IDTPHY_REGN_MRID,	IDTPHY_REGX_MRID },		\
+	{ /* 01 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_CONF,		\
+	  IDTPHY_REGN_CONF,	IDTPHY_REGX_CONF },		\
+	{ /* 02 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_INT,		\
+	  IDTPHY_REGN_INT,	IDTPHY_REGX_INT },		\
+	  /* 03 unused */					\
+	{ /* 04 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_MCM,		\
+	  IDTPHY_REGN_MCM,	IDTPHY_REGX_MCM },		\
+	{ /* 05 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_MCTL,		\
+	  IDTPHY_REGN_MCTL,	IDTPHY_REGX_MCTL },		\
+	{ /* 06 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TXC,		\
+	  IDTPHY_REGN_TXC,	IDTPHY_REGX_TXC },		\
+	{ /* 07 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RXC,		\
+	  IDTPHY_REGN_RXC,	IDTPHY_REGX_RXC },		\
+	  /* 08-0f unused */					\
+	{ /* 10 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RSOC,		\
+	  IDTPHY_REGN_RSOC,	IDTPHY_REGX_RSOC },		\
+	{ /* 11 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RSOS,		\
+	  IDTPHY_REGN_RSOS,	IDTPHY_REGX_RSOS },		\
+	{ /* 12, 13 */						\
+	  UTP_REGT_INT16,	IDTPHY_REGO_BIPC,		\
+	  IDTPHY_REGN_BIPC,	NULL },				\
+	{ /* 14 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TSOC,		\
+	  IDTPHY_REGN_TSOC,	IDTPHY_REGX_TSOC },		\
+	{ /* 15 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TSOC2,		\
+	  IDTPHY_REGN_TSOC2,	IDTPHY_REGX_TSOC2 },		\
+	  /* 16, 17 unused */					\
+	{ /* 18 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RLOS,		\
+	  IDTPHY_REGN_RLOS,	IDTPHY_REGX_RLOS },		\
+	{ /* 19 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RLOI,		\
+	  IDTPHY_REGN_RLOI,	IDTPHY_REGX_RLOI },		\
+	{ /* 1a-1c */						\
+	  UTP_REGT_INT20,	IDTPHY_REGO_B2EC,		\
+	  IDTPHY_REGN_B2EC,	NULL },				\
+	{ /* 1d-1f */						\
+	  UTP_REGT_INT20,	IDTPHY_REGO_FEBEC,		\
+	  IDTPHY_REGN_FEBEC,	NULL },				\
+	{ /* 20 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TLOS,		\
+	  IDTPHY_REGN_TLOS,	IDTPHY_REGX_TLOS },		\
+	{ /* 21 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TLOC,		\
+	  IDTPHY_REGN_TLOC,	IDTPHY_REGX_TLOC },		\
+	  /* 22, 23 unused */					\
+	{ /* 24 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_TK1,		\
+	  IDTPHY_REGN_TK1,	NULL },				\
+	{ /* 25 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_TK2,		\
+	  IDTPHY_REGN_TK2,	NULL },				\
+	{ /* 26 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_RK1,		\
+	  IDTPHY_REGN_RK1,	NULL },				\
+	{ /* 27 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_RK2,		\
+	  IDTPHY_REGN_RK2,	NULL },				\
+	  /* 28-2f unused */					\
+	{ /* 30 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RPOS,		\
+	  IDTPHY_REGN_RPOS,	IDTPHY_REGX_RPOS },		\
+	{ /* 31 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RPOI,		\
+	  IDTPHY_REGN_RPOI,	IDTPHY_REGX_RPOI },		\
+	  /* 32 unused */					\
+	{ /* 33 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RPIE,		\
+	  IDTPHY_REGN_RPIE,	IDTPHY_REGX_RPIE },		\
+	  /* 34-36 unused */					\
+	{ /* 37 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_RC2,		\
+	  IDTPHY_REGN_RC2,	NULL },				\
+	{ /* 38-39 */						\
+	  UTP_REGT_INT16,	IDTPHY_REGO_B3EC,		\
+	  IDTPHY_REGN_B3EC,	NULL },				\
+	{ /* 3a-3b */						\
+	  UTP_REGT_INT16,	IDTPHY_REGO_PFEBEC,		\
+	  IDTPHY_REGN_PFEBEC,	NULL },				\
+	  /* 3c unused */					\
+	{ /* 3d */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RPEC,		\
+	  IDTPHY_REGN_RPEC,	IDTPHY_REGX_RPEC },		\
+	  /* 3e, 3f unused */					\
+	{ /* 40 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TPOC,		\
+	  IDTPHY_REGN_TPOC,	IDTPHY_REGX_TPOC },		\
+	{ /* 41 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TPTC,		\
+	  IDTPHY_REGN_TPTC,	IDTPHY_REGX_TPTC },		\
+	  /* 42-44 unused */					\
+	{ /* 45 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_PTRL,		\
+	  IDTPHY_REGN_PTRL,	IDTPHY_REGX_PTRL },		\
+	{ /* 46 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_PTRM,		\
+	  IDTPHY_REGN_PTRM,	IDTPHY_REGX_PTRM },		\
+	  /* 47 unused */					\
+	{ /* 48 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_TC2,		\
+	  IDTPHY_REGN_TC2,	NULL },				\
+	{ /* 49 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TPOC2,		\
+	  IDTPHY_REGN_TPOC2,	IDTPHY_REGX_TPOC2 },		\
+	  /* 4a-4f unused */					\
+	{ /* 50 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RCC,		\
+	  IDTPHY_REGN_RCC,	IDTPHY_REGX_RCC },		\
+	{ /* 51 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RCI,		\
+	  IDTPHY_REGN_RCI,	IDTPHY_REGX_RCI },		\
+	{ /* 52 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_CMH,		\
+	  IDTPHY_REGN_CMH,	IDTPHY_REGX_CMH },		\
+	{ /* 53 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_CMHM,		\
+	  IDTPHY_REGN_CMHM,	IDTPHY_REGX_CMHM },		\
+	{ /* 54 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_CEC,		\
+	  IDTPHY_REGN_CEC,	NULL },				\
+	{ /* 55 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_UEC,		\
+	  IDTPHY_REGN_UEC,	NULL },				\
+	{ /* 56-58 */						\
+	  UTP_REGT_INT19,	IDTPHY_REGO_RCCNT,		\
+	  IDTPHY_REGN_RCCNT,	NULL },				\
+	{ /* 59 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RCCF,		\
+	  IDTPHY_REGN_RCCF,	IDTPHY_REGX_RCCF },		\
+	{ /* 5a */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RXID,		\
+	  IDTPHY_REGN_RXID,	IDTPHY_REGX_RXID },		\
+	  /* 5b-5f unused */					\
+	{ /* 60 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TCC,		\
+	  IDTPHY_REGN_TCC,	IDTPHY_REGX_TCC },		\
+	{ /* 61 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TCHP,		\
+	  IDTPHY_REGN_TCHP,	IDTPHY_REGX_TCHP },		\
+	{ /* 62 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_TPLD,		\
+	  IDTPHY_REGN_TPLD,	NULL },				\
+	{ /* 63 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TCC2,		\
+	  IDTPHY_REGN_TCC2,	IDTPHY_REGX_TCC2 },		\
+	{ /* 64-66 */						\
+	  UTP_REGT_INT19,	IDTPHY_REGO_TXCNT,		\
+	  IDTPHY_REGN_TXCNT,	NULL },				\
+	{ /* 67 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TCC3,		\
+	  IDTPHY_REGN_TCC3,	IDTPHY_REGX_TCC3 },		\
+	{ /* 68 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_TXID,		\
+	  IDTPHY_REGN_TXID,	IDTPHY_REGX_TXID },		\
+	  /* 69-6f unused */					\
+	{ /* 70 */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_RBER,		\
+	  IDTPHY_REGN_RBER,	IDTPHY_REGX_RBER },		\
+	{ /* 71 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_BFTH,		\
+	  IDTPHY_REGN_BFTH,	NULL },				\
+	{ /* 72 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_BFWIN,		\
+	  IDTPHY_REGN_BFWIN,	NULL },				\
+	{ /* 73,74 */						\
+	  UTP_REGT_INT16,	IDTPHY_REGO_BFDEN,		\
+	  IDTPHY_REGN_BFDEN,	NULL },				\
+	{ /* 75 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_BWTH,		\
+	  IDTPHY_REGN_BWTH,	NULL },				\
+	{ /* 76 */						\
+	  UTP_REGT_INT8,	IDTPHY_REGO_BWWIN,		\
+	  IDTPHY_REGN_BWWIN,	NULL },				\
+	{ /* 77,78 */						\
+	  UTP_REGT_INT16,	IDTPHY_REGO_BWDEN,		\
+	  IDTPHY_REGN_BWDEN,	NULL },				\
+	  /* 79-7e unused */					\
+	{ /* 7f */						\
+	  UTP_REGT_BITS,	IDTPHY_REGO_OPEC,		\
+	  IDTPHY_REGN_OPEC,	IDTPHY_REGX_OPEC }
+
+
+#endif	/* _DEV_UTOPIA_IDTPHY_H */
diff --git a/sys/dev/utopia/suni.c b/sys/dev/utopia/suni.c
new file mode 100644
index 000000000000..ffc49e8e84da
--- /dev/null
+++ b/sys/dev/utopia/suni.c
@@ -0,0 +1,545 @@
+/*-
+ * Copyright (c) 2003
+ *	Fraunhofer Institute for Open Communication Systems (FhG Fokus).
+ * 	All rights reserved.
+ *
+ * Author: Hartmut Brandt <harti@freebsd.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/unistd.h>
+#include <sys/kernel.h>
+#include <sys/kthread.h>
+#include <sys/proc.h>
+#include <sys/bus.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/sysctl.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_var.h>
+#include <net/if_media.h>
+#include <net/if_atm.h>
+
+#include <dev/utopia/suni.h>
+#include <dev/utopia/utopia.h>
+#include <dev/utopia/utopia_priv.h>
+
+/*
+ * set SONET/SDH mode
+ */
+static int
+suni_set_sdh(struct utopia *utp, int sdh)
+{
+	int err;
+
+	if (sdh)
+		err = UTP_WRITEREG(utp, SUNI_REGO_TPOPAPTR + 1,
+		    SUNI_REGM_TPOPAPTR_S,
+		    SUNI_REGM_SDH << SUNI_REGS_TPOPAPTR_S);
+	else
+		err = UTP_WRITEREG(utp, SUNI_REGO_TPOPAPTR + 1,
+		    SUNI_REGM_TPOPAPTR_S,
+		    SUNI_REGM_SONET << SUNI_REGS_TPOPAPTR_S);
+	if (err != 0)
+		return (err);
+
+	utp->state &= ~UTP_ST_SDH;
+	if (sdh)
+		utp->state |= UTP_ST_SDH;
+
+	return (0);
+}
+
+/*
+ * set idle/unassigned cells
+ */
+static int
+suni_set_unass(struct utopia *utp, int unass)
+{
+	int err;
+
+	if (unass)
+		err = UTP_WRITEREG(utp, SUNI_REGO_TACPIDLEH,
+		    0xff, (0 << SUNI_REGS_TACPIDLEH_CLP));
+	else
+		err = UTP_WRITEREG(utp, SUNI_REGO_TACPIDLEH,
+		    0xff, (1 << SUNI_REGS_TACPIDLEH_CLP));
+	if (err != 0)
+		return (err);
+
+	utp->state &= ~UTP_ST_UNASS;
+	if (unass)
+		utp->state |= UTP_ST_UNASS;
+
+	return (0);
+}
+
+/*
+ * enable/disable scrambling
+ */
+static int
+suni_set_noscramb(struct utopia *utp, int noscramb)
+{
+	int err;
+
+	if (noscramb) {
+		err = UTP_WRITEREG(utp, SUNI_REGO_TACPCTRL,
+		    SUNI_REGM_TACPCTRL_DSCR, SUNI_REGM_TACPCTRL_DSCR);
+		if (err)
+			return (err);
+		err = UTP_WRITEREG(utp, SUNI_REGO_RACPCTRL,
+		    SUNI_REGM_RACPCTRL_DDSCR, SUNI_REGM_RACPCTRL_DDSCR);
+		if (err)
+			return (err);
+		utp->state |= UTP_ST_NOSCRAMB;
+	} else {
+		err = UTP_WRITEREG(utp, SUNI_REGO_TACPCTRL,
+		    SUNI_REGM_TACPCTRL_DSCR, 0);
+		if (err)
+			return (err);
+		err = UTP_WRITEREG(utp, SUNI_REGO_RACPCTRL,
+		    SUNI_REGM_RACPCTRL_DDSCR, 0);
+		if (err)
+			return (err);
+		utp->state &= ~UTP_ST_NOSCRAMB;
+	}
+	return (0);
+}
+
+/*
+ * Get current carrier state
+ */
+static int
+suni_update_carrier(struct utopia *utp)
+{
+	int err;
+	uint8_t reg;
+	u_int n = 1;
+
+	if ((err = UTP_READREGS(utp, SUNI_REGO_RSOPSIS, &reg, &n)) != 0) {
+		utp->carrier = UTP_CARR_UNKNOWN;
+		return (err);
+	}
+	utopia_check_carrier(utp, !(reg & SUNI_REGM_RSOPSIS_LOSV));
+	return (0);
+}
+
+/*
+ * Set the SUNI chip to reflect the current state in utopia.
+ * Assume, that the chip has been reset.
+ */
+static int
+suni_set_chip(struct utopia *utp)
+{
+	int err = 0;
+
+	/* set sonet/sdh */
+	err |= utopia_set_sdh(utp, utp->state & UTP_ST_SDH);
+
+	/* unassigned or idle cells */
+	err |= utopia_set_unass(utp, utp->state & UTP_ST_UNASS);
+	err |= UTP_WRITEREG(utp, SUNI_REGO_TACPIDLEP, 0xff, 0x6a);
+
+	/* set scrambling */
+	err |= utopia_set_noscramb(utp, utp->state & UTP_ST_NOSCRAMB);
+
+	/* loopback */
+	err |= utopia_set_loopback(utp, utp->loopback);
+
+	/* update carrier state */
+	err |= utopia_update_carrier(utp);
+
+	/* enable interrupts on LOS */
+	err |= UTP_WRITEREG(utp, SUNI_REGO_RSOPCIE,
+	    SUNI_REGM_RSOPCIE_LOSE, SUNI_REGM_RSOPCIE_LOSE);
+
+	return (err ? EIO : 0);
+}
+
+/*
+ * Reset the SUNI chip to reflect the current state of utopia.
+ */
+static int
+suni_reset_default(struct utopia *utp)
+{
+	int err = 0;
+
+	if (!(utp->flags & UTP_FL_NORESET)) {
+		err |= UTP_WRITEREG(utp, SUNI_REGO_MRESET,
+		    SUNI_REGM_MRESET_RESET, SUNI_REGM_MRESET_RESET);
+		err |= UTP_WRITEREG(utp, SUNI_REGO_MRESET,
+		    SUNI_REGM_MRESET_RESET, 0);
+	}
+
+	/* disable test mode */
+	err |= UTP_WRITEREG(utp, SUNI_REGO_MTEST, 0xff, 0x00);
+
+	err |= suni_set_chip(utp);
+
+	return (err ? EIO : 0);
+}
+
+/*
+ * Set loopback mode for the Lite
+ */
+static int
+suni_set_loopback_lite(struct utopia *utp, u_int mode)
+{
+	int err;
+	uint32_t val;
+	u_int nmode;
+
+	val = 0;
+	nmode = mode;
+	if (mode & UTP_LOOP_TIME) {
+		nmode &= ~UTP_LOOP_TIME;
+		val |= SUNI_REGM_MCTRL_LOOPT;
+	}
+	if (mode & UTP_LOOP_DIAG) {
+		nmode &= ~UTP_LOOP_DIAG;
+		val |= SUNI_REGM_MCTRL_DLE;
+	}
+	if (mode & UTP_LOOP_LINE) {
+		nmode &= ~UTP_LOOP_LINE;
+		if (val & SUNI_REGM_MCTRL_DLE)
+			return (EINVAL);
+		val |= SUNI_REGM_MCTRL_LLE;
+	}
+	if (nmode != 0)
+		return (EINVAL);
+
+	err = UTP_WRITEREG(utp, SUNI_REGO_MCTRL,
+	    SUNI_REGM_MCTRL_LLE | SUNI_REGM_MCTRL_DLE | SUNI_REGM_MCTRL_LOOPT,
+	    val);
+	if (err)
+		return (err);
+	utp->loopback = mode;
+
+	return (0);
+}
+
+/*
+ * Update statistics from a SUNI/LITE or SUNI/ULTRA
+ */
+static void
+suni_lite_update_stats(struct utopia *utp)
+{
+	int err;
+
+	/* write to the master if we can */
+	if (!(utp->flags & UTP_FL_NORESET)) {
+		err = UTP_WRITEREG(utp, SUNI_REGO_MRESET, 0, 0);
+	} else {
+		err = UTP_WRITEREG(utp, SUNI_REGO_RSOP_BIP8, 0, 0);
+		err |= UTP_WRITEREG(utp, SUNI_REGO_RLOPBIP8_24, 0, 0);
+		err |= UTP_WRITEREG(utp, SUNI_REGO_RPOPBIP8, 0, 0);
+		err |= UTP_WRITEREG(utp, SUNI_REGO_RACPCHCS, 0, 0);
+		err |= UTP_WRITEREG(utp, SUNI_REGO_TACPCNT, 0, 0);
+
+	}
+	if (err) {
+#ifdef DIAGNOSTIC
+		printf("%s: register write error %s: %d\n", __func__,
+		    utp->chip->name, err);
+#endif
+		return;
+	}
+
+	DELAY(8);
+
+	utp->stats.rx_sbip += utopia_update(utp,
+	    SUNI_REGO_RSOP_BIP8, 2, 0xffff);
+	utp->stats.rx_lbip += utopia_update(utp,
+	    SUNI_REGO_RLOPBIP8_24, 3, 0xfffff);
+	utp->stats.rx_lfebe += utopia_update(utp,
+	    SUNI_REGO_RLOPFEBE, 3, 0xfffff);
+	utp->stats.rx_pbip += utopia_update(utp,
+	    SUNI_REGO_RPOPBIP8, 2, 0xffff);
+	utp->stats.rx_pfebe += utopia_update(utp,
+	    SUNI_REGO_RPOPFEBE, 2, 0xffff);
+	utp->stats.rx_corr += utopia_update(utp,
+	    SUNI_REGO_RACPCHCS, 1, 0xff);
+	utp->stats.rx_uncorr += utopia_update(utp,
+	    SUNI_REGO_RACPUHCS, 1, 0xff);
+	utp->stats.rx_cells += utopia_update(utp,
+	    SUNI_REGO_RACPCNT, 3, 0x7ffff);
+	utp->stats.tx_cells += utopia_update(utp,
+	    SUNI_REGO_TACPCNT, 3, 0x7ffff);
+}
+
+/*
+ * Handle interrupt on SUNI chip
+ */
+static void
+suni_intr_default(struct utopia *utp)
+{
+	uint8_t regs[SUNI_REGO_MTEST];
+	u_int n = SUNI_REGO_MTEST;
+	int err;
+
+	/* Read all registers. This acks the interrupts */
+	if ((err = UTP_READREGS(utp, SUNI_REGO_MRESET, regs, &n)) != 0) {
+		printf("SUNI read error %d\n", err);
+		return;
+	}
+	if (n <= SUNI_REGO_RSOPSIS) {
+		printf("%s: could not read RSOPSIS", __func__);
+		return;
+	}
+	/* check for LOSI (loss of signal) */
+	if ((regs[SUNI_REGO_MISTATUS] & SUNI_REGM_MISTATUS_RSOPI) &&
+	    (regs[SUNI_REGO_RSOPSIS] & SUNI_REGM_RSOPSIS_LOSI))
+		utopia_check_carrier(utp, !(regs[SUNI_REGO_RSOPSIS]
+		    & SUNI_REGM_RSOPSIS_LOSV));
+}
+
+const struct utopia_chip utopia_chip_lite = {
+	UTP_TYPE_SUNI_LITE,
+	"Suni/Lite (PMC-5346)",
+	256,
+	suni_reset_default,
+	suni_set_sdh,
+	suni_set_unass,
+	suni_set_noscramb,
+	suni_update_carrier,
+	suni_set_loopback_lite,
+	suni_intr_default,
+	suni_lite_update_stats,
+};
+
+/*
+ * Set loopback mode for the Ultra
+ */
+static int
+suni_set_loopback_ultra(struct utopia *utp, u_int mode)
+{
+	int err;
+	uint32_t val;
+	u_int nmode;
+
+	val = 0;
+	nmode = mode;
+	if (mode & UTP_LOOP_TIME) {
+		nmode &= ~UTP_LOOP_TIME;
+		val |= SUNI_REGM_MCTRL_LOOPT;
+	}
+	if (mode & UTP_LOOP_DIAG) {
+		nmode &= ~UTP_LOOP_DIAG;
+		if (val & SUNI_REGM_MCTRL_LOOPT)
+			return (EINVAL);
+		val |= SUNI_REGM_MCTRL_SDLE;
+	}
+	if (mode & UTP_LOOP_LINE) {
+		nmode &= ~UTP_LOOP_LINE;
+		if (val & (SUNI_REGM_MCTRL_LOOPT | SUNI_REGM_MCTRL_SDLE))
+			return (EINVAL);
+		val |= SUNI_REGM_MCTRL_LLE;
+	}
+	if (mode & UTP_LOOP_PARAL) {
+		nmode &= ~UTP_LOOP_PARAL;
+		val |= SUNI_REGM_MCTRL_PDLE;
+	}
+	if (mode & UTP_LOOP_TWIST) {
+		nmode &= ~UTP_LOOP_TWIST;
+		val |= SUNI_REGM_MCTRL_TPLE;
+	}
+	if (nmode != 0)
+		return (EINVAL);
+
+	err = UTP_WRITEREG(utp, SUNI_REGO_MCTRL,
+	    SUNI_REGM_MCTRL_LLE | SUNI_REGM_MCTRL_SDLE | SUNI_REGM_MCTRL_LOOPT |
+	    SUNI_REGM_MCTRL_PDLE | SUNI_REGM_MCTRL_TPLE, val);
+	if (err)
+		return (err);
+	utp->loopback = mode;
+
+	return (0);
+}
+
+const struct utopia_chip utopia_chip_ultra = {
+	UTP_TYPE_SUNI_ULTRA,
+	"Suni/Ultra (PMC-5350)",
+	256,
+	suni_reset_default,
+	suni_set_sdh,
+	suni_set_unass,
+	suni_set_noscramb,
+	suni_update_carrier,
+	suni_set_loopback_ultra,
+	suni_intr_default,
+	suni_lite_update_stats,
+};
+
+/*
+ * Set loopback mode for the 622
+ */
+static int
+suni_set_loopback_622(struct utopia *utp, u_int mode)
+{
+	int err;
+	uint32_t val;
+	uint8_t config;
+	int smode;
+	u_int nmode;
+	u_int n = 1;
+
+	val = 0;
+	nmode = mode;
+	if (mode & UTP_LOOP_PATH) {
+		nmode &= ~UTP_LOOP_PATH;
+		val |= SUNI_REGM_MCTRLM_DPLE;
+	}
+
+	err = UTP_READREGS(utp, SUNI_REGO_MCONFIG, &config, &n);
+	if (err != 0)
+		return (err);
+	smode = ((config & SUNI_REGM_MCONFIG_TMODE_622) ==
+	    SUNI_REGM_MCONFIG_TMODE_STS1_BIT &&
+	    (config & SUNI_REGM_MCONFIG_RMODE_622) ==
+	    SUNI_REGM_MCONFIG_RMODE_STS1_BIT);
+
+	if (mode & UTP_LOOP_TIME) {
+		if (!smode)
+			return (EINVAL);
+		nmode &= ~UTP_LOOP_TIME;
+		val |= SUNI_REGM_MCTRLM_LOOPT;
+	}
+	if (mode & UTP_LOOP_DIAG) {
+		nmode &= ~UTP_LOOP_DIAG;
+		if (val & SUNI_REGM_MCTRLM_LOOPT)
+			return (EINVAL);
+		val |= SUNI_REGM_MCTRLM_DLE;
+	}
+	if (mode & UTP_LOOP_LINE) {
+		nmode &= ~UTP_LOOP_LINE;
+		if (val & (SUNI_REGM_MCTRLM_LOOPT | SUNI_REGM_MCTRLM_DLE))
+			return (EINVAL);
+		val |= SUNI_REGM_MCTRLM_LLE;
+	}
+	if (nmode != 0)
+		return (EINVAL);
+
+	err = UTP_WRITEREG(utp, SUNI_REGO_MCTRLM,
+	    SUNI_REGM_MCTRLM_LLE | SUNI_REGM_MCTRLM_DLE |
+	    SUNI_REGM_MCTRLM_DPLE | SUNI_REGM_MCTRL_LOOPT, val);
+	if (err)
+		return (err);
+	utp->loopback = mode;
+
+	return (0);
+}
+
+/*
+ * Reset the SUNI chip to reflect the current state of utopia.
+ */
+static int
+suni_reset_622(struct utopia *utp)
+{
+	int err = 0;
+
+	if (!(utp->flags & UTP_FL_NORESET)) {
+		err |= UTP_WRITEREG(utp, SUNI_REGO_MRESET,
+		    SUNI_REGM_MRESET_RESET, SUNI_REGM_MRESET_RESET);
+		err |= UTP_WRITEREG(utp, SUNI_REGO_MRESET,
+		    SUNI_REGM_MRESET_RESET, 0);
+	}
+
+	/* disable test mode */
+	err |= UTP_WRITEREG(utp, SUNI_REGO_MTEST, 0xff,
+	    SUNI_REGM_MTEST_DS27_53_622);
+
+	err |= suni_set_chip(utp);
+
+	return (err ? EIO : 0);
+}
+
+/*
+ * Update statistics from a SUNI/622
+ */
+static void
+suni_622_update_stats(struct utopia *utp)
+{
+	int err;
+
+	/* write to the master if we can */
+	if (!(utp->flags & UTP_FL_NORESET)) {
+		err = UTP_WRITEREG(utp, SUNI_REGO_MRESET, 0, 0);
+	} else {
+		err = UTP_WRITEREG(utp, SUNI_REGO_RSOP_BIP8, 0, 0);
+		err |= UTP_WRITEREG(utp, SUNI_REGO_RLOPBIP8_24, 0, 0);
+		err |= UTP_WRITEREG(utp, SUNI_REGO_RPOPBIP8, 0, 0);
+		err |= UTP_WRITEREG(utp, SUNI_REGO_RACPCHCS, 0, 0);
+		err |= UTP_WRITEREG(utp, SUNI_REGO_TACPCNT, 0, 0);
+	}
+	if (err) {
+#ifdef DIAGNOSTIC
+		printf("%s: register write error %s: %d\n", __func__,
+		    utp->chip->name, err);
+#endif
+		return;
+	}
+
+	DELAY(8);
+
+	utp->stats.rx_sbip += utopia_update(utp,
+	    SUNI_REGO_RSOP_BIP8, 2, 0xffff);
+	utp->stats.rx_lbip += utopia_update(utp,
+	    SUNI_REGO_RLOPBIP8_24, 3, 0xfffff);
+	utp->stats.rx_lfebe += utopia_update(utp,
+	    SUNI_REGO_RLOPFEBE, 3, 0xfffff);
+	utp->stats.rx_pbip += utopia_update(utp,
+	    SUNI_REGO_RPOPBIP8, 2, 0xffff);
+	utp->stats.rx_pfebe += utopia_update(utp,
+	    SUNI_REGO_RPOPFEBE, 2, 0xffff);
+	utp->stats.rx_corr += utopia_update(utp,
+	    SUNI_REGO_RACPCHCS_622, 2, 0xfff);
+	utp->stats.rx_uncorr += utopia_update(utp,
+	    SUNI_REGO_RACPUHCS_622, 2, 0xfff);
+	utp->stats.rx_cells += utopia_update(utp,
+	    SUNI_REGO_RACPCNT_622, 3, 0x1fffff);
+	utp->stats.tx_cells += utopia_update(utp,
+	    SUNI_REGO_TACPCNT, 3, 0x1fffff);
+}
+
+const struct utopia_chip utopia_chip_622 = {
+	UTP_TYPE_SUNI_622,
+	"Suni/622 (PMC-5355)",
+	256,
+	suni_reset_622,
+	suni_set_sdh,
+	suni_set_unass,
+	suni_set_noscramb,
+	suni_update_carrier,
+	suni_set_loopback_622,
+	suni_intr_default,
+	suni_622_update_stats,
+};
diff --git a/sys/dev/utopia/suni.h b/sys/dev/utopia/suni.h
new file mode 100644
index 000000000000..fd1be7e13e39
--- /dev/null
+++ b/sys/dev/utopia/suni.h
@@ -0,0 +1,1515 @@
+/*-
+ * Copyright (c) 2003
+ *	Fraunhofer Institute for Open Communication Systems (FhG Fokus).
+ * 	All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Author: Hartmut Brandt <harti@freebsd.org>
+ *
+ * $FreeBSD$
+ *
+ * Register definitions for the following chips:
+ *	PMC-Sierra PMC-5346 (S/UNI-LITE)
+ *	PMC-Sierra PMC-5350 (S/UNI-ULTRA)
+ *	PMC-Sierra PMC-5355 (S/UNI-622)
+ *
+ * All definitions ending with _ULTRA are for the ULTRA chip only, all
+ * definitions ending with _LITE are for the LITE chip only. Some registers
+ * are only in the ULTRA and the definitions are not suffixed. All other
+ * definitions are for all chips.
+ */
+#ifndef _DEV_UTOPIA_SUNI_H
+#define	_DEV_UTOPIA_SUNI_H
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_MRESET 	"Master Reset and Identity/Load Meters"
+#define	SUNI_REGO_MRESET		0x00
+#define	SUNI_REGM_MRESET_RESET		0x80
+#define	SUNI_REGM_MRESET_TYPE		0x70
+#define	SUNI_REGM_MRESET_TYPE_622	0x10
+#define	SUNI_REGM_MRESET_TYPE_LITE	0x30
+#define	SUNI_REGM_MRESET_TYPE_ULTRA	0x70
+#define	SUNI_REGM_MRESET_TIP_ULTRA	0x08
+#define	SUNI_REGM_MRESET_ID_ULTRA	0x07
+#define	SUNI_REGM_MRESET_ID_LITE	0x0f
+#define	SUNI_REGM_MRESET_ID_622		0x0f
+#define	SUNI_REGX_MRESET_ULTRA	"\020\10RESET\12\x70\12TYPE\4TIP\12\7\12ID"
+#define	SUNI_REGX_MRESET_LITE	"\020\10RESET\12\x70\12TYPE\12\xf\12ID"
+#define	SUNI_REGX_MRESET_622	"\020\10RESET\12\x70\12TYPE\12\xf\12ID"
+
+/* lite, ultra */
+#define	SUNI_REGN_MCONFIG "Master Configuration"
+#define	SUNI_REGO_MCONFIG		0x01
+#define	SUNI_REGM_MCONFIG_AUTOFEBE	0x40
+#define	SUNI_REGM_MCONFIG_AUTOLRDI	0x20
+#define	SUNI_REGM_MCONFIG_AUTOPRDI	0x10
+#define	SUNI_REGM_MCONFIG_TCAINV	0x08
+#define	SUNI_REGM_MCONFIG_RCAINV	0x04
+#define	SUNI_REGM_MCONFIG_RXDINV_LITE	0x02
+#define	SUNI_REGM_MCONFIG_TFP_IN_ULTRA	0x01
+#define	SUNI_REGM_MCONFIG_RESERVED	0x00
+#define	SUNI_REGX_MCONFIG_LITE "\020\7AUTOFEBE\6AUTOLRDI\5AUTOPRDI\4TCAINV\3RCAINV\2RXDINV"
+#define	SUNI_REGX_MCONFIG_ULTRA "\020\7AUTOFEBE\6AUTOLRDI\5AUTOPRDI\4TCAINV\3RCAINV\1TFPI_IN"
+
+/* 622 */
+#define	SUNI_REGM_MCONFIG_TPTBEN_622	0x80
+#define	SUNI_REGM_MCONFIG_TSTBEN_622	0x40
+#define	SUNI_REGM_MCONFIG_SDH_C1_622	0x20
+#define	SUNI_REGM_MCONFIG_FIXPTR_622	0x10
+#define	SUNI_REGM_MCONFIG_TMODE_622	0x0C
+#define	SUNI_REGM_MCONFIG_TMODE_STS1_BYTE	0x00
+#define	SUNI_REGM_MCONFIG_TMODE_STS3c		0x04
+#define	SUNI_REGM_MCONFIG_TMODE_STS1_BIT	0x08
+#define	SUNI_REGM_MCONFIG_TMODE_STS12c		0x0C
+#define	SUNI_REGM_MCONFIG_RMODE_622	0x03
+#define	SUNI_REGM_MCONFIG_RMODE_STS1_BYTE	0x00
+#define	SUNI_REGM_MCONFIG_RMODE_STS3c		0x01
+#define	SUNI_REGM_MCONFIG_RMODE_STS1_BIT	0x02
+#define	SUNI_REGM_MCONFIG_RMODE_STS12c		0x03
+#define	SUNI_REGX_MCONFIG_622	"\020\10TPTBEN\7TSTBEN\6SDH_C1\5FIXPTR\11\x0C\0x00XSTS1BYTE\11\0x0C\0x04XSTS3c\11\0x0C\0x08XSTS1BIT\11\0x0C\0x0CXSTS12c\11\0x03\0x00RSTS1BYTE\11\0x03\0x01RSTS3c\11\0x03\0x02RSTS1BIT\11\0x03\0x03RSTS12c"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_MISTATUS "Master Interrupt Status"
+#define	SUNI_REGO_MISTATUS		0x02
+#define	SUNI_REGM_MISTATUS_CSUI_ULTRA	0x80
+#define	SUNI_REGM_MISTATUS_TROOLI_LITE	0x80
+#define	SUNI_REGM_MISTATUS_SUNII_622	0x80
+#define	SUNI_REGM_MISTATUS_LCDI		0x40
+#define	SUNI_REGM_MISTATUS_STBI_622	0x40
+#define	SUNI_REGM_MISTATUS_CRUI_ULTRA	0x20
+#define	SUNI_REGM_MISTATUS_RDOOLI_LITE	0x20
+#define	SUNI_REGM_MISTATUS_RESERVED_622	0x20
+#define	SUNI_REGM_MISTATUS_TACPI	0x10
+#define	SUNI_REGM_MISTATUS_RACPI	0x08
+#define	SUNI_REGM_MISTATUS_RPOPI	0x04
+#define	SUNI_REGM_MISTATUS_RLOPI	0x02
+#define	SUNI_REGM_MISTATUS_RSOPI	0x01
+#define	SUNI_REGX_MISTATUS_LITE "\020\10TROOLI\7LCDI\6RDOOLI\5TACPI\4RACPI\3RPOPI\2RLOPI\1RSOPI"
+#define	SUNI_REGX_MISTATUS_ULTRA "\020\10CSUI\7LCDI\6CRUI\5TACPI\4RACPI\3RPOPI\2RLOPI\1RSOPI"
+#define	SUNI_REGX_MISTATUS_622	"\020\10S/UNII\7STBI\5TACPI\4RACPI\3RPOPI\2RLOPI\1RSOPI"
+
+/* ultra */
+#define	SUNI_REGN_MMCTRL	"Master Mode Control"
+#define	SUNI_REGO_MMCTRL		0x03
+#define	SUNI_REGM_MMCTRL_51		0x02
+#define	SUNI_REGM_MMCTRL_155		0x03
+#define	SUNI_REGX_MMCTRL	"\020\11\3\00251MBIT\11\3\003155MBIT"
+
+/* 622 */
+#define	SUNI_REGN_PISO		"PISO Interrupt"
+#define	SUNI_REGO_PISO			0x03
+#define	SUNI_REGM_PISO_PAEE		0x02
+#define	SUNI_REGM_PISO_PAEI		0x01
+#define	SUNI_REGX_PISO		"\020\2PAEE\1PAEI"
+
+/* ultra/lite */
+#define	SUNI_REGN_MCLKM		"Master Clock Monitor"
+#define	SUNI_REGO_MCLKM			0x04
+#define	SUNI_REGM_MCLKM_RFCLKA		0x10	/* ultra */
+#define	SUNI_REGM_MCLKM_TFCLKA		0x08	/* ultra */
+#define	SUNI_REGM_MCLKM_RRCLKA		0x08	/* lite */
+#define	SUNI_REGM_MCLKM_REFCLKA		0x04	/* ultra */
+#define	SUNI_REGM_MCLKM_TRCLKA		0x04	/* lite */
+#define	SUNI_REGM_MCLKM_RCLKA		0x02
+#define	SUNI_REGM_MCLKM_TCLKA		0x01
+#define	SUNI_REGX_MCLKM_LITE	"\020\4RRCLKA\3TRCLKA\2RCLKA\1TCLKA"
+#define	SUNI_REGX_MCLKM_ULTRA	"\020\5RFCLKA\4TFCLKA\3REFCLKA\2RCLKA\1TCLKA"
+
+/* 622 */
+#define	SUNI_REGN_MCTRLM	"Master Control/Monitor"
+#define	SUNI_REGO_MCTRLM		0x04
+#define	SUNI_REGM_MCTRLM_TCAINV		0x80
+#define	SUNI_REGM_MCTRLM_RCAINV		0x40
+#define	SUNI_REGM_MCTRLM_LLE		0x20
+#define	SUNI_REGM_MCTRLM_DLE		0x10
+#define	SUNI_REGM_MCTRLM_LOOPT		0x08
+#define	SUNI_REGM_MCTRLM_DPLE		0x04
+#define	SUNI_REGM_MCTRLM_PICLKA		0x02
+#define	SUNI_REGM_MCTRLM_TCLKA		0x01
+#define	SUNI_REGX_MCTRLM	"\020\10TCAINV\7RCAINV\6LLE\5DLE\4LOOPT\3DPLE\2PICLKA\1TCLKA"
+
+/* ultra/lite */
+#define	SUNI_REGN_MCTRL		"Master Control"
+#define	SUNI_REGO_MCTRL			0x05
+#define	SUNI_REGM_MCTRL_LCDE		0x80
+#define	SUNI_REGM_MCTRL_LCDV		0x40
+#define	SUNI_REGM_MCTRL_FIXPTR		0x20
+#define	SUNI_REGM_MCTRL_TPLE		0x10	/* ultra */
+#define	SUNI_REGM_MCTRL_PDLE		0x08	/* ultra */
+#define	SUNI_REGM_MCTRL_LLE		0x04
+#define	SUNI_REGM_MCTRL_SDLE		0x02	/* ultra */
+#define	SUNI_REGM_MCTRL_DLE		0x02	/* lite */
+#define	SUNI_REGM_MCTRL_LOOPT		0x01
+#define	SUNI_REGX_MCTRL_ULTRA	"\020\10LCDE\7LCDV\6FIXPTR\5TPLE\4PDLE\3LLE\2SDLE\1LOOPT"
+#define	SUNI_REGX_MCTRL_LITE	"\020\10LCDE\7LCDV\6FIXPTR\3LLE\2DLE\1LOOPT"
+
+/* 622 */
+#define	SUNI_REGN_MALARM	"Master Auto Alarm"
+#define	SUNI_REGO_MALARM		0x05
+#define	SUNI_REGM_MALARM_AUTOFEBE	0x04
+#define	SUNI_REGM_MALARM_AUTOLRDI	0x02
+#define	SUNI_REGM_MALARM_AUTOPRDI	0x01
+#define	SUNI_REGX_MALARM	"\020\4AUTOFEBE\2AUTOLRDI\1AUTOPRDI"
+
+/* ultra/lite */
+#define	SUNI_REGN_CLKSYN	"Clock Synthesis Control and Status"
+#define	SUNI_REGO_CLKSYN		0x06
+#define	SUNI_REGM_CLKSYN_TROOLI		0x20	/* ultra */
+#define	SUNI_REGM_CLKSYN_TROOLV		0x08
+#define	SUNI_REGM_CLKSYN_TROOLE		0x02
+#define	SUNI_REGM_CLKSYN_TREFSEL	0x01	/* lite */
+#define	SUNI_REGM_CLKSYN_RESERVED	0x00
+#define	SUNI_REGX_CLKSYN_ULTRA	"\020\6TROOLI\4TROOLV\2TROOLE"
+#define	SUNI_REGX_CLKSYN_LITE	"\020\4TROOLV\2TROOLE\1TREFSEL"
+
+/* 622 */
+#define	SUNI_REGN_POUT	"Parallel Output Port"
+#define	SUNI_REGO_POUT			0x06
+#define	SUNI_REGM_POUT_POP		0x3f
+#define	SUNI_REGX_POUT	"\020\12\x3f\12POP"
+
+/* ultra/lite */
+#define	SUNI_REGN_CLKREC "Clock Recovery Control and Status"
+#define	SUNI_REGO_CLKREC_LITE		0x07
+#define	SUNI_REGO_CLKREC_ULTRA		0x08
+#define	SUNI_REGM_CLKREC_RROOLI		0x40	/* ultra */
+#define	SUNI_REGM_CLKREC_RDOOLI		0x20	/* ultra */
+#define	SUNI_REGM_CLKREC_RROOLV		0x10
+#define	SUNI_REGM_CLKREC_RDOOLV		0x08
+#define	SUNI_REGM_CLKREC_RROOLE		0x04	/* ultra */
+#define	SUNI_REGM_CLKREC_RDOOLE		0x02
+#define	SUNI_REGM_CLKREC_RREFSEL	0x01	/* lite */
+#define	SUNI_REGM_CLKREC_RESERVED	0x00
+#define	SUNI_REGX_CLKREC_ULTRA "\020\7RROOLI\6RDOOLI\5RROOLV\4RDOOLV\3RROOLE\2RDOOLE"
+#define	SUNI_REGX_CLKREC_LITE "\020\5RROOLV\4RDOOLV\2RDOOLE\1RREFSEL"
+
+/* 622 */
+#define	SUNI_REGN_PIN	"Parallel Input Port"
+#define	SUNI_REGO_PIN			0x07
+
+/* 622 */
+#define	SUNI_REGN_PINV	"Parallel Input Port Value"
+#define	SUNI_REGO_PINV			0x08
+#define	SUNI_REGM_PINV_PIPV		0x0f
+#define	SUNI_REGX_PINV	"\020\12\0x0f\12PIPIV"
+
+/* ultra */
+#define	SUNI_REGN_CLKRECCFG	"Clock Recovery Configuration"
+#define	SUNI_REGO_CLKRECCFG		0x09
+#define	SUNI_REGM_CLKRECCFG_RESERVED	0x07
+#define	SUNI_REGX_CLKRECCFG	"\020"
+
+/* 622 */
+#define	SUNI_REGN_PINE	"Parallel Input Port Enable"
+#define	SUNI_REGO_PINE			0x09
+
+/* ultra */
+#define	SUNI_REGN_LTXCFG1 "Line Transmitter Configuration 1"
+#define	SUNI_REGO_LTXCFG1		0x0A
+#define	SUNI_REGM_LTXCFG1_VREFSEL	0x80
+#define	SUNI_REGM_LTXCFG1_OEN		0x20
+#define	SUNI_REGM_LTXCFG1_OTQ		0x10
+#define	SUNI_REGM_LTXCFG1_RESERVED	0x0C
+#define	SUNI_REGX_LTXCFG1 "\020\10VREFSEL\6OEN\5OTQ"
+
+/* 622 */
+#define	SUNI_REGN_XC1	"Transmit C1"
+#define	SUNI_REGO_XC1			0x0A
+
+/* ultra */
+#define	SUNI_REGN_LTXCFG2 "Line Transmitter Configuration 2"
+#define	SUNI_REGO_LTXCFG2		0x0B
+#define	SUNI_REGM_LTXCFG2_RESERVED	0xFF
+#define	SUNI_REGX_LTXCFG2 "\020"
+
+/* 622 */
+#define	SUNI_REGN_APSCS	"APS Control/Status"
+#define	SUNI_REGO_APSCS			0x0B
+#define	SUNI_REGM_APSCS_PSBFE		0x80
+#define	SUNI_REGM_APSCS_COAPSE		0x40
+#define	SUNI_REGM_APSCS_Z1E		0x20
+#define	SUNI_REGM_APSCS_Zi1		0x10
+#define	SUNI_REGM_APSCS_PSBFI		0x08
+#define	SUNI_REGM_APSCS_COAPSI		0x04
+#define	SUNI_REGM_APSCS_RESERVED	0x02
+#define	SUNI_REGM_APSCS_PSBFV		0x01
+#define	SUNI_REGX_APSCS	"\020\10PSBFE\7COAPSE\6Z1E\5Z1I\4PSBFI\3COAPSI\1PSBFV"
+
+/* ultra */
+#define	SUNI_REGN_LRXCFG "Line Receiver Configuration"
+#define	SUNI_REGO_LRXCFG		0x0C
+#define	SUNI_REGM_LRXCFG_RESERVED	0x01
+#define	SUNI_REGX_LRXCFG "\020"
+
+/* 622 */
+#define	SUNI_REGN_RK1	"Receive K1"
+#define	SUNI_REGO_RK1			0x0C
+
+/* 622 */
+#define	SUNI_REGN_RK2	"Receive K2"
+#define	SUNI_REGO_RK2			0x0D
+
+/* 622 */
+#define	SUNI_REGN_RZ1	"Receive Z1"
+#define	SUNI_REGO_RZ1			0x0E
+
+/* 622 */
+#define	SUNI_REGN_XZ1	"Transmit Z1"
+#define	SUNI_REGO_XZ1			0x0F
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RSOPCIE "RSOP Control/Interrupt Enable"
+#define	SUNI_REGO_RSOPCIE		0x10
+#define	SUNI_REGO_RSOPCIE_BIPWORD_622	0x80
+#define	SUNI_REGM_RSOPCIE_DDS		0x40
+#define	SUNI_REGM_RSOPCIE_FOOF		0x20
+#define	SUNI_REGM_RSOPCIE_RESV		0x10
+#define	SUNI_REGM_RSOPCIE_ALGO2_622	0x10
+#define	SUNI_REGM_RSOPCIE_BIPEE		0x08
+#define	SUNI_REGM_RSOPCIE_LOSE		0x04
+#define	SUNI_REGM_RSOPCIE_LOFE		0x02
+#define	SUNI_REGM_RSOPCIE_OOFE		0x01
+#define	SUNI_REGX_RSOPCIE	"\020\7DDS\6FOOF\4BIPEE\3LOSE\2LOFE\1OOFE"
+#define	SUNI_REGX_RSOPCIE_622	"\020\10BIPWORD\7DDS\6FOOF\5ALGO2\4BIPEE\3LOSE\2LOFE\1OOFE"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RSOPSIS "RSOP Status/Interrupt Status"
+#define	SUNI_REGO_RSOPSIS		0x11
+#define	SUNI_REGM_RSOPSIS_BIPEI		0x40
+#define	SUNI_REGM_RSOPSIS_LOSI		0x20
+#define	SUNI_REGM_RSOPSIS_LOFI		0x10
+#define	SUNI_REGM_RSOPSIS_OOFI		0x08
+#define	SUNI_REGM_RSOPSIS_LOSV		0x04
+#define	SUNI_REGM_RSOPSIS_LOFV		0x02
+#define	SUNI_REGM_RSOPSIS_OOFV		0x01
+#define	SUNI_REGX_RSOPSIS "\020\7BIPEI\6LOSI\5LOFI\4OOFI\3LOSV\2LOFV\1OOFV"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RSOP_BIP8 "RSOP Section BIP-8"
+#define	SUNI_REGO_RSOP_BIP8		0x12	/* +0x13 */
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TSOPCTRL "TSOP Control"
+#define	SUNI_REGO_TSOPCTRL		0x14
+#define	SUNI_REGM_TSOPCTRL_DS		0x40
+#define	SUNI_REGM_TSOPCTRL_LAIS		0x01
+#define	SUNI_REGM_TSOPCTRL_RESERVED	0x00
+#define	SUNI_REGX_TSOPCTRL "\020\7DS\1LAIS"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TSOPDIAG "TSOP Diagnostics"
+#define	SUNI_REGO_TSOPDIAG		0x15
+#define	SUNI_REGM_TSOPDIAG_DLOS		0x04
+#define	SUNI_REGM_TSOPDIAG_DBIP8	0x02
+#define	SUNI_REGM_TSOPDIAG_DFP		0x01
+#define	SUNI_REGX_TSOPDIAG "\020\3DLOS\2DBIP8\1DFP"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RLOPCTRL "RLOP Control/Status"
+#define	SUNI_REGO_RLOPCTRL		0x18
+#define	SUNI_REGO_RLOPCTRL_BIPWORD	0x80
+#define	SUNI_REGO_RLOPCTRL_ALLONES_622	0x40
+#define	SUNI_REGO_RLOPCTRL_AISDET_622	0x20
+#define	SUNI_REGO_RLOPCTRL_LRDIDET_622	0x10
+#define	SUNI_REGO_RLOPCTRL_BIPWORDO_622	0x08
+#define	SUNI_REGO_RLOPCTRL_LAISV	0x02
+#define	SUNI_REGO_RLOPCTRL_RDIV		0x01
+#define	SUNI_REGO_RLOPCTRL_RESERVED	0x00
+#define	SUNI_REGX_RLOPCTRL	"\020\10BIPWORD\2LAISV\1RDIV"
+#define	SUNI_REGX_RLOPCTRL_622	"\020\10BIPWORD\7ALLONES\6AISDET\5LRDIDET\4BIPWORDO\2LAISV\1RDIV"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RLOPINTR "RLOP Interrupt Enable/Interrupt Status"
+#define	SUNI_REGO_RLOPINTR		0x19
+#define	SUNI_REGO_RLOPINTR_FEBEE	0x80
+#define	SUNI_REGO_RLOPINTR_BIPEE	0x40
+#define	SUNI_REGO_RLOPINTR_LAISE	0x20
+#define	SUNI_REGO_RLOPINTR_RDIE		0x10
+#define	SUNI_REGO_RLOPINTR_FEBEI	0x08
+#define	SUNI_REGO_RLOPINTR_BIPEI	0x04
+#define	SUNI_REGO_RLOPINTR_LAISI	0x02
+#define	SUNI_REGO_RLOPINTR_RDII		0x01
+#define	SUNI_REGX_RLOPINTR "\020\10FEBEE\7BIPEE\6LAISE\5DRIE\4FEBEI\3BIPEI\2LAISI\1RDII"
+
+/* lite, ultra */
+#define	SUNI_REGN_RLOPBIP8_24 "RLOP Line BIP-8/24"
+#define	SUNI_REGO_RLOPBIP8_24		0x1A	/* +1B,1C */
+#define	SUNI_REGM_RLOPBIP8_24		0x0F
+
+/* 622 */
+#define	SUNI_REGN_RLOPBIP8_24_96 "RLOP Line BIP-8/24/96"
+#define	SUNI_REGO_RLOPBIP8_24_96	0x1A	/* +1B,1C */
+#define	SUNI_REGM_RLOPBIP8_24_96	0x0F
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RLOPFEBE "RLOP Line FEBE"
+#define	SUNI_REGO_RLOPFEBE		0x1D	/* +1E,1F */
+#define	SUNI_REGM_RLOPFEBE		0x0F
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TLOPCTRL "TLOP Control"
+#define	SUNI_REGO_TLOPCTRL		0x20
+#define	SUNI_REGM_TLOPCTRL_APSREG_622	0x20
+#define	SUNI_REGM_TLOPCTRL_RDI		0x01
+#define	SUNI_REGM_TLOPCTRL_RESERVED	0x00
+#define	SUNI_REGX_TLOPCTRL	"\020\1RDI"
+#define	SUNI_REGX_TLOPCTRL_622	"\020\6APSREG\1LRDI"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TLOPDIAG "TLOP Diagnostics"
+#define	SUNI_REGO_TLOPDIAG		0x21
+#define	SUNI_REGM_TLOPDIAG_DBIP		0x01
+#define	SUNI_REGX_TLOPDIAG "\020\1DBIP"
+
+/* 622 */
+#define	SUNI_REGN_TLOP_XK1	"TLOP Transmit K1"
+#define	SUNI_REGO_TLOP_XK1		0x22
+
+/* 622 */
+#define	SUNI_REGN_TLOP_XK2	"TLOP Transmit K2"
+#define	SUNI_REGO_TLOP_XK2		0x23
+
+/* 622 */
+#define	SUNI_REGN_SSTBCTRL	"SSTB Control"
+#define	SUNI_REGO_SSTBCTRL		0x28
+#define	SUNI_REGM_SSTBCTRL_RRAMACC	0x40
+#define	SUNI_REGM_SSTBCTRL_RTIUIE	0x20
+#define	SUNI_REGM_SSTBCTRL_RTIMIE	0x10
+#define	SUNI_REGM_SSTBCTRL_PER5		0x08
+#define	SUNI_REGM_SSTBCTRL_TNULL	0x04
+#define	SUNI_REGM_SSTBCTRL_NOSYNC	0x02
+#define	SUNI_REGM_SSTBCTRL_LEN16	0x01
+#define	SUNI_REGX_SSTBCTRL	"\020\7RRAMACC\6RTIUIE\5RTIMIE\4PER5\3TNULL\2NOSYNC\1LEN16"
+
+/* 622 */
+#define	SUNI_REGN_SSTBSTIS	"SSTB Section Trace Identifier Status"
+#define	SUNI_REGO_SSTBSTIS		0x29
+#define	SUNI_REGM_SSTBSTIS_BUSY		0x80
+#define	SUNI_REGM_SSTBSTIS_RTIUI	0x08
+#define	SUNI_REGM_SSTBSTIS_RTIUV	0x04
+#define	SUNI_REGM_SSTBSTIS_RTIMI	0x02
+#define	SUNI_REGM_SSTBSTIS_RTIMV	0x01
+#define	SUNI_REGX_SSTBSTIS	"\020\10BUSY\4RTIUI\3RTIUV\2RTIMI\1RTIMV"
+
+/* 622 */
+#define	SUNI_REGN_SSTBIAR	"SSTB Indirect Address Register"
+#define	SUNI_REGO_SSTBIAR		0x2A
+#define	SUNI_REGM_SSTBIAR_RWB		0x80
+#define	SUNI_REGM_SSTBIAR_A		0x7F
+#define	SUNI_REGX_SSTBIAR	"\020\10RWB\12\x7f\20"
+
+/* 622 */
+#define	SUNI_REGN_SSTBIDR	"SSTB Indirect Data Register"
+#define	SUNI_REGO_SSTBIDR		0x2B
+
+#if 0	/* see chip errata */
+/* 622 */
+#define	SUNI_REGN_SSTBECSM	"SSTB Expected Clock Synchronization Message"
+#define	SUNI_REGO_SSTBECSM		0x2C
+#endif
+
+/* 622 */
+#define	SUNI_REGN_SSTBCSMS	"SSTB Clock Synchronisation Message Status"
+#define	SUNI_REGO_SSTBCSMS		0x2D
+#define	SUNI_REGM_SSTBCSMS_RCSMUIE	0x80
+#define	SUNI_REGM_SSTBCSMS_RCSMMIE	0x40
+#define	SUNI_REGM_SSTBCSMS_RCSMUI	0x08
+#define	SUNI_REGM_SSTBCSMS_RCSMUV	0x04
+#define	SUNI_REGM_SSTBCSMS_RCSMMI	0x02
+#define	SUNI_REGM_SSTBCSMS_RCSMMV	0x01
+#define	SUNI_REGX_SSTBCSMS	"\020\10RCSMUIE\7RCSMMIE\4RCSMUI\3RCSMUV\2RCSMMI\1RCSMMV"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RPOPCTRL	"RPOP Status/Control"
+#define	SUNI_REGO_RPOPCTRL		0x30
+#define	SUNI_REGM_RPOPCTRL_LOP		0x20
+#define	SUNI_REGM_RPOPCTRL_PAIS		0x08
+#define	SUNI_REGM_RPOPCTRL_PRDI		0x04
+#define	SUNI_REGM_RPOPCTRL_NEWPTRI_622	0x02
+#define	SUNI_REGM_RPOPCTRL_NEWPTRE_622	0x01
+#define	SUNI_REGM_RPOPCTRL_RESERVED	0x00
+#define	SUNI_REGX_RPOPCTRL	"\020\6LOP\4PAIS\3PRDI"
+#define	SUNI_REGX_RPOPCTRL_622	"\020\6LOP\4PAIS\3PRDI\2NEWPTRI\1NEWPTRE"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RPOPISTAT	"RPOP Interrupt Status"
+#define	SUNI_REGO_RPOPISTAT		0x31
+#define	SUNI_REGM_RPOPISTAT_PSLI	0x80
+#define	SUNI_REGM_RPOPISTAT_LOPI	0x20
+#define	SUNI_REGM_RPOPISTAT_PAISI	0x08
+#define	SUNI_REGM_RPOPISTAT_PRDII	0x04
+#define	SUNI_REGM_RPOPISTAT_BIPEI	0x02
+#define	SUNI_REGM_RPOPISTAT_FEBEI	0x01
+#define	SUNI_REGX_RPOPISTAT	"\02010PSLI\6LOPI\4PAISI\3PRDII\2BIPEI\1FEBEI"
+
+/* 622 */
+#define	SUNI_REGN_RPOPPIS	"RPOP Pointer Interrupt Status"
+#define	SUNI_REGO_RPOPPIS		0x32
+#define	SUNI_REGM_RPOPPIS_ILLJREQI	0x80
+#define	SUNI_REGM_RPOPPIS_DISCOPAI	0x20
+#define	SUNI_REGM_RPOPPIS_INVNDFI	0x10
+#define	SUNI_REGM_RPOPPIS_ILLPTRI	0x08
+#define	SUNI_REGM_RPOPPIS_NSEI		0x04
+#define	SUNI_REGM_RPOPPIS_PSEI		0x02
+#define	SUNI_REGM_RPOPPIS_NDFI		0x01
+#define	SUNI_REGX_RPOPPIS	"\020\10ILLJREQI\6DISCOPAI\5INVNDFI\4ILLPTRI\3NSEI\2PSEI\1NDFI"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RPOPIEN	"RPOP Interrupt Enable"
+#define	SUNI_REGO_RPOPIEN		0x33
+#define	SUNI_REGM_RPOPIEN_PSLE		0x80
+#define	SUNI_REGM_RPOPIEN_LOPE		0x20
+#define	SUNI_REGM_RPOPIEN_PAISE		0x08
+#define	SUNI_REGM_RPOPIEN_PRDIE		0x04
+#define	SUNI_REGM_RPOPIEN_BIPEE		0x02
+#define	SUNI_REGM_RPOPIEN_FEBEE		0x01
+#define	SUNI_REGM_RPOPIEN_RESERVED	0x00
+#define	SUNI_REGX_RPOPIEN	"\02010PSLE\6LOPE\4PAISE\3PRDIE\2BIPEE\1FEBEE"
+
+/* 622 */
+#define	SUNI_REGN_RPOPPIE	"RPOP Pointer Interrupt Enable"
+#define	SUNI_REGO_RPOPPIE		0x34
+#define	SUNI_REGM_RPOPPIE_ILLJREQE	0x80
+#define	SUNI_REGM_RPOPPIE_DISCOPAE	0x20
+#define	SUNI_REGM_RPOPPIE_INVNDFE	0x10
+#define	SUNI_REGM_RPOPPIE_ILLPTRE	0x08
+#define	SUNI_REGM_RPOPPIE_NSEE		0x04
+#define	SUNI_REGM_RPOPPIE_PSEE		0x02
+#define	SUNI_REGM_RPOPPIE_NDFE		0x01
+#define	SUNI_REGX_RPOPPIE	"\020\10ILLJREQE\6DISCOPAE\5INVNDFE\4ILLPTRE\3NSEE\2PSEE\1NDFE"
+
+/* 622 */
+#define	SUNI_REGN_RPOPPTR	"RPOP Pointer"
+#define	SUNI_REGO_RPOPPTR		0x35	/* +36 */
+#define	SUNI_REGM_RPOPPTR_RDI10		0x20
+#define	SUNI_REGM_RPOPPTR_S		0x0c
+#define	SUNI_REGS_RPOPPTR_S		2
+#define	SUNI_REGM_RPOPPTR		0x03
+#define	SUNI_REGS_RPOPPTR		0
+#define	SUNI_REGX_RPOPPTR		"\020\6RDI10\12\xc\20S"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RPOPPSL "RPOP Path Signal Label"
+#define	SUNI_REGO_RPOPPSL		0x37
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RPOPBIP8 "RPOP Path BIP-8"
+#define	SUNI_REGO_RPOPBIP8		0x38	/* +39 */
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RPOPFEBE "RPOP Path FEBE"
+#define	SUNI_REGO_RPOPFEBE		0x3A	/* +3B */
+
+/* 622 */
+#define	SUNI_REGN_RPOPRDI	"RPOP RDI"
+#define	SUNI_REGO_RPOPRDI		0x3C
+#define	SUNI_REGM_RPOPRDI_BLKFEBE	0x10
+#define	SUNI_REGM_RPOPRDI_ARDIE		0x02
+#define	SUNI_REGM_RPOPRDI_ARDIV		0x01
+#define	SUNI_REGM_RPOPRDI_RESERVED	0x00
+#define	SUNI_REGX_RPOPRDI	"\020\5BLKFEBE\2ARDIE\1ARDIV"
+
+/* lite, ultra */
+#define	SUNI_REGN_RPOPBIP8CFG 	"RPOP Path BIP-8 Configuration"
+#define	SUNI_REGO_RPOPBIP8CFG		0x3D
+#define	SUNI_REGM_RPOPBIP8CFG_BLKBIP	0x20
+#define	SUNI_REGM_RPOPBIP8CFG_RESERVED	0x00
+#define	SUNI_REGX_RPOPBIP8CFG 	"\020\6BLKBIP"
+
+/* 622 */
+#define	SUNI_REGN_RPOPRING	"RPOP Ring Control"
+#define	SUNI_REGO_RPOPRING		0x3D
+#define	SUNI_REGM_RPOPRING_SOS		0x80
+#define	SUNI_REGM_RPOPRING_ENSS		0x40
+#define	SUNI_REGM_RPOPRING_BLKBIP	0x20
+#define	SUNI_REGM_RPOPRING_DISFS	0x10
+#define	SUNI_REGM_RPOPRING_BLKBIPO	0x08
+#define	SUNI_REGM_RPOPRING_RESERVED	0x00
+#define	SUNI_REGX_RPOPRING	"\020\10SOS\7ENSS\6BLKBIP\5DISFS\4BLKBIPO"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TPOPCTRL	"TPOP Control/Diagnostic"
+#define	SUNI_REGO_TPOPCTRL		0x40
+#define	SUNI_REGM_TPOPCTRL_EXCFS	0x80	/* 622 */
+#define	SUNI_REGM_TPOPCTRL_DB3		0x02
+#define	SUNI_REGM_TPOPCTRL_PAIS		0x01
+#define	SUNI_REGM_TPOPCTRL_RESERVED	0x00
+#define	SUNI_REGX_TPOPCTRL	"\020\2DB3\1PAIS"
+#define	SUNI_REGX_TPOPCTRL_622	"\020\4EXCFS\2DB3\1PAIS"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TPOPPTRC "TPOP Pointer Control"
+#define	SUNI_REGO_TPOPPTRC		0x41
+#define	SUNI_REGM_TPOPPTRC_FTPTR	0x40
+#define	SUNI_REGM_TPOPPTRC_SOS		0x20
+#define	SUNI_REGM_TPOPPTRC_PLD		0x10
+#define	SUNI_REGM_TPOPPTRC_NDF		0x08
+#define	SUNI_REGM_TPOPPTRC_NSE		0x04
+#define	SUNI_REGM_TPOPPTRC_PSE		0x02
+#define	SUNI_REGM_TPOPPTRC_RESERVED	0x00
+#define	SUNI_REGX_TPOPPTRC "\020\7FTPTR\6SOS\5PLD\4NDF\3NSE\2PSE"
+
+/* 622 */
+#define	SUNI_REGN_TPOPCP	"TPOP Current Pointer"
+#define	SUNI_REGO_TPOPCP		0x43	/* +44 */
+#define	SUNI_REGM_TPOPCP		0x03
+#define	SUNI_REGS_TPOPCP		0
+#define	SUNI_REGX_TPOPCP	"\020"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TPOPAPTR 	"TPOP Arbitrary Pointer"
+#define	SUNI_REGO_TPOPAPTR		0x45	/* +46 */
+#define	SUNI_REGM_TPOPAPTR_NDF		0xF0
+#define	SUNI_REGS_TPOPAPTR_NDF		4
+#define	SUNI_REGM_TPOPAPTR_S		0x0C
+#define	SUNI_REGS_TPOPAPTR_S		2
+#define	SUNI_REGM_TPOPAPTR		0x03
+#define	SUNI_REGS_TPOPAPTR		0
+#define	SUNI_REGX_TPOPAPTR	"\020\12\x0C\12S\12\xF0\12NDF"
+
+#define	SUNI_REGM_SONET			0
+#define	SUNI_REGM_SDH			2
+
+/* 622 */
+#define	SUNI_REGN_TPOPPT	"TPOP Path Trace"
+#define	SUNI_REGO_TPOPPT		0x47
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TPOPPSL	"TPOP Path Signal Label"
+#define	SUNI_REGO_TPOPPSL		0x48
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TPOPSTATUS "TPOP Path Status"
+#define	SUNI_REGO_TPOPSTATUS		0x49
+#define	SUNI_REGM_TPOPSTATUS_FEBE	0xF0
+#define	SUNI_REGS_TPOPSTATUS_FEBE	4
+#define	SUNI_REGM_TPOPSTATUS_PRDI	0x08
+#define	SUNI_REGM_TPOPSTATUS_G1		0x07
+#define	SUNI_REGS_TPOPSTATUS_G1		0
+#define	SUNI_REGX_TPOPSTATUS "\020\12\xF0\12FEBE\4PRDI\12\x7\12G"
+
+/* 622 */
+#define	SUNI_REGN_TPOPPUC	"TPOP Path User Channel"
+#define	SUNI_REGO_TPOPPUC		0x4A
+
+/* 622 */
+#define	SUNI_REGN_TPOPPG1	"TPOP Path Grow #1"
+#define	SUNI_REGO_TPOPPG1		0x4B
+
+/* 622 */
+#define	SUNI_REGN_TPOPPG2	"TPOP Path Grow #2"
+#define	SUNI_REGO_TPOPPG2		0x4C
+
+/* 622 */
+#define	SUNI_REGN_TPOPPG3	"TPOP Path Grow #3"
+#define	SUNI_REGO_TPOPPG3		0x4D
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_RACPCTRL	"RACP Control/Status"
+#define	SUNI_REGO_RACPCTRL		0x50
+#define	SUNI_REGM_RACPCTRL_OOCDV	0x80
+#define	SUNI_REGM_RACPCTRL_FSEN		0x80
+#define	SUNI_REGM_RACPCTRL_RXPTYP	0x40
+#define	SUNI_REGM_RACPCTRL_PASS		0x20
+#define	SUNI_REGM_RACPCTRL_DISCOR	0x10
+#define	SUNI_REGM_RACPCTRL_HCSPASS	0x08
+#define	SUNI_REGM_RACPCTRL_HCSADD	0x04
+#define	SUNI_REGM_RACPCTRL_DDSCR	0x02
+#define	SUNI_REGM_RACPCTRL_FIFORST	0x01
+#define	SUNI_REGX_RACPCTRL	"\020\10OOCDV\7RXPTYP\6PASS\5DISCO\4HCSPASS\3HCSADD\2DDSCR\1FIFORST"
+#define	SUNI_REGX_RACPCTRL_622	"\020\10FSEN\7RXPTYP\6PASS\5DISCO\4HCSPASS\3HCSADD\2DDSCR\1FIFORST"
+
+/* lite, ultra */
+#define	SUNI_REGN_RACPINTR "RACP Interrupt Enable/Status"
+#define	SUNI_REGO_RACPINTR		0x51
+#define	SUNI_REGM_RACPINTR_OOCDE	0x80
+#define	SUNI_REGM_RACPINTR_HCSE		0x40
+#define	SUNI_REGM_RACPINTR_FIFOE	0x20
+#define	SUNI_REGM_RACPINTR_OOCDI	0x10
+#define	SUNI_REGM_RACPINTR_CHCSI	0x08
+#define	SUNI_REGM_RACPINTR_UHCSI	0x04
+#define	SUNI_REGM_RACPINTR_FOVRI	0x02
+#define	SUNI_REGX_RACPINTR "\020\10OOCDE\7HCSE\6FIFOE\5OOCDI\4CHCSI\3UHCSI\2FOVRI"
+
+/* 622 */
+#define	SUNI_REGN_RACPIS	"RACP Interrupt Status"
+#define	SUNI_REGO_RACPIS		0x51
+#define	SUNI_REGM_RACPIS_OCDV		0x80
+#define	SUNI_REGM_RACPIS_LCDV		0x40
+#define	SUNI_REGM_RACPIS_OCDI		0x20
+#define	SUNI_REGM_RACPIS_LCDI		0x10
+#define	SUNI_REGM_RACPIS_CHCSI		0x08
+#define	SUNI_REGM_RACPIS_UHCSI		0x04
+#define	SUNI_REGM_RACPIS_FOVRI		0x02
+#define	SUNI_REGM_RACPIS_FUDRI		0x01
+#define	SUNI_REGX_RACPIS	"\020\10OCDV\7LCDV\6OCDI\5LCDI\4CHCSI\3UHCSI\2FOVRI\1FUDRI"
+
+/* lite, ultra */
+#define	SUNI_REGN_RACPPATTERN "RACP Match Header Pattern"
+#define	SUNI_REGO_RACPPATTERN		0x52
+#define	SUNI_REGM_RACPPATTERN_GFC	0xF0
+#define	SUNI_REGS_RACPPATTERN_GFC	4
+#define	SUNI_REGM_RACPPATTERN_PTI	0x0E
+#define	SUNI_REGS_RACPPATTERN_PTI	1
+#define	SUNI_REGM_RACPPATTERN_CLP	0x01
+#define	SUNI_REGS_RACPPATTERN_CLP	0
+#define	SUNI_REGX_RACPPATTERN "\020\12\xF0\12GFC\12\x0E\12PTI\1CLP"
+
+/* 622 */
+#define	SUNI_REGN_RACPIEC	"RACP Interrupt Enable/Control"
+#define	SUNI_REGO_RACPIEC		0x52
+#define	SUNI_REGM_RACPIEC_OCDE		0x80
+#define	SUNI_REGM_RACPIEC_LCDE		0x40
+#define	SUNI_REGM_RACPIEC_HCSE		0x20
+#define	SUNI_REGM_RACPIEC_FIFOE		0x10
+#define	SUNI_REGM_RACPIEC_LCDDROP	0x08
+#define	SUNI_REGM_RACPIEC_RCALEVEL0	0x04
+#define	SUNI_REGM_RACPIEC_HCSFTR	0x03
+#define	SUNI_REGX_RACPIEC	"\020\10OCDE\7LCDE\6HCSE\5FIFOE\4LCDDROP\3RCALEVEL0\12\0x3\12HCSFTR"
+
+/* lite, ultra */
+#define	SUNI_REGN_RACPMASK "RACP Match Header Mask"
+#define	SUNI_REGO_RACPMASK		0x53
+#define	SUNI_REGM_RACPMASK_MGFC		0xF0
+#define	SUNI_REGS_RACPMASK_MGFC		4
+#define	SUNI_REGM_RACPMASK_MPTI		0x0E
+#define	SUNI_REGS_RACPMASK_MPTI		1
+#define	SUNI_REGM_RACPMASK_MCLP		0x01
+#define	SUNI_REGS_RACPMASK_MCLP		0
+#define	SUNI_REGX_RACPMASK "\020\12\xF0\12MGFC\12\x0E\12MPTI\1MCLP"
+
+/* 622 */
+#define	SUNI_REGO_RACPPATTERN_622	0x53
+
+/* lite, ultra */
+#define	SUNI_REGN_RACPCHCS "RACP Correctable HCS Error Count"
+#define	SUNI_REGO_RACPCHCS		0x54
+
+/* 622 */
+#define	SUNI_REGO_RACPMASK_622		0x54
+
+/* lite, ultra */
+#define	SUNI_REGN_RACPUHCS "RACP Uncorrectable HCS Error Count"
+#define	SUNI_REGO_RACPUHCS		0x55
+
+/* 622 */
+#define	SUNI_REGO_RACPCHCS_622		0x55	/* +56 */
+#define	SUNI_REGM_RACPCHCS_622		0x0f
+
+/* lite, ultra */
+#define	SUNI_REGN_RACPCNT "RACP Receive Cell Counter"
+#define	SUNI_REGO_RACPCNT		0x56	/* +57,58 */
+#define	SUNI_REGM_RACPCNT		0x07
+
+/* 622 */
+#define	SUNI_REGO_RACPUHCS_622		0x57	/* +58 */
+#define	SUNI_REGM_RACPUHCS_622		0x0f
+
+/* 622 */
+#define	SUNI_REGO_RACPCNT_622		0x59	/* +5A,5B */
+#define	SUNI_REGM_RACPCNT_622		0x1F
+
+/* lite, ultra */
+#define	SUNI_REGN_RACPCFG "RACP Configuration"
+#define	SUNI_REGO_RACPCFG		0x59
+#define	SUNI_REGM_RACPCFG_RGFCE		0xF0
+#define	SUNI_REGS_RACPCFG_RGFCE		4
+#define	SUNI_REGM_RACPCFG_FSEN		0x08
+#define	SUNI_REGM_RACPCFG_LEVEL0	0x04
+#define	SUNI_REGM_RACPCFG_HCSFTR	0x03
+#define	SUNI_REGS_RACPCFG_HCSFTR	0
+#define	SUNI_REGX_RACPCFG "\020\12\xF0\20RGFCE\4FSEN\3RCALEVEL0\12\x03\12HCSFTR"
+
+/* 622 */
+#define	SUNI_REGN_RACPGFC	"RACP GFC Control/Misc. Control"
+#define	SUNI_REGO_RACPGFC		0x5C
+#define	SUNI_REGM_RACPGFC_CDDIS		0x80
+#define	SUNI_REGM_RACPGFC_RXBYTEPRTY	0x40
+#define	SUNI_REGM_RACPGFC_RGFCE		0x0f
+#define	SUNI_REGX_RACPGFC	"\020\10CDDIS\7RXBYTEPRTY\12\xf\20"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TACPCTRL "TACP Control/Status"
+#define	SUNI_REGO_TACPCTRL		0x60
+#define	SUNI_REGM_TACPCTRL_FIFOE	0x80
+#define	SUNI_REGM_TACPCTRL_TSOCI	0x40
+#define	SUNI_REGM_TACPCTRL_FOVRI	0x20
+#define	SUNI_REGM_TACPCTRL_DHCS		0x10
+#define	SUNI_REGM_TACPCTRL_HCSB		0x08	/* ultra, 622 */
+#define	SUNI_REGM_TACPCTRL_HCSADD	0x04
+#define	SUNI_REGM_TACPCTRL_DSCR		0x02
+#define	SUNI_REGM_TACPCTRL_FIFORST	0x01
+#define	SUNI_REGX_TACPCTRL_LITE		"\020\10FIFOE\7TSOCI\6FOVRI\5DHCS\3HCSADD\2DSCR\1FIFORST"
+#define	SUNI_REGX_TACPCTRL_ULTRA	"\020\10FIFOE\7TSOCI\6FOVRI\5DHCS\4HCSB\3HCSADD\2DSCR\1FIFORST"
+#define	SUNI_REGX_TACPCTRL_622		"\020\10FIFOE\7TSOCI\6FOVRI\5DHCS\4HCSB\3HCSADD\2DSCR\1FIFORST"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TACPIDLEH 	"TACP Idle/Unassigned Cell Header Pattern"
+#define	SUNI_REGO_TACPIDLEH		0x61
+#define	SUNI_REGM_TACPIDLEH_GFC		0xF0
+#define	SUNI_REGS_TACPIDLEH_GFC		4
+#define	SUNI_REGM_TACPIDLEH_PTI		0x0E
+#define	SUNI_REGS_TACPIDLEH_PTI		1
+#define	SUNI_REGM_TACPIDLEH_CLP		0x01
+#define	SUNI_REGS_TACPIDLEH_CLP		0
+#define	SUNI_REGX_TACPIDLEH 	"\020\12\xF0\20GFC\12\x0E\20PTI\12\x01\20CLP"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TACPIDLEP "TACP Idle/Unassigned Cell Payload Octet Pattern"
+#define	SUNI_REGO_TACPIDLEP		0x62
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TACPFIFOC		"TACP FIFO Control"
+#define	SUNI_REGO_TACPFIFOC		0x63
+#define	SUNI_REGM_TACPFIFOC_TXPTYP	0x80
+#define	SUNI_REGM_TACPFIFOC_TXPRTYE	0x40
+#define	SUNI_REGM_TACPFIFOC_TXPRTYI	0x10
+#define	SUNI_REGM_TACPFIFOC_TXPRTYI_622	0x30
+#define	SUNI_REGS_TACPFIFOC_TXPRTYI_622	4
+#define	SUNI_REGM_TACPFIFOC_FIFODP	0x0C
+#define	SUNI_REGS_TACPFIFOC_FIFODP	2
+#define	SUNI_REGM_TACPFIFOC_TCALEVEL0	0x02
+#define	SUNI_REGM_TACPFIFOC_HCSCTLEB	0x01
+#define	SUNI_REGM_TACPFIFOC_RESERVED	0x00
+#define	SUNI_REGX_TACPFIFOC		"\020\10TXPTYP\7TXPRTYE\5TXPRTYI\12\x0C\20FIFODP\2TCALEVEL0"
+#define	SUNI_REGX_TACPFIFOC_622		"\020\10TXPTYP\7TXPRTYE\12\x30\12TXPRTYI\12\x0C\20FIFODP\2TCALEVEL0\1HCSCTLEB"
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_TACPCNT "TACP Transmit Cell Counter"
+#define	SUNI_REGO_TACPCNT		0x64	/* +65,66 */
+#define	SUNI_REGM_TACPCNT		0x07
+#define	SUNI_REGM_TACPCNT_622		0x1F
+
+/* lite, ultra */
+#define	SUNI_REGN_TACPCFG "TACP Configuration"
+#define	SUNI_REGO_TACPCFG		0x67
+#define	SUNI_REGM_TACPCFG_TGFCE		0xF0
+#define	SUNI_REGS_TACPCFG_TGFCE		4
+#define	SUNI_REGM_TACPCFG_FSEN		0x08
+#define	SUNI_REGM_TACPCFG_H4INSB	0x04
+#define	SUNI_REGM_TACPCFG_FIXBYTE	0x03
+#define	SUNI_REGS_TACPCFG_FIXBYTE	0
+#define	SUNI_REGX_TACPCFG "\020\12\xF0\20TGFCE\4FSEN\3H4INSB\12\x03\20FIXBYTE"
+
+/* 622 */
+#define	SUNI_REGN_TACPGFC	"TACP Fixed Stuff/GFC"
+#define	SUNI_REGO_TACPGFC		0x67
+#define	SUNI_REGO_TACPGFC_TGFCE		0xf0
+#define	SUNI_REGS_TACPGFC_TGFCE		4
+#define	SUNI_REGO_TACPGFC_FSEN		0x08
+#define	SUNI_REGO_TACPGFC_TXBYTEPRTY	0x04
+#define	SUNI_REGO_TACPGFC_FIXBYTE	0x03
+#define	SUNI_REGS_TACPGFC_FIXBYTE	0
+#define	SUNI_REGX_TACPGFC	"\020\12\xf0\20TGFCE\4FSEN\3TXBYTEPRTY\12\x3\20FIXBYTE"
+
+/* 622 */
+#define	SUNI_REGN_SPTBCTRL	"SPTB Control"
+#define	SUNI_REGO_SPTBCTRL		0x68
+#define	SUNI_REGO_SPTBCTRL_RRAMACC	0x40
+#define	SUNI_REGO_SPTBCTRL_RTIUIE	0x20
+#define	SUNI_REGO_SPTBCTRL_RTIMIE	0x10
+#define	SUNI_REGO_SPTBCTRL_PER5		0x08
+#define	SUNI_REGO_SPTBCTRL_TNULL	0x04
+#define	SUNI_REGO_SPTBCTRL_NOSYNC	0x02
+#define	SUNI_REGO_SPTBCTRL_LEN16	0x01
+#define	SUNI_REGX_SPTBCTRL	"\020\7RRAMACC\6RTIUIE\5RTIMIE\4PER5\3TNULL\2NOSYNC\1LEN16"
+
+/* 622 */
+#define	SUNI_REGN_SPTBPTIS	"SPTB Path Trace Identifier Status"
+#define	SUNI_REGO_SPTBPTIS		0x69
+#define	SUNI_REGM_SPTBPTIS_BUSY		0x80
+#define	SUNI_REGM_SPTBPTIS_RTIUI	0x08
+#define	SUNI_REGM_SPTBPTIS_RTIUV	0x04
+#define	SUNI_REGM_SPTBPTIS_RTIMI	0x02
+#define	SUNI_REGM_SPTBPTIS_RTIMV	0x01
+#define	SUNI_REGX_SPTBPTIS	"\020\10BUSY\4RTIUI\3RTIUV\2RTIMI\1RTIMV"
+
+/* 622 */
+#define	SUNI_REGN_SPTBIAR	"SPTB Indirect Address Register"
+#define	SUNI_REGO_SPTBIAR		0x6A
+#define	SUNI_REGM_SPTBIAR_RWB		0x80
+#define	SUNI_REGM_SPTBIAR_A		0x7f
+#define	SUNI_REGX_SPTBIAR	"\020\10RWB\12\x7f\20A"
+
+/* 622 */
+#define	SUNI_REGN_SPTBIDR	"SPTB Indirect Data Register"
+#define	SUNI_REGO_SPTBIDR		0x6B
+
+/* 622 */
+#define	SUNI_REGN_SPTBEPSL	"SPTB Expected Path Signal Label"
+#define	SUNI_REGO_SPTBEPSL		0x6C
+
+/* 622 */
+#define	SUNI_REGN_SPTBPSLS	"SPTB Path Signal Label Status"
+#define	SUNI_REGO_SPTBPSLS		0x6D
+#define	SUNI_REGM_SPTBPSLS_RPSLUIE	0x80
+#define	SUNI_REGM_SPTBPSLS_RPSLMIE	0x40
+#define	SUNI_REGM_SPTBPSLS_RPSLUI	0x08
+#define	SUNI_REGM_SPTBPSLS_RPSLUV	0x04
+#define	SUNI_REGM_SPTBPSLS_RPSLMI	0x02
+#define	SUNI_REGM_SPTBPSLS_RPSLMV	0x01
+#define	SUNI_REGX_SPTBPSLS	"\020\10RPSLUIE\7RPSLMIE\4RPSLUI\3RPSLUV\2RPSLMI\1RPSLMV"
+
+/* ultra */
+#define	SUNI_REGN_POPCCTRL "POPC Control"
+#define	SUNI_REGO_POPCCTRL		0x68
+#define	SUNI_REGM_POPCCTRL_PDAT		0xC0
+#define	SUNI_REGS_POPCCTRL_PDAT		6
+#define	SUNI_REGM_POPCCTRL_TOGGLE	0x30
+#define	SUNI_REGS_POPCCTRL_TOGGLE	4
+#define	SUNI_REGM_POPCCTRL_TRAFFIC	0x02
+#define	SUNI_REGM_POPCCTRL_ALARM	0x01
+#define	SUNI_REGX_POPCCTRL "\020\12\xC0\20PDAT\12\x30\20TOGGLE\2TRAFFIC\1ALARM"
+
+/* ultra */
+#define	SUNI_REGN_POPCSTROBE0 "POPC Strobe Rate 0"
+#define	SUNI_REGO_POPCSTROBE0		0x69
+
+/* ultra */
+#define	SUNI_REGN_POPCSTROBE1 "POPC Strobe Rate 1"
+#define	SUNI_REGO_POPCSTROBE1		0x6A
+
+/* 622 */
+#define	SUNI_REGN_BERMCTRL	"BERM Control"
+#define	SUNI_REGO_BERMCTRL		0x70
+#define	SUNI_REGM_BERMCTRL_BERTEN	0x80
+#define	SUNI_REGM_BERMCTRL_BERIE	0x01
+#define	SUNI_REGX_BERMCTRL	"\020\10BERTEN\1BERIE"
+
+/* 622 */
+#define	SUNI_REGN_BERMINT	"BERM Interrupt"
+#define	SUNI_REGO_BERMINT		0x71
+#define	SUNI_REGM_BERMINT_TST		0xf0
+#define	SUNI_REGS_BERMINT_TST		4
+#define	SUNI_REGM_BERMINT_BERI		0x01
+#define	SUNI_REGX_BERMINT	"\020\12\xf0\20BERM_TST\1BERI"
+
+/* 622 */
+#define	SUNI_REGN_BERMLAP	"BERM Line BIP Accumulation Period"
+#define	SUNI_REGO_BERMLAP		0x72	/* +73 */
+
+/* 622 */
+#define	SUNI_REGN_BERMLT	"BERM Line BIP Threshold"
+#define	SUNI_REGO_BERMLT		0x74	/* +75 */
+
+/* lite, ultra, 622 */
+#define	SUNI_REGN_MTEST "Master Test"
+#define	SUNI_REGO_MTEST			0x80
+#define	SUNI_REGM_MTEST_DS27_53_622	0x80
+#define	SUNI_REGM_MTEST_BYPASS_ULTRA	0x40
+#define	SUNI_REGM_MTEST_PMCATST_ULTRA	0x20
+#define	SUNI_REGM_MTEST_PMCTST		0x10
+#define	SUNI_REGM_MTEST_DBCTRL		0x08
+#define	SUNI_REGM_MTEST_IOTST		0x04
+#define	SUNI_REGM_MTEST_HIZDATA		0x02
+#define	SUNI_REGM_MTEST_HIZIO		0x01
+#define	SUNI_REGX_MTEST_LITE	"\020\5PMCTST\4DBCTRL\3IOTST\2HIZDATA\1HIZIO"
+#define	SUNI_REGX_MTEST_ULTRA	"\020\7BYPASS\6PMCATST\5PMCTST\4DBCTRL\3IOTST\2HIZDATA\1HIZIO"
+#define	SUNI_REGX_MTEST_622	"\020\10DS27_53\5PMCTST\4DBCTRL\3IOTST\2HIZDATA\1HIZIO"
+
+/*
+ * Printing support
+ */
+#define	SUNI_PRINT_LITE							\
+	{ /* 00 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MRESET, 			\
+	  SUNI_REGN_MRESET,	SUNI_REGX_MRESET_LITE },		\
+	{ /* 01 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MCONFIG,			\
+	  SUNI_REGN_MCONFIG,	SUNI_REGX_MCONFIG_LITE },		\
+	{ /* 02 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MISTATUS,			\
+	  SUNI_REGN_MISTATUS,	SUNI_REGX_MISTATUS_LITE },		\
+	  /* 03 unused */						\
+	{ /* 04 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MCLKM,			\
+	  SUNI_REGN_MCLKM,	SUNI_REGX_MCLKM_LITE },			\
+	{ /* 05 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MCTRL,			\
+	  SUNI_REGN_MCTRL,	SUNI_REGX_MCTRL_LITE },			\
+	{ /* 06 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_CLKSYN,			\
+	  SUNI_REGN_CLKSYN,	SUNI_REGX_CLKSYN_LITE },		\
+	{ /* 07 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_CLKREC_LITE,			\
+	  SUNI_REGN_CLKREC,	SUNI_REGX_CLKREC_LITE },		\
+	  /* 08-0F unused */						\
+	{ /* 10 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RSOPCIE,			\
+	  SUNI_REGN_RSOPCIE,	SUNI_REGX_RSOPCIE },			\
+	{ /* 11 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RSOPSIS,			\
+	  SUNI_REGN_RSOPSIS,	SUNI_REGX_RSOPSIS },			\
+	{ /* 12, 13 */							\
+	  UTP_REGT_INT16,	SUNI_REGO_RSOP_BIP8,			\
+	  SUNI_REGN_RSOP_BIP8,	NULL },					\
+	{ /* 14 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TSOPCTRL,			\
+	  SUNI_REGN_TSOPCTRL,	SUNI_REGX_TSOPCTRL },			\
+	{ /* 15 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TSOPDIAG,			\
+	  SUNI_REGN_TSOPDIAG,	SUNI_REGX_TSOPDIAG },			\
+	  /* 16-17 unused */						\
+	{ /* 18 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RLOPCTRL,			\
+	  SUNI_REGN_RLOPCTRL,	SUNI_REGX_RLOPCTRL },			\
+	{ /* 19 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RLOPINTR,			\
+	  SUNI_REGN_RLOPINTR,	SUNI_REGX_RLOPINTR },			\
+	{ /* 1A, 1B, 1C */						\
+	  UTP_REGT_INT20,	SUNI_REGO_RLOPBIP8_24,			\
+	  SUNI_REGN_RLOPBIP8_24, NULL },				\
+	{ /* 1D, 1E, 1F */						\
+	  UTP_REGT_INT20,	SUNI_REGO_RLOPFEBE,			\
+	  SUNI_REGN_RLOPFEBE,	NULL },					\
+	{ /* 20 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TLOPCTRL,			\
+	  SUNI_REGN_TLOPCTRL,	SUNI_REGX_TLOPCTRL },			\
+	{ /* 21 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TLOPDIAG,			\
+	  SUNI_REGN_TLOPDIAG,	SUNI_REGX_TLOPDIAG },			\
+	  /* 22-2F unused */						\
+	{ /* 30 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPCTRL,			\
+	  SUNI_REGN_RPOPCTRL,	SUNI_REGX_RPOPCTRL },			\
+	{ /* 31 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPISTAT,			\
+	  SUNI_REGN_RPOPISTAT,	SUNI_REGX_RPOPISTAT },			\
+	  /* 32 unused */						\
+	{ /* 33 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPIEN,			\
+	  SUNI_REGN_RPOPIEN,	SUNI_REGX_RPOPIEN },			\
+	  /* 34-36 unused */						\
+	{ /* 37 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_RPOPPSL,			\
+	  SUNI_REGN_RPOPPSL,	NULL },					\
+	{ /* 38, 39 */							\
+	  UTP_REGT_INT16,	SUNI_REGO_RPOPBIP8,			\
+	  SUNI_REGN_RPOPBIP8,	NULL },					\
+	{ /* 3A, 3B */							\
+	  UTP_REGT_INT16,	SUNI_REGO_RPOPFEBE,			\
+	  SUNI_REGN_RPOPFEBE,	NULL },					\
+	  /* 3C unused */						\
+	{ /* 3D */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPBIP8CFG,			\
+	  SUNI_REGN_RPOPBIP8CFG, SUNI_REGX_RPOPBIP8CFG },		\
+	  /* 3E-3F unused */						\
+	{ /* 40 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TPOPCTRL,			\
+	  SUNI_REGN_TPOPCTRL,	SUNI_REGX_TPOPCTRL },			\
+	{ /* 41 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TPOPPTRC,			\
+	  SUNI_REGN_TPOPPTRC,	SUNI_REGX_TPOPPTRC },			\
+	  /* 42-44 unused */						\
+	{ /* 45, 46 */							\
+	  UTP_REGT_INT10BITS,	SUNI_REGO_TPOPAPTR,			\
+	  SUNI_REGN_TPOPAPTR,	SUNI_REGX_TPOPAPTR },			\
+	  /* 47 unused */						\
+	{ /* 48 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TPOPPSL,			\
+	  SUNI_REGN_TPOPPSL,	NULL },					\
+	{ /* 49 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TPOPSTATUS,			\
+	  SUNI_REGN_TPOPSTATUS,	SUNI_REGX_TPOPSTATUS },			\
+	  /* 4A-4F unused */						\
+	{ /* 50 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPCTRL,			\
+	  SUNI_REGN_RACPCTRL,	SUNI_REGX_RACPCTRL },			\
+	{ /* 51 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPINTR,			\
+	  SUNI_REGN_RACPINTR,	SUNI_REGX_RACPINTR },			\
+	{ /* 52 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPPATTERN,			\
+	  SUNI_REGN_RACPPATTERN, SUNI_REGX_RACPPATTERN },		\
+	{ /* 53 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPMASK,			\
+	  SUNI_REGN_RACPMASK,	SUNI_REGX_RACPMASK },			\
+	{ /* 54 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_RACPCHCS,			\
+	  SUNI_REGN_RACPCHCS,	NULL },					\
+	{ /* 55 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_RACPUHCS,			\
+	  SUNI_REGN_RACPUHCS,	NULL },					\
+	{ /* 56, 57, 58 */						\
+	  UTP_REGT_INT19,	SUNI_REGO_RACPCNT,			\
+	  SUNI_REGN_RACPCNT,	NULL },					\
+	{ /* 59 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPCFG,			\
+	  SUNI_REGN_RACPCFG,	SUNI_REGX_RACPCFG },			\
+	  /* 5A-5F unused */						\
+	{ /* 60 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPCTRL,			\
+	  SUNI_REGN_TACPCTRL,	SUNI_REGX_TACPCTRL_LITE },		\
+	{ /* 61 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPIDLEH,			\
+	  SUNI_REGN_TACPIDLEH,	SUNI_REGX_TACPIDLEH },			\
+	{ /* 62 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TACPIDLEP,			\
+	  SUNI_REGN_TACPIDLEP,	NULL },					\
+	{ /* 63 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPFIFOC,			\
+	  SUNI_REGN_TACPFIFOC,	SUNI_REGX_TACPFIFOC },			\
+	{ /* 64, 65, 66 */						\
+	  UTP_REGT_INT19,	SUNI_REGO_TACPCNT,			\
+	  SUNI_REGN_TACPCNT,	NULL },					\
+	{ /* 67 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPGFC,			\
+	  SUNI_REGN_TACPGFC,	SUNI_REGX_TACPGFC },			\
+	  /* 68-7f unused */						\
+	{ /* 80 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MTEST,			\
+	  SUNI_REGN_MTEST,	SUNI_REGX_MTEST_LITE }
+
+#define	SUNI_PRINT_ULTRA						\
+	{ /* 00 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MRESET, 			\
+	  SUNI_REGN_MRESET,	SUNI_REGX_MRESET_ULTRA },		\
+	{ /* 01 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MCONFIG,			\
+	  SUNI_REGN_MCONFIG,	SUNI_REGX_MCONFIG_ULTRA },		\
+	{ /* 02 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MISTATUS,			\
+	  SUNI_REGN_MISTATUS,	SUNI_REGX_MISTATUS_ULTRA },		\
+	{ /* 03 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MMCTRL,			\
+	  SUNI_REGN_MMCTRL,	SUNI_REGX_MMCTRL },			\
+	{ /* 04 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MCLKM,			\
+	  SUNI_REGN_MCLKM,	SUNI_REGX_MCLKM_ULTRA },		\
+	{ /* 05 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MCTRL,			\
+	  SUNI_REGN_MCTRL,	SUNI_REGX_MCTRL_ULTRA },		\
+	{ /* 06 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_CLKSYN,			\
+	  SUNI_REGN_CLKSYN,	SUNI_REGX_CLKSYN_ULTRA },		\
+	  /* 07 unused */						\
+	{ /* 08 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_CLKREC_ULTRA,			\
+	  SUNI_REGN_CLKREC,	SUNI_REGX_CLKREC_ULTRA },		\
+	{ /* 09 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_CLKRECCFG,			\
+	  SUNI_REGN_CLKRECCFG,	SUNI_REGX_CLKRECCFG },			\
+	{ /* 0A */							\
+	  UTP_REGT_BITS,	SUNI_REGO_LTXCFG1,			\
+	  SUNI_REGN_LTXCFG1,	SUNI_REGX_LTXCFG1 },			\
+	{ /* 0B */							\
+	  UTP_REGT_BITS,	SUNI_REGO_LTXCFG2,			\
+	  SUNI_REGN_LTXCFG2,	SUNI_REGX_LTXCFG2 },			\
+	{ /* 0C */							\
+	  UTP_REGT_BITS,	SUNI_REGO_LRXCFG,			\
+	  SUNI_REGN_LRXCFG,	SUNI_REGX_LRXCFG },			\
+	  /* 0D-0F unused */						\
+	{ /* 10 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RSOPCIE,			\
+	  SUNI_REGN_RSOPCIE,	SUNI_REGX_RSOPCIE },			\
+	{ /* 11 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RSOPSIS,			\
+	  SUNI_REGN_RSOPSIS,	SUNI_REGX_RSOPSIS },			\
+	{ /* 12, 13 */							\
+	  UTP_REGT_INT16,	SUNI_REGO_RSOP_BIP8,			\
+	  SUNI_REGN_RSOP_BIP8,	NULL },					\
+	{ /* 14 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TSOPCTRL,			\
+	  SUNI_REGN_TSOPCTRL,	SUNI_REGX_TSOPCTRL },			\
+	{ /* 15 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TSOPDIAG,			\
+	  SUNI_REGN_TSOPDIAG,	SUNI_REGX_TSOPDIAG },			\
+	  /* 16-17 unused */						\
+	{ /* 18 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RLOPCTRL,			\
+	  SUNI_REGN_RLOPCTRL,	SUNI_REGX_RLOPCTRL },			\
+	{ /* 19 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RLOPINTR,			\
+	  SUNI_REGN_RLOPINTR,	SUNI_REGX_RLOPINTR },			\
+	{ /* 1A, 1B, 1C */						\
+	  UTP_REGT_INT20,	SUNI_REGO_RLOPBIP8_24,			\
+	  SUNI_REGN_RLOPBIP8_24, NULL },				\
+	{ /* 1D, 1E, 1F */						\
+	  UTP_REGT_INT20,	SUNI_REGO_RLOPFEBE,			\
+	  SUNI_REGN_RLOPFEBE,	NULL },					\
+	{ /* 20 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TLOPCTRL,			\
+	  SUNI_REGN_TLOPCTRL,	SUNI_REGX_TLOPCTRL },			\
+	{ /* 21 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TLOPDIAG,			\
+	  SUNI_REGN_TLOPDIAG,	SUNI_REGX_TLOPDIAG },			\
+	  /* 22-2F unused */						\
+	{ /* 30 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPCTRL,			\
+	  SUNI_REGN_RPOPCTRL,	SUNI_REGX_RPOPCTRL },			\
+	{ /* 31 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPISTAT,			\
+	  SUNI_REGN_RPOPISTAT,	SUNI_REGX_RPOPISTAT },			\
+	  /* 32 unused */						\
+	{ /* 33 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPIEN,			\
+	  SUNI_REGN_RPOPIEN,	SUNI_REGX_RPOPIEN },			\
+	  /* 34-36 unused */						\
+	{ /* 37 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_RPOPPSL,			\
+	  SUNI_REGN_RPOPPSL,	NULL },					\
+	{ /* 38, 39 */							\
+	  UTP_REGT_INT16,	SUNI_REGO_RPOPBIP8,			\
+	  SUNI_REGN_RPOPBIP8,	NULL },					\
+	{ /* 3A, 3B */							\
+	  UTP_REGT_INT16,	SUNI_REGO_RPOPFEBE,			\
+	  SUNI_REGN_RPOPFEBE,	NULL },					\
+	  /* 3C unused */						\
+	{ /* 3D */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPBIP8CFG,			\
+	  SUNI_REGN_RPOPBIP8CFG, SUNI_REGX_RPOPBIP8CFG },		\
+	  /* 3E-3F unused */						\
+	{ /* 40 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TPOPCTRL,			\
+	  SUNI_REGN_TPOPCTRL,	SUNI_REGX_TPOPCTRL },			\
+	{ /* 41 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TPOPPTRC,			\
+	  SUNI_REGN_TPOPPTRC,	SUNI_REGX_TPOPPTRC },			\
+	  /* 42-44 unused */						\
+	{ /* 45, 46 */							\
+	  UTP_REGT_INT10BITS,	SUNI_REGO_TPOPAPTR,			\
+	  SUNI_REGN_TPOPAPTR,	SUNI_REGX_TPOPAPTR },			\
+	  /* 47 unused */						\
+	{ /* 48 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TPOPPSL,			\
+	  SUNI_REGN_TPOPPSL,	NULL },					\
+	{ /* 49 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TPOPSTATUS,			\
+	  SUNI_REGN_TPOPSTATUS,	SUNI_REGX_TPOPSTATUS },			\
+	  /* 4A-4F unused */						\
+	{ /* 50 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPCTRL,			\
+	  SUNI_REGN_RACPCTRL,	SUNI_REGX_RACPCTRL },			\
+	{ /* 51 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPINTR,			\
+	  SUNI_REGN_RACPINTR,	SUNI_REGX_RACPINTR },			\
+	{ /* 52 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPPATTERN,			\
+	  SUNI_REGN_RACPPATTERN, SUNI_REGX_RACPPATTERN },		\
+	{ /* 53 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPMASK,			\
+	  SUNI_REGN_RACPMASK,	SUNI_REGX_RACPMASK },			\
+	{ /* 54 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_RACPCHCS,			\
+	  SUNI_REGN_RACPCHCS,	NULL },					\
+	{ /* 55 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_RACPUHCS,			\
+	  SUNI_REGN_RACPUHCS,	NULL },					\
+	{ /* 56, 57, 58 */						\
+	  UTP_REGT_INT19,	SUNI_REGO_RACPCNT,			\
+	  SUNI_REGN_RACPCNT,	NULL },					\
+	{ /* 59 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPCFG,			\
+	  SUNI_REGN_RACPCFG,	SUNI_REGX_RACPCFG },			\
+	  /* 5A-5F unused */						\
+	{ /* 60 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPCTRL,			\
+	  SUNI_REGN_TACPCTRL,	SUNI_REGX_TACPCTRL_ULTRA },		\
+	{ /* 61 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPIDLEH,			\
+	  SUNI_REGN_TACPIDLEH,	SUNI_REGX_TACPIDLEH },			\
+	{ /* 62 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TACPIDLEP,			\
+	  SUNI_REGN_TACPIDLEP,	NULL },					\
+	{ /* 63 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPFIFOC,			\
+	  SUNI_REGN_TACPFIFOC,	SUNI_REGX_TACPFIFOC },			\
+	{ /* 64, 65, 66 */						\
+	  UTP_REGT_INT19,	SUNI_REGO_TACPCNT,			\
+	  SUNI_REGN_TACPCNT,	NULL },					\
+	{ /* 67 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPGFC,			\
+	  SUNI_REGN_TACPGFC,	SUNI_REGX_TACPGFC },			\
+	{ /* 68 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_POPCCTRL,			\
+	  SUNI_REGN_POPCCTRL,	SUNI_REGX_POPCCTRL },			\
+	{ /* 69 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_POPCSTROBE0,			\
+	  SUNI_REGN_POPCSTROBE0, NULL },				\
+	{ /* 6A */							\
+	  UTP_REGT_INT8,	SUNI_REGO_POPCSTROBE1,			\
+	  SUNI_REGN_POPCSTROBE1, NULL },				\
+	  /* 6B-7f unused */						\
+	{ /* 80 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MTEST,			\
+	  SUNI_REGN_MTEST,	SUNI_REGX_MTEST_ULTRA }
+
+#define	SUNI_PRINT_622 							\
+	{ /* 00 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MRESET, 			\
+	  SUNI_REGN_MRESET,	SUNI_REGX_MRESET_622 },			\
+	{ /* 01 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MCONFIG,			\
+	  SUNI_REGN_MCONFIG,	SUNI_REGX_MCONFIG_622 },		\
+	{ /* 02 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MISTATUS,			\
+	  SUNI_REGN_MISTATUS,	SUNI_REGX_MISTATUS_622 },		\
+	{ /* 03 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_PISO, 			\
+	  SUNI_REGN_PISO,	SUNI_REGX_PISO },			\
+	{ /* 04 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MCTRLM, 			\
+	  SUNI_REGN_MCTRLM,	SUNI_REGX_MCTRLM },			\
+	{ /* 05 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MALARM,			\
+	  SUNI_REGN_MALARM,	SUNI_REGX_MALARM },			\
+	{ /* 06 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_POUT,				\
+	  SUNI_REGN_POUT,	SUNI_REGX_POUT },			\
+	{ /* 07 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_PIN,				\
+	  SUNI_REGN_PIN,	NULL },					\
+	{ /* 08 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_PINV,				\
+	  SUNI_REGN_PINV,	SUNI_REGX_PINV },			\
+	{ /* 09 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_PINE,				\
+	  SUNI_REGN_PINE,	NULL },					\
+	{ /* 0A */							\
+	  UTP_REGT_INT8,	SUNI_REGO_XC1,				\
+	  SUNI_REGN_XC1,	NULL },					\
+	{ /* 0B */							\
+	  UTP_REGT_BITS,	SUNI_REGO_APSCS,			\
+	  SUNI_REGN_APSCS,	SUNI_REGX_APSCS },			\
+	{ /* 0C */							\
+	  UTP_REGT_INT8,	SUNI_REGO_RK1,				\
+	  SUNI_REGN_RK1,	NULL },					\
+	{ /* 0D */							\
+	  UTP_REGT_INT8,	SUNI_REGO_RK2,				\
+	  SUNI_REGN_RK2,	NULL },					\
+	{ /* 0E */							\
+	  UTP_REGT_INT8,	SUNI_REGO_RZ1,				\
+	  SUNI_REGN_RZ1,	NULL },					\
+	{ /* 0F */							\
+	  UTP_REGT_INT8,	SUNI_REGO_XZ1,				\
+	  SUNI_REGN_XZ1,	NULL },					\
+	{ /* 10 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RSOPCIE,			\
+	  SUNI_REGN_RSOPCIE,	SUNI_REGX_RSOPCIE_622 },		\
+	{ /* 11 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RSOPSIS,			\
+	  SUNI_REGN_RSOPSIS,	SUNI_REGX_RSOPSIS },			\
+	{ /* 12, 13 */							\
+	  UTP_REGT_INT16,	SUNI_REGO_RSOP_BIP8,			\
+	  SUNI_REGN_RSOP_BIP8,	NULL },					\
+	{ /* 14 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TSOPCTRL,			\
+	  SUNI_REGN_TSOPCTRL,	SUNI_REGX_TSOPCTRL },			\
+	{ /* 15 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TSOPDIAG,			\
+	  SUNI_REGN_TSOPDIAG,	SUNI_REGX_TSOPDIAG },			\
+	  /* 16-17 unused */						\
+	{ /* 18 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RLOPCTRL,			\
+	  SUNI_REGN_RLOPCTRL,	SUNI_REGX_RLOPCTRL_622 },		\
+	{ /* 19 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RLOPINTR,			\
+	  SUNI_REGN_RLOPINTR,	SUNI_REGX_RLOPINTR },			\
+	{ /* 1A, 1B, 1C */						\
+	  UTP_REGT_INT20,	SUNI_REGO_RLOPBIP8_24_96,		\
+	  SUNI_REGN_RLOPBIP8_24_96, NULL },				\
+	{ /* 1D, 1E, 1F */						\
+	  UTP_REGT_INT20,	SUNI_REGO_RLOPFEBE,			\
+	  SUNI_REGN_RLOPFEBE,	NULL },					\
+	{ /* 20 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TLOPCTRL,			\
+	  SUNI_REGN_TLOPCTRL,	SUNI_REGX_TLOPCTRL_622 },		\
+	{ /* 21 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TLOPDIAG,			\
+	  SUNI_REGN_TLOPDIAG,	SUNI_REGX_TLOPDIAG },			\
+	{ /* 22 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TLOP_XK1,			\
+	  SUNI_REGN_TLOP_XK1,	NULL },					\
+	{ /* 23 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TLOP_XK2,			\
+	  SUNI_REGN_TLOP_XK2,	NULL },					\
+	  /* 24-27 unused */						\
+	{ /* 28 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_SSTBCTRL,			\
+	  SUNI_REGN_SSTBCTRL,	SUNI_REGX_SSTBCTRL },			\
+	{ /* 29 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_SSTBSTIS,			\
+	  SUNI_REGN_SSTBSTIS,	SUNI_REGX_SSTBSTIS },			\
+	{ /* 2A */							\
+	  UTP_REGT_BITS,	SUNI_REGO_SSTBIAR,			\
+	  SUNI_REGN_SSTBIAR,	SUNI_REGX_SSTBIAR },			\
+	{ /* 2B */							\
+	  UTP_REGT_INT8,	SUNI_REGO_SSTBIDR,			\
+	  SUNI_REGN_SSTBIDR,	NULL },					\
+	  /* 2C unused (see chip errata) */				\
+	{ /* 2D */							\
+	  UTP_REGT_BITS,	SUNI_REGO_SSTBCSMS,			\
+	  SUNI_REGN_SSTBCSMS,	SUNI_REGX_SSTBCSMS },			\
+	  /* 2E-2F unused */						\
+	{ /* 30 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPCTRL,			\
+	  SUNI_REGN_RPOPCTRL,	SUNI_REGX_RPOPCTRL_622 },		\
+	{ /* 31 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPISTAT,			\
+	  SUNI_REGN_RPOPISTAT,	SUNI_REGX_RPOPISTAT },			\
+	{ /* 32 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPPIS,			\
+	  SUNI_REGN_RPOPPIS,	SUNI_REGX_RPOPPIS },			\
+	{ /* 33 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPIEN,			\
+	  SUNI_REGN_RPOPIEN,	SUNI_REGX_RPOPIEN },			\
+	{ /* 34 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPPIE,			\
+	  SUNI_REGN_RPOPPIE,	SUNI_REGX_RPOPPIE },			\
+	{ /* 35, 36 */							\
+	  UTP_REGT_INT10BITS,	SUNI_REGO_RPOPPTR,			\
+	  SUNI_REGN_RPOPPTR,	SUNI_REGX_RPOPPTR },			\
+	{ /* 37 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_RPOPPSL,			\
+	  SUNI_REGN_RPOPPSL,	NULL },					\
+	{ /* 38, 39 */							\
+	  UTP_REGT_INT16,	SUNI_REGO_RPOPBIP8,			\
+	  SUNI_REGN_RPOPBIP8,	NULL },					\
+	{ /* 3A, 3B */							\
+	  UTP_REGT_INT16,	SUNI_REGO_RPOPFEBE,			\
+	  SUNI_REGN_RPOPFEBE,	NULL },					\
+	{ /* 3C */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPRDI,			\
+	  SUNI_REGN_RPOPRDI,	SUNI_REGX_RPOPRDI },			\
+	{ /* 3D */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RPOPRING,			\
+	  SUNI_REGN_RPOPRING,	SUNI_REGX_RPOPRING },			\
+	  /* 3E-3F unused */						\
+	{ /* 40 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TPOPCTRL,			\
+	  SUNI_REGN_TPOPCTRL,	SUNI_REGX_TPOPCTRL_622 },		\
+	{ /* 41 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TPOPPTRC,			\
+	  SUNI_REGN_TPOPPTRC,	SUNI_REGX_TPOPPTRC },			\
+	  /* 42 unused */						\
+	{ /* 43, 44 */							\
+	  UTP_REGT_INT10BITS,	SUNI_REGO_TPOPCP,			\
+	  SUNI_REGN_TPOPCP,	SUNI_REGX_TPOPCP },			\
+	{ /* 45, 46 */							\
+	  UTP_REGT_INT10BITS,	SUNI_REGO_TPOPAPTR,			\
+	  SUNI_REGN_TPOPAPTR,	SUNI_REGX_TPOPAPTR },			\
+	{ /* 47 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TPOPPT,			\
+	  SUNI_REGN_TPOPPT,	NULL },					\
+	{ /* 48 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TPOPPSL,			\
+	  SUNI_REGN_TPOPPSL,	NULL },					\
+	{ /* 49 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TPOPSTATUS,			\
+	  SUNI_REGN_TPOPSTATUS,	SUNI_REGX_TPOPSTATUS },			\
+	{ /* 4A */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TPOPPUC,			\
+	  SUNI_REGN_TPOPPUC,	NULL },					\
+	{ /* 4B */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TPOPPG1,			\
+	  SUNI_REGN_TPOPPG1,	NULL },					\
+	{ /* 4C */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TPOPPG2,			\
+	  SUNI_REGN_TPOPPG2,	NULL },					\
+	{ /* 4D */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TPOPPG3,			\
+	  SUNI_REGN_TPOPPG3,	NULL },					\
+	  /* 4E-4F unused */						\
+	{ /* 50 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPCTRL,			\
+	  SUNI_REGN_RACPCTRL,	SUNI_REGX_RACPCTRL_622 },		\
+	{ /* 51 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPIS,			\
+	  SUNI_REGN_RACPIS,	SUNI_REGX_RACPIS },			\
+	{ /* 52 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPIEC,			\
+	  SUNI_REGN_RACPIEC,	SUNI_REGX_RACPIEC },			\
+	{ /* 53 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPPATTERN_622,		\
+	  SUNI_REGN_RACPPATTERN, SUNI_REGX_RACPPATTERN },		\
+	{ /* 54 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPMASK_622,			\
+	  SUNI_REGN_RACPMASK,	SUNI_REGX_RACPMASK },			\
+	{ /* 55, 56 */							\
+	  UTP_REGT_INT12,	SUNI_REGO_RACPCHCS_622,			\
+	  SUNI_REGN_RACPCHCS,	NULL },					\
+	{ /* 57, 58 */							\
+	  UTP_REGT_INT12,	SUNI_REGO_RACPUHCS_622,			\
+	  SUNI_REGN_RACPUHCS,	NULL },					\
+	{ /* 59, 5A, 5B */						\
+	  UTP_REGT_INT21,	SUNI_REGO_RACPCNT_622,			\
+	  SUNI_REGN_RACPCNT,	NULL },					\
+	{ /* 5C */							\
+	  UTP_REGT_BITS,	SUNI_REGO_RACPGFC,			\
+	  SUNI_REGN_RACPGFC,	SUNI_REGX_RACPGFC },			\
+	  /* 5D-5F unused */						\
+	{ /* 60 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPCTRL,			\
+	  SUNI_REGN_TACPCTRL,	SUNI_REGX_TACPCTRL_622 },		\
+	{ /* 61 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPIDLEH,			\
+	  SUNI_REGN_TACPIDLEH,	SUNI_REGX_TACPIDLEH },			\
+	{ /* 62 */							\
+	  UTP_REGT_INT8,	SUNI_REGO_TACPIDLEP,			\
+	  SUNI_REGN_TACPIDLEP,	NULL },					\
+	{ /* 63 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPFIFOC,			\
+	  SUNI_REGN_TACPFIFOC,	SUNI_REGX_TACPFIFOC_622 },		\
+	{ /* 64, 65, 66 */						\
+	  UTP_REGT_INT21,	SUNI_REGO_TACPCNT,			\
+	  SUNI_REGN_TACPCNT,	NULL },					\
+	{ /* 67 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_TACPGFC,			\
+	  SUNI_REGN_TACPGFC,	SUNI_REGX_TACPGFC },			\
+	{ /* 68 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_SPTBCTRL,			\
+	  SUNI_REGN_SPTBCTRL,	SUNI_REGX_SPTBCTRL },			\
+	{ /* 69 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_SPTBPTIS,			\
+	  SUNI_REGN_SPTBPTIS,	SUNI_REGX_SPTBPTIS },			\
+	{ /* 6A */							\
+	  UTP_REGT_BITS,	SUNI_REGO_SPTBIAR,			\
+	  SUNI_REGN_SPTBIAR,	SUNI_REGX_SPTBIAR },			\
+	{ /* 6B */							\
+	  UTP_REGT_INT8,	SUNI_REGO_SPTBIDR,			\
+	  SUNI_REGN_SPTBIDR,	NULL },					\
+	{ /* 6C */							\
+	  UTP_REGT_INT8,	SUNI_REGO_SPTBEPSL,			\
+	  SUNI_REGN_SPTBEPSL,	NULL },					\
+	{ /* 6D */							\
+	  UTP_REGT_BITS,	SUNI_REGO_SPTBPSLS,			\
+	  SUNI_REGN_SPTBPSLS,	SUNI_REGX_SPTBPSLS },			\
+	  /* 6E-6F unused */						\
+	{ /* 70 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_BERMCTRL,			\
+	  SUNI_REGN_BERMCTRL,	SUNI_REGX_BERMCTRL },			\
+	{ /* 71 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_BERMINT,			\
+	  SUNI_REGN_BERMINT,	SUNI_REGX_BERMINT },			\
+	{ /* 72, 73 */							\
+	  UTP_REGT_INT16,	SUNI_REGO_BERMLAP,			\
+	  SUNI_REGN_BERMLAP,	NULL },					\
+	{ /* 74, 75 */							\
+	  UTP_REGT_INT16,	SUNI_REGO_BERMLT,			\
+	  SUNI_REGN_BERMLT,	NULL },					\
+	  /* 76-7f unused */						\
+	{ /* 80 */							\
+	  UTP_REGT_BITS,	SUNI_REGO_MTEST,			\
+	  SUNI_REGN_MTEST,	SUNI_REGX_MTEST_622 }
+
+#endif /* _DEV_UTOPIA_SUNI_H */
diff --git a/sys/dev/utopia/utopia.c b/sys/dev/utopia/utopia.c
new file mode 100644
index 000000000000..7480efc3da6f
--- /dev/null
+++ b/sys/dev/utopia/utopia.c
@@ -0,0 +1,676 @@
+/*-
+ * Copyright (c) 2003
+ *	Fraunhofer Institute for Open Communication Systems (FhG Fokus).
+ * 	All rights reserved.
+ *
+ * Author: Hartmut Brandt <harti@freebsd.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/unistd.h>
+#include <sys/kernel.h>
+#include <sys/kthread.h>
+#include <sys/proc.h>
+#include <sys/bus.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/sysctl.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/if_var.h>
+#include <net/if_media.h>
+#include <net/if_atm.h>
+
+#include <dev/utopia/suni.h>
+#include <dev/utopia/idtphy.h>
+#include <dev/utopia/utopia.h>
+#include <dev/utopia/utopia_priv.h>
+
+/* known chips */
+extern const struct utopia_chip utopia_chip_idt77155;
+extern const struct utopia_chip utopia_chip_idt77105;
+extern const struct utopia_chip utopia_chip_lite;
+extern const struct utopia_chip utopia_chip_ultra;
+extern const struct utopia_chip utopia_chip_622;
+
+/*
+ * Global list of all registered interfaces
+ */
+static struct mtx utopia_list_mtx;
+static LIST_HEAD(, utopia) utopia_list = LIST_HEAD_INITIALIZER(utopia_list);
+
+#define UTP_RLOCK_LIST()	mtx_lock(&utopia_list_mtx)
+#define UTP_RUNLOCK_LIST()	mtx_unlock(&utopia_list_mtx)
+#define UTP_WLOCK_LIST()	mtx_lock(&utopia_list_mtx)
+#define UTP_WUNLOCK_LIST()	mtx_unlock(&utopia_list_mtx)
+
+#define UTP_LOCK(UTP)		mtx_lock((UTP)->lock)
+#define UTP_UNLOCK(UTP)		mtx_unlock((UTP)->lock)
+#define UTP_LOCK_ASSERT(UTP)	mtx_assert((UTP)->lock, MA_OWNED)
+
+static struct proc *utopia_kproc;
+
+static void utopia_dump(struct utopia *) __unused;
+
+/*
+ * Read a multi-register value.
+ */
+uint32_t
+utopia_update(struct utopia *utp, u_int reg, u_int nreg, uint32_t mask)
+{
+	int err;
+	u_int n;
+	uint8_t regs[4];
+	uint32_t val;
+
+	n = nreg;
+	if ((err = UTP_READREGS(utp, reg, regs, &n)) != 0) {
+#ifdef DIAGNOSTIC
+		printf("%s: register read error %s(%u,%u): %d\n", __func__,
+		    utp->chip->name, reg, nreg, err);
+#endif
+		return (0);
+	}
+	if (n < nreg) {
+#ifdef DIAGNOSTIC
+		printf("%s: got only %u regs %s(%u,%u): %d\n", __func__, n,
+		    utp->chip->name, reg, nreg, err);
+#endif
+		return (0);
+	}
+	val = 0;
+	for (n = nreg; n > 0; n--) {
+		val <<= 8;
+		val |= regs[n - 1];
+	}
+	return (val & mask);
+}
+
+/*
+ * Debugging - dump all registers.
+ */
+static void
+utopia_dump(struct utopia *utp)
+{
+	uint8_t regs[256];
+	u_int n = 256, i;
+	int err;
+
+	if ((err = UTP_READREGS(utp, 0, regs, &n)) != 0) {
+		printf("UTOPIA reg read error %d\n", err);
+		return;
+	}
+	for (i = 0; i < n; i++) {
+		if (i % 16 == 0)
+			printf("%02x:", i);
+		if (i % 16 == 8)
+			printf(" ");
+		printf(" %02x", regs[i]);
+		if (i % 16 == 15)
+			printf("\n");
+	}
+	if (i % 16 != 0)
+		printf("\n");
+}
+
+/*
+ * Update the carrier status
+ */
+void
+utopia_check_carrier(struct utopia *utp, u_int carr_ok)
+{
+	int old;
+
+	old = utp->carrier;
+	if (carr_ok) {
+		/* carrier */
+		utp->carrier = UTP_CARR_OK;
+		if (old != UTP_CARR_OK) {
+			if_printf(utp->ifatm->ifp, "carrier detected\n");
+			ATMEV_SEND_IFSTATE_CHANGED(utp->ifatm, 1);
+		}
+	} else {
+		/* no carrier */
+		utp->carrier = UTP_CARR_LOST;
+		if (old == UTP_CARR_OK) {
+			if_printf(utp->ifatm->ifp, "carrier lost\n");
+			ATMEV_SEND_IFSTATE_CHANGED(utp->ifatm, 0);
+		}
+	}
+}
+
+static int
+unknown_inval(struct utopia *utp, int what __unused)
+{
+
+	return (EINVAL);
+}
+
+static int
+unknown_reset(struct utopia *utp __unused)
+{
+	return (EIO);
+}
+
+static int
+unknown_update_carrier(struct utopia *utp)
+{
+	utp->carrier = UTP_CARR_UNKNOWN;
+	return (0);
+}
+
+static int
+unknown_set_loopback(struct utopia *utp __unused, u_int mode __unused)
+{
+	return (EINVAL);
+}
+
+static void
+unknown_intr(struct utopia *utp __unused)
+{
+}
+
+static void
+unknown_update_stats(struct utopia *utp __unused)
+{
+}
+
+static const struct utopia_chip utopia_chip_unknown = {
+	UTP_TYPE_UNKNOWN,
+	"unknown",
+	0,
+	unknown_reset,
+	unknown_inval,
+	unknown_inval,
+	unknown_inval,
+	unknown_update_carrier,
+	unknown_set_loopback,
+	unknown_intr,
+	unknown_update_stats,
+};
+
+/*
+ * Callbacks for the ifmedia infrastructure.
+ */
+static int
+utopia_media_change(struct ifnet *ifp)
+{
+	struct ifatm *ifatm = IFP2IFATM(ifp);
+	struct utopia *utp = ifatm->phy;
+	int error = 0;
+
+	UTP_LOCK(utp);
+	if (utp->chip->type != UTP_TYPE_UNKNOWN && utp->state & UTP_ST_ACTIVE) {
+		if (utp->media->ifm_media & IFM_ATM_SDH) {
+			if (!(utp->state & UTP_ST_SDH))
+				error = utopia_set_sdh(utp, 1);
+		} else {
+			if (utp->state & UTP_ST_SDH)
+				error = utopia_set_sdh(utp, 0);
+		}
+		if (utp->media->ifm_media & IFM_ATM_UNASSIGNED) {
+			if (!(utp->state & UTP_ST_UNASS))
+				error = utopia_set_unass(utp, 1);
+		} else {
+			if (utp->state & UTP_ST_UNASS)
+				error = utopia_set_unass(utp, 0);
+		}
+		if (utp->media->ifm_media & IFM_ATM_NOSCRAMB) {
+			if (!(utp->state & UTP_ST_NOSCRAMB))
+				error = utopia_set_noscramb(utp, 1);
+		} else {
+			if (utp->state & UTP_ST_NOSCRAMB)
+				error = utopia_set_noscramb(utp, 0);
+		}
+	} else
+		error = EIO;
+	UTP_UNLOCK(utp);
+	return (error);
+}
+
+/*
+ * Look at the carrier status.
+ */
+static void
+utopia_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+	struct utopia *utp = IFP2IFATM(ifp)->phy;
+
+	UTP_LOCK(utp);
+	if (utp->chip->type != UTP_TYPE_UNKNOWN && utp->state & UTP_ST_ACTIVE) {
+		ifmr->ifm_active = IFM_ATM | utp->ifatm->mib.media;
+
+		switch (utp->carrier) {
+
+		  case UTP_CARR_OK:
+			ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
+			break;
+
+		  case UTP_CARR_LOST:
+			ifmr->ifm_status = IFM_AVALID;
+			break;
+
+		  default:
+			ifmr->ifm_status = 0;
+			break;
+		}
+		if (utp->state & UTP_ST_SDH) {
+			ifmr->ifm_active |= IFM_ATM_SDH;
+			ifmr->ifm_current |= IFM_ATM_SDH;
+		}
+		if (utp->state & UTP_ST_UNASS) {
+			ifmr->ifm_active |= IFM_ATM_UNASSIGNED;
+			ifmr->ifm_current |= IFM_ATM_UNASSIGNED;
+		}
+		if (utp->state & UTP_ST_NOSCRAMB) {
+			ifmr->ifm_active |= IFM_ATM_NOSCRAMB;
+			ifmr->ifm_current |= IFM_ATM_NOSCRAMB;
+		}
+	} else {
+		ifmr->ifm_active = 0;
+		ifmr->ifm_status = 0;
+	}
+	UTP_UNLOCK(utp);
+}
+
+/*
+ * Initialize media from the mib
+ */
+void
+utopia_init_media(struct utopia *utp)
+{
+
+	ifmedia_removeall(utp->media);
+	ifmedia_add(utp->media, IFM_ATM | utp->ifatm->mib.media, 0, NULL);
+	ifmedia_set(utp->media, IFM_ATM | utp->ifatm->mib.media);
+}
+
+/*
+ * Reset all media
+ */
+void
+utopia_reset_media(struct utopia *utp)
+{
+
+	ifmedia_removeall(utp->media);
+}
+
+/*
+ * This is called by the driver as soon as the SUNI registers are accessible.
+ * This may be either in the attach routine or the init routine of the driver.
+ */
+int
+utopia_start(struct utopia *utp)
+{
+	uint8_t reg;
+	int err;
+	u_int n = 1;
+
+	/*
+	 * Try to find out what chip we have
+	 */
+	if ((err = UTP_READREGS(utp, SUNI_REGO_MRESET, &reg, &n)) != 0)
+		return (err);
+
+	switch (reg & SUNI_REGM_MRESET_TYPE) {
+
+	  case SUNI_REGM_MRESET_TYPE_622:
+		utp->chip = &utopia_chip_622;
+		break;
+
+	  case SUNI_REGM_MRESET_TYPE_LITE:
+		/* this may be either a SUNI LITE or a IDT77155 *
+		 * Read register 0x70. The SUNI doesn't have it */
+		n = 1;
+		if ((err = UTP_READREGS(utp, IDTPHY_REGO_RBER, &reg, &n)) != 0)
+			return (err);
+		if ((reg & ~IDTPHY_REGM_RBER_RESV) ==
+		    (IDTPHY_REGM_RBER_FAIL | IDTPHY_REGM_RBER_WARN))
+			utp->chip = &utopia_chip_idt77155;
+		else
+			utp->chip = &utopia_chip_lite;
+		break;
+
+	  case SUNI_REGM_MRESET_TYPE_ULTRA:
+		utp->chip = &utopia_chip_ultra;
+		break;
+
+	  default:
+		if (reg == (IDTPHY_REGM_MCR_DRIC | IDTPHY_REGM_MCR_EI))
+			utp->chip = &utopia_chip_idt77105;
+		else {
+			if_printf(utp->ifatm->ifp,
+			    "unknown ATM-PHY chip %#x\n", reg);
+			utp->chip = &utopia_chip_unknown;
+		}
+		break;
+	}
+	utp->state |= UTP_ST_ACTIVE;
+	return (0);
+}
+
+/*
+ * Stop the chip
+ */
+void
+utopia_stop(struct utopia *utp)
+{
+	utp->state &= ~UTP_ST_ACTIVE;
+}
+
+/*
+ * Handle the sysctls
+ */
+static int
+utopia_sysctl_regs(SYSCTL_HANDLER_ARGS)
+{
+	struct utopia *utp = (struct utopia *)arg1;
+	int error;
+	u_int n;
+	uint8_t *val;
+	uint8_t new[3];
+
+	if ((n = utp->chip->nregs) == 0)
+		return (EIO);
+	val = malloc(sizeof(uint8_t) * n, M_TEMP, M_WAITOK);
+
+	UTP_LOCK(utp);
+	error = UTP_READREGS(utp, 0, val, &n);
+	UTP_UNLOCK(utp);
+
+	if (error) {
+		free(val, M_TEMP);
+		return (error);
+	}
+
+	error = SYSCTL_OUT(req, val, sizeof(uint8_t) * n);
+	free(val, M_TEMP);
+	if (error != 0 || req->newptr == NULL)
+		return (error);
+
+	error = SYSCTL_IN(req, new, sizeof(new));
+	if (error)
+		return (error);
+
+	UTP_LOCK(utp);
+	error = UTP_WRITEREG(utp, new[0], new[1], new[2]);
+	UTP_UNLOCK(utp);
+
+	return (error);
+}
+
+static int
+utopia_sysctl_stats(SYSCTL_HANDLER_ARGS)
+{
+	struct utopia *utp = (struct utopia *)arg1;
+	void *val;
+	int error;
+
+	val = malloc(sizeof(utp->stats), M_TEMP, M_WAITOK);
+
+	UTP_LOCK(utp);
+	bcopy(&utp->stats, val, sizeof(utp->stats));
+	if (req->newptr != NULL)
+		bzero((char *)&utp->stats + sizeof(utp->stats.version),
+		    sizeof(utp->stats) - sizeof(utp->stats.version));
+	UTP_UNLOCK(utp);
+
+	error = SYSCTL_OUT(req, val, sizeof(utp->stats));
+	free(val, M_TEMP);
+
+	if (error && req->newptr != NULL)
+		bcopy(val, &utp->stats, sizeof(utp->stats));
+
+	/* ignore actual new value */
+
+	return (error);
+}
+
+/*
+ * Handle the loopback sysctl
+ */
+static int
+utopia_sysctl_loopback(SYSCTL_HANDLER_ARGS)
+{
+	struct utopia *utp = (struct utopia *)arg1;
+	int error;
+	u_int loopback;
+
+	error = SYSCTL_OUT(req, &utp->loopback, sizeof(u_int));
+	if (error != 0 || req->newptr == NULL)
+		return (error);
+
+	error = SYSCTL_IN(req, &loopback, sizeof(u_int));
+	if (error)
+		return (error);
+
+	UTP_LOCK(utp);
+	error = utopia_set_loopback(utp, loopback);
+	UTP_UNLOCK(utp);
+
+	return (error);
+}
+
+/*
+ * Handle the type sysctl
+ */
+static int
+utopia_sysctl_type(SYSCTL_HANDLER_ARGS)
+{
+	struct utopia *utp = (struct utopia *)arg1;
+
+	return (SYSCTL_OUT(req, &utp->chip->type, sizeof(utp->chip->type)));
+}
+
+/*
+ * Handle the name sysctl
+ */
+static int
+utopia_sysctl_name(SYSCTL_HANDLER_ARGS)
+{
+	struct utopia *utp = (struct utopia *)arg1;
+
+	return (SYSCTL_OUT(req, utp->chip->name, strlen(utp->chip->name) + 1));
+}
+
+/*
+ * Initialize the state. This is called from the drivers attach
+ * function. The mutex must be already initialized.
+ */
+int
+utopia_attach(struct utopia *utp, struct ifatm *ifatm, struct ifmedia *media,
+    struct mtx *lock, struct sysctl_ctx_list *ctx,
+    struct sysctl_oid_list *children, const struct utopia_methods *m)
+{
+
+	bzero(utp, sizeof(*utp));
+	utp->ifatm = ifatm;
+	utp->methods = m;
+	utp->media = media;
+	utp->lock = lock;
+	utp->chip = &utopia_chip_unknown;
+	utp->stats.version = 1;
+
+	ifmedia_init(media,
+	    IFM_ATM_SDH | IFM_ATM_UNASSIGNED | IFM_ATM_NOSCRAMB,
+	    utopia_media_change, utopia_media_status);
+
+	if (SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "phy_regs",
+	    CTLFLAG_RW | CTLTYPE_OPAQUE, utp, 0, utopia_sysctl_regs, "S",
+	    "phy registers") == NULL)
+		return (-1);
+
+	if (SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "phy_loopback",
+	    CTLFLAG_RW | CTLTYPE_UINT, utp, 0, utopia_sysctl_loopback, "IU",
+	    "phy loopback mode") == NULL)
+		return (-1);
+
+	if (SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "phy_type",
+	    CTLFLAG_RD | CTLTYPE_UINT, utp, 0, utopia_sysctl_type, "IU",
+	    "phy type") == NULL)
+		return (-1);
+
+	if (SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "phy_name",
+	    CTLFLAG_RD | CTLTYPE_STRING, utp, 0, utopia_sysctl_name, "A",
+	    "phy name") == NULL)
+		return (-1);
+
+	if (SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "phy_stats",
+	    CTLFLAG_RW | CTLTYPE_OPAQUE, utp, 0, utopia_sysctl_stats, "S",
+	    "phy statistics") == NULL)
+		return (-1);
+
+	if (SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "phy_state",
+	    CTLFLAG_RD, &utp->state, 0, "phy state") == NULL)
+		return (-1);
+
+	if (SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "phy_carrier",
+	    CTLFLAG_RD, &utp->carrier, 0, "phy carrier") == NULL)
+		return (-1);
+
+	UTP_WLOCK_LIST();
+	LIST_INSERT_HEAD(&utopia_list, utp, link);
+	UTP_WUNLOCK_LIST();
+
+	utp->state |= UTP_ST_ATTACHED;
+	return (0);
+}
+
+/*
+ * Detach. We set a flag here, wakeup the daemon and let him do it.
+ * Here we need the lock for synchronisation with the daemon.
+ */
+void
+utopia_detach(struct utopia *utp)
+{
+
+	UTP_LOCK_ASSERT(utp);
+	if (utp->state & UTP_ST_ATTACHED) {
+		utp->state |= UTP_ST_DETACH;
+		while (utp->state & UTP_ST_DETACH) {
+			wakeup(&utopia_list);
+			msleep(utp, utp->lock, PZERO, "utopia_detach", hz);
+		}
+	}
+}
+
+/*
+ * The carrier state kernel proc for those adapters that do not interrupt.
+ *
+ * We assume, that utopia_attach can safely add a new utopia while we are going
+ * through the list without disturbing us (we lock the list while getting
+ * the address of the first element, adding is always done at the head).
+ * Removing is entirely handled here.
+ */
+static void
+utopia_daemon(void *arg __unused)
+{
+	struct utopia *utp, *next;
+
+	UTP_RLOCK_LIST();
+	while (utopia_kproc != NULL) {
+		utp = LIST_FIRST(&utopia_list);
+		UTP_RUNLOCK_LIST();
+
+		while (utp != NULL) {
+			mtx_lock(&Giant);	/* XXX depend on MPSAFE */
+			UTP_LOCK(utp);
+			next = LIST_NEXT(utp, link);
+			if (utp->state & UTP_ST_DETACH) {
+				LIST_REMOVE(utp, link);
+				utp->state &= ~UTP_ST_DETACH;
+				wakeup_one(utp);
+			} else if (utp->state & UTP_ST_ACTIVE) {
+				if (utp->flags & UTP_FL_POLL_CARRIER)
+					utopia_update_carrier(utp);
+				utopia_update_stats(utp);
+			}
+			UTP_UNLOCK(utp);
+			mtx_unlock(&Giant);	/* XXX depend on MPSAFE */
+			utp = next;
+		}
+
+		UTP_RLOCK_LIST();
+		msleep(&utopia_list, &utopia_list_mtx, PZERO, "*idle*", hz);
+	}
+	wakeup_one(&utopia_list);
+	UTP_RUNLOCK_LIST();
+	kthread_exit(0);
+}
+
+/*
+ * Module initialisation
+ */
+static int
+utopia_mod_init(module_t mod, int what, void *arg)
+{
+	int err;
+	struct proc *kp;
+
+	switch (what) {
+
+	  case MOD_LOAD:
+		mtx_init(&utopia_list_mtx, "utopia list mutex", NULL, MTX_DEF);
+		err = kthread_create(utopia_daemon, NULL, &utopia_kproc,
+		    RFHIGHPID, 0, "utopia");
+		if (err != 0) {
+			printf("cannot created utopia thread %d\n", err);
+			return (err);
+		}
+		break;
+
+	  case MOD_UNLOAD:
+		UTP_WLOCK_LIST();
+		if ((kp = utopia_kproc) != NULL) {
+			utopia_kproc = NULL;
+			wakeup_one(&utopia_list);
+			PROC_LOCK(kp);
+			UTP_WUNLOCK_LIST();
+			msleep(kp, &kp->p_mtx, PWAIT, "utopia_destroy", 0);
+			PROC_UNLOCK(kp);
+		} else
+			UTP_WUNLOCK_LIST();
+		mtx_destroy(&utopia_list_mtx);
+		break;
+	  default:
+		return (EOPNOTSUPP);
+	}
+	return (0);
+}
+
+static moduledata_t utopia_mod = {
+        "utopia",
+        utopia_mod_init,
+        0
+};
+                
+DECLARE_MODULE(utopia, utopia_mod, SI_SUB_INIT_IF, SI_ORDER_ANY);
+MODULE_VERSION(utopia, 1);
diff --git a/sys/dev/utopia/utopia.h b/sys/dev/utopia/utopia.h
new file mode 100644
index 000000000000..6e42e99b2e51
--- /dev/null
+++ b/sys/dev/utopia/utopia.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright (c) 2003
+ *	Fraunhofer Institute for Open Communication Systems (FhG Fokus).
+ * 	All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Author: Hartmut Brandt <harti@freebsd.org>
+ *
+ * $FreeBSD$
+ */
+#ifndef _DEV_UTOPIA_UTOPIA_H
+#define	_DEV_UTOPIA_UTOPIA_H
+
+/* Structure for user-level register formatting */
+struct utopia_print {
+	uint8_t		type;	/* register type */
+	uint8_t		reg;	/* register number */
+	const char	*name;	/* register name */
+	const char	*fmt;	/* format for printing */
+};
+
+/*
+ * Types of registers
+ */
+#define	UTP_REGT_BITS		0x0	/* use printb to print */
+#define	UTP_REGT_INT8		0x1	/* 8 bit hex number */
+#define	UTP_REGT_INT10BITS	0x2	/* 10 bit hex number + 6 bit printb */
+#define	UTP_REGT_INT12		0x3	/* 12 bit LE hex */
+#define	UTP_REGT_INT16		0x4	/* 16 bit LE hex */
+#define	UTP_REGT_INT19		0x5	/* 19 bit LE hex */
+#define	UTP_REGT_INT20		0x6	/* 20 bit LE hex */
+#define	UTP_REGT_INT21		0x7	/* 21 bit LE hex */
+#define	UTP_REGT_INT18		0x8	/* 18 bit LE hex */
+
+/* number of additional registers per type */
+#define	UTP_REG_ADD	0, 0, 1, 1, 1, 2, 2, 2, 2
+
+/* flags field */
+#define	UTP_FL_NORESET		0x0001	/* cannot write MRESET register */
+#define	UTP_FL_POLL_CARRIER	0x0002	/* need to poll for carrier */
+
+/* state field */
+#define	UTP_ST_ACTIVE		0x0001	/* registers accessible */
+#define	UTP_ST_SDH		0x0002	/* SDH or SONET */
+#define	UTP_ST_UNASS		0x0004	/* produce unassigned cells */
+#define	UTP_ST_NOSCRAMB		0x0008	/* no scrambling */
+#define	UTP_ST_DETACH		0x0010	/* detaching */
+#define	UTP_ST_ATTACHED		0x0020	/* successful attached */
+
+/* carrier field */
+#define	UTP_CARR_UNKNOWN	0
+#define	UTP_CARR_OK		1
+#define	UTP_CARR_LOST		2
+
+/* loopback field */
+#define	UTP_LOOP_NONE		0x0000
+#define	UTP_LOOP_TIME		0x0001	/* timing source loopback */
+#define	UTP_LOOP_DIAG		0x0002	/* diagnostic loopback */
+#define	UTP_LOOP_LINE		0x0004	/* serial line loopback */
+#define	UTP_LOOP_PARAL		0x0008	/* parallel diagnostic loopback */
+#define	UTP_LOOP_TWIST		0x0010	/* twisted pair diagnostic loopback */
+#define	UTP_LOOP_PATH		0x0020	/* diagnostic path loopback */
+
+/* type */
+#define	UTP_TYPE_UNKNOWN	0
+#define	UTP_TYPE_SUNI_LITE	1
+#define	UTP_TYPE_SUNI_ULTRA	2
+#define	UTP_TYPE_SUNI_622	3
+#define	UTP_TYPE_IDT77105	4
+#define	UTP_TYPE_IDT77155	5
+#define	UTP_TYPE_CX28250	6
+
+/*
+ * Statistics. These structures are versioned.
+ */
+struct utopia_stats1 {
+	uint32_t	version;	/* version of this statistics struct */
+	uint32_t	fill;
+
+	uint64_t	rx_sbip;	/* rx section BIP errors */
+	uint64_t	rx_lbip;	/* rx line BIP errors */
+	uint64_t	rx_lfebe;	/* rx line far end block errors */
+	uint64_t	rx_pbip;	/* rx path BIP errors */
+	uint64_t	rx_pfebe;	/* rx path far end block errors */
+	uint64_t	rx_cells;	/* received cells */
+	uint64_t	rx_corr;	/* correctable cell errors */
+	uint64_t	rx_uncorr;	/* uncorrectable cell errors */
+	uint64_t	rx_symerr;	/* symbol errors */
+
+	uint64_t	tx_cells;	/* transmitted cells */
+};
+
+#ifdef _KERNEL
+
+#include <sys/queue.h>
+
+/*
+ * These must be implemented by the card driver
+ */
+struct utopia_methods {
+	/* read at most n PHY registers starting at reg into val */
+	int	(*readregs)(struct ifatm *, u_int reg, uint8_t *val, u_int *n);
+
+	/* change the bits given by mask to them in val in register reg */
+	int	(*writereg)(struct ifatm *, u_int reg, u_int mask, u_int val);
+};
+
+/*
+ * Public state
+ */
+struct utopia {
+	struct ifatm	*ifatm;		/* driver data */
+	struct ifmedia	*media;		/* driver supplied */
+	struct mtx	*lock;		/* driver supplied */
+	const struct utopia_methods *methods;
+	LIST_ENTRY(utopia) link;	/* list of these structures */
+	u_int		flags;		/* flags set by the driver */
+	u_int		state;		/* current state */
+	u_int		carrier;	/* carrier state */
+	u_int		loopback;	/* loopback mode */
+	const struct utopia_chip *chip;	/* chip operations */
+	struct utopia_stats1 stats;	/* statistics */
+};
+
+struct utopia_chip {
+	/* type and name of the chip */
+	u_int	type;
+	const char *const name;
+
+	/* number of registers */
+	u_int	nregs;
+
+	/* reset chip to known state */
+	int	(*reset)(struct utopia *);
+
+	/* set SONET/SDH mode */
+	int	(*set_sdh)(struct utopia *, int sdh);
+
+	/* set idle/unassigned cells */
+	int	(*set_unass)(struct utopia *, int unass);
+
+	/* enable/disable scrambling */
+	int	(*set_noscramb)(struct utopia *, int noscramb);
+
+	/* update carrier status */
+	int	(*update_carrier)(struct utopia *);
+
+	/* set loopback mode */
+	int	(*set_loopback)(struct utopia *, u_int mode);
+
+	/* handle interrupt */
+	void	(*intr)(struct utopia *);
+
+	/* update statistics */
+	void	(*update_stats)(struct utopia *);
+};
+
+/*
+ * These are implemented in the common utopia code
+ */
+int utopia_attach(struct utopia *, struct ifatm *, struct ifmedia *,
+    struct mtx *, struct sysctl_ctx_list *, struct sysctl_oid_list *,
+    const struct utopia_methods *);
+void utopia_detach(struct utopia *);
+
+int utopia_start(struct utopia *);
+void utopia_stop(struct utopia *);
+
+void utopia_init_media(struct utopia *);
+void utopia_reset_media(struct utopia *);
+
+#define	utopia_reset(S)			((S)->chip->reset((S)))
+#define	utopia_set_sdh(S, SDH)		((S)->chip->set_sdh((S), (SDH)))
+#define	utopia_set_unass(S, U)		((S)->chip->set_unass((S), (U)))
+#define	utopia_set_noscramb(S, N)	((S)->chip->set_noscramb((S), (N)))
+#define	utopia_update_carrier(S)	((S)->chip->update_carrier((S)))
+#define	utopia_update_stats(S)		((S)->chip->update_stats((S)))
+#define	utopia_set_loopback(S, L)	((S)->chip->set_loopback((S), (L)))
+#define	utopia_intr(S)			((S)->chip->intr((S)))
+
+#endif /* _KERNEL */
+
+#endif	/* _DEV_UTOPIA_UTOPIA_H */
diff --git a/sys/dev/utopia/utopia_priv.h b/sys/dev/utopia/utopia_priv.h
new file mode 100644
index 000000000000..cbb242cb9991
--- /dev/null
+++ b/sys/dev/utopia/utopia_priv.h
@@ -0,0 +1,46 @@
+/*-
+ * Copyright (c) 2005
+ *	Hartmut Brandt.
+ * 	All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Author: Hartmut Brandt <harti@freebsd.org>
+ *
+ * $FreeBSD$
+ *
+ * Private include file for the interface between chip files and
+ * the utopia main stuff.
+ */
+
+#ifndef _DEV_UTOPIA_UTOPIA_PRIV_H
+#define	_DEV_UTOPIA_UTOPIA_PRIV_H
+
+#define UTP_READREGS(UTOPIA, REG, VALP, NP)				\
+    (UTOPIA)->methods->readregs((UTOPIA)->ifatm, REG, VALP, NP)
+#define UTP_WRITEREG(UTOPIA, REG, MASK, VAL)			\
+    (UTOPIA)->methods->writereg((UTOPIA)->ifatm, REG, MASK, VAL)
+
+uint32_t utopia_update(struct utopia *, u_int, u_int, uint32_t);
+void utopia_check_carrier(struct utopia *, u_int);
+
+#endif	/* _DEV_UTOPIA_UTOPIA_PRIV_H */