3 files changed, 451 insertions, 0 deletions

diff --git a/sys/dev/sound/pci/hda/hdac.h b/sys/dev/sound/pci/hda/hdac.h
new file mode 100644
index 000000000000..298afde5728d
--- /dev/null
+++ b/sys/dev/sound/pci/hda/hdac.h
@@ -0,0 +1,69 @@
+/*-
+ * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _HDAC_H_
+#define _HDAC_H_
+
+
+#if 0
+/****************************************************************************
+ * Miscellanious defines
+ ****************************************************************************/
+
+/****************************************************************************
+ * Helper Macros
+ ****************************************************************************/
+
+/****************************************************************************
+ * Simplified Accessors for HDA devices
+ ****************************************************************************/
+enum hdac_device_ivars {
+    HDAC_IVAR_CODEC_ID,
+    HDAC_IVAR_NODE_ID,
+    HDAC_IVAR_VENDOR_ID,
+    HDAC_IVAR_DEVICE_ID,
+    HDAC_IVAR_REVISION_ID,
+    HDAC_IVAR_STEPPING_ID,
+    HDAC_IVAR_NODE_TYPE,
+};
+
+#define HDAC_ACCESSOR(var, ivar, type)					\
+    __BUS_ACCESSOR(hdac, var, HDAC, ivar, type)
+
+HDAC_ACCESSOR(codec_id,		CODEC_ID,	uint8_t);
+HDAC_ACCESSOR(node_id,		NODE_ID,	uint8_t);
+HDAC_ACCESSOR(vendor_id,	VENDOR_ID,	uint16_t);
+HDAC_ACCESSOR(device_id,	DEVICE_ID,	uint16_t);
+HDAC_ACCESSOR(revision_id,	REVISION_ID,	uint8_t);
+HDAC_ACCESSOR(stepping_id,	STEPPING_ID,	uint8_t);
+HDAC_ACCESSOR(node_type,	NODE_TYPE,	uint8_t);
+#endif
+
+#define PCIS_MULTIMEDIA_HDA    0x03
+
+#endif
diff --git a/sys/dev/sound/pci/hda/hdac_reg.h b/sys/dev/sound/pci/hda/hdac_reg.h
new file mode 100644
index 000000000000..969471023d34
--- /dev/null
+++ b/sys/dev/sound/pci/hda/hdac_reg.h
@@ -0,0 +1,266 @@
+/*-
+ * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _HDAC_REG_H_
+#define _HDAC_REG_H_
+
+/****************************************************************************
+ * HDA Controller Register Set
+ ****************************************************************************/
+#define HDAC_GCAP	0x00	/* 2 - Global Capabilities*/
+#define HDAC_VMIN	0x02	/* 1 - Minor Version */
+#define HDAC_VMAJ	0x03	/* 1 - Major Version */
+#define	HDAC_OUTPAY	0x04	/* 2 - Output Payload Capability */
+#define HDAC_INPAY	0x06	/* 2 - Input Payload Capability */
+#define HDAC_GCTL	0x08	/* 4 - Global Control */
+#define HDAC_WAKEEN	0x0c	/* 2 - Wake Enable */
+#define HDAC_STATESTS	0x0e	/* 2 - State Change Status */
+#define HDAC_GSTS	0x10	/* 2 - Global Status */
+#define HDAC_OUTSTRMPAY	0x18	/* 2 - Output Stream Payload Capability */
+#define HDAC_INSTRMPAY	0x1a	/* 2 - Input Stream Payload Capability */
+#define HDAC_INTCTL	0x20	/* 4 - Interrupt Control */
+#define HDAC_INTSTS	0x24	/* 4 - Interrupt Status */
+#define HDAC_WALCLK	0x30	/* 4 - Wall Clock Counter */
+#define HDAC_SSYNC	0x38	/* 4 - Stream Synchronization */
+#define HDAC_CORBLBASE	0x40	/* 4 - CORB Lower Base Address */
+#define HDAC_CORBUBASE	0x44	/* 4 - CORB Upper Base Address */
+#define HDAC_CORBWP	0x48	/* 2 - CORB Write Pointer */
+#define HDAC_CORBRP	0x4a	/* 2 - CORB Read Pointer */
+#define HDAC_CORBCTL	0x4c	/* 1 - CORB Control */
+#define HDAC_CORBSTS	0x4d	/* 1 - CORB Status */
+#define HDAC_CORBSIZE	0x4e	/* 1 - CORB Size */
+#define HDAC_RIRBLBASE	0x50	/* 4 - RIRB Lower Base Address */
+#define HDAC_RIRBUBASE	0x54	/* 4 - RIRB Upper Base Address */
+#define HDAC_RIRBWP	0x58	/* 2 - RIRB Write Pointer */
+#define HDAC_RINTCNT	0x5a	/* 2 - Response Interrupt Count */
+#define HDAC_RIRBCTL	0x5c	/* 1 - RIRB Control */
+#define HDAC_RIRBSTS	0x5d	/* 1 - RIRB Status */
+#define HDAC_RIRBSIZE	0x5e	/* 1 - RIRB Size */
+#define HDAC_ICOI	0x60	/* 4 - Immediate Command Output Interface */
+#define HDAC_ICII	0x64	/* 4 - Immediate Command Input Interface */
+#define HDAC_ICIS	0x68	/* 2 - Immediate Command Status */
+#define HDAC_DPIBLBASE	0x70	/* 4 - DMA Position Buffer Lower Base */
+#define HDAC_DPIBUBASE	0x74	/* 4 - DMA Position Buffer Upper Base */
+#define HDAC_SDCTL0	0x80	/* 3 - Stream Descriptor Control */
+#define HDAC_SDCTL1	0x81	/* 3 - Stream Descriptor Control */
+#define HDAC_SDCTL2	0x82	/* 3 - Stream Descriptor Control */
+#define HDAC_SDSTS	0x83	/* 1 - Stream Descriptor Status */
+#define HDAC_SDLPIB	0x84	/* 4 - Link Position in Buffer */
+#define HDAC_SDCBL	0x88	/* 4 - Cyclic Buffer Length */
+#define HDAC_SDLVI	0x8C	/* 2 - Last Valid Index */
+#define HDAC_SDFIFOS	0x90	/* 2 - FIFOS */
+#define HDAC_SDFMT	0x92	/* 2 - fmt */
+#define HDAC_SDBDPL	0x98	/* 4 - Buffer Descriptor Pointer Lower Base */
+#define HDAC_SDBDPU	0x9C	/* 4 - Buffer Descriptor Pointer Upper Base */
+
+#define _HDAC_ISDOFFSET(n, iss, oss)	(0x80 + ((n) * 0x20))
+#define _HDAC_ISDCTL(n, iss, oss)	(0x00 + _HDAC_ISDOFFSET(n, iss, oss))
+#define _HDAC_ISDSTS(n, iss, oss)	(0x03 + _HDAC_ISDOFFSET(n, iss, oss))
+#define _HDAC_ISDPICB(n, iss, oss)	(0x04 + _HDAC_ISDOFFSET(n, iss, oss))
+#define _HDAC_ISDCBL(n, iss, oss)	(0x08 + _HDAC_ISDOFFSET(n, iss, oss))
+#define _HDAC_ISDLVI(n, iss, oss)	(0x0c + _HDAC_ISDOFFSET(n, iss, oss))
+#define _HDAC_ISDFIFOD(n, iss, oss)	(0x10 + _HDAC_ISDOFFSET(n, iss, oss))
+#define _HDAC_ISDFMT(n, iss, oss)	(0x12 + _HDAC_ISDOFFSET(n, iss, oss))
+#define _HDAC_ISDBDPL(n, iss, oss)	(0x18 + _HDAC_ISDOFFSET(n, iss, oss))
+#define _HDAC_ISDBDPU(n, iss, oss)	(0x1c + _HDAC_ISDOFFSET(n, iss, oss))
+
+#define _HDAC_OSDOFFSET(n, iss, oss)	(0x80 + ((iss) * 0x20) + ((n) * 0x20))
+#define _HDAC_OSDCTL(n, iss, oss)	(0x00 + _HDAC_OSDOFFSET(n, iss, oss))
+#define _HDAC_OSDSTS(n, iss, oss)	(0x03 + _HDAC_OSDOFFSET(n, iss, oss))
+#define _HDAC_OSDPICB(n, iss, oss)	(0x04 + _HDAC_OSDOFFSET(n, iss, oss))
+#define _HDAC_OSDCBL(n, iss, oss)	(0x08 + _HDAC_OSDOFFSET(n, iss, oss))
+#define _HDAC_OSDLVI(n, iss, oss)	(0x0c + _HDAC_OSDOFFSET(n, iss, oss))
+#define _HDAC_OSDFIFOD(n, iss, oss)	(0x10 + _HDAC_OSDOFFSET(n, iss, oss))
+#define _HDAC_OSDFMT(n, iss, oss)	(0x12 + _HDAC_OSDOFFSET(n, iss, oss))
+#define _HDAC_OSDBDPL(n, iss, oss)	(0x18 + _HDAC_OSDOFFSET(n, iss, oss))
+#define _HDAC_OSDBDPU(n, iss, oss)	(0x1c + _HDAC_OSDOFFSET(n, iss, oss))
+
+#define _HDAC_BSDOFFSET(n, iss, oss)	(0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20))
+#define _HDAC_BSDCTL(n, iss, oss)	(0x00 + _HDAC_BSDOFFSET(n, iss, oss))
+#define _HDAC_BSDSTS(n, iss, oss)	(0x03 + _HDAC_BSDOFFSET(n, iss, oss))
+#define _HDAC_BSDPICB(n, iss, oss)	(0x04 + _HDAC_BSDOFFSET(n, iss, oss))
+#define _HDAC_BSDCBL(n, iss, oss)	(0x08 + _HDAC_BSDOFFSET(n, iss, oss))
+#define _HDAC_BSDLVI(n, iss, oss)	(0x0c + _HDAC_BSDOFFSET(n, iss, oss))
+#define _HDAC_BSDFIFOD(n, iss, oss)	(0x10 + _HDAC_BSDOFFSET(n, iss, oss))
+#define _HDAC_BSDFMT(n, iss, oss)	(0x12 + _HDAC_BSDOFFSET(n, iss, oss))
+#define _HDAC_BSDBDPL(n, iss, oss)	(0x18 + _HDAC_BSDOFFSET(n, iss, oss))
+#define _HDAC_BSDBDBU(n, iss, oss)	(0x1c + _HDAC_BSDOFFSET(n, iss, oss))
+
+/****************************************************************************
+ * HDA Controller Register Fields
+ ****************************************************************************/
+
+/* GCAP - Global Capabilities */
+#define HDAC_GCAP_64OK			0x0001
+#define HDAC_GCAP_NSDO_MASK		0x0006
+#define HDAC_GCAP_NSDO_SHIFT		1
+#define HDAC_GCAP_BSS_MASK		0x00f8
+#define HDAC_GCAP_BSS_SHIFT		3
+#define HDAC_GCAP_ISS_MASK		0x0f00
+#define HDAC_GCAP_ISS_SHIFT		8
+#define HDAC_GCAP_OSS_MASK		0xf000
+#define HDAC_GCAP_OSS_SHIFT		12
+
+#define HDAC_GCAP_NSDO_1SDO		0x00
+#define HDAC_GCAP_NSDO_2SDO		0x02
+#define HDAC_GCAP_NSDO_4SDO		0x04
+
+#define HDAC_GCAP_BSS(gcap)						\
+	(((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT)
+#define HDAC_GCAP_ISS(gcap)						\
+	(((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT)
+#define HDAC_GCAP_OSS(gcap)						\
+	(((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT)
+
+/* GCTL - Global Control */
+#define HDAC_GCTL_CRST			0x00000001
+#define HDAC_GCTL_FCNTRL		0x00000002
+#define HDAC_GCTL_UNSOL			0x00000100
+
+/* WAKEEN - Wake Enable */
+#define HDAC_WAKEEN_SDIWEN_MASK		0x7fff
+#define HDAC_WAKEEN_SDIWEN_SHIFT	0
+
+/* STATESTS - State Change Status */
+#define HDAC_STATESTS_SDIWAKE_MASK	0x7fff
+#define HDAC_STATESTS_SDIWAKE_SHIFT	0
+
+#define HDAC_STATESTS_SDIWAKE(statests, n)				\
+    (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >>			\
+    HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001)
+
+/* GSTS - Global Status */
+#define HDAC_GSTS_FSTS			0x0002
+
+/* INTCTL - Interrut Control */
+#define HDAC_INTCTL_SIE_MASK		0x3fffffff
+#define HDAC_INTCTL_SIE_SHIFT		0
+#define HDAC_INTCTL_CIE			0x40000000
+#define HDAC_INTCTL_GIE			0x80000000
+
+/* INTSTS - Interrupt Status */
+#define HDAC_INTSTS_SIS_MASK		0x3fffffff
+#define HDAC_INTSTS_SIS_SHIFT		0
+#define HDAC_INTSTS_CIS			0x40000000
+#define HDAC_INTSTS_GIS			0x80000000
+
+/* SSYNC - Stream Synchronization */
+#define HDAC_SSYNC_SSYNC_MASK		0x3fffffff
+#define HDAC_SSYNC_SSYNC_SHIFT		0
+
+/* CORBWP - CORB Write Pointer */
+#define HDAC_CORBWP_CORBWP_MASK		0x00ff
+#define HDAC_CORBWP_CORBWP_SHIFT	0
+
+/* CORBRP - CORB Read Pointer */
+#define HDAC_CORBRP_CORBRP_MASK		0x00ff
+#define HDAC_CORBRP_CORBRP_SHIFT	0
+#define HDAC_CORBRP_CORBRPRST		0x8000
+
+/* CORBCTL - CORB Control */
+#define HDAC_CORBCTL_CMEIE		0x01
+#define HDAC_CORBCTL_CORBRUN		0x02
+
+/* CORBSTS - CORB Status */
+#define HDAC_CORBSTS_CMEI		0x01
+
+/* CORBSIZE - CORB Size */
+#define HDAC_CORBSIZE_CORBSIZE_MASK	0x03
+#define HDAC_CORBSIZE_CORBSIZE_SHIFT	0
+#define HDAC_CORBSIZE_CORBSZCAP_MASK	0xf0
+#define HDAC_CORBSIZE_CORBSZCAP_SHIFT	4
+
+#define HDAC_CORBSIZE_CORBSIZE_2	0x00
+#define HDAC_CORBSIZE_CORBSIZE_16	0x01
+#define HDAC_CORBSIZE_CORBSIZE_256	0x02
+
+#define HDAC_CORBSIZE_CORBSZCAP_2	0x10
+#define HDAC_CORBSIZE_CORBSZCAP_16	0x20
+#define HDAC_CORBSIZE_CORBSZCAP_256	0x40
+
+#define HDAC_CORBSIZE_CORBSIZE(corbsize)				\
+    (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT)
+
+/* RIRBWP - RIRB Write Pointer */
+#define HDAC_RIRBWP_RIRBWP_MASK		0x00ff
+#define HDAC_RIRBWP_RIRBWP_SHIFT	0
+#define HDAC_RIRBWP_RIRBWPRST		0x8000
+
+/* RINTCTN - Response Interrupt Count */
+#define HDAC_RINTCNT_MASK		0x00ff
+#define HDAC_RINTCNT_SHIFT		0
+
+/* RIRBCTL - RIRB Control */
+#define HDAC_RIRBCTL_RINTCTL		0x01
+#define HDAC_RIRBCTL_RIRBDMAEN		0x02
+#define HDAC_RIRBCTL_RIRBOIC		0x04
+
+/* RIRBSTS - RIRB Status */
+#define HDAC_RIRBSTS_RINTFL		0x01
+#define HDAC_RIRBSTS_RIRBOIS		0x04
+
+/* RIRBSIZE - RIRB Size */
+#define HDAC_RIRBSIZE_RIRBSIZE_MASK	0x03
+#define HDAC_RIRBSIZE_RIRBSIZE_SHIFT	0
+#define HDAC_RIRBSIZE_RIRBSZCAP_MASK	0xf0
+#define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT	4
+
+#define HDAC_RIRBSIZE_RIRBSIZE_2	0x00
+#define HDAC_RIRBSIZE_RIRBSIZE_16	0x01
+#define HDAC_RIRBSIZE_RIRBSIZE_256	0x02
+
+#define HDAC_RIRBSIZE_RIRBSZCAP_2	0x10
+#define HDAC_RIRBSIZE_RIRBSZCAP_16	0x20
+#define HDAC_RIRBSIZE_RIRBSZCAP_256	0x40
+
+#define HDAC_RIRBSIZE_RIRBSIZE(rirbsize)				\
+    (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT)
+
+/* DPLBASE - DMA Position Lower Base Address */
+#define HDAC_DPLBASE_DPLBASE_MASK	0xffffff80
+#define HDAC_DPLBASE_DPLBASE_SHIFT	7
+#define HDAC_DPLBASE_DPLBASE_DMAPBE	0x00000001
+
+/* SDCTL - Stream Descriptor Control */
+#define HDAC_SDCTL_SRST			0x000001
+#define HDAC_SDCTL_RUN			0x000002
+#define HDAC_SDCTL_IOCE			0x000004
+#define HDAC_SDCTL_FEIE			0x000008
+#define HDAC_SDCTL_DEIE			0x000010
+#define HDAC_SDCTL_STRIPE_MASK		0x030000
+#define HDAC_SDCTL_STRIPE_SHIFT		16
+#define HDAC_SDCTL_TP			0x040000
+#define HDAC_SDCTL_DIR			0x080000
+#define HDAC_SDCTL2_STRM_MASK		0xf0
+#define HDAC_SDCTL2_STRM_SHIFT		4
+
+#define HDAC_SDSTS_DESE			(1 << 4)
+#define HDAC_SDSTS_FIFOE		(1 << 3)
+#define HDAC_SDSTS_BCIS			(1 << 2)
+
+#endif
diff --git a/sys/dev/sound/pci/spicds.h b/sys/dev/sound/pci/spicds.h
new file mode 100644
index 000000000000..c999b4ce1aa8
--- /dev/null
+++ b/sys/dev/sound/pci/spicds.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2006 Konstantin Dimitrov <kosio.dimitrov@gmail.com>
+ * Copyright (c) 2001 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/* supported CODECs */
+#define SPICDS_TYPE_AK4524 0
+#define SPICDS_TYPE_AK4528 1
+#define SPICDS_TYPE_WM8770 2
+#define SPICDS_TYPE_AK4358 3
+#define SPICDS_TYPE_AK4381 4
+
+/* AK4524/AK4528 control registers */
+#define AK4524_POWER 0x00
+#define AK4528_POWER 0x00
+#define   AK452X_POWER_PWDA 0x01
+#define   AK452X_POWER_PWAD 0x02
+#define   AK452X_POWER_PWVR 0x04
+#define AK4524_RESET 0x01
+#define AK4528_RESET 0x01
+#define   AK452X_RESET_RSDA 0x01
+#define   AK452X_RESET_RSAD 0x02
+#define AK4524_FORMAT 0x02
+#define AK4528_FORMAT 0x02
+#define   AK452X_FORMAT_1X       0x00
+#define   AK452X_FORMAT_2X       0x01
+#define   AK452X_FORMAT_4X1      0x02
+#define   AK452X_FORMAT_4X2      0x03
+#define   AK452X_FORMAT_256FSN   0x00
+#define   AK452X_FORMAT_512FSN   0x04
+#define   AK452X_FORMAT_1024FSN  0x08
+#define   AK452X_FORMAT_384FSN   0x10
+#define   AK452X_FORMAT_768FSN   0x14
+#define   AK452X_FORMAT_OM24IL16 0x00
+#define   AK452X_FORMAT_OM24IL20 0x20
+#define   AK452X_FORMAT_OM24IM24 0x40
+#define   AK452X_FORMAT_I2S      0x60
+#define   AK452X_FORMAT_OM24IL24 0x80
+#define AK4524_DVC 0x03
+#define   AK452X_DVC_DEM441  0x00
+#define   AK452X_DVC_DEMOFF  0x01
+#define   AK452X_DVC_DEM48   0x02
+#define   AK452X_DVC_DEM32   0x03
+#define   AK452X_DVC_ZTM256  0x00
+#define   AK452X_DVC_ZTM512  0x04
+#define   AK452X_DVC_ZTM1024 0x08
+#define   AK452X_DVC_ZTM2048 0x0c
+#define   AK452X_DVC_ZCE     0x10
+#define   AK452X_DVC_HPFL    0x04
+#define   AK452X_DVC_HPFR    0x08
+#define   AK452X_DVC_SMUTE   0x80
+#define AK4524_LIPGA 0x04
+#define AK4524_RIPGA 0x05
+#define AK4524_LOATT 0x06
+#define AK4524_ROATT 0x07
+#define AK4528_LOATT 0x04
+#define AK4528_ROATT 0x05
+
+/* WM8770 control registers */
+#define WM8770_AOATT_L1 0x00
+#define WM8770_AOATT_R1 0x01
+#define WM8770_AOATT_L2 0x02
+#define WM8770_AOATT_R2 0x03
+#define WM8770_AOATT_L3 0x04
+#define WM8770_AOATT_R3 0x05
+#define WM8770_AOATT_L4 0x06
+#define WM8770_AOATT_R4 0x07
+#define WM8770_AOATT_MAST 0x08
+#define WM8770_AOATT_UPDATE 0x100
+
+/* AK4358 control registers */
+#define AK4358_LO1ATT 0x04
+#define AK4358_RO1ATT 0x05 
+#define AK4358_OATT_ENABLE 0x80
+
+/* AK4381 control registers */
+#define AK4381_LOATT 0x03
+#define AK4381_ROATT 0x04
+
+struct spicds_info;
+
+typedef void (*spicds_ctrl)(void *, unsigned int, unsigned int, unsigned int);
+
+struct spicds_info *spicds_create(device_t dev, void *devinfo, int num, spicds_ctrl);
+void spicds_destroy(struct spicds_info *codec);
+void spicds_settype(struct spicds_info *codec, unsigned int type);
+void spicds_setcif(struct spicds_info *codec, unsigned int cif);
+void spicds_setformat(struct spicds_info *codec, unsigned int format);
+void spicds_setdvc(struct spicds_info *codec, unsigned int dvc);
+void spicds_init(struct spicds_info *codec);
+void spicds_reinit(struct spicds_info *codec);
+void spicds_set(struct spicds_info *codec, int dir, unsigned int left, unsigned int right);