diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2015-08-07 23:01:33 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-08-07 23:01:33 +0000 |
| commit | ee8648bdac07986a0f1ec897b02ec82a2f144d46 (patch) | |
| tree | 52d1861acda1205241ee35a94aa63129c604d469 /test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll | |
| parent | 1a82d4c088707c791c792f6822f611b47a12bdfe (diff) | |
Notes
Diffstat (limited to 'test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll')
| -rw-r--r-- | test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll | 60 |
1 files changed, 55 insertions, 5 deletions
diff --git a/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll index a31c66bad4be..739570236da9 100644 --- a/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll +++ b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll @@ -255,7 +255,7 @@ entry: ; CHECK: ubfx x9, x0, #0, #32 ; CHECK: lsl x9, x9, #2 ; CHECK: add x9, x9, #15 -; CHECK: and x9, x9, #0xfffffffffffffff0 +; CHECK: and x9, x9, #0x7fffffff0 ; CHECK: mov x10, sp ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: mov sp, x[[VLASPTMP]] @@ -302,7 +302,7 @@ entry: ; CHECK: ubfx x9, x0, #0, #32 ; CHECK: lsl x9, x9, #2 ; CHECK: add x9, x9, #15 -; CHECK: and x9, x9, #0xfffffffffffffff0 +; CHECK: and x9, x9, #0x7fffffff0 ; CHECK: mov x10, sp ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: mov sp, x[[VLASPTMP]] @@ -364,7 +364,7 @@ entry: ; CHECK: ubfx x9, x0, #0, #32 ; CHECK: lsl x9, x9, #2 ; CHECK: add x9, x9, #15 -; CHECK: and x9, x9, #0xfffffffffffffff0 +; CHECK: and x9, x9, #0x7fffffff0 ; CHECK: mov x10, sp ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: mov sp, x[[VLASPTMP]] @@ -417,7 +417,7 @@ entry: ; CHECK: ubfx x9, x0, #0, #32 ; CHECK: lsl x9, x9, #2 ; CHECK: add x9, x9, #15 -; CHECK: and x9, x9, #0xfffffffffffffff0 +; CHECK: and x9, x9, #0x7fffffff0 ; CHECK: mov x10, sp ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: mov sp, x[[VLASPTMP]] @@ -468,7 +468,7 @@ entry: ; CHECK: ubfx x9, x0, #0, #32 ; CHECK: lsl x9, x9, #2 ; CHECK: add x9, x9, #15 -; CHECK: and x9, x9, #0xfffffffffffffff0 +; CHECK: and x9, x9, #0x7fffffff0 ; CHECK: mov x10, sp ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: mov sp, x[[VLASPTMP]] @@ -482,6 +482,56 @@ entry: ; CHECK: ldp x20, x19, [sp], #32 ; CHECK: ret + +define void @realign_conditional(i1 %b) { +entry: + br i1 %b, label %bb0, label %bb1 + +bb0: + %MyAlloca = alloca i8, i64 64, align 32 + br label %bb1 + +bb1: + ret void +} + +; CHECK-LABEL: realign_conditional +; No realignment in the prologue. +; CHECK-NOT: and +; CHECK-NOT: 0xffffffffffffffe0 +; CHECK: tbz {{.*}} .[[LABEL:.*]] +; Stack is realigned in a non-entry BB. +; CHECK: sub [[REG:x[01-9]+]], sp, #64 +; CHECK: and sp, [[REG]], #0xffffffffffffffe0 +; CHECK: .[[LABEL]]: +; CHECK: ret + + +define void @realign_conditional2(i1 %b) { +entry: + %tmp = alloca i8, i32 4 + br i1 %b, label %bb0, label %bb1 + +bb0: + %MyAlloca = alloca i8, i64 64, align 32 + br label %bb1 + +bb1: + ret void +} + +; CHECK-LABEL: realign_conditional2 +; Extra realignment in the prologue (performance issue). +; CHECK: sub x9, sp, #32 // =32 +; CHECK: and sp, x9, #0xffffffffffffffe0 +; CHECK: mov x19, sp +; CHECK: tbz {{.*}} .[[LABEL:.*]] +; Stack is realigned in a non-entry BB. +; CHECK: sub [[REG:x[01-9]+]], sp, #64 +; CHECK: and sp, [[REG]], #0xffffffffffffffe0 +; CHECK: .[[LABEL]]: +; CHECK: ret + attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } |