Vendor import of llvm trunk r303291: - src

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author	Dimitry Andric <dim@FreeBSD.org>	2017-05-17 20:22:39 +0000
committer	Dimitry Andric <dim@FreeBSD.org>	2017-05-17 20:22:39 +0000
commit	7af96fb3afd6725a2824a0a5ca5dad34e5e0b056 (patch)
tree	6661ffbabf869009597684462f5a3df3beccc952 /test/CodeGen/AArch64
parent	6b3f41ed88e8e440e11a4fbf20b6600529f80049 (diff)

vendor/llvm/llvm-trunk-r303291

Notes

Diffstat (limited to 'test/CodeGen/AArch64')

-rw-r--r--

test/CodeGen/AArch64/aarch64-addv.ll

-rw-r--r--

test/CodeGen/AArch64/aarch64-minmaxv.ll

424

-rw-r--r--

test/CodeGen/AArch64/arm64-vabs.ll

-rw-r--r--

test/CodeGen/AArch64/ldst-zero.ll

-rw-r--r--

test/CodeGen/AArch64/misched-stp.ll

5 files changed, 127 insertions, 460 deletions

diff --git a/test/CodeGen/AArch64/aarch64-addv.ll b/test/CodeGen/AArch64/aarch64-addv.ll
index 91797c062b88..e65992e9913d 100644
--- a/test/CodeGen/AArch64/aarch64-addv.ll
+++ b/test/CodeGen/AArch64/aarch64-addv.ll

@@ -1,18 +1,16 @@

; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=generic | FileCheck %s

+; Function Attrs: nounwind readnone

+declare i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64>)

+declare i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32>)

+declare i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16>)

+declare i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8>)

define i8 @add_B(<16 x i8>* %arr) {

; CHECK-LABEL: add_B

; CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.16b

%bin.rdx = load <16 x i8>, <16 x i8>* %arr

- %rdx.shuf0 = shufflevector <16 x i8> %bin.rdx, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx0 = add <16 x i8> %bin.rdx, %rdx.shuf0

- %rdx.shuf = shufflevector <16 x i8> %bin.rdx0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef >

- %bin.rdx11 = add <16 x i8> %bin.rdx0, %rdx.shuf

- %rdx.shuf12 = shufflevector <16 x i8> %bin.rdx11, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef>

- %bin.rdx13 = add <16 x i8> %bin.rdx11, %rdx.shuf12

- %rdx.shuf13 = shufflevector <16 x i8> %bin.rdx13, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef>

- %bin.rdx14 = add <16 x i8> %bin.rdx13, %rdx.shuf13

- %r = extractelement <16 x i8> %bin.rdx14, i32 0

+ %r = call i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8> %bin.rdx)

ret i8 %r

}

@@ -20,13 +18,7 @@ define i16 @add_H(<8 x i16>* %arr) {

; CHECK-LABEL: add_H

; CHECK: addv {{h[0-9]+}}, {{v[0-9]+}}.8h

%bin.rdx = load <8 x i16>, <8 x i16>* %arr

- %rdx.shuf = shufflevector <8 x i16> %bin.rdx, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef,i32 undef, i32 undef>

- %bin.rdx11 = add <8 x i16> %bin.rdx, %rdx.shuf

- %rdx.shuf12 = shufflevector <8 x i16> %bin.rdx11, <8 x i16> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx13 = add <8 x i16> %bin.rdx11, %rdx.shuf12

- %rdx.shuf13 = shufflevector <8 x i16> %bin.rdx13, <8 x i16> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx14 = add <8 x i16> %bin.rdx13, %rdx.shuf13

- %r = extractelement <8 x i16> %bin.rdx14, i32 0

+ %r = call i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16> %bin.rdx)

ret i16 %r

}

@@ -34,11 +26,7 @@ define i32 @add_S( <4 x i32>* %arr) {

; CHECK-LABEL: add_S

; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s

%bin.rdx = load <4 x i32>, <4 x i32>* %arr

- %rdx.shuf = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>

- %bin.rdx11 = add <4 x i32> %bin.rdx, %rdx.shuf

- %rdx.shuf12 = shufflevector <4 x i32> %bin.rdx11, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>

- %bin.rdx13 = add <4 x i32> %bin.rdx11, %rdx.shuf12

- %r = extractelement <4 x i32> %bin.rdx13, i32 0

+ %r = call i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32> %bin.rdx)

ret i32 %r

}

@@ -46,12 +34,12 @@ define i64 @add_D(<2 x i64>* %arr) {

; CHECK-LABEL: add_D

; CHECK-NOT: addv

%bin.rdx = load <2 x i64>, <2 x i64>* %arr

- %rdx.shuf0 = shufflevector <2 x i64> %bin.rdx, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>

- %bin.rdx0 = add <2 x i64> %bin.rdx, %rdx.shuf0

- %r = extractelement <2 x i64> %bin.rdx0, i32 0

+ %r = call i64 @llvm.experimental.vector.reduce.add.i64.v2i64(<2 x i64> %bin.rdx)

ret i64 %r

}

+declare i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32>)

define i32 @oversized_ADDV_256(i8* noalias nocapture readonly %arg1, i8* noalias nocapture readonly %arg2) {

; CHECK-LABEL: oversized_ADDV_256

; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s

@@ -66,33 +54,16 @@ entry:

%7 = icmp slt <8 x i32> %6, zeroinitializer

%8 = sub nsw <8 x i32> zeroinitializer, %6

%9 = select <8 x i1> %7, <8 x i32> %8, <8 x i32> %6

- %rdx.shuf = shufflevector <8 x i32> %9, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx = add <8 x i32> %9, %rdx.shuf

- %rdx.shuf1 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx2 = add <8 x i32> %bin.rdx, %rdx.shuf1

- %rdx.shuf3 = shufflevector <8 x i32> %bin.rdx2, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx4 = add <8 x i32> %bin.rdx2, %rdx.shuf3

- %10 = extractelement <8 x i32> %bin.rdx4, i32 0

- ret i32 %10

+ %r = call i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32> %9)

+ ret i32 %r

}

+declare i32 @llvm.experimental.vector.reduce.add.i32.v16i32(<16 x i32>)

define i32 @oversized_ADDV_512(<16 x i32>* %arr) {

; CHECK-LABEL: oversized_ADDV_512

; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s

%bin.rdx = load <16 x i32>, <16 x i32>* %arr

- %rdx.shuf0 = shufflevector <16 x i32> %bin.rdx, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx0 = add <16 x i32> %bin.rdx, %rdx.shuf0

- %rdx.shuf = shufflevector <16 x i32> %bin.rdx0, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef >

- %bin.rdx11 = add <16 x i32> %bin.rdx0, %rdx.shuf

- %rdx.shuf12 = shufflevector <16 x i32> %bin.rdx11, <16 x i32> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef>

- %bin.rdx13 = add <16 x i32> %bin.rdx11, %rdx.shuf12

- %rdx.shuf13 = shufflevector <16 x i32> %bin.rdx13, <16 x i32> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef, i32 undef, i32 undef,i32 undef, i32 undef>

- %bin.rdx14 = add <16 x i32> %bin.rdx13, %rdx.shuf13

- %r = extractelement <16 x i32> %bin.rdx14, i32 0

+ %r = call i32 @llvm.experimental.vector.reduce.add.i32.v16i32(<16 x i32> %bin.rdx)

ret i32 %r

}

diff --git a/test/CodeGen/AArch64/aarch64-minmaxv.ll b/test/CodeGen/AArch64/aarch64-minmaxv.ll
index 9a56cd6ae7c0..760a8f8419f9 100644
--- a/test/CodeGen/AArch64/aarch64-minmaxv.ll
+++ b/test/CodeGen/AArch64/aarch64-minmaxv.ll

@@ -2,344 +2,148 @@

target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"

+declare i8 @llvm.experimental.vector.reduce.smax.i8.v16i8(<16 x i8>)

+declare i16 @llvm.experimental.vector.reduce.smax.i16.v8i16(<8 x i16>)

+declare i32 @llvm.experimental.vector.reduce.smax.i32.v4i32(<4 x i32>)

+declare i8 @llvm.experimental.vector.reduce.umax.i8.v16i8(<16 x i8>)

+declare i16 @llvm.experimental.vector.reduce.umax.i16.v8i16(<8 x i16>)

+declare i32 @llvm.experimental.vector.reduce.umax.i32.v4i32(<4 x i32>)

+declare i8 @llvm.experimental.vector.reduce.smin.i8.v16i8(<16 x i8>)

+declare i16 @llvm.experimental.vector.reduce.smin.i16.v8i16(<8 x i16>)

+declare i32 @llvm.experimental.vector.reduce.smin.i32.v4i32(<4 x i32>)

+declare i8 @llvm.experimental.vector.reduce.umin.i8.v16i8(<16 x i8>)

+declare i16 @llvm.experimental.vector.reduce.umin.i16.v8i16(<8 x i16>)

+declare i32 @llvm.experimental.vector.reduce.umin.i32.v4i32(<4 x i32>)

+declare float @llvm.experimental.vector.reduce.fmax.f32.v4f32(<4 x float>)

+declare float @llvm.experimental.vector.reduce.fmin.f32.v4f32(<4 x float>)

; CHECK-LABEL: smax_B

; CHECK: smaxv {{b[0-9]+}}, {{v[0-9]+}}.16b

define i8 @smax_B(<16 x i8>* nocapture readonly %arr) {

%arr.load = load <16 x i8>, <16 x i8>* %arr

- %rdx.shuf = shufflevector <16 x i8> %arr.load, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp22 = icmp sgt <16 x i8> %arr.load, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i8> %arr.load, <16 x i8> %rdx.shuf

- %rdx.shuf24 = shufflevector <16 x i8> %rdx.minmax.select23, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp25 = icmp sgt <16 x i8> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i8> %rdx.minmax.select23, <16 x i8> %rdx.shuf24

- %rdx.shuf27 = shufflevector <16 x i8> %rdx.minmax.select26, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp28 = icmp sgt <16 x i8> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i8> %rdx.minmax.select26, <16 x i8> %rdx.shuf27

- %rdx.shuf30 = shufflevector <16 x i8> %rdx.minmax.select29, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp31 = icmp sgt <16 x i8> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i8> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i8> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i8 %rdx.minmax.select29.elt, i8 %rdx.shuf30.elt

+ %r = call i8 @llvm.experimental.vector.reduce.smax.i8.v16i8(<16 x i8> %arr.load)

ret i8 %r

}

; CHECK-LABEL: smax_H

; CHECK: smaxv {{h[0-9]+}}, {{v[0-9]+}}.8h

define i16 @smax_H(<8 x i16>* nocapture readonly %arr) {

- %rdx.minmax.select = load <8 x i16>, <8 x i16>* %arr

- %rdx.shuf = shufflevector <8 x i16> %rdx.minmax.select, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp23 = icmp sgt <8 x i16> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select24 = select <8 x i1> %rdx.minmax.cmp23, <8 x i16> %rdx.minmax.select, <8 x i16> %rdx.shuf

- %rdx.shuf25 = shufflevector <8 x i16> %rdx.minmax.select24, <8 x i16> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp26 = icmp sgt <8 x i16> %rdx.minmax.select24, %rdx.shuf25

- %rdx.minmax.select27 = select <8 x i1> %rdx.minmax.cmp26, <8 x i16> %rdx.minmax.select24, <8 x i16> %rdx.shuf25

- %rdx.shuf28 = shufflevector <8 x i16> %rdx.minmax.select27, <8 x i16> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp29 = icmp sgt <8 x i16> %rdx.minmax.select27, %rdx.shuf28

- %rdx.minmax.cmp29.elt = extractelement <8 x i1> %rdx.minmax.cmp29, i32 0

- %rdx.minmax.select27.elt = extractelement <8 x i16> %rdx.minmax.select27, i32 0

- %rdx.shuf28.elt = extractelement <8 x i16> %rdx.minmax.select27, i32 1

- %r = select i1 %rdx.minmax.cmp29.elt, i16 %rdx.minmax.select27.elt, i16 %rdx.shuf28.elt

+ %arr.load = load <8 x i16>, <8 x i16>* %arr

+ %r = call i16 @llvm.experimental.vector.reduce.smax.i16.v8i16(<8 x i16> %arr.load)

ret i16 %r

}

; CHECK-LABEL: smax_S

; CHECK: smaxv {{s[0-9]+}}, {{v[0-9]+}}.4s

define i32 @smax_S(<4 x i32> * nocapture readonly %arr) {

- %rdx.minmax.select = load <4 x i32>, <4 x i32>* %arr

- %rdx.shuf = shufflevector <4 x i32> %rdx.minmax.select, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>

- %rdx.minmax.cmp18 = icmp sgt <4 x i32> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select19 = select <4 x i1> %rdx.minmax.cmp18, <4 x i32> %rdx.minmax.select, <4 x i32> %rdx.shuf

- %rdx.shuf20 = shufflevector <4 x i32> %rdx.minmax.select19, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp21 = icmp sgt <4 x i32> %rdx.minmax.select19, %rdx.shuf20

- %rdx.minmax.cmp21.elt = extractelement <4 x i1> %rdx.minmax.cmp21, i32 0

- %rdx.minmax.select19.elt = extractelement <4 x i32> %rdx.minmax.select19, i32 0

- %rdx.shuf20.elt = extractelement <4 x i32> %rdx.minmax.select19, i32 1

- %r = select i1 %rdx.minmax.cmp21.elt, i32 %rdx.minmax.select19.elt, i32 %rdx.shuf20.elt

+ %arr.load = load <4 x i32>, <4 x i32>* %arr

+ %r = call i32 @llvm.experimental.vector.reduce.smax.i32.v4i32(<4 x i32> %arr.load)

ret i32 %r

}

-; CHECK-LABEL: smax_D

-; CHECK-NOT: smaxv

-define i64 @smax_D(<2 x i64>* nocapture readonly %arr) {

- %rdx.minmax.select = load <2 x i64>, <2 x i64>* %arr

- %rdx.shuf = shufflevector <2 x i64> %rdx.minmax.select, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>

- %rdx.minmax.cmp18 = icmp sgt <2 x i64> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.cmp18.elt = extractelement <2 x i1> %rdx.minmax.cmp18, i32 0

- %rdx.minmax.select.elt = extractelement <2 x i64> %rdx.minmax.select, i32 0

- %rdx.shuf.elt = extractelement <2 x i64> %rdx.minmax.select, i32 1

- %r = select i1 %rdx.minmax.cmp18.elt, i64 %rdx.minmax.select.elt, i64 %rdx.shuf.elt

- ret i64 %r

; CHECK-LABEL: umax_B

; CHECK: umaxv {{b[0-9]+}}, {{v[0-9]+}}.16b

define i8 @umax_B(<16 x i8>* nocapture readonly %arr) {

- %rdx.minmax.select = load <16 x i8>, <16 x i8>* %arr

- %rdx.shuf = shufflevector <16 x i8> %rdx.minmax.select, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp22 = icmp ugt <16 x i8> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i8> %rdx.minmax.select, <16 x i8> %rdx.shuf

- %rdx.minmax.cmp25 = icmp ugt <16 x i8> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i8> %rdx.minmax.select23, <16 x i8> %rdx.shuf24

- %rdx.minmax.cmp28 = icmp ugt <16 x i8> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i8> %rdx.minmax.select26, <16 x i8> %rdx.shuf27

- %rdx.minmax.cmp31 = icmp ugt <16 x i8> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i8> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i8> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i8 %rdx.minmax.select29.elt, i8 %rdx.shuf30.elt

+ %arr.load = load <16 x i8>, <16 x i8>* %arr

+ %r = call i8 @llvm.experimental.vector.reduce.umax.i8.v16i8(<16 x i8> %arr.load)

ret i8 %r

}

; CHECK-LABEL: umax_H

; CHECK: umaxv {{h[0-9]+}}, {{v[0-9]+}}.8h

define i16 @umax_H(<8 x i16>* nocapture readonly %arr) {

- %rdx.minmax.select = load <8 x i16>, <8 x i16>* %arr

- %rdx.shuf = shufflevector <8 x i16> %rdx.minmax.select, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp23 = icmp ugt <8 x i16> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select24 = select <8 x i1> %rdx.minmax.cmp23, <8 x i16> %rdx.minmax.select, <8 x i16> %rdx.shuf

- %rdx.shuf25 = shufflevector <8 x i16> %rdx.minmax.select24, <8 x i16> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp26 = icmp ugt <8 x i16> %rdx.minmax.select24, %rdx.shuf25

- %rdx.minmax.select27 = select <8 x i1> %rdx.minmax.cmp26, <8 x i16> %rdx.minmax.select24, <8 x i16> %rdx.shuf25

- %rdx.shuf28 = shufflevector <8 x i16> %rdx.minmax.select27, <8 x i16> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp29 = icmp ugt <8 x i16> %rdx.minmax.select27, %rdx.shuf28

- %rdx.minmax.cmp29.elt = extractelement <8 x i1> %rdx.minmax.cmp29, i32 0

- %rdx.minmax.select27.elt = extractelement <8 x i16> %rdx.minmax.select27, i32 0

- %rdx.shuf28.elt = extractelement <8 x i16> %rdx.minmax.select27, i32 1

- %r = select i1 %rdx.minmax.cmp29.elt, i16 %rdx.minmax.select27.elt, i16 %rdx.shuf28.elt

+ %arr.load = load <8 x i16>, <8 x i16>* %arr

+ %r = call i16 @llvm.experimental.vector.reduce.umax.i16.v8i16(<8 x i16> %arr.load)

ret i16 %r

}

; CHECK-LABEL: umax_S

; CHECK: umaxv {{s[0-9]+}}, {{v[0-9]+}}.4s

define i32 @umax_S(<4 x i32>* nocapture readonly %arr) {

- %rdx.minmax.select = load <4 x i32>, <4 x i32>* %arr

- %rdx.shuf = shufflevector <4 x i32> %rdx.minmax.select, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>

- %rdx.minmax.cmp18 = icmp ugt <4 x i32> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select19 = select <4 x i1> %rdx.minmax.cmp18, <4 x i32> %rdx.minmax.select, <4 x i32> %rdx.shuf

- %rdx.shuf20 = shufflevector <4 x i32> %rdx.minmax.select19, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp21 = icmp ugt <4 x i32> %rdx.minmax.select19, %rdx.shuf20

- %rdx.minmax.cmp21.elt = extractelement <4 x i1> %rdx.minmax.cmp21, i32 0

- %rdx.minmax.select19.elt = extractelement <4 x i32> %rdx.minmax.select19, i32 0

- %rdx.shuf20.elt = extractelement <4 x i32> %rdx.minmax.select19, i32 1

- %r = select i1 %rdx.minmax.cmp21.elt, i32 %rdx.minmax.select19.elt, i32 %rdx.shuf20.elt

+ %arr.load = load <4 x i32>, <4 x i32>* %arr

+ %r = call i32 @llvm.experimental.vector.reduce.umax.i32.v4i32(<4 x i32> %arr.load)

ret i32 %r

}

-; CHECK-LABEL: umax_D

-; CHECK-NOT: umaxv

-define i64 @umax_D(<2 x i64>* nocapture readonly %arr) {

- %rdx.minmax.select = load <2 x i64>, <2 x i64>* %arr

- %rdx.shuf = shufflevector <2 x i64> %rdx.minmax.select, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>

- %rdx.minmax.cmp18 = icmp ugt <2 x i64> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.cmp18.elt = extractelement <2 x i1> %rdx.minmax.cmp18, i32 0

- %rdx.minmax.select.elt = extractelement <2 x i64> %rdx.minmax.select, i32 0

- %rdx.shuf.elt = extractelement <2 x i64> %rdx.minmax.select, i32 1

- %r = select i1 %rdx.minmax.cmp18.elt, i64 %rdx.minmax.select.elt, i64 %rdx.shuf.elt

- ret i64 %r

; CHECK-LABEL: smin_B

; CHECK: sminv {{b[0-9]+}}, {{v[0-9]+}}.16b

define i8 @smin_B(<16 x i8>* nocapture readonly %arr) {

- %rdx.minmax.select = load <16 x i8>, <16 x i8>* %arr

- %rdx.minmax.cmp22 = icmp slt <16 x i8> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i8> %rdx.minmax.select, <16 x i8> %rdx.shuf

- %rdx.minmax.cmp25 = icmp slt <16 x i8> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i8> %rdx.minmax.select23, <16 x i8> %rdx.shuf24

- %rdx.minmax.cmp28 = icmp slt <16 x i8> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i8> %rdx.minmax.select26, <16 x i8> %rdx.shuf27

- %rdx.minmax.cmp31 = icmp slt <16 x i8> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i8> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i8> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i8 %rdx.minmax.select29.elt, i8 %rdx.shuf30.elt

+ %arr.load = load <16 x i8>, <16 x i8>* %arr

+ %r = call i8 @llvm.experimental.vector.reduce.smin.i8.v16i8(<16 x i8> %arr.load)

ret i8 %r

}

; CHECK-LABEL: smin_H

; CHECK: sminv {{h[0-9]+}}, {{v[0-9]+}}.8h

define i16 @smin_H(<8 x i16>* nocapture readonly %arr) {

- %rdx.minmax.select = load <8 x i16>, <8 x i16>* %arr

- %rdx.shuf = shufflevector <8 x i16> %rdx.minmax.select, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp23 = icmp slt <8 x i16> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select24 = select <8 x i1> %rdx.minmax.cmp23, <8 x i16> %rdx.minmax.select, <8 x i16> %rdx.shuf

- %rdx.shuf25 = shufflevector <8 x i16> %rdx.minmax.select24, <8 x i16> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp26 = icmp slt <8 x i16> %rdx.minmax.select24, %rdx.shuf25

- %rdx.minmax.select27 = select <8 x i1> %rdx.minmax.cmp26, <8 x i16> %rdx.minmax.select24, <8 x i16> %rdx.shuf25

- %rdx.shuf28 = shufflevector <8 x i16> %rdx.minmax.select27, <8 x i16> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp29 = icmp slt <8 x i16> %rdx.minmax.select27, %rdx.shuf28

- %rdx.minmax.cmp29.elt = extractelement <8 x i1> %rdx.minmax.cmp29, i32 0

- %rdx.minmax.select27.elt = extractelement <8 x i16> %rdx.minmax.select27, i32 0

- %rdx.shuf28.elt = extractelement <8 x i16> %rdx.minmax.select27, i32 1

- %r = select i1 %rdx.minmax.cmp29.elt, i16 %rdx.minmax.select27.elt, i16 %rdx.shuf28.elt

+ %arr.load = load <8 x i16>, <8 x i16>* %arr

+ %r = call i16 @llvm.experimental.vector.reduce.smin.i16.v8i16(<8 x i16> %arr.load)

ret i16 %r

}

; CHECK-LABEL: smin_S

; CHECK: sminv {{s[0-9]+}}, {{v[0-9]+}}.4s

define i32 @smin_S(<4 x i32>* nocapture readonly %arr) {

- %rdx.minmax.select = load <4 x i32>, <4 x i32>* %arr

- %rdx.shuf = shufflevector <4 x i32> %rdx.minmax.select, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>

- %rdx.minmax.cmp18 = icmp slt <4 x i32> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select19 = select <4 x i1> %rdx.minmax.cmp18, <4 x i32> %rdx.minmax.select, <4 x i32> %rdx.shuf

- %rdx.shuf20 = shufflevector <4 x i32> %rdx.minmax.select19, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp21 = icmp slt <4 x i32> %rdx.minmax.select19, %rdx.shuf20

- %rdx.minmax.cmp21.elt = extractelement <4 x i1> %rdx.minmax.cmp21, i32 0

- %rdx.minmax.select19.elt = extractelement <4 x i32> %rdx.minmax.select19, i32 0

- %rdx.shuf20.elt = extractelement <4 x i32> %rdx.minmax.select19, i32 1

- %r = select i1 %rdx.minmax.cmp21.elt, i32 %rdx.minmax.select19.elt, i32 %rdx.shuf20.elt

+ %arr.load = load <4 x i32>, <4 x i32>* %arr

+ %r = call i32 @llvm.experimental.vector.reduce.smin.i32.v4i32(<4 x i32> %arr.load)

ret i32 %r

}

-; CHECK-LABEL: smin_D

-; CHECK-NOT: sminv

-define i64 @smin_D(<2 x i64>* nocapture readonly %arr) {

- %rdx.minmax.select = load <2 x i64>, <2 x i64>* %arr

- %rdx.shuf = shufflevector <2 x i64> %rdx.minmax.select, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>

- %rdx.minmax.cmp18 = icmp slt <2 x i64> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.cmp18.elt = extractelement <2 x i1> %rdx.minmax.cmp18, i32 0

- %rdx.minmax.select.elt = extractelement <2 x i64> %rdx.minmax.select, i32 0

- %rdx.shuf.elt = extractelement <2 x i64> %rdx.minmax.select, i32 1

- %r = select i1 %rdx.minmax.cmp18.elt, i64 %rdx.minmax.select.elt, i64 %rdx.shuf.elt

- ret i64 %r

; CHECK-LABEL: umin_B

; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b

define i8 @umin_B(<16 x i8>* nocapture readonly %arr) {

- %rdx.minmax.select = load <16 x i8>, <16 x i8>* %arr

- %rdx.minmax.cmp22 = icmp ult <16 x i8> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i8> %rdx.minmax.select, <16 x i8> %rdx.shuf

- %rdx.minmax.cmp25 = icmp ult <16 x i8> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i8> %rdx.minmax.select23, <16 x i8> %rdx.shuf24

- %rdx.minmax.cmp28 = icmp ult <16 x i8> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i8> %rdx.minmax.select26, <16 x i8> %rdx.shuf27

- %rdx.minmax.cmp31 = icmp ult <16 x i8> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i8> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i8> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i8 %rdx.minmax.select29.elt, i8 %rdx.shuf30.elt

+ %arr.load = load <16 x i8>, <16 x i8>* %arr

+ %r = call i8 @llvm.experimental.vector.reduce.umin.i8.v16i8(<16 x i8> %arr.load)

ret i8 %r

}

; CHECK-LABEL: umin_H

; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h

define i16 @umin_H(<8 x i16>* nocapture readonly %arr) {

- %rdx.minmax.select = load <8 x i16>, <8 x i16>* %arr

- %rdx.shuf = shufflevector <8 x i16> %rdx.minmax.select, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp23 = icmp ult <8 x i16> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select24 = select <8 x i1> %rdx.minmax.cmp23, <8 x i16> %rdx.minmax.select, <8 x i16> %rdx.shuf

- %rdx.shuf25 = shufflevector <8 x i16> %rdx.minmax.select24, <8 x i16> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp26 = icmp ult <8 x i16> %rdx.minmax.select24, %rdx.shuf25

- %rdx.minmax.select27 = select <8 x i1> %rdx.minmax.cmp26, <8 x i16> %rdx.minmax.select24, <8 x i16> %rdx.shuf25

- %rdx.shuf28 = shufflevector <8 x i16> %rdx.minmax.select27, <8 x i16> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp29 = icmp ult <8 x i16> %rdx.minmax.select27, %rdx.shuf28

- %rdx.minmax.cmp29.elt = extractelement <8 x i1> %rdx.minmax.cmp29, i32 0

- %rdx.minmax.select27.elt = extractelement <8 x i16> %rdx.minmax.select27, i32 0

- %rdx.shuf28.elt = extractelement <8 x i16> %rdx.minmax.select27, i32 1

- %r = select i1 %rdx.minmax.cmp29.elt, i16 %rdx.minmax.select27.elt, i16 %rdx.shuf28.elt

+ %arr.load = load <8 x i16>, <8 x i16>* %arr

+ %r = call i16 @llvm.experimental.vector.reduce.umin.i16.v8i16(<8 x i16> %arr.load)

ret i16 %r

}

; CHECK-LABEL: umin_S

; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s

define i32 @umin_S(<4 x i32>* nocapture readonly %arr) {

- %rdx.minmax.select = load <4 x i32>, <4 x i32>* %arr

- %rdx.shuf = shufflevector <4 x i32> %rdx.minmax.select, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>

- %rdx.minmax.cmp18 = icmp ult <4 x i32> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select19 = select <4 x i1> %rdx.minmax.cmp18, <4 x i32> %rdx.minmax.select, <4 x i32> %rdx.shuf

- %rdx.shuf20 = shufflevector <4 x i32> %rdx.minmax.select19, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp21 = icmp ult <4 x i32> %rdx.minmax.select19, %rdx.shuf20

- %rdx.minmax.cmp21.elt = extractelement <4 x i1> %rdx.minmax.cmp21, i32 0

- %rdx.minmax.select19.elt = extractelement <4 x i32> %rdx.minmax.select19, i32 0

- %rdx.shuf20.elt = extractelement <4 x i32> %rdx.minmax.select19, i32 1

- %r = select i1 %rdx.minmax.cmp21.elt, i32 %rdx.minmax.select19.elt, i32 %rdx.shuf20.elt

+ %arr.load = load <4 x i32>, <4 x i32>* %arr

+ %r = call i32 @llvm.experimental.vector.reduce.umin.i32.v4i32(<4 x i32> %arr.load)

ret i32 %r

}

-; CHECK-LABEL: umin_D

-; CHECK-NOT: uminv

-define i64 @umin_D(<2 x i64>* nocapture readonly %arr) {

- %rdx.minmax.select = load <2 x i64>, <2 x i64>* %arr

- %rdx.shuf = shufflevector <2 x i64> %rdx.minmax.select, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>

- %rdx.minmax.cmp18 = icmp ult <2 x i64> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.cmp18.elt = extractelement <2 x i1> %rdx.minmax.cmp18, i32 0

- %rdx.minmax.select.elt = extractelement <2 x i64> %rdx.minmax.select, i32 0

- %rdx.shuf.elt = extractelement <2 x i64> %rdx.minmax.select, i32 1

- %r = select i1 %rdx.minmax.cmp18.elt, i64 %rdx.minmax.select.elt, i64 %rdx.shuf.elt

- ret i64 %r

; CHECK-LABEL: fmaxnm_S

; CHECK: fmaxnmv

define float @fmaxnm_S(<4 x float>* nocapture readonly %arr) {

- %rdx.minmax.select = load <4 x float>, <4 x float>* %arr

- %rdx.shuf = shufflevector <4 x float> %rdx.minmax.select, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>

- %rdx.minmax.cmp = fcmp fast oge <4 x float> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select1 = select <4 x i1> %rdx.minmax.cmp, <4 x float> %rdx.minmax.select, <4 x float> %rdx.shuf

- %rdx.shuf1 = shufflevector <4 x float> %rdx.minmax.select1, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp1 = fcmp fast oge <4 x float> %rdx.minmax.select1, %rdx.shuf1

- %rdx.minmax.cmp1.elt = extractelement <4 x i1> %rdx.minmax.cmp1, i32 0

- %rdx.minmax.select1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 0

- %rdx.shuf1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 1

- %r = select i1 %rdx.minmax.cmp1.elt, float %rdx.minmax.select1.elt, float %rdx.shuf1.elt

+ %arr.load = load <4 x float>, <4 x float>* %arr

+ %r = call nnan float @llvm.experimental.vector.reduce.fmax.f32.v4f32(<4 x float> %arr.load)

ret float %r

}

; CHECK-LABEL: fminnm_S

; CHECK: fminnmv

define float @fminnm_S(<4 x float>* nocapture readonly %arr) {

- %rdx.minmax.select = load <4 x float>, <4 x float>* %arr

- %rdx.shuf = shufflevector <4 x float> %rdx.minmax.select, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>

- %rdx.minmax.cmp = fcmp fast ole <4 x float> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select1 = select <4 x i1> %rdx.minmax.cmp, <4 x float> %rdx.minmax.select, <4 x float> %rdx.shuf

- %rdx.shuf1 = shufflevector <4 x float> %rdx.minmax.select1, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp1 = fcmp fast ole <4 x float> %rdx.minmax.select1, %rdx.shuf1

- %rdx.minmax.cmp1.elt = extractelement <4 x i1> %rdx.minmax.cmp1, i32 0

- %rdx.minmax.select1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 0

- %rdx.shuf1.elt = extractelement <4 x float> %rdx.minmax.select1, i32 1

- %r = select i1 %rdx.minmax.cmp1.elt, float %rdx.minmax.select1.elt, float %rdx.shuf1.elt

+ %arr.load = load <4 x float>, <4 x float>* %arr

+ %r = call nnan float @llvm.experimental.vector.reduce.fmin.f32.v4f32(<4 x float> %arr.load)

ret float %r

}

+declare i16 @llvm.experimental.vector.reduce.umax.i16.v16i16(<16 x i16>)

define i16 @oversized_umax_256(<16 x i16>* nocapture readonly %arr) {

; CHECK-LABEL: oversized_umax_256

; CHECK: umax [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h

; CHECK: umaxv {{h[0-9]+}}, [[V0]]

- %rdx.minmax.select = load <16 x i16>, <16 x i16>* %arr

- %rdx.shuf = shufflevector <16 x i16> %rdx.minmax.select, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp22 = icmp ugt <16 x i16> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i16> %rdx.minmax.select, <16 x i16> %rdx.shuf

- %rdx.shuf24 = shufflevector <16 x i16> %rdx.minmax.select23, <16 x i16> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp25 = icmp ugt <16 x i16> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i16> %rdx.minmax.select23, <16 x i16> %rdx.shuf24

- %rdx.shuf27 = shufflevector <16 x i16> %rdx.minmax.select26, <16 x i16> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp28 = icmp ugt <16 x i16> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i16> %rdx.minmax.select26, <16 x i16> %rdx.shuf27

- %rdx.shuf30 = shufflevector <16 x i16> %rdx.minmax.select29, <16 x i16> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp31 = icmp ugt <16 x i16> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i16> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i16> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i16 %rdx.minmax.select29.elt, i16 %rdx.shuf30.elt

+ %arr.load = load <16 x i16>, <16 x i16>* %arr

+ %r = call i16 @llvm.experimental.vector.reduce.umax.i16.v16i16(<16 x i16> %arr.load)

ret i16 %r

}

+declare i32 @llvm.experimental.vector.reduce.umax.i32.v16i32(<16 x i32>)

define i32 @oversized_umax_512(<16 x i32>* nocapture readonly %arr) {

; CHECK-LABEL: oversized_umax_512

; CHECK: umax v

@@ -347,47 +151,23 @@ define i32 @oversized_umax_512(<16 x i32>* nocapture readonly %arr) {

; CHECK-NEXT: umax [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s

; CHECK-NEXT: umaxv {{s[0-9]+}}, [[V0]]

%arr.load = load <16 x i32>, <16 x i32>* %arr

- %rdx.shuf = shufflevector <16 x i32> %arr.load, <16 x i32> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp22 = icmp ugt <16 x i32> %arr.load, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i32> %arr.load, <16 x i32> %rdx.shuf

- %rdx.shuf24 = shufflevector <16 x i32> %rdx.minmax.select23, <16 x i32> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp25 = icmp ugt <16 x i32> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i32> %rdx.minmax.select23, <16 x i32> %rdx.shuf24

- %rdx.shuf27 = shufflevector <16 x i32> %rdx.minmax.select26, <16 x i32> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp28 = icmp ugt <16 x i32> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i32> %rdx.minmax.select26, <16 x i32> %rdx.shuf27

- %rdx.shuf30 = shufflevector <16 x i32> %rdx.minmax.select29, <16 x i32> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp31 = icmp ugt <16 x i32> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i32> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i32> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i32 %rdx.minmax.select29.elt, i32 %rdx.shuf30.elt

+ %r = call i32 @llvm.experimental.vector.reduce.umax.i32.v16i32(<16 x i32> %arr.load)

ret i32 %r

}

+declare i16 @llvm.experimental.vector.reduce.umin.i16.v16i16(<16 x i16>)

define i16 @oversized_umin_256(<16 x i16>* nocapture readonly %arr) {

; CHECK-LABEL: oversized_umin_256

; CHECK: umin [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h

; CHECK: uminv {{h[0-9]+}}, [[V0]]

- %rdx.minmax.select = load <16 x i16>, <16 x i16>* %arr

- %rdx.minmax.cmp22 = icmp ult <16 x i16> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i16> %rdx.minmax.select, <16 x i16> %rdx.shuf

- %rdx.minmax.cmp25 = icmp ult <16 x i16> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i16> %rdx.minmax.select23, <16 x i16> %rdx.shuf24

- %rdx.minmax.cmp28 = icmp ult <16 x i16> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i16> %rdx.minmax.select26, <16 x i16> %rdx.shuf27

- %rdx.minmax.cmp31 = icmp ult <16 x i16> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i16> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i16> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i16 %rdx.minmax.select29.elt, i16 %rdx.shuf30.elt

+ %arr.load = load <16 x i16>, <16 x i16>* %arr

+ %r = call i16 @llvm.experimental.vector.reduce.umin.i16.v16i16(<16 x i16> %arr.load)

ret i16 %r

}

+declare i32 @llvm.experimental.vector.reduce.umin.i32.v16i32(<16 x i32>)

define i32 @oversized_umin_512(<16 x i32>* nocapture readonly %arr) {

; CHECK-LABEL: oversized_umin_512

; CHECK: umin v

@@ -395,47 +175,23 @@ define i32 @oversized_umin_512(<16 x i32>* nocapture readonly %arr) {

; CHECK-NEXT: umin [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s

; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]

%arr.load = load <16 x i32>, <16 x i32>* %arr

- %rdx.minmax.cmp22 = icmp ult <16 x i32> %arr.load, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i32> %arr.load, <16 x i32> %rdx.shuf

- %rdx.minmax.cmp25 = icmp ult <16 x i32> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i32> %rdx.minmax.select23, <16 x i32> %rdx.shuf24

- %rdx.minmax.cmp28 = icmp ult <16 x i32> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i32> %rdx.minmax.select26, <16 x i32> %rdx.shuf27

- %rdx.minmax.cmp31 = icmp ult <16 x i32> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i32> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i32> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i32 %rdx.minmax.select29.elt, i32 %rdx.shuf30.elt

+ %r = call i32 @llvm.experimental.vector.reduce.umin.i32.v16i32(<16 x i32> %arr.load)

ret i32 %r

}

+declare i16 @llvm.experimental.vector.reduce.smax.i16.v16i16(<16 x i16>)

define i16 @oversized_smax_256(<16 x i16>* nocapture readonly %arr) {

; CHECK-LABEL: oversized_smax_256

; CHECK: smax [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h

; CHECK: smaxv {{h[0-9]+}}, [[V0]]

%arr.load = load <16 x i16>, <16 x i16>* %arr

- %rdx.shuf = shufflevector <16 x i16> %arr.load, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %rdx.minmax.cmp22 = icmp sgt <16 x i16> %arr.load, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i16> %arr.load, <16 x i16> %rdx.shuf

- %rdx.minmax.cmp25 = icmp sgt <16 x i16> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i16> %rdx.minmax.select23, <16 x i16> %rdx.shuf24

- %rdx.minmax.cmp28 = icmp sgt <16 x i16> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i16> %rdx.minmax.select26, <16 x i16> %rdx.shuf27

- %rdx.minmax.cmp31 = icmp sgt <16 x i16> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i16> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i16> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i16 %rdx.minmax.select29.elt, i16 %rdx.shuf30.elt

+ %r = call i16 @llvm.experimental.vector.reduce.smax.i16.v16i16(<16 x i16> %arr.load)

ret i16 %r

}

+declare i32 @llvm.experimental.vector.reduce.smax.i32.v16i32(<16 x i32>)

define i32 @oversized_smax_512(<16 x i32>* nocapture readonly %arr) {

; CHECK-LABEL: oversized_smax_512

; CHECK: smax v

@@ -443,47 +199,23 @@ define i32 @oversized_smax_512(<16 x i32>* nocapture readonly %arr) {

; CHECK-NEXT: smax [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s

; CHECK-NEXT: smaxv {{s[0-9]+}}, [[V0]]

%arr.load = load <16 x i32>, <16 x i32>* %arr

- %rdx.minmax.cmp22 = icmp sgt <16 x i32> %arr.load, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i32> %arr.load, <16 x i32> %rdx.shuf

- %rdx.minmax.cmp25 = icmp sgt <16 x i32> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i32> %rdx.minmax.select23, <16 x i32> %rdx.shuf24

- %rdx.minmax.cmp28 = icmp sgt <16 x i32> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i32> %rdx.minmax.select26, <16 x i32> %rdx.shuf27

- %rdx.minmax.cmp31 = icmp sgt <16 x i32> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i32> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i32> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i32 %rdx.minmax.select29.elt, i32 %rdx.shuf30.elt

+ %r = call i32 @llvm.experimental.vector.reduce.smax.i32.v16i32(<16 x i32> %arr.load)

ret i32 %r

}

+declare i16 @llvm.experimental.vector.reduce.smin.i16.v16i16(<16 x i16>)

define i16 @oversized_smin_256(<16 x i16>* nocapture readonly %arr) {

; CHECK-LABEL: oversized_smin_256

; CHECK: smin [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h

; CHECK: sminv {{h[0-9]+}}, [[V0]]

- %rdx.minmax.select = load <16 x i16>, <16 x i16>* %arr

- %rdx.minmax.cmp22 = icmp slt <16 x i16> %rdx.minmax.select, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i16> %rdx.minmax.select, <16 x i16> %rdx.shuf

- %rdx.minmax.cmp25 = icmp slt <16 x i16> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i16> %rdx.minmax.select23, <16 x i16> %rdx.shuf24

- %rdx.minmax.cmp28 = icmp slt <16 x i16> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i16> %rdx.minmax.select26, <16 x i16> %rdx.shuf27

- %rdx.minmax.cmp31 = icmp slt <16 x i16> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i16> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i16> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i16 %rdx.minmax.select29.elt, i16 %rdx.shuf30.elt

+ %arr.load = load <16 x i16>, <16 x i16>* %arr

+ %r = call i16 @llvm.experimental.vector.reduce.smin.i16.v16i16(<16 x i16> %arr.load)

ret i16 %r

}

+declare i32 @llvm.experimental.vector.reduce.smin.i32.v16i32(<16 x i32>)

define i32 @oversized_smin_512(<16 x i32>* nocapture readonly %arr) {

; CHECK-LABEL: oversized_smin_512

; CHECK: smin v

@@ -491,20 +223,6 @@ define i32 @oversized_smin_512(<16 x i32>* nocapture readonly %arr) {

; CHECK-NEXT: smin [[V0:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s

; CHECK-NEXT: sminv {{s[0-9]+}}, [[V0]]

%arr.load = load <16 x i32>, <16 x i32>* %arr

- %rdx.minmax.cmp22 = icmp slt <16 x i32> %arr.load, %rdx.shuf

- %rdx.minmax.select23 = select <16 x i1> %rdx.minmax.cmp22, <16 x i32> %arr.load, <16 x i32> %rdx.shuf

- %rdx.minmax.cmp25 = icmp slt <16 x i32> %rdx.minmax.select23, %rdx.shuf24

- %rdx.minmax.select26 = select <16 x i1> %rdx.minmax.cmp25, <16 x i32> %rdx.minmax.select23, <16 x i32> %rdx.shuf24

- %rdx.minmax.cmp28 = icmp slt <16 x i32> %rdx.minmax.select26, %rdx.shuf27

- %rdx.minmax.select29 = select <16 x i1> %rdx.minmax.cmp28, <16 x i32> %rdx.minmax.select26, <16 x i32> %rdx.shuf27

- %rdx.minmax.cmp31 = icmp slt <16 x i32> %rdx.minmax.select29, %rdx.shuf30

- %rdx.minmax.cmp31.elt = extractelement <16 x i1> %rdx.minmax.cmp31, i32 0

- %rdx.minmax.select29.elt = extractelement <16 x i32> %rdx.minmax.select29, i32 0

- %rdx.shuf30.elt = extractelement <16 x i32> %rdx.minmax.select29, i32 1

- %r = select i1 %rdx.minmax.cmp31.elt, i32 %rdx.minmax.select29.elt, i32 %rdx.shuf30.elt

+ %r = call i32 @llvm.experimental.vector.reduce.smin.i32.v16i32(<16 x i32> %arr.load)

ret i32 %r

}

diff --git a/test/CodeGen/AArch64/arm64-vabs.ll b/test/CodeGen/AArch64/arm64-vabs.ll
index c7b0c33550d0..ff7a0a8300e2 100644
--- a/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/test/CodeGen/AArch64/arm64-vabs.ll

@@ -134,8 +134,10 @@ define <2 x i64> @uabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind {

ret <2 x i64> %tmp4

}

-define i16 @uabdl8h_log2_shuffle(<16 x i8>* %a, <16 x i8>* %b) {

-; CHECK-LABEL: uabdl8h_log2_shuffle

+declare i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16>)

+define i16 @uabdl8h_rdx(<16 x i8>* %a, <16 x i8>* %b) {

+; CHECK-LABEL: uabdl8h_rdx

; CHECK: uabdl2.8h

; CHECK: uabdl.8h

%aload = load <16 x i8>, <16 x i8>* %a, align 1

@@ -146,20 +148,14 @@ define i16 @uabdl8h_log2_shuffle(<16 x i8>* %a, <16 x i8>* %b) {

%abcmp = icmp slt <16 x i16> %abdiff, zeroinitializer

%ababs = sub nsw <16 x i16> zeroinitializer, %abdiff

%absel = select <16 x i1> %abcmp, <16 x i16> %ababs, <16 x i16> %abdiff

- %rdx.shuf = shufflevector <16 x i16> %absel, <16 x i16> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin1.rdx = add <16 x i16> %absel, %rdx.shuf

- %rdx.shufx = shufflevector <16 x i16> %bin1.rdx, <16 x i16> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx = add <16 x i16> %bin1.rdx, %rdx.shufx

- %rdx.shuf136 = shufflevector <16 x i16> %bin.rdx, <16 x i16> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx137 = add <16 x i16> %bin.rdx, %rdx.shuf136

- %rdx.shuf138 = shufflevector <16 x i16> %bin.rdx137, <16 x i16> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx139 = add <16 x i16> %bin.rdx137, %rdx.shuf138

- %reduced_v = extractelement <16 x i16> %bin.rdx139, i16 0

+ %reduced_v = call i16 @llvm.experimental.vector.reduce.add.i16.v16i16(<16 x i16> %absel)

ret i16 %reduced_v

}

-define i32 @uabdl4s_log2_shuffle(<8 x i16>* %a, <8 x i16>* %b) {

-; CHECK-LABEL: uabdl4s_log2_shuffle

+declare i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32>)

+define i32 @uabdl4s_rdx(<8 x i16>* %a, <8 x i16>* %b) {

+; CHECK-LABEL: uabdl4s_rdx

; CHECK: uabdl2.4s

; CHECK: uabdl.4s

%aload = load <8 x i16>, <8 x i16>* %a, align 1

@@ -170,18 +166,14 @@ define i32 @uabdl4s_log2_shuffle(<8 x i16>* %a, <8 x i16>* %b) {

%abcmp = icmp slt <8 x i32> %abdiff, zeroinitializer

%ababs = sub nsw <8 x i32> zeroinitializer, %abdiff

%absel = select <8 x i1> %abcmp, <8 x i32> %ababs, <8 x i32> %abdiff

- %rdx.shuf = shufflevector <8 x i32> %absel, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx = add <8 x i32> %absel, %rdx.shuf

- %rdx.shuf136 = shufflevector <8 x i32> %bin.rdx, <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx137 = add <8 x i32> %bin.rdx, %rdx.shuf136

- %rdx.shuf138 = shufflevector <8 x i32> %bin.rdx137, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>

- %bin.rdx139 = add <8 x i32> %bin.rdx137, %rdx.shuf138

- %reduced_v = extractelement <8 x i32> %bin.rdx139, i32 0

+ %reduced_v = call i32 @llvm.experimental.vector.reduce.add.i32.v8i32(<8 x i32> %absel)

ret i32 %reduced_v

}

-define i64 @uabdl2d_log2_shuffle(<4 x i32>* %a, <4 x i32>* %b, i32 %h) {

-; CHECK: uabdl2d_log2_shuffle

+declare i64 @llvm.experimental.vector.reduce.add.i64.v4i64(<4 x i64>)

+define i64 @uabdl2d_rdx(<4 x i32>* %a, <4 x i32>* %b, i32 %h) {

+; CHECK: uabdl2d_rdx

; CHECK: uabdl2.2d

; CHECK: uabdl.2d

%aload = load <4 x i32>, <4 x i32>* %a, align 1

@@ -192,11 +184,7 @@ define i64 @uabdl2d_log2_shuffle(<4 x i32>* %a, <4 x i32>* %b, i32 %h) {

%abcmp = icmp slt <4 x i64> %abdiff, zeroinitializer

%ababs = sub nsw <4 x i64> zeroinitializer, %abdiff

%absel = select <4 x i1> %abcmp, <4 x i64> %ababs, <4 x i64> %abdiff

- %rdx.shuf136 = shufflevector <4 x i64> %absel, <4 x i64> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>

- %bin.rdx137 = add <4 x i64> %absel, %rdx.shuf136

- %rdx.shuf138 = shufflevector <4 x i64> %bin.rdx137, <4 x i64> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>

- %bin.rdx139 = add <4 x i64> %bin.rdx137, %rdx.shuf138

- %reduced_v = extractelement <4 x i64> %bin.rdx139, i16 0

+ %reduced_v = call i64 @llvm.experimental.vector.reduce.add.i64.v4i64(<4 x i64> %absel)

ret i64 %reduced_v

}

diff --git a/test/CodeGen/AArch64/ldst-zero.ll b/test/CodeGen/AArch64/ldst-zero.ll
index 95b92ac70879..7d443a631f91 100644
--- a/test/CodeGen/AArch64/ldst-zero.ll
+++ b/test/CodeGen/AArch64/ldst-zero.ll

@@ -9,9 +9,9 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)

; Original test case which exhibited the bug

define void @test1(%struct.tree_common* %t, i32 %code, i8* %type) {

; CHECK-LABEL: test1:

-; CHECK: stp xzr, xzr, [x0, #8]

-; CHECK: stp xzr, x2, [x0]

-; CHECK: str w1, [x0, #16]

+; CHECK-DAG: stp x2, xzr, [x0, #8]

+; CHECK-DAG: str w1, [x0, #16]

+; CHECK-DAG: str xzr, [x0]

entry:

%0 = bitcast %struct.tree_common* %t to i8*

tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 24, i32 8, i1 false)

@@ -25,10 +25,8 @@ entry:

; Store to each struct element instead of using memset

define void @test2(%struct.tree_common* %t, i32 %code, i8* %type) {

; CHECK-LABEL: test2:

-; CHECK: stp xzr, xzr, [x0]

-; CHECK: str wzr, [x0, #16]

-; CHECK: str w1, [x0, #16]

-; CHECK: str x2, [x0, #8]

+; CHECK-DAG: str w1, [x0, #16]

+; CHECK-DAG: stp xzr, x2, [x0]

entry:

%0 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 0

%1 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 1

@@ -44,9 +42,9 @@ entry:

; Vector store instead of memset

define void @test3(%struct.tree_common* %t, i32 %code, i8* %type) {

; CHECK-LABEL: test3:

-; CHECK: stp xzr, xzr, [x0, #8]

-; CHECK: stp xzr, x2, [x0]

-; CHECK: str w1, [x0, #16]

+; CHECK-DAG: stp x2, xzr, [x0, #8]

+; CHECK-DAG: str w1, [x0, #16]

+; CHECK-DAG: str xzr, [x0]

entry:

%0 = bitcast %struct.tree_common* %t to <3 x i64>*

store <3 x i64> zeroinitializer, <3 x i64>* %0, align 8

@@ -60,9 +58,8 @@ entry:

; Vector store, then store to vector elements

define void @test4(<3 x i64>* %p, i64 %x, i64 %y) {

; CHECK-LABEL: test4:

-; CHECK: stp xzr, xzr, [x0, #8]

-; CHECK: stp xzr, x2, [x0]

-; CHECK: str x1, [x0, #16]

+; CHECK-DAG: stp x2, x1, [x0, #8]

+; CHECK-DAG: str xzr, [x0]

entry:

store <3 x i64> zeroinitializer, <3 x i64>* %p, align 8

%0 = bitcast <3 x i64>* %p to i64*

diff --git a/test/CodeGen/AArch64/misched-stp.ll b/test/CodeGen/AArch64/misched-stp.ll
index 4ea481cae68e..1c9ea68834c2 100644
--- a/test/CodeGen/AArch64/misched-stp.ll
+++ b/test/CodeGen/AArch64/misched-stp.ll

@@ -1,20 +1,18 @@

; REQUIRES: asserts

-; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+use-aa -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s

+; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+use-aa -enable-misched -verify-misched -o - | FileCheck %s

; Tests to check that the scheduler dependencies derived from alias analysis are

; correct when we have loads that have been split up so that they can later be

; merged into STP.

-; CHECK: ********** MI Scheduling **********

-; CHECK: test_splat:BB#0 entry

-; CHECK: SU({{[0-9]+}}): STRWui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 3; mem:ST4[%3+8]

-; CHECK: Successors:

-; CHECK-NEXT: ord [[SU1:SU\([0-9]+\)]]

-; CHECK: SU({{[0-9]+}}): STRWui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 2; mem:ST4[%3+4]

-; CHECK: Successors:

-; CHECK-NEXT: ord [[SU2:SU\([0-9]+\)]]

-; CHECK: [[SU1]]: STRWui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 3; mem:ST4[%2]

-; CHECK: [[SU2]]: STRWui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 2; mem:ST4[%1]

+; Now that overwritten stores are elided in SelectionDAG, dependencies

+; are resolved and removed before MISCHED. Check that we have

+; equivalent pair of stp calls as a baseline.

+; CHECK-LABEL: test_splat

+; CHECK: ldr [[REG:w[0-9]+]], [x2]

+; CHECK-DAG: stp w0, [[REG]], [x2, #12]

+; CHECK-DAG: stp [[REG]], w1, [x2, #4]

define void @test_splat(i32 %x, i32 %y, i32* %p) {

entry:

%val = load i32, i32* %p, align 4

@@ -35,16 +33,11 @@ entry:

declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1)

%struct.tree_common = type { i8*, i8*, i32 }

-; CHECK: ********** MI Scheduling **********

-; CHECK: test_zero:BB#0 entry

-; CHECK: SU({{[0-9]+}}): STRXui %XZR, %vreg{{[0-9]+}}, 2; mem:ST8[%0+16]

-; CHECK: Successors:

-; CHECK-NEXT: ord [[SU3:SU\([0-9]+\)]]

-; CHECK: SU({{[0-9]+}}): STRXui %XZR, %vreg{{[0-9]+}}, 1; mem:ST8[%0+8]

-; CHECK: Successors:

-; CHECK-NEXT: ord [[SU4:SU\([0-9]+\)]]

-; CHECK: [[SU3]]: STRWui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 4; mem:ST4[%code1]

-; CHECK: [[SU4]]: STRXui %vreg{{[0-9]+}}, %vreg{{[0-9]+}}, 1; mem:ST8[%type2]

+; CHECK-LABEL: test_zero

+; CHECK-DAG: stp x2, xzr, [x0, #8]

+; CHECK-DAG: str w1, [x0, #16]

+; CHECK-DAG: str xzr, [x0]

define void @test_zero(%struct.tree_common* %t, i32 %code, i8* %type) {

entry:

%0 = bitcast %struct.tree_common* %t to i8*