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authorDimitry Andric <dim@FreeBSD.org>2017-05-02 18:30:13 +0000
committerDimitry Andric <dim@FreeBSD.org>2017-05-02 18:30:13 +0000
commita303c417bbdb53703c2c17398b08486bde78f1f6 (patch)
tree98366d6b93d863cefdc53f16c66c0c5ae7fb2261 /test/CodeGen/AArch64
parent12f3ca4cdb95b193af905a00e722a4dcb40b3de3 (diff)
vendor/llvm/llvm-trunk-r301939
Notes
Diffstat (limited to 'test/CodeGen/AArch64')
-rw-r--r--test/CodeGen/AArch64/arm64-anyregcc.ll194
-rw-r--r--test/CodeGen/AArch64/arm64-stackmap.ll76
-rw-r--r--test/CodeGen/AArch64/arm64-tls-dynamics.ll32
-rw-r--r--test/CodeGen/AArch64/stackmap-liveness.ll3
4 files changed, 217 insertions, 88 deletions
diff --git a/test/CodeGen/AArch64/arm64-anyregcc.ll b/test/CodeGen/AArch64/arm64-anyregcc.ll
index 1af310383243..10989a07990c 100644
--- a/test/CodeGen/AArch64/arm64-anyregcc.ll
+++ b/test/CodeGen/AArch64/arm64-anyregcc.ll
@@ -4,7 +4,7 @@
; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
; CHECK-NEXT: __LLVM_StackMaps:
; Header
-; CHECK-NEXT: .byte 2
+; CHECK-NEXT: .byte 3
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .short 0
; Num Functions
@@ -48,18 +48,24 @@
; CHECK-NEXT: .short 3
; Loc 0: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 4
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 4
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Constant 3
; CHECK-NEXT: .byte 4
-; CHECK-NEXT: .byte 8
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
+; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 3
define i64 @test() nounwind ssp uwtable {
entry:
@@ -69,18 +75,22 @@ entry:
; property access 1 - %obj is an anyreg call argument and should therefore be in a register
; CHECK-LABEL: .long L{{.*}}-_property_access1
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
entry:
@@ -91,18 +101,22 @@ entry:
; property access 2 - %obj is an anyreg call argument and should therefore be in a register
; CHECK-LABEL: .long L{{.*}}-_property_access2
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @property_access2() nounwind ssp uwtable {
entry:
@@ -114,18 +128,22 @@ entry:
; property access 3 - %obj is a frame index
; CHECK-LABEL: .long L{{.*}}-_property_access3
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Direct FP - 8
; CHECK-NEXT: .byte 2
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long -8
define i64 @property_access3() nounwind ssp uwtable {
entry:
@@ -137,78 +155,106 @@ entry:
; anyreg_test1
; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; 14 locations
; CHECK-NEXT: .short 14
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 3: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 4: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 5: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 6: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 7: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 8: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 9: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 10: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 11: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 12: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 13: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
entry:
@@ -219,78 +265,106 @@ entry:
; anyreg_test2
; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 0
; 14 locations
; CHECK-NEXT: .short 14
; Loc 0: Register <-- this is the return register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 3: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 4: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 5: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 6: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 7: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 8: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 9: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 10: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 11: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 12: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 13: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
entry:
@@ -308,18 +382,24 @@ entry:
; CHECK-NEXT: .short 3
; Loc 0: Register (some register that will be spilled to the stack)
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry:
@@ -337,28 +417,38 @@ entry:
; CHECK-NEXT: .short 5
; Loc 0: Return a register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 1: Arg0 in a Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 2: Arg1 in a Register
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; Loc 3: Arg2 spilled to FP -96
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long -96
; Loc 4: Arg3 spilled to FP - 88
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long -88
define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry:
diff --git a/test/CodeGen/AArch64/arm64-stackmap.ll b/test/CodeGen/AArch64/arm64-stackmap.ll
index 0b2e9776263d..e12a35a93e22 100644
--- a/test/CodeGen/AArch64/arm64-stackmap.ll
+++ b/test/CodeGen/AArch64/arm64-stackmap.ll
@@ -10,7 +10,7 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
; CHECK-NEXT: __LLVM_StackMaps:
; Header
-; CHECK-NEXT: .byte 2
+; CHECK-NEXT: .byte 3
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .short 0
; Num Functions
@@ -67,22 +67,30 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
; CHECK-NEXT: .short 4
; SmallConstant
; CHECK-NEXT: .byte 4
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 65535
; SmallConstant
; CHECK-NEXT: .byte 4
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 65536
; SmallConstant
; CHECK-NEXT: .byte 5
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; LargeConstant at index 0
; CHECK-NEXT: .byte 5
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 1
@@ -99,12 +107,16 @@ entry:
; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 2
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define void @osrinline(i64 %a, i64 %b) {
entry:
@@ -123,12 +135,16 @@ entry:
; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 2
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define void @osrcold(i64 %a, i64 %b) {
entry:
@@ -163,12 +179,16 @@ entry:
; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 2
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) {
entry:
@@ -185,12 +205,16 @@ entry:
; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 2
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
entry:
@@ -207,12 +231,16 @@ entry:
; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 2
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
; CHECK-NEXT: .byte 1
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 0
define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) {
entry:
@@ -233,8 +261,11 @@ entry:
; Check that at least one is a spilled entry from RBP.
; Location: Indirect FP + ...
; CHECK: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short
; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
+; CHECK-NEXT: .long
define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) {
entry:
call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 20, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27)
@@ -252,8 +283,11 @@ entry:
; Check that at least one is a spilled entry from RBP.
; Location: Indirect FP + ...
; CHECK: .byte 3
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short
; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
+; CHECK-NEXT: .long
define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) {
entry:
call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29)
@@ -269,7 +303,9 @@ entry:
; CHECK-NEXT: .short 1
; Loc 0: SmallConstant
; CHECK-NEXT: .byte 4
-; CHECK-NEXT: .byte 8
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 8
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 0
; CHECK-NEXT: .long 33
@@ -286,8 +322,10 @@ define void @liveConstant() {
; CHECK-NEXT: .short 1
; Loc 0: Indirect FP (r29) - offset
; CHECK-NEXT: .byte 3
-; CHECK-NEXT: .byte 4
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 4
; CHECK-NEXT: .short 29
+; CHECK-NEXT: .short 0
; CHECK-NEXT: .long -{{[0-9]+}}
define void @clobberLR(i32 %a) {
tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x31}"() nounwind
diff --git a/test/CodeGen/AArch64/arm64-tls-dynamics.ll b/test/CodeGen/AArch64/arm64-tls-dynamics.ll
index 88700a153437..17979f4036cb 100644
--- a/test/CodeGen/AArch64/arm64-tls-dynamics.ll
+++ b/test/CodeGen/AArch64/arm64-tls-dynamics.ll
@@ -30,13 +30,13 @@ define i32 @test_generaldynamic() {
; CHECK-NOLD: ldr w0, [x[[TP]], x0]
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
}
@@ -56,13 +56,13 @@ define i32* @test_generaldynamic_addr() {
; CHECK: add x0, [[TP]], x0
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
}
@@ -95,15 +95,15 @@ define i32 @test_localdynamic() {
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12
; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
}
@@ -131,15 +131,15 @@ define i32* @test_localdynamic_addr() {
ret i32* @local_dynamic_var
; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12
; CHECK-RELOC: R_AARCH64_TLSDESC_CALL
; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12
; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC
-; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12
+; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12
; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL
}
diff --git a/test/CodeGen/AArch64/stackmap-liveness.ll b/test/CodeGen/AArch64/stackmap-liveness.ll
index 4b04276ac226..b66dbfae6c8a 100644
--- a/test/CodeGen/AArch64/stackmap-liveness.ll
+++ b/test/CodeGen/AArch64/stackmap-liveness.ll
@@ -5,7 +5,7 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
; CHECK-NEXT: __LLVM_StackMaps:
; Header
-; CHECK-NEXT: .byte 2
+; CHECK-NEXT: .byte 3
; CHECK-NEXT: .byte 0
; CHECK-NEXT: .short 0
; Num Functions
@@ -25,6 +25,7 @@ define i64 @stackmap_liveness(i1 %c) {
; CHECK-NEXT: .short 0
; CHECK-NEXT: .short 0
; Padding
+; CHECK-NEXT: .p2align 3
; CHECK-NEXT: .short 0
; Num LiveOut Entries: 1
; CHECK-NEXT: .short 2
generated by cgit v1.3 (git 2.53.0) at 2026-05-02 23:40:17 +0000