vendor/llvm/llvm-trunk-r300422

43 files changed, 81 insertions, 43 deletions

diff --git a/test/CodeGen/AVR/inline-asm/inline-asm.ll b/test/CodeGen/AVR/inline-asm/inline-asm.ll
index 678395a3e5c4..88d0c3af2e88 100644
--- a/test/CodeGen/AVR/inline-asm/inline-asm.ll
+++ b/test/CodeGen/AVR/inline-asm/inline-asm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=movw | FileCheck %s
+; RUN: llc < %s -march=avr -mattr=movw -no-integrated-as | FileCheck %s
 
 ; CHECK-LABEL: no_operands:
 define void @no_operands() {
diff --git a/test/CodeGen/AVR/inline-asm/inline-asm2.ll b/test/CodeGen/AVR/inline-asm/inline-asm2.ll
index 083390999b8a..74365b42c60e 100644
--- a/test/CodeGen/AVR/inline-asm/inline-asm2.ll
+++ b/test/CodeGen/AVR/inline-asm/inline-asm2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -no-integrated-as | FileCheck %s
 
 ; CHECK-LABEL: foo
 define void @foo(i16 %a) {
diff --git a/test/CodeGen/AVR/inline-asm/multibyte.ll b/test/CodeGen/AVR/inline-asm/multibyte.ll
index 34cdf5d006e9..a7c8f6e75f0f 100644
--- a/test/CodeGen/AVR/inline-asm/multibyte.ll
+++ b/test/CodeGen/AVR/inline-asm/multibyte.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -no-integrated-as | FileCheck %s
 ; XFAIL: *
 
 ; Multibyte references
diff --git a/test/CodeGen/AVR/intrinsics/stacksave-restore.ll b/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
new file mode 100644
index 000000000000..3985f49b92f5
--- /dev/null
+++ b/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
@@ -0,0 +1,27 @@
+; RUN: llc -O0 < %s -march=avr | FileCheck %s
+
+; CHECK-LABEL: foo
+define void @foo() {
+entry:
+  br label %save
+
+; CHECK-LABEL: save
+; CHECK: in [[SREG1:r[0-9]+]], 61
+; CHECK-NEXT: in [[SREG2:r[0-9]+]], 62
+save:
+  %saved = call i8* @llvm.stacksave()
+  br label %restore
+
+; CHECK-LABEL: restore
+; CHECK: in r0, 63
+; CHECK-NEXT: cli
+; CHECK-NEXT: out 62, [[SREG2]]
+; CHECK-NEXT: out 63, r0
+; CHECK-NEXT: out 61, [[SREG1]]
+restore:
+  call void @llvm.stackrestore(i8* %saved)
+  ret void
+}
+
+declare i8* @llvm.stacksave()
+declare void @llvm.stackrestore(i8* %ptr)
diff --git a/test/CodeGen/AVR/no-print-operand-twice.ll b/test/CodeGen/AVR/no-print-operand-twice.ll
new file mode 100644
index 000000000000..8326507768ba
--- /dev/null
+++ b/test/CodeGen/AVR/no-print-operand-twice.ll
@@ -0,0 +1,8 @@
+; RUN: llc -no-integrated-as -march=avr < %s | FileCheck %s
+
+define void @test() {
+entry:
+; CHECK: /* result: 68719476738 */
+  tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 )
+  ret void
+}
diff --git a/test/CodeGen/AVR/pseudo/ADCWRdRr.mir b/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
index 475d5b39299c..b1fc792d6594 100644
--- a/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
+++ b/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit add with carry pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/ADDWRdRr.mir b/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
index 2205febcc933..5743b1536330 100644
--- a/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
+++ b/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit add pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/ANDIWRdK.mir b/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
index 5af8db159519..bcea4e6dfe27 100644
--- a/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
+++ b/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit ANDO pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/ANDWRdRr.mir b/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
index c9458e9ba5d6..f6b060a5d734 100644
--- a/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
+++ b/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit AND pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/ASRWRd.mir b/test/CodeGen/AVR/pseudo/ASRWRd.mir
index 3e809564ca1c..5253dcd87f13 100644
--- a/test/CodeGen/AVR/pseudo/ASRWRd.mir
+++ b/test/CodeGen/AVR/pseudo/ASRWRd.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/COMWRd.mir b/test/CodeGen/AVR/pseudo/COMWRd.mir
index 282d601686ad..58ff7af7cb3c 100644
--- a/test/CodeGen/AVR/pseudo/COMWRd.mir
+++ b/test/CodeGen/AVR/pseudo/COMWRd.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit COM pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/CPCWRdRr.mir b/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
index 2081aa0b5ee4..c0ab60e89291 100644
--- a/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
+++ b/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit CPCW pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/CPWRdRr.mir b/test/CodeGen/AVR/pseudo/CPWRdRr.mir
index 7e25e7fe2272..c93c99151a49 100644
--- a/test/CodeGen/AVR/pseudo/CPWRdRr.mir
+++ b/test/CodeGen/AVR/pseudo/CPWRdRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit CPW pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/EORWRdRr.mir b/test/CodeGen/AVR/pseudo/EORWRdRr.mir
index 8769c12cbb11..de53c2d077ed 100644
--- a/test/CodeGen/AVR/pseudo/EORWRdRr.mir
+++ b/test/CodeGen/AVR/pseudo/EORWRdRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit EOR pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/FRMIDX.mir b/test/CodeGen/AVR/pseudo/FRMIDX.mir
index 47a9397fa6b0..b56122a43ada 100644
--- a/test/CodeGen/AVR/pseudo/FRMIDX.mir
+++ b/test/CodeGen/AVR/pseudo/FRMIDX.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # TODO: Write this test.
 # This instruction isn't expanded by the pseudo expansion passs, but
diff --git a/test/CodeGen/AVR/pseudo/INWRdA.mir b/test/CodeGen/AVR/pseudo/INWRdA.mir
index a801598faddd..1b2d7fa0f539 100644
--- a/test/CodeGen/AVR/pseudo/INWRdA.mir
+++ b/test/CodeGen/AVR/pseudo/INWRdA.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir b/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
index 781cb5d82433..5ff2ef1742e0 100644
--- a/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
+++ b/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0  %s -o - 2>&1 -march=avr | FileCheck %s
+# RUN: llc -O0  %s -o - -march=avr | FileCheck %s
 
 # This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction.
 
@@ -12,6 +12,7 @@
 
 ---
 name:            test_lddwrdptrq
+tracksRegLiveness: true
 body: |
   bb.0.entry:
 
@@ -20,5 +21,5 @@ body: |
     ; CHECK:      ldd     r30, Y+10
     ; CHECK-NEXT: ldd     r31, Y+11
 
-    early-clobber %r31r30 = LDDWRdPtrQ %r29r28, 10
+    early-clobber %r31r30 = LDDWRdPtrQ undef %r29r28, 10
 ...
diff --git a/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir b/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
index 472f498b912c..831c75b38b17 100644
--- a/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
+++ b/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0  %s -o - 2>&1 -march=avr | FileCheck %s
+# RUN: llc -O0  %s -o - -march=avr | FileCheck %s
 
 # This test checks the expansion of the 16-bit 'LDDWRdYQ instruction
 
@@ -12,6 +12,7 @@
 
 ---
 name:            test_lddwrdyq
+tracksRegLiveness: true
 body: |
   bb.0.entry:
 
@@ -20,5 +21,5 @@ body: |
     ; CHECK:      ldd     r30, Y+1
     ; CHECK-NEXT: ldd     r31, Y+2
 
-    early-clobber %r31r30 = LDDWRdYQ %r29r28, 1
+    early-clobber %r31r30 = LDDWRdYQ undef %r29r28, 1
 ...
diff --git a/test/CodeGen/AVR/pseudo/LDIWRdK.mir b/test/CodeGen/AVR/pseudo/LDIWRdK.mir
index 23d16d9c5692..f4788adf20b4 100644
--- a/test/CodeGen/AVR/pseudo/LDIWRdK.mir
+++ b/test/CodeGen/AVR/pseudo/LDIWRdK.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDIWRdK pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/LDSWRdK.mir b/test/CodeGen/AVR/pseudo/LDSWRdK.mir
index aa4883634d74..b813923abcb2 100644
--- a/test/CodeGen/AVR/pseudo/LDSWRdK.mir
+++ b/test/CodeGen/AVR/pseudo/LDSWRdK.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDSWRdK pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/LDWRdPtr.mir b/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
index aaf9f182f2be..6db615878b95 100644
--- a/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
+++ b/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDWRdPtr pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir b/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
index f304cc220cbc..eb65c6538d11 100644
--- a/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
+++ b/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDWRdPtrPd pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir b/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
index 9153be0bf1c9..50bad2a4c765 100644
--- a/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
+++ b/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit LDWRdPtrPi pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/LSLWRd.mir b/test/CodeGen/AVR/pseudo/LSLWRd.mir
index 441939856aef..537944866e53 100644
--- a/test/CodeGen/AVR/pseudo/LSLWRd.mir
+++ b/test/CodeGen/AVR/pseudo/LSLWRd.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/LSRWRd.mir b/test/CodeGen/AVR/pseudo/LSRWRd.mir
index f5ffb93f4035..a1a513f4e364 100644
--- a/test/CodeGen/AVR/pseudo/LSRWRd.mir
+++ b/test/CodeGen/AVR/pseudo/LSRWRd.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/ORIWRdK.mir b/test/CodeGen/AVR/pseudo/ORIWRdK.mir
index 92bc36769eb8..d77a6ba88488 100644
--- a/test/CodeGen/AVR/pseudo/ORIWRdK.mir
+++ b/test/CodeGen/AVR/pseudo/ORIWRdK.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit OR pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/ORWRdRr.mir b/test/CodeGen/AVR/pseudo/ORWRdRr.mir
index f7a377ec860b..834c21cba8f9 100644
--- a/test/CodeGen/AVR/pseudo/ORWRdRr.mir
+++ b/test/CodeGen/AVR/pseudo/ORWRdRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit OR pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/OUTWARr.mir b/test/CodeGen/AVR/pseudo/OUTWARr.mir
index 85e9f5259a87..99abad1c31b8 100644
--- a/test/CodeGen/AVR/pseudo/OUTWARr.mir
+++ b/test/CodeGen/AVR/pseudo/OUTWARr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/POPWRd.mir b/test/CodeGen/AVR/pseudo/POPWRd.mir
index 6794742bf54a..8bd7fe68727c 100644
--- a/test/CodeGen/AVR/pseudo/POPWRd.mir
+++ b/test/CodeGen/AVR/pseudo/POPWRd.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/PUSHWRr.mir b/test/CodeGen/AVR/pseudo/PUSHWRr.mir
index 93920867030f..ec94ecbf5bb6 100644
--- a/test/CodeGen/AVR/pseudo/PUSHWRr.mir
+++ b/test/CodeGen/AVR/pseudo/PUSHWRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/SBCIWRdK.mir b/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
index 9152c6d91266..644e6106ee79 100644
--- a/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
+++ b/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction with carry pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/SBCWRdRr.mir b/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
index 9159906b76a0..5cf5d33252c7 100644
--- a/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
+++ b/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction with carry pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/SEXT.mir b/test/CodeGen/AVR/pseudo/SEXT.mir
index 069eb883dcc1..0d10358c10e1 100644
--- a/test/CodeGen/AVR/pseudo/SEXT.mir
+++ b/test/CodeGen/AVR/pseudo/SEXT.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir b/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
index ff2fdb9155e1..9252997d489e 100644
--- a/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
+++ b/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo  %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo  %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/STSWKRr.mir b/test/CodeGen/AVR/pseudo/STSWKRr.mir
index ccf852271ae9..18f101808094 100644
--- a/test/CodeGen/AVR/pseudo/STSWKRr.mir
+++ b/test/CodeGen/AVR/pseudo/STSWKRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir b/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
index 0d0d9e909e4a..d884d2121c2c 100644
--- a/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
+++ b/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir b/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
index a436d9b109bb..962776aa6330 100644
--- a/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
+++ b/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/STWPtrRr.mir b/test/CodeGen/AVR/pseudo/STWPtrRr.mir
index f85f4f8a0452..efed707bfe8a 100644
--- a/test/CodeGen/AVR/pseudo/STWPtrRr.mir
+++ b/test/CodeGen/AVR/pseudo/STWPtrRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit STSWRdK pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/SUBIWRdK.mir b/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
index 95c68c0a122a..c7d88d7ab3f6 100644
--- a/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
+++ b/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/SUBWRdRr.mir b/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
index 9892cf5b7f33..b12b0e5349e2 100644
--- a/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
+++ b/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 # This test checks the expansion of the 16-bit subtraction pseudo instruction.
 
diff --git a/test/CodeGen/AVR/pseudo/ZEXT.mir b/test/CodeGen/AVR/pseudo/ZEXT.mir
index 069eb883dcc1..0d10358c10e1 100644
--- a/test/CodeGen/AVR/pseudo/ZEXT.mir
+++ b/test/CodeGen/AVR/pseudo/ZEXT.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"
diff --git a/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir b/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir
index 5ed95ad76a7f..8427a2bfb4ed 100644
--- a/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir
+++ b/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 %s -o - 2>&1 -march=avr | FileCheck %s
+# RUN: llc -O0 %s -o - -march=avr | FileCheck %s
 
 # This test ensures that the pseudo expander can correctly handle the case
 # where we are expanding a 16-bit LDD instruction where the source and
@@ -18,6 +18,7 @@
 ...
 ---
 name:            test_lddw
+tracksRegLiveness: true
 stack:
   - { id: 0, type: spill-slot, offset: -4, size: 1, alignment: 1, callee-saved-register: '%r28' }
 body:             |
diff --git a/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir b/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
index b43c77508328..7421bd4c4e81 100644
--- a/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
+++ b/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - 2>&1 | FileCheck %s
+# RUN: llc -O0 -run-pass=avr-relax-mem %s -o - | FileCheck %s
 
 --- |
   target triple = "avr--"