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authorDimitry Andric <dim@FreeBSD.org>2011-05-02 19:34:44 +0000
committerDimitry Andric <dim@FreeBSD.org>2011-05-02 19:34:44 +0000
commit6b943ff3a3f8617113ecbf611cf0f8957e4e19d2 (patch)
treefc5f365fb9035b2d0c622bbf06c9bbe8627d7279 /test/CodeGen/CellSPU/loads.ll
parentd0e4e96dc17a6c1c6de3340842c80f0e187ba349 (diff)
Notes
Diffstat (limited to 'test/CodeGen/CellSPU/loads.ll')
-rw-r--r--test/CodeGen/CellSPU/loads.ll7
1 files changed, 7 insertions, 0 deletions
diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll
index 03d7ad1153a1..4771752f5f4c 100644
--- a/test/CodeGen/CellSPU/loads.ll
+++ b/test/CodeGen/CellSPU/loads.ll
@@ -50,3 +50,10 @@ define i32 @load_misaligned( i32* %ptr ){
%rv = load i32* %ptr, align 2
ret i32 %rv
}
+
+define <4 x i32> @load_null_vec( ) {
+;CHECK: lqa
+;CHECK: bi $lr
+ %rv = load <4 x i32>* null
+ ret <4 x i32> %rv
+}