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| author | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
| commit | 71d5a2540a98c81f5bcaeb48805e0e2881f530ef (patch) | |
| tree | 5343938942df402b49ec7300a1c25a2d4ccd5821 /test/CodeGen/Hexagon/bit-validate-reg.ll | |
| parent | 31bbf64f3a4974a2d6c8b3b27ad2f519caf74057 (diff) | |
Diffstat (limited to 'test/CodeGen/Hexagon/bit-validate-reg.ll')
| -rw-r--r-- | test/CodeGen/Hexagon/bit-validate-reg.ll | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/test/CodeGen/Hexagon/bit-validate-reg.ll b/test/CodeGen/Hexagon/bit-validate-reg.ll index 16d4a5e4484d..42eed97786cd 100644 --- a/test/CodeGen/Hexagon/bit-validate-reg.ll +++ b/test/CodeGen/Hexagon/bit-validate-reg.ll @@ -1,10 +1,13 @@ -; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -march=hexagon -hexbit-extract=0 < %s | FileCheck %s ; Make sure we don't generate zxtb to transfer a predicate register into ; a general purpose register. ; CHECK: r0 = p0 ; CHECK-NOT: zxtb(p +; CHECK-NOT: and(p +; CHECK-NOT: extract(p +; CHECK-NOT: extractu(p target triple = "hexagon" |