diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
| commit | 71d5a2540a98c81f5bcaeb48805e0e2881f530ef (patch) | |
| tree | 5343938942df402b49ec7300a1c25a2d4ccd5821 /test/CodeGen/Hexagon/clr_set_toggle.ll | |
| parent | 31bbf64f3a4974a2d6c8b3b27ad2f519caf74057 (diff) | |
Diffstat (limited to 'test/CodeGen/Hexagon/clr_set_toggle.ll')
| -rw-r--r-- | test/CodeGen/Hexagon/clr_set_toggle.ll | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/test/CodeGen/Hexagon/clr_set_toggle.ll b/test/CodeGen/Hexagon/clr_set_toggle.ll index 19e3ed0cf897..4e9838316522 100644 --- a/test/CodeGen/Hexagon/clr_set_toggle.ll +++ b/test/CodeGen/Hexagon/clr_set_toggle.ll @@ -4,7 +4,7 @@ define i32 @my_clrbit(i32 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4 @@ -15,7 +15,7 @@ entry: define i64 @my_clrbit2(i64 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit2 -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -26,7 +26,7 @@ entry: define i64 @my_clrbit3(i64 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit3 -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#31) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -37,7 +37,7 @@ entry: define i32 @my_clrbit4(i32 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit4 -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#13) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4 @@ -48,7 +48,7 @@ entry: define i64 @my_clrbit5(i64 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit5 -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#13) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -59,7 +59,7 @@ entry: define i64 @my_clrbit6(i64 %x) nounwind { entry: ; CHECK-LABEL: my_clrbit6 -; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #27) +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}},#27) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -70,7 +70,7 @@ entry: define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind { entry: ; CHECK-LABEL: my_setbit -; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}){{ *}}={{ *}}setbit(#15) +; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}) = setbit(#15) %crc.addr = alloca i16, align 2 store i16 %crc, i16* %crc.addr, align 2 %0 = load i16, i16* %crc.addr, align 2 @@ -85,7 +85,7 @@ entry: define i32 @my_setbit2(i32 %x) nounwind { entry: ; CHECK-LABEL: my_setbit2 -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15) +; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4 @@ -96,7 +96,7 @@ entry: define i64 @my_setbit3(i64 %x) nounwind { entry: ; CHECK-LABEL: my_setbit3 -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15) +; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -107,7 +107,7 @@ entry: define i32 @my_setbit4(i32 %x) nounwind { entry: ; CHECK-LABEL: my_setbit4 -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #31) +; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#31) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4 @@ -118,7 +118,7 @@ entry: define i64 @my_setbit5(i64 %x) nounwind { entry: ; CHECK-LABEL: my_setbit5 -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #13) +; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#13) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -129,7 +129,7 @@ entry: define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind { entry: ; CHECK-LABEL: my_togglebit -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15) %crc.addr = alloca i16, align 2 store i16 %crc, i16* %crc.addr, align 2 %0 = load i16, i16* %crc.addr, align 2 @@ -144,7 +144,7 @@ entry: define i32 @my_togglebit2(i32 %x) nounwind { entry: ; CHECK-LABEL: my_togglebit2 -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4 @@ -155,7 +155,7 @@ entry: define i64 @my_togglebit3(i64 %x) nounwind { entry: ; CHECK-LABEL: my_togglebit3 -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#15) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 @@ -166,7 +166,7 @@ entry: define i64 @my_togglebit4(i64 %x) nounwind { entry: ; CHECK-LABEL: my_togglebit4 -; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #20) +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}},#20) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 %0 = load i64, i64* %x.addr, align 8 |