diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
| commit | 71d5a2540a98c81f5bcaeb48805e0e2881f530ef (patch) | |
| tree | 5343938942df402b49ec7300a1c25a2d4ccd5821 /test/CodeGen/Hexagon/extload-combine.ll | |
| parent | 31bbf64f3a4974a2d6c8b3b27ad2f519caf74057 (diff) | |
Diffstat (limited to 'test/CodeGen/Hexagon/extload-combine.ll')
| -rw-r--r-- | test/CodeGen/Hexagon/extload-combine.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/test/CodeGen/Hexagon/extload-combine.ll b/test/CodeGen/Hexagon/extload-combine.ll index c492343d7915..c7a386a664ba 100644 --- a/test/CodeGen/Hexagon/extload-combine.ll +++ b/test/CodeGen/Hexagon/extload-combine.ll @@ -15,8 +15,8 @@ ; Function Attrs: nounwind define i64 @short_test1() #0 { -; CHECK: [[VAR:r[0-9]+]]{{ *}}={{ *}}memuh(## -; CHECK: combine(#0, [[VAR]]) +; CHECK: [[VAR:r[0-9]+]] = memuh(## +; CHECK: combine(#0,[[VAR]]) entry: store i16 0, i16* @a, align 2 %0 = load i16, i16* @b, align 2 @@ -26,7 +26,7 @@ entry: ; Function Attrs: nounwind define i64 @short_test2() #0 { -; CHECK: [[VAR1:r[0-9]+]]{{ *}}={{ *}}memh(## +; CHECK: [[VAR1:r[0-9]+]] = memh(## ; CHECK: sxtw([[VAR1]]) entry: store i16 0, i16* @a, align 2 @@ -37,8 +37,8 @@ entry: ; Function Attrs: nounwind define i64 @char_test1() #0 { -; CHECK: [[VAR2:r[0-9]+]]{{ *}}={{ *}}memub(## -; CHECK: combine(#0, [[VAR2]]) +; CHECK: [[VAR2:r[0-9]+]] = memub(## +; CHECK: combine(#0,[[VAR2]]) entry: store i8 0, i8* @char_a, align 1 %0 = load i8, i8* @char_b, align 1 @@ -48,7 +48,7 @@ entry: ; Function Attrs: nounwind define i64 @char_test2() #0 { -; CHECK: [[VAR3:r[0-9]+]]{{ *}}={{ *}}memb(## +; CHECK: [[VAR3:r[0-9]+]] = memb(## ; CHECK: sxtw([[VAR3]]) entry: store i8 0, i8* @char_a, align 1 @@ -59,8 +59,8 @@ entry: ; Function Attrs: nounwind define i64 @int_test1() #0 { -; CHECK: [[VAR4:r[0-9]+]]{{ *}}={{ *}}memw(## -; CHECK: combine(#0, [[VAR4]]) +; CHECK: [[VAR4:r[0-9]+]] = memw(## +; CHECK: combine(#0,[[VAR4]]) entry: store i32 0, i32* @int_a, align 4 %0 = load i32, i32* @int_b, align 4 @@ -70,7 +70,7 @@ entry: ; Function Attrs: nounwind define i64 @int_test2() #0 { -; CHECK: [[VAR5:r[0-9]+]]{{ *}}={{ *}}memw(## +; CHECK: [[VAR5:r[0-9]+]] = memw(## ; CHECK: sxtw([[VAR5]]) entry: store i32 0, i32* @int_a, align 4 |