diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
| commit | 01095a5d43bbfde13731688ddcf6048ebb8b7721 (patch) | |
| tree | 4def12e759965de927d963ac65840d663ef9d1ea /test/CodeGen/Mips | |
| parent | f0f4822ed4b66e3579e92a89f368f8fb860e218e (diff) | |
Notes
Diffstat (limited to 'test/CodeGen/Mips')
187 files changed, 6011 insertions, 2133 deletions
diff --git a/test/CodeGen/Mips/2010-07-20-Switch.ll b/test/CodeGen/Mips/2010-07-20-Switch.ll index fd0254e9f5ec..7d66d1a1a204 100644 --- a/test/CodeGen/Mips/2010-07-20-Switch.ll +++ b/test/CodeGen/Mips/2010-07-20-Switch.ll @@ -55,19 +55,19 @@ bb5: ; preds = %entry ret i32 1 } -; STATIC-O32: .align 2 +; STATIC-O32: .p2align 2 ; STATIC-O32: $JTI0_0: ; STATIC-O32: .4byte ; STATIC-O32: .4byte ; STATIC-O32: .4byte ; STATIC-O32: .4byte -; PIC-O32: .align 2 +; PIC-O32: .p2align 2 ; PIC-O32: $JTI0_0: ; PIC-O32: .gpword ; PIC-O32: .gpword ; PIC-O32: .gpword ; PIC-O32: .gpword -; N64: .align 3 +; N64: .p2align 3 ; N64: $JTI0_0: ; N64: .gpdword ; N64: .gpdword diff --git a/test/CodeGen/Mips/Fast-ISel/callabi.ll b/test/CodeGen/Mips/Fast-ISel/callabi.ll index 34616a50b1a0..9988622db54f 100644 --- a/test/CodeGen/Mips/Fast-ISel/callabi.ll +++ b/test/CodeGen/Mips/Fast-ISel/callabi.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -O0 \ -; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 -; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \ -; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 +; RUN: llc -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ +; RUN: -fast-isel-abort=1 -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1 +; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ +; RUN: -fast-isel-abort=1 -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R2 declare void @xb(i8) diff --git a/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll b/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll index 203e5a7e1595..290e4ecb7405 100644 --- a/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll +++ b/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll @@ -1,20 +1,22 @@ ; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s diff --git a/test/CodeGen/Mips/Fast-ISel/div1.ll b/test/CodeGen/Mips/Fast-ISel/div1.ll index 89055aa12805..b0865e649d96 100644 --- a/test/CodeGen/Mips/Fast-ISel/div1.ll +++ b/test/CodeGen/Mips/Fast-ISel/div1.ll @@ -22,7 +22,7 @@ define void @divs() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: div $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mflo $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @sj, align 4 @@ -44,7 +44,7 @@ define void @divu() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: divu $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mflo $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @uj, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/fastalloca.ll b/test/CodeGen/Mips/Fast-ISel/fastalloca.ll index 00bc7f485e08..9c91567eabf0 100644 --- a/test/CodeGen/Mips/Fast-ISel/fastalloca.ll +++ b/test/CodeGen/Mips/Fast-ISel/fastalloca.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s +; RUN: < %s -verify-machineinstrs | FileCheck %s %struct.x = type { i32 } diff --git a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll index e346acfeff13..d661a281ea1d 100644 --- a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll +++ b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s +; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s +; RUN: -verify-machineinstrs < %s | FileCheck %s @f1 = common global float 0.000000e+00, align 4 @f2 = common global float 0.000000e+00, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/memtest1.ll b/test/CodeGen/Mips/Fast-ISel/memtest1.ll index b98200d7456d..7deb5c08ec69 100644 --- a/test/CodeGen/Mips/Fast-ISel/memtest1.ll +++ b/test/CodeGen/Mips/Fast-ISel/memtest1.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R1 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R2 @str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1 diff --git a/test/CodeGen/Mips/Fast-ISel/rem1.ll b/test/CodeGen/Mips/Fast-ISel/rem1.ll index cf709e7e4954..a5cc24361e6a 100644 --- a/test/CodeGen/Mips/Fast-ISel/rem1.ll +++ b/test/CodeGen/Mips/Fast-ISel/rem1.ll @@ -22,7 +22,7 @@ define void @rems() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: div $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mfhi $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @sj, align 4 @@ -45,7 +45,7 @@ define void @remu() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: divu $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mfhi $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @uj, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/shift.ll b/test/CodeGen/Mips/Fast-ISel/shift.ll index 9fe694bb5827..651fb6ad1f5a 100644 --- a/test/CodeGen/Mips/Fast-ISel/shift.ll +++ b/test/CodeGen/Mips/Fast-ISel/shift.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -fast-isel=true -filetype=obj %s -o - \ -; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s +; RUN: | llvm-objdump -d - | FileCheck %s ; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used. diff --git a/test/CodeGen/Mips/abicalls.ll b/test/CodeGen/Mips/abicalls.ll index 7edc3e25c352..26bbab40b3b3 100644 --- a/test/CodeGen/Mips/abicalls.ll +++ b/test/CodeGen/Mips/abicalls.ll @@ -1,7 +1,7 @@ -; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | FileCheck -check-prefix=ABICALLS -check-prefix=STATIC %s -; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | FileCheck -check-prefix=ABICALLS -check-prefix=PIC %s -; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips4 -relocation-model=static %s -o - | FileCheck -check-prefix=ABICALLS -check-prefix=PIC %s -; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | FileCheck -check-prefix=ABICALLS -check-prefix=PIC %s +; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | FileCheck -check-prefixes=ABICALLS,STATIC %s +; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=pic %s -o - | FileCheck -check-prefixes=ABICALLS,PIC %s +; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips4 -relocation-model=static %s -o - | FileCheck -check-prefixes=ABICALLS,PIC %s +; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | FileCheck -check-prefixes=ABICALLS,PIC %s ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr noabicalls -relocation-model=static %s -o - | FileCheck -implicit-check-not='.abicalls' -implicit-check-not='pic0' %s diff --git a/test/CodeGen/Mips/adjust-callstack-sp.ll b/test/CodeGen/Mips/adjust-callstack-sp.ll index e4afcd835005..32d77ac19ae6 100644 --- a/test/CodeGen/Mips/adjust-callstack-sp.ll +++ b/test/CodeGen/Mips/adjust-callstack-sp.ll @@ -2,18 +2,18 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips3 | FileCheck %s -check-prefix=GP64 -; RUN: llc < %s -march=mips -mcpu=mips64 | FileCheck %s -check-prefix=GP64 -; RUN: llc < %s -march=mips -mcpu=mips64r6 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips3 -target-abi n64 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 | FileCheck %s -check-prefix=GP64 declare void @bar(i32*) define void @foo(i32 %sz) { ; ALL-LABEL: foo: - ; M16-NOT: addiu $sp, 0 # 16 bit inst - ; GP32-NOT: addiu $sp, $sp, 0 - ; GP64-NOT: daddiu $sp, $sp, 0 + ; M16-NOT: addiu $sp, 0 # 16 bit inst + ; GP32-NOT: addiu $sp, $sp, 0 + ; GP64-NOT: daddiu $sp, $sp, 0 %a = alloca i32, i32 %sz call void @bar(i32* %a) ret void diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll index 747a1362161d..b708ddb134ce 100644 --- a/test/CodeGen/Mips/alloca.ll +++ b/test/CodeGen/Mips/alloca.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s define i32 @twoalloca(i32 %size) nounwind { entry: diff --git a/test/CodeGen/Mips/analyzebranch.ll b/test/CodeGen/Mips/analyzebranch.ll index d5ecaaeddc33..377fe9327e0e 100644 --- a/test/CodeGen/Mips/analyzebranch.ll +++ b/test/CodeGen/Mips/analyzebranch.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR -; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC -; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC -; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC -; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR +; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,FCC +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,FCC +; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,32-GPR +; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,FCC +; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,FCC +; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,FCC +; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,64-GPR define double @foo(double %a, double %b) nounwind readnone { entry: @@ -19,7 +19,7 @@ entry: ; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], $BB +; GPR: bnezc $[[GPRCC]], $BB %cmp = fcmp ogt double %a, 0.000000e+00 br i1 %cmp, label %if.end6, label %if.else @@ -50,7 +50,8 @@ entry: ; GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $[[Z]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: beqz $[[GPRCC]], $BB +; 64-GPR beqzc $[[GPRCC]], $BB +; 32-GPR beqz $[[GPRCC]], $BB %cmp = fcmp une float %f, 0.000000e+00 br i1 %cmp, label %if.then, label %if.end diff --git a/test/CodeGen/Mips/assertzext-trunc.ll b/test/CodeGen/Mips/assertzext-trunc.ll new file mode 100644 index 000000000000..2295727834eb --- /dev/null +++ b/test/CodeGen/Mips/assertzext-trunc.ll @@ -0,0 +1,62 @@ +; RUN: llc < %s -march=mips64 -mcpu=mips3 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \ +; RUN: FileCheck %s -check-prefixes=ALL,R6 + +; Check that we don't emit redundant SLLs for sequences of +; (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8) +define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) { +entry: +; ALL-LABEL: udiv_i8: + + ; PRE-R6-NOT: sll {{.*}} + ; PRE-R6: divu $zero, $4, $5 + ; PRE-R6: teq $5, $zero, 7 + ; PRE-R6: mflo $2 + + ; R6-NOT: sll {{.*}} + ; R6: divu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = udiv i8 %a, %b + ret i8 %r +} + +; Check that we do sign-extend when we have a (trunc:i32 (AssertZext:i64 X, i32)) +define i64 @foo1(i64 zeroext %var) { +entry: +; ALL-LABEL: foo1: + + %shr = lshr i64 %var, 32 + %cmp = icmp eq i64 %shr, 0 + br i1 %cmp, label %if.end6, label %if.then + + ; ALL: dsrl $[[T0:[0-9]+]], $4, 32 + ; ALL: sll $[[T1:[0-9]+]], $[[T0]], 0 + if.then: ; preds = %entry + %conv = trunc i64 %shr to i32 + %cmp2 = icmp slt i32 %conv, 0 + br i1 %cmp2, label %if.then4, label %if.else + + if.then4: ; preds = %if.then + %add = add i64 %var, 16 + br label %if.end6 + + if.else: ; preds = %if.then + %add5 = add i64 %var, 32 + br label %if.end6 + + if.end6: ; preds = %entry, %if.then4, %if.else + %var.addr.0 = phi i64 [ %add, %if.then4 ], [ %add5, %if.else ], [ %var, %entry ] + ret i64 %var.addr.0 +} diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll index 031cce0b6074..8f4ccb19958a 100644 --- a/test/CodeGen/Mips/atomic.ll +++ b/test/CodeGen/Mips/atomic.ll @@ -1,15 +1,26 @@ -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS32-ANY,NO-SEB-SEH,CHECK-EL,NOT-MICROMIPS +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS32-ANY,HAS-SEB-SEH,CHECK-EL,NOT-MICROMIPS +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS32-ANY,HAS-SEB-SEH,CHECK-EL,MIPSR6 +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS64-ANY,NO-SEB-SEH,CHECK-EL,NOT-MICROMIPS +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS64-ANY,NO-SEB-SEH,CHECK-EL,NOT-MICROMIPS +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS64-ANY,HAS-SEB-SEH,CHECK-EL,NOT-MICROMIPS +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS64-ANY,HAS-SEB-SEH,CHECK-EL,MIPSR6 +; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL-LABEL,MIPS64-ANY,O0 +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS32-ANY,HAS-SEB-SEH,CHECK-EL,MICROMIPS ; Keep one big-endian check so that we don't reduce testing, but don't add more ; since endianness doesn't affect the body of the atomic operations. -; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB -check-prefix=NOT-MICROMIPS +; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS32-ANY,NO-SEB-SEH,CHECK-EB,NOT-MICROMIPS @x = common global i32 0, align 4 @@ -23,12 +34,17 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( +; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: ld $[[R1:[0-9]+]] +; O0-NEXT: ll $[[R2:[0-9]+]], 0($[[R1]]) + ; ALL: $[[BB0:[A-Z_0-9]+]]: -; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) -; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4 -; ALL: sc $[[R2]], 0($[[R0]]) -; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] -; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; ALL: ll $[[R3:[0-9]+]], 0($[[R0]]) +; ALL: addu $[[R4:[0-9]+]], $[[R3]], $4 +; ALL: sc $[[R4]], 0($[[R0]]) +; NOT-MICROMIPS: beqz $[[R4]], $[[BB0]] +; MICROMIPS: beqzc $[[R4]], $[[BB0]] +; MIPSR6: beqzc $[[R4]], $[[BB0]] } define i32 @AtomicLoadNand32(i32 signext %incr) nounwind { @@ -41,6 +57,8 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( + + ; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) ; ALL: and $[[R3:[0-9]+]], $[[R1]], $4 @@ -48,6 +66,7 @@ entry: ; ALL: sc $[[R2]], 0($[[R0]]) ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; MIPSR6: beqzc $[[R2]], $[[BB0]] } define i32 @AtomicSwap32(i32 signext %newval) nounwind { @@ -68,6 +87,7 @@ entry: ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; MIPSR6: beqzc $[[R2]], $[[BB0]] } define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind { @@ -86,10 +106,13 @@ entry: ; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $2, 0($[[R0]]) -; ALL: bne $2, $4, $[[BB1:[A-Z_0-9]+]] +; NOT-MICROMIPS: bne $2, $4, $[[BB1:[A-Z_0-9]+]] +; MICROMIPS: bne $2, $4, $[[BB1:[A-Z_0-9]+]] +; MIPSR6: bnec $2, $4, $[[BB1:[A-Z_0-9]+]] ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; MIPSR6: beqzc $[[R2]], $[[BB0]] ; ALL: $[[BB1]]: } @@ -118,23 +141,28 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] +; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: ld $[[R10:[0-9]+]] +; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) + ; ALL: $[[BB0:[A-Z_0-9]+]]: -; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) -; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] -; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] -; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] -; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] -; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] -; MICROMIPS: beqzc $[[R14]], $[[BB0]] +; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) +; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]] +; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] +; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] +; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] +; ALL: sc $[[R16]], 0($[[R2]]) +; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] +; MICROMIPS: beqzc $[[R16]], $[[BB0]] +; MIPSR6: beqzc $[[R16]], $[[BB0]] -; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] -; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] +; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] +; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] -; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 -; NO-SEB-SEH: sra $2, $[[R17]], 24 +; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24 +; NO-SEB-SEH: sra $2, $[[R19]], 24 -; HAS-SEB-SEH: seb $2, $[[R16]] +; HAS-SEB-SEH: seb $2, $[[R18]] } define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { @@ -158,23 +186,28 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] +; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: ld $[[R10:[0-9]+]] +; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) + ; ALL: $[[BB0:[A-Z_0-9]+]]: -; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) -; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]] -; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] -; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] -; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] -; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] -; MICROMIPS: beqzc $[[R14]], $[[BB0]] +; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) +; ALL: subu $[[R13:[0-9]+]], $[[R12]], $[[R9]] +; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] +; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] +; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] +; ALL: sc $[[R16]], 0($[[R2]]) +; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] +; MICROMIPS: beqzc $[[R16]], $[[BB0]] +; MIPSR6: beqzc $[[R16]], $[[BB0]] -; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] -; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] +; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] +; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] -; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 -; NO-SEB-SEH: sra $2, $[[R17]], 24 +; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24 +; NO-SEB-SEH: sra $2, $[[R19]], 24 -; HAS-SEB-SEH:seb $2, $[[R16]] +; HAS-SEB-SEH:seb $2, $[[R18]] } define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { @@ -198,24 +231,29 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] +; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: ld $[[R10:[0-9]+]] +; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) + ; ALL: $[[BB0:[A-Z_0-9]+]]: -; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) -; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]] -; ALL: nor $[[R11:[0-9]+]], $zero, $[[R18]] -; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] -; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] -; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] -; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] -; MICROMIPS: beqzc $[[R14]], $[[BB0]] +; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) +; ALL: and $[[R13:[0-9]+]], $[[R12]], $[[R9]] +; ALL: nor $[[R14:[0-9]+]], $zero, $[[R13]] +; ALL: and $[[R15:[0-9]+]], $[[R14]], $[[R7]] +; ALL: and $[[R16:[0-9]+]], $[[R12]], $[[R8]] +; ALL: or $[[R17:[0-9]+]], $[[R16]], $[[R15]] +; ALL: sc $[[R17]], 0($[[R2]]) +; NOT-MICROMIPS: beqz $[[R17]], $[[BB0]] +; MICROMIPS: beqzc $[[R17]], $[[BB0]] +; MIPSR6: beqzc $[[R17]], $[[BB0]] -; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] -; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] +; ALL: and $[[R18:[0-9]+]], $[[R12]], $[[R7]] +; ALL: srlv $[[R19:[0-9]+]], $[[R18]], $[[R5]] -; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 -; NO-SEB-SEH: sra $2, $[[R17]], 24 +; NO-SEB-SEH: sll $[[R20:[0-9]+]], $[[R19]], 24 +; NO-SEB-SEH: sra $2, $[[R20]], 24 -; HAS-SEB-SEH: seb $2, $[[R16]] +; HAS-SEB-SEH: seb $2, $[[R19]] } define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { @@ -247,6 +285,7 @@ entry: ; ALL: sc $[[R14]], 0($[[R2]]) ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] ; MICROMIPS: beqzc $[[R14]], $[[BB0]] +; MIPSR6: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -286,13 +325,16 @@ entry: ; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] -; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; NOT-MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; MIPSR6: bnec $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: sc $[[R16]], 0($[[R2]]) ; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] ; MICROMIPS: beqzc $[[R16]], $[[BB0]] +; MIPSR6: beqzc $[[R16]], $[[BB0]] ; ALL: $[[BB1]]: ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] @@ -327,13 +369,16 @@ entry: ; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] -; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; NOT-MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; MIPSR6: bnec $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: sc $[[R16]], 0($[[R2]]) ; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] ; MICROMIPS: beqzc $[[R16]], $[[BB0]] +; MIPSR6: beqzc $[[R16]], $[[BB0]] ; ALL: $[[BB1]]: ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] @@ -341,10 +386,17 @@ entry: ; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24 ; NO-SEB-SEH: sra $[[R19:[0-9]+]], $[[R18]], 24 +; FIXME: -march=mips produces a redundant sign extension here... +; NO-SEB-SEH: sll $[[R20:[0-9]+]], $5, 24 +; NO-SEB-SEH: sra $[[R20]], $[[R20]], 24 + ; HAS-SEB-SEH: seb $[[R19:[0-9]+]], $[[R17]] -; ALL: xor $[[R20:[0-9]+]], $[[R19]], $5 -; ALL: sltiu $2, $[[R20]], 1 +; FIXME: ...Leading to this split check. +; NO-SEB-SEH: xor $[[R21:[0-9]+]], $[[R19]], $[[R20]] +; HAS-SEB-SEH: xor $[[R21:[0-9]+]], $[[R19]], $5 + +; ALL: sltiu $2, $[[R21]], 1 } ; Check one i16 so that we cover the seh sign extend @@ -371,25 +423,73 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] +; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: ld $[[R10:[0-9]+]] +; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) + ; ALL: $[[BB0:[A-Z_0-9]+]]: -; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) -; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] -; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] -; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] -; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] -; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] -; MICROMIPS: beqzc $[[R14]], $[[BB0]] +; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) +; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]] +; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] +; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] +; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] +; ALL: sc $[[R16]], 0($[[R2]]) +; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] +; MICROMIPS: beqzc $[[R16]], $[[BB0]] +; MIPSR6: beqzc $[[R16]], $[[BB0]] -; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] -; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] +; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] +; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] -; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 16 -; NO-SEB-SEH: sra $2, $[[R17]], 16 +; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 16 +; NO-SEB-SEH: sra $2, $[[R19]], 16 -; MIPS32R2: seh $2, $[[R16]] +; MIPS32R2: seh $2, $[[R18]] } +; Test that the i16 return value from cmpxchg is recognised as signed, +; so that setCC doesn't end up comparing an unsigned value to a signed +; value. +; The rest of the functions here are testing the atomic expansion, so +; we just match the end of the function. +define {i16, i1} @foo(i16* %addr, i16 %l, i16 %r, i16 %new) { + %desired = add i16 %l, %r + %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst seq_cst + ret {i16, i1} %res + +; ALL-LABEL: foo +; MIPSR6: addu $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]] +; NOT-MICROMIPS: addu $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]] +; MICROMIPS: addu16 $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]] + +; ALL: sync + +; ALL: andi $[[R3:[0-9]+]], $[[R2]], 65535 +; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: ll $[[R4:[0-9]+]], 0($[[R5:[0-9]+]]) +; ALL: and $[[R6:[0-9]+]], $[[R4]], $ +; ALL: and $[[R7:[0-9]+]], $[[R4]], $ +; ALL: or $[[R8:[0-9]+]], $[[R7]], $ +; ALL: sc $[[R8]], 0($[[R5]]) +; NOT-MICROMIPS: beqz $[[R8]], $[[BB0]] +; MICROMIPS: beqzc $[[R8]], $[[BB0]] +; MIPSR6: beqzc $[[R8]], $[[BB0]] + +; ALL: srlv $[[R9:[0-9]+]], $[[R6]], $ + +; NO-SEB-SEH: sll $[[R10:[0-9]+]], $[[R9]], 16 +; NO-SEB-SEH: sra $[[R11:[0-9]+]], $[[R10]], 16 + +; NO-SEB-SEH: sll $[[R12:[0-9]+]], $[[R2]], 16 +; NO-SEB-SEH: sra $[[R13:[0-9]+]], $[[R12]], 16 + +; HAS-SEB-SEH: seh $[[R11:[0-9]+]], $[[R9]] +; HAS-SEB-SEH: seh $[[R13:[0-9]+]], $[[R2]] + +; ALL: xor $[[R12:[0-9]+]], $[[R11]], $[[R13]] +; ALL: sltiu $3, $[[R12]], 1 +; ALL: sync +} @countsint = common global i32 0, align 4 @@ -444,4 +544,5 @@ entry: ; ALL: sc $[[R2]], 0($[[PTR]]) ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; MIPSR6: beqzc $[[R2]], $[[BB0]] } diff --git a/test/CodeGen/Mips/atomicCmpSwapPW.ll b/test/CodeGen/Mips/atomicCmpSwapPW.ll new file mode 100644 index 000000000000..981f0983fa4c --- /dev/null +++ b/test/CodeGen/Mips/atomicCmpSwapPW.ll @@ -0,0 +1,17 @@ +; RUN: llc -O0 -march=mipsel -mcpu=mips32r2 -target-abi=o32 < %s -filetype=asm -o - \ +; RUN: | FileCheck -check-prefixes=PTR32,ALL %s +; RUN: llc -O0 -march=mips64el -mcpu=mips64r2 -target-abi=n32 < %s -filetype=asm -o - \ +; RUN: | FileCheck -check-prefixes=PTR32,ALL %s +; RUN: llc -O0 -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s -filetype=asm -o - \ +; RUN: | FileCheck -check-prefixes=PTR64,ALL %s + +; PTR32: lw $[[R0:[0-9]+]] +; PTR64: ld $[[R0:[0-9]+]] + +; ALL: ll ${{[0-9]+}}, 0($[[R0]]) + +define {i16, i1} @foo(i16* %addr, i16 signext %r, i16 zeroext %new) { + %res = cmpxchg i16* %addr, i16 %r, i16 %new seq_cst seq_cst + ret {i16, i1} %res +} + diff --git a/test/CodeGen/Mips/biggot.ll b/test/CodeGen/Mips/biggot.ll index b56ce6ba87b1..aafaf55ae184 100644 --- a/test/CodeGen/Mips/biggot.ll +++ b/test/CodeGen/Mips/biggot.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mxgot < %s | FileCheck %s -check-prefix=O32 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+n64 -mxgot < %s | \ +; RUN: llc -march=mipsel -mxgot -relocation-model=pic < %s | FileCheck %s -check-prefix=O32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+n64 -mxgot -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=N64 @v0 = external global i32 diff --git a/test/CodeGen/Mips/brdelayslot.ll b/test/CodeGen/Mips/brdelayslot.ll index 0f46619b8272..3a5d4dcded26 100644 --- a/test/CodeGen/Mips/brdelayslot.ll +++ b/test/CodeGen/Mips/brdelayslot.ll @@ -1,23 +1,24 @@ ; RUN: llc -march=mipsel -O0 < %s | FileCheck %s -check-prefix=None -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=Default +; RUN: llc -march=mipsel -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefix=Default ; RUN: llc -march=mipsel -O1 -relocation-model=static < %s | \ ; RUN: FileCheck %s -check-prefix=STATICO1 ; RUN: llc -march=mipsel -disable-mips-df-forward-search=false \ ; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=FORWARD -; RUN: llc -march=mipsel -disable-mips-df-backward-search \ -; RUN: -disable-mips-df-succbb-search=false < %s | \ +; RUN: llc -march=mipsel -disable-mips-df-backward-search -relocation-model=pic \ +; RUN: -disable-mips-df-succbb-search=false -disable-preheader-prot=true < %s | \ ; RUN: FileCheck %s -check-prefix=SUCCBB define void @foo1() nounwind { entry: -; Default: jalr -; Default-NOT: nop -; Default: jr +; Default: jalr +; Default-NOT: nop +; Default: jr ; Default-NOT: nop ; Default: .end -; None: jalr -; None: nop -; None: jr +; None: jalr +; None: nop +; None: jr ; None: nop ; None: .end diff --git a/test/CodeGen/Mips/brsize3.ll b/test/CodeGen/Mips/brsize3.ll index 1e76879409c6..ce8b8f6e35b1 100644 --- a/test/CodeGen/Mips/brsize3.ll +++ b/test/CodeGen/Mips/brsize3.ll @@ -1,6 +1,12 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-no-short +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: -mattr=+soft-float -mips16-hard-float -relocation-model=pic \ +; RUN: -mips16-constant-islands -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefix=b-no-short -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-long +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: -mattr=+soft-float -mips16-hard-float -relocation-model=pic \ +; RUN: -mips16-constant-islands -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefix=b-long ; ModuleID = 'brsize3.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/test/CodeGen/Mips/buildpairextractelementf64.ll b/test/CodeGen/Mips/buildpairextractelementf64.ll index 7682a98ace99..19ef04f040d8 100644 --- a/test/CodeGen/Mips/buildpairextractelementf64.ll +++ b/test/CodeGen/Mips/buildpairextractelementf64.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL -; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL +; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL +; RUN: llc -march=mips < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL @a = external global i32 diff --git a/test/CodeGen/Mips/call-optimization.ll b/test/CodeGen/Mips/call-optimization.ll index bfa09eaae3cb..762b00effc97 100644 --- a/test/CodeGen/Mips/call-optimization.ll +++ b/test/CodeGen/Mips/call-optimization.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel -disable-mips-delay-filler < %s | \ +; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=O32 ; RUN: llc -march=mipsel -mips-load-target-from-got=false \ -; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=O32-LOADTGT +; RUN: -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck %s -check-prefix=O32-LOADTGT @gd1 = common global double 0.000000e+00, align 8 @gd2 = common global double 0.000000e+00, align 8 diff --git a/test/CodeGen/Mips/cannot-copy-registers.ll b/test/CodeGen/Mips/cannot-copy-registers.ll new file mode 100644 index 000000000000..75cceb2011eb --- /dev/null +++ b/test/CodeGen/Mips/cannot-copy-registers.ll @@ -0,0 +1,24 @@ +; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s + +; Check that message "Cannot copy registers" is not asserted in case of microMIPS64r6. + +@x = global i32 65504, align 4 +@y = global i32 60929, align 4 +@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32, i32* @x, align 4 + %and1 = and i32 %0, 4 + %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds + ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and1) + + %1 = load i32, i32* @y, align 4 + %and2 = and i32 %1, 5 + %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds + ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and2) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/cconv/arguments-float.ll b/test/CodeGen/Mips/cconv/arguments-float.ll index c81c7215e164..a76cf6226dc0 100644 --- a/test/CodeGen/Mips/cconv/arguments-float.ll +++ b/test/CodeGen/Mips/cconv/arguments-float.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s -; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s +; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s +; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s -; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s -; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s -; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s ; Test the floating point arguments for all ABI's and byte orders as specified ; by section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/arguments-fp128.ll b/test/CodeGen/Mips/cconv/arguments-fp128.ll index 6c62609396c5..70df97608aa9 100644 --- a/test/CodeGen/Mips/cconv/arguments-fp128.ll +++ b/test/CodeGen/Mips/cconv/arguments-fp128.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s -; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s +; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32 %s +; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32 %s -; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s -; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s +; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64 %s +; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64 %s ; Test the fp128 arguments for all ABI's and byte orders as specified ; by section 2 of the MIPSpro N32 Handbook. diff --git a/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll b/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll index 9f1fe91ec172..5f7a86534bdf 100644 --- a/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll +++ b/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s -; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s +; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s -; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW --check-prefix=NEWBE %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW --check-prefix=NEWLE %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,N32,NEW,NEWBE %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,N32,NEW,NEWLE %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW --check-prefix=NEWBE %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW --check-prefix=NEWLE %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,N64,NEW,NEWBE %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,N64,NEW,NEWLE %s ; Test the effect of varargs on floating point types in the non-variable part ; of the argument list as specified by section 2 of the MIPSpro N32 Handbook. diff --git a/test/CodeGen/Mips/cconv/arguments-hard-float.ll b/test/CodeGen/Mips/cconv/arguments-hard-float.ll index 24148ed176db..2e753d0f07cb 100644 --- a/test/CodeGen/Mips/cconv/arguments-hard-float.ll +++ b/test/CodeGen/Mips/cconv/arguments-hard-float.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s -; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s +; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s -; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s ; Test the floating point arguments for all ABI's and byte orders as specified ; by section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll b/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll index 26eb569f865d..1a3b664d9159 100644 --- a/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll +++ b/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32 %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32 %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64 %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64 %s ; Test the fp128 arguments for all ABI's and byte orders as specified ; by section 2 of the MIPSpro N32 Handbook. diff --git a/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll b/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll index 087a0515f379..56f9a64908bc 100644 --- a/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll +++ b/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=mips64 -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEB -; RUN: llc < %s -march=mips64el -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEL -; RUN: llc < %s -march=mips64 -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEB -; RUN: llc < %s -march=mips64el -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEL +; RUN: llc < %s -march=mips64 -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB +; RUN: llc < %s -march=mips64el -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL +; RUN: llc < %s -march=mips64 -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB +; RUN: llc < %s -march=mips64el -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL ; #include <stdio.h> ; diff --git a/test/CodeGen/Mips/cconv/arguments-struct.ll b/test/CodeGen/Mips/cconv/arguments-struct.ll index ee6bfaeb9537..44ea7c0f8337 100644 --- a/test/CodeGen/Mips/cconv/arguments-struct.ll +++ b/test/CodeGen/Mips/cconv/arguments-struct.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-BE %s -; RUN: llc -mtriple=mipsel-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-LE %s +; RUN: llc -mtriple=mips-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32-BE %s +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32-LE %s -; RUN-TODO: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-BE %s -; RUN-TODO: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-LE %s +; RUN-TODO: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32-BE %s +; RUN-TODO: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32-LE %s -; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW-BE %s -; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW-LE %s +; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW-BE %s +; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW-LE %s -; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW-BE %s -; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW-LE %s +; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW-BE %s +; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW-LE %s ; Test small structures for all ABI's and byte orders. ; diff --git a/test/CodeGen/Mips/cconv/arguments-varargs.ll b/test/CodeGen/Mips/cconv/arguments-varargs.ll index d1a196738aee..9c20b882dcb6 100644 --- a/test/CodeGen/Mips/cconv/arguments-varargs.ll +++ b/test/CodeGen/Mips/cconv/arguments-varargs.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips-linux -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-BE %s -; RUN: llc -mtriple=mipsel-linux -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-LE %s +; RUN: llc -mtriple=mips-linux -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32,O32-BE %s +; RUN: llc -mtriple=mipsel-linux -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32,O32-LE %s -; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64-linux -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N32 --check-prefix=NEW-BE %s -; RUN: llc -mtriple=mips64el-linux -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N32 --check-prefix=NEW-LE %s +; RUN: llc -mtriple=mips64-linux -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,NEW,N32,NEW-BE %s +; RUN: llc -mtriple=mips64el-linux -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,NEW,N32,NEW-LE %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N64 --check-prefix=NEW-BE %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N64 --check-prefix=NEW-LE %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,NEW,N64,NEW-BE %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,NEW,N64,NEW-LE %s @hwords = global [3 x i16] zeroinitializer, align 1 @words = global [3 x i32] zeroinitializer, align 1 diff --git a/test/CodeGen/Mips/cconv/arguments.ll b/test/CodeGen/Mips/cconv/arguments.ll index 430705f8d418..7af4e5517d51 100644 --- a/test/CodeGen/Mips/cconv/arguments.ll +++ b/test/CodeGen/Mips/cconv/arguments.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s -; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s +; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s -; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s ; Test the integer arguments for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/callee-saved-float.ll b/test/CodeGen/Mips/cconv/callee-saved-float.ll index c84f0f439c26..30a5727f344d 100644 --- a/test/CodeGen/Mips/cconv/callee-saved-float.ll +++ b/test/CodeGen/Mips/cconv/callee-saved-float.ll @@ -1,22 +1,24 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=O32-INV %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=O32-INV %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N32-INV %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N32-INV %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s + +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump -no-show-raw-insn -arch mips -mcpu=mips32r6 -mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s ; Test the the callee-saved registers are callee-saved as specified by section ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec. @@ -109,3 +111,6 @@ entry: ; N64-DAG: ldc1 [[F30]], [[OFF30]]($sp) ; N64-DAG: ldc1 [[F31]], [[OFF31]]($sp) ; N64: addiu $sp, $sp, 64 + +; Check the mapping between LDC164 and LDC1_64_MMR6. +; MM32R6: ldc1 diff --git a/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll b/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll index 4b28b9962075..bd33e0c51697 100644 --- a/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll +++ b/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll @@ -1,12 +1,12 @@ -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV %s -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV %s +; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s +; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s +; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV %s +; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV %s -; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s -; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s -; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV --check-prefix=O32-FPXX-INV %s -; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV --check-prefix=O32-FPXX-INV %s +; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s +; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s +; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV,O32-FPXX-INV %s +; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV,O32-FPXX-INV %s define void @fpu_clobber() nounwind { entry: diff --git a/test/CodeGen/Mips/cconv/callee-saved.ll b/test/CodeGen/Mips/cconv/callee-saved.ll index 0570ab35fd00..b7e94f882282 100644 --- a/test/CodeGen/Mips/cconv/callee-saved.ll +++ b/test/CodeGen/Mips/cconv/callee-saved.ll @@ -1,22 +1,22 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32-INV %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32-INV %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32-INV %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32-INV %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32-INV %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32-INV %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64-INV %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64-INV %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64-INV %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64-INV %s ; Test the callee-saved registers are callee-saved as specified by section ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec. diff --git a/test/CodeGen/Mips/cconv/memory-layout.ll b/test/CodeGen/Mips/cconv/memory-layout.ll index 33a68da157f6..e992169f6b64 100644 --- a/test/CodeGen/Mips/cconv/memory-layout.ll +++ b/test/CodeGen/Mips/cconv/memory-layout.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the memory layout for all ABI's and byte orders as specified by section ; 4 of MD00305 (MIPS ABIs Described). @@ -27,39 +27,39 @@ @double = global double 1.0, align 1 @pointer = global i8* @byte -; ALL-NOT: .align +; ALL-NOT: .p2align ; ALL-LABEL: byte: ; ALL: .byte 1 ; ALL: .size byte, 1 -; ALL: .align 1 +; ALL: .p2align 1 ; ALL-LABEL: halfword: ; ALL: .2byte 258 ; ALL: .size halfword, 2 -; ALL: .align 2 +; ALL: .p2align 2 ; ALL-LABEL: word: ; ALL: .4byte 16909060 ; ALL: .size word, 4 -; ALL: .align 2 +; ALL: .p2align 2 ; ALL-LABEL: float: ; ALL: .4byte 1065353216 ; ALL: .size float, 4 -; ALL: .align 3 +; ALL: .p2align 3 ; ALL-LABEL: dword: ; ALL: .8byte 283686952306183 ; ALL: .size dword, 8 -; ALL: .align 3 +; ALL: .p2align 3 ; ALL-LABEL: double: ; ALL: .8byte 4607182418800017408 ; ALL: .size double, 8 -; O32: .align 2 -; N32: .align 2 -; N64: .align 3 +; O32: .p2align 2 +; N32: .p2align 2 +; N64: .p2align 3 ; ALL-LABEL: pointer: ; O32: .4byte byte ; O32: .size pointer, 4 @@ -76,44 +76,44 @@ @double_array = global [2 x double] [double 1.0, double 2.0], align 1 @pointer_array = global [2 x i8*] [i8* @byte, i8* @byte] -; ALL-NOT: .align +; ALL-NOT: .p2align ; ALL-LABEL: byte_array: ; ALL: .ascii "\001\002" ; ALL: .size byte_array, 2 -; ALL: .align 1 +; ALL: .p2align 1 ; ALL-LABEL: halfword_array: ; ALL: .2byte 1 ; ALL: .2byte 2 ; ALL: .size halfword_array, 4 -; ALL: .align 2 +; ALL: .p2align 2 ; ALL-LABEL: word_array: ; ALL: .4byte 1 ; ALL: .4byte 2 ; ALL: .size word_array, 8 -; ALL: .align 2 +; ALL: .p2align 2 ; ALL-LABEL: float_array: ; ALL: .4byte 1065353216 ; ALL: .4byte 1073741824 ; ALL: .size float_array, 8 -; ALL: .align 3 +; ALL: .p2align 3 ; ALL-LABEL: dword_array: ; ALL: .8byte 1 ; ALL: .8byte 2 ; ALL: .size dword_array, 16 -; ALL: .align 3 +; ALL: .p2align 3 ; ALL-LABEL: double_array: ; ALL: .8byte 4607182418800017408 ; ALL: .8byte 4611686018427387904 ; ALL: .size double_array, 16 -; O32: .align 2 -; N32: .align 2 -; N64: .align 3 +; O32: .p2align 2 +; N32: .p2align 2 +; N64: .p2align 3 ; ALL-LABEL: pointer_array: ; O32: .4byte byte ; O32: .4byte byte @@ -128,7 +128,7 @@ %mixed = type { i8, double, i16 } @mixed = global %mixed { i8 1, double 1.0, i16 515 }, align 1 -; ALL: .align 3 +; ALL: .p2align 3 ; ALL-LABEL: mixed: ; ALL: .byte 1 ; ALL: .space 7 diff --git a/test/CodeGen/Mips/cconv/reserved-space.ll b/test/CodeGen/Mips/cconv/reserved-space.ll index 23190c2790cc..a17377ba0e56 100644 --- a/test/CodeGen/Mips/cconv/reserved-space.ll +++ b/test/CodeGen/Mips/cconv/reserved-space.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test that O32 correctly reserved space for the four arguments, even when ; there aren't any as per section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/return-float.ll b/test/CodeGen/Mips/cconv/return-float.ll index 8eb8c411e081..b9a6d6c5bc0d 100644 --- a/test/CodeGen/Mips/cconv/return-float.ll +++ b/test/CodeGen/Mips/cconv/return-float.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips-linux-gnu -mattr=+soft-float -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+soft-float -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -mtriple=mips-linux-gnu -mattr=+soft-float -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+soft-float -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the float returns for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/return-hard-float.ll b/test/CodeGen/Mips/cconv/return-hard-float.ll index 14853c8ca6f7..768cb6a9f2c6 100644 --- a/test/CodeGen/Mips/cconv/return-hard-float.ll +++ b/test/CodeGen/Mips/cconv/return-hard-float.ll @@ -1,17 +1,17 @@ -; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s -; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s -; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefixes=ALL,032FP64 %s +; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefixes=ALL,032FP64 %s ; Test the float returns for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/return-hard-fp128.ll b/test/CodeGen/Mips/cconv/return-hard-fp128.ll index 34e9647acddd..bdbfb80bd4aa 100644 --- a/test/CodeGen/Mips/cconv/return-hard-fp128.ll +++ b/test/CodeGen/Mips/cconv/return-hard-fp128.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the fp128 returns for N32/N64 and all byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll b/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll index c4c8f10ca3b4..9b178e4380d1 100644 --- a/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll +++ b/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll @@ -1,8 +1,8 @@ -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test return of {fp128} agrees with de-facto N32/N64 ABI. diff --git a/test/CodeGen/Mips/cconv/return-struct.ll b/test/CodeGen/Mips/cconv/return-struct.ll index 8decd04f089b..da20919ffd42 100644 --- a/test/CodeGen/Mips/cconv/return-struct.ll +++ b/test/CodeGen/Mips/cconv/return-struct.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-BE %s -; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-LE %s +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32,O32-BE %s +; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32,O32-LE %s -; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 --check-prefix=N32-BE %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 --check-prefix=N32-LE %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32,N32-BE %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32,N32-LE %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 --check-prefix=N64-BE %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 --check-prefix=N64-LE %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64,N64-BE %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64,N64-LE %s ; Test struct returns for all ABI's and byte orders. @@ -158,9 +158,6 @@ entry: ; sret pointer is already in $4 ; N32-DAG: lui [[PTR_HI:\$[0-9]+]], %hi(struct_128xi16) ; N32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_128xi16) -; FIXME: This signext isn't necessary. Like integers, pointers are -; but unlike integers, pointers cannot have the signext attribute. -; N32-DAG: sll $5, [[PTR]], 0 ; N32: jal memcpy ; sret pointer is already in $4 diff --git a/test/CodeGen/Mips/cconv/return.ll b/test/CodeGen/Mips/cconv/return.ll index a53767275434..561c94cb5783 100644 --- a/test/CodeGen/Mips/cconv/return.ll +++ b/test/CodeGen/Mips/cconv/return.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the integer returns for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/roundl-call.ll b/test/CodeGen/Mips/cconv/roundl-call.ll new file mode 100644 index 000000000000..8e4d6597784c --- /dev/null +++ b/test/CodeGen/Mips/cconv/roundl-call.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \ +; RUN: %s | FileCheck %s -check-prefixes=ALL,N32,HARD-FLOAT +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \ +; RUN: %s | FileCheck %s -check-prefixes=ALL,N32,HARD-FLOAT + +; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \ +; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \ +; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT + +; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT +; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT + +; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < %s \ +; RUN: | FileCheck %s -check-prefixes=ALL,N64,SOFT-FLOAT +; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < \ +; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,SOFT-FLOAT + +@fp128 = global fp128 zeroinitializer + +define void @roundl_call(fp128 %value) { +entry: +; ALL-LABEL: roundl_call: +; N32: lw $25, %call16(roundl)($gp) +; N64: ld $25, %call16(roundl)($gp) + +; SOFT-FLOAT: sd $4, 8(${{[0-9]+}}) +; SOFT-FLOAT: sd $2, 0(${{[0-9]+}}) + +; HARD-FLOAT: sdc1 $f2, 8(${{[0-9]+}}) +; HARD-FLOAT: sdc1 $f0, 0(${{[0-9]+}}) + + %call = call fp128 @roundl(fp128 %value) + store fp128 %call, fp128* @fp128 + ret void +} + +declare fp128 @roundl(fp128) nounwind readnone diff --git a/test/CodeGen/Mips/cconv/stack-alignment.ll b/test/CodeGen/Mips/cconv/stack-alignment.ll index f21bc3066f72..c957e311b1b3 100644 --- a/test/CodeGen/Mips/cconv/stack-alignment.ll +++ b/test/CodeGen/Mips/cconv/stack-alignment.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the stack alignment for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cfi_offset.ll b/test/CodeGen/Mips/cfi_offset.ll index 97233328fd55..0e85ea0a42be 100644 --- a/test/CodeGen/Mips/cfi_offset.ll +++ b/test/CodeGen/Mips/cfi_offset.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL -; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL +; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL @var = global double 0.0 diff --git a/test/CodeGen/Mips/check-adde-redundant-moves.ll b/test/CodeGen/Mips/check-adde-redundant-moves.ll index 7bc63a494ac7..cf0fda66ad62 100644 --- a/test/CodeGen/Mips/check-adde-redundant-moves.ll +++ b/test/CodeGen/Mips/check-adde-redundant-moves.ll @@ -1,15 +1,9 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index a8008a2cb29f..b0ef2b973d6a 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV -; RUN: llc -march=mips -mcpu=mips32 -regalloc=basic < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP +; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc -march=mips -mcpu=mips32 -regalloc=basic -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMP +; RUN: llc -march=mips64el -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc -march=mips64el -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc -march=mips64el -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMP @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @i3 = common global i32* null, align 4 @@ -521,14 +521,14 @@ entry: ; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 ; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]] -; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 -; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4 +; 64-CMP-DAG: daddiu $[[I4:[0-9]+]], $zero, 4 +; 64-CMP-DAG: daddiu $[[I5:2]], $zero, 5 ; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766 ; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 ; FIXME: We can do better than this by using selccz to choose between -0 and -2 -; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]] -; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]] -; 64-CMP-DAG: or $2, $[[T0]], $[[T1]] +; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I4]], $[[R0]] +; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]] +; 64-CMP-DAG: or $2, $[[T1]], $[[T0]] define i64 @slti64_3(i64 %a) { entry: diff --git a/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll b/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll new file mode 100644 index 000000000000..3cec194a3786 --- /dev/null +++ b/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll @@ -0,0 +1,55 @@ +; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s + +; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0 +; Cases where $rs == 0 and $rt != 0 should be transformed into beqzc/bnezc. +; Cases where $rs > $rt can have the operands swapped as ==,!= are commutative. + +; Cases where beq & bne where $rs == $rt have to inhibited from being turned +; into compact branches but arguably should not occur. This test covers the +; $rs == $rt case. + +; Starting from dwarf exception handling preparation skips optimizations that +; may simplify out the crucical bnec $4, $4 instruction. + +define internal void @_ZL14TestRemoveLastv(i32* %alist.sroa.0.4) { +entry: + %ascevgep = getelementptr i32, i32* %alist.sroa.0.4, i64 99 + br label %do.body121 + +for.cond117: + %alsr.iv.next = add nsw i32 %alsr.iv, -1 + %ascevgep340 = getelementptr i32, i32* %alsr.iv339, i64 -1 + %acmp118 = icmp sgt i32 %alsr.iv.next, 0 + br i1 %acmp118, label %do.body121, label %if.then143 + +do.body121: + %alsr.iv339 = phi i32* [ %ascevgep, %entry ], [ %ascevgep340, %for.cond117 ] + %alsr.iv = phi i32 [ 100, %entry ], [ %alsr.iv.next, %for.cond117 ] + %a9 = add i32 %alsr.iv, -1 + %alnot124 = icmp eq i32 %alsr.iv, %alsr.iv + br i1 %alnot124, label %do.body134, label %if.then143, !prof !11 + +do.body134: + %a10 = add i32 %alsr.iv, -1 + %a11 = load i32, i32* %alsr.iv339, align 4, !tbaa !5 +; CHECK-NOT: bnec $[[R0:[0-9]+]], $[[R0]] +; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]] + %alnot137 = icmp eq i32 %a9, %a11 + br i1 %alnot137, label %do.end146, label %if.then143, !prof !11 + +if.then143: + ret void + unreachable + +do.end146: + %alnot151 = icmp eq i32 %a9, %a10 + br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11 + +} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C++ TBAA"} +!5 = !{!6, !6, i64 0} +!6 = !{!"int", !3, i64 0} +!11 = !{!"branch_weights", i32 2000, i32 1} +!12 = !{!"branch_weights", i32 -388717296, i32 7818360} + diff --git a/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll b/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll new file mode 100644 index 000000000000..c819bf59ace6 --- /dev/null +++ b/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll @@ -0,0 +1,28 @@ +; Check that -mips-compact-branches={never,optimal,always} is accepted and honoured. +; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=never < %s | FileCheck %s -check-prefix=NEVER +; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=optimal < %s | FileCheck %s -check-prefix=OPTIMAL +; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=always < %s | FileCheck %s -check-prefix=ALWAYS + +define i32 @l(i32 signext %a, i32 signext %b) { +entry: + %add = add nsw i32 %b, %a + %cmp = icmp slt i32 %add, 100 +; NEVER: beq +; OPTIMAL: beq +; ALWAYS: beqzc +; This nop is required for correct as having (j|b)al as the instruction +; immediately following beqzc would cause a forbidden slot hazard. +; ALWAYS: nop + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = tail call i32 @k() + br label %if.end + +if.end: ; preds = %entry, %if.then + %call.pn = phi i32 [ %call, %if.then ], [ -1, %entry ] + %c.0 = add nsw i32 %call.pn, %add + ret i32 %c.0 +} + +declare i32 @k() #1 diff --git a/test/CodeGen/Mips/compactbranches/compact-branches.ll b/test/CodeGen/Mips/compactbranches/compact-branches.ll new file mode 100644 index 000000000000..75ff8a0bbcbb --- /dev/null +++ b/test/CodeGen/Mips/compactbranches/compact-branches.ll @@ -0,0 +1,206 @@ +; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32 +; RUN: llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC + +; Function Attrs: nounwind +define void @l() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() +; PIC: jalrc $25 + %call1 = tail call i32 @j() + %cmp = icmp eq i32 %call, %call1 +; CHECK: bnec + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext -2) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +declare i32 @k() + +declare i32 @j() + +declare void @f(i32 signext) + +; Function Attrs: define void @l2() { +define void @l2() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() +; PIC: jalrc $25 + %call1 = tail call i32 @i() + %cmp = icmp eq i32 %call, %call1 +; CHECK beqc + br i1 %cmp, label %if.end, label %if.then + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext -1) + br label %if.end + +if.end: ; preds = %entry, %if.then +; CHECK: jrc $ra + ret void +} + +declare i32 @i() + +; Function Attrs: nounwind +define void @l3() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() + %cmp = icmp slt i32 %call, 0 +; CHECK : bgez + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext 0) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +; Function Attrs: nounwind +define void @l4() { +entry: + %call = tail call i32 @k() + %cmp = icmp slt i32 %call, 1 +; CHECK: bgtzc + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal + tail call void @f(i32 signext 1) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +; Function Attrs: nounwind +define void @l5() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() +; PIC: jalrc $25 + %cmp = icmp sgt i32 %call, 0 +; CHECK: blezc + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext 2) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +; Function Attrs: nounwind +define void @l6() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() +; PIC: jalrc $25 + %cmp = icmp sgt i32 %call, -1 +; CHECK: bltzc + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext 3) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +; Function Attrs: nounwind +define void @l7() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() + %cmp = icmp eq i32 %call, 0 +; CHECK: bnezc + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext 4) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +; Function Attrs: nounwind +define void @l8() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() + %cmp = icmp eq i32 %call, 0 +; CHECK: beqzc + br i1 %cmp, label %if.end, label %if.then + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext 5) + br label %if.end + +if.end: ; preds = %entry, %if.then +; CHECK: jrc $ra + ret void +} + +define i32 @l9(i8* ()* %i) #0 { +entry: + %i.addr = alloca i8* ()*, align 4 + store i8* ()* %i, i8* ()** %i.addr, align 4 +; STATIC32: jal +; STATIC32: nop +; PIC: jalrc $25 + %call = call i32 @k() +; PIC: jalrc $25 + %cmp = icmp ne i32 %call, 0 +; CHECK: beqzc + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + %0 = load i8* ()*, i8* ()** %i.addr, align 4 +; CHECK: jalrc $25 + %call1 = call i8* %0() + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret i32 -1 +} diff --git a/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll b/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll new file mode 100644 index 000000000000..f6fef90d01b9 --- /dev/null +++ b/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll @@ -0,0 +1,53 @@ +; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s \ +; RUN: -filetype=obj -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING + +; bnezc and beqzc have restriction that $rt != 0 + +define i32 @f() { +; CHECK-LABEL: f +; CHECK-NOT: bnezc $0 + + %cmp = icmp eq i32 1, 1 + br i1 %cmp, label %if.then, label %if.end + + if.then: + ret i32 1 + + if.end: + ret i32 0 +} + +define i32 @f1() { +; CHECK-LABEL: f1 +; CHECK-NOT: beqzc $0 + + %cmp = icmp eq i32 0, 0 + br i1 %cmp, label %if.then, label %if.end + + if.then: + ret i32 1 + + if.end: + ret i32 0 +} + +; We silently fixup cases where the register allocator or user has given us +; an instruction with incorrect operands that is trivially acceptable. +; beqc and bnec have the restriction that $rs < $rt. + +define i32 @f2(i32 %a, i32 %b) { +; ENCODING-LABEL: f2 +; ENCODING-NOT: beqc $5, $4 +; ENCODING-NOT: bnec $5, $4 + + %cmp = icmp eq i32 %b, %a + br i1 %cmp, label %if.then, label %if.end + + if.then: + ret i32 1 + + if.end: + ret i32 0 +} + diff --git a/test/CodeGen/Mips/const-mult.ll b/test/CodeGen/Mips/const-mult.ll index 60b2a88196bd..7f4e896572a6 100644 --- a/test/CodeGen/Mips/const-mult.ll +++ b/test/CodeGen/Mips/const-mult.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK -; RUN: llc -march=mips64el < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK64 +; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mips64el < %s | FileCheck %s -check-prefixes=CHECK,CHECK64 ; CHECK-LABEL: mul5_32: ; CHECK: sll $[[R0:[0-9]+]], $4, 2 diff --git a/test/CodeGen/Mips/const4a.ll b/test/CodeGen/Mips/const4a.ll index d1182d7fc6ec..df4a1d9ff9ae 100644 --- a/test/CodeGen/Mips/const4a.ll +++ b/test/CodeGen/Mips/const4a.ll @@ -21,7 +21,7 @@ entry: ; no-load-relax: beqz ${{[0-9]+}}, $BB0_3 ; no-load-relax: lw ${{[0-9]+}}, %call16(foo)(${{[0-9]+}}) ; no-load-relax: b $BB0_4 -; no-load-relax: .align 2 +; no-load-relax: .p2align 2 ; no-load-relax: $CPI0_1: ; no-load-relax: .4byte 3735943886 ; no-load-relax: $BB0_3: diff --git a/test/CodeGen/Mips/const6.ll b/test/CodeGen/Mips/const6.ll index c576f573a43b..9085e38b3f60 100644 --- a/test/CodeGen/Mips/const6.ll +++ b/test/CodeGen/Mips/const6.ll @@ -18,7 +18,7 @@ entry: store i32 -559023410, i32* @i, align 4 ; load-relax: lw ${{[0-9]+}}, $CPI0_0 ; load-relax: jrc $ra -; load-relax: .align 2 +; load-relax: .p2align 2 ; load-relax: $CPI0_0: ; load-relax: .4byte 3735943886 ; load-relax: .end t @@ -26,7 +26,7 @@ entry: ; no-load-relax: lw ${{[0-9]+}}, $CPI0_1 # 16 bit inst ; no-load-relax: jalrc ${{[0-9]+}} ; no-load-relax: b $BB0_2 -; no-load-relax: .align 2 +; no-load-relax: .p2align 2 ; no-load-relax: $CPI0_1: ; no-load-relax: .4byte 3735943886 ; no-load-relax: $BB0_2: diff --git a/test/CodeGen/Mips/const6a.ll b/test/CodeGen/Mips/const6a.ll index 653cdeb920f3..80eedb4c897d 100644 --- a/test/CodeGen/Mips/const6a.ll +++ b/test/CodeGen/Mips/const6a.ll @@ -15,7 +15,7 @@ entry: ; load-relax-NOT: lw ${{[0-9]+}}, $CPI0_0 # 16 bit inst ; load-relax1: lw ${{[0-9]+}}, $CPI0_0 ; load-relax: jrc $ra -; load-relax: .align 2 +; load-relax: .p2align 2 ; load-relax: $CPI0_0: ; load-relax: .4byte 3735943886 ; load-relax: .end t diff --git a/test/CodeGen/Mips/countleading.ll b/test/CodeGen/Mips/countleading.ll index b7aad049e8ab..1b61be5ed2ac 100644 --- a/test/CodeGen/Mips/countleading.ll +++ b/test/CodeGen/Mips/countleading.ll @@ -1,10 +1,11 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6 -check-prefix=MIPS32-GT-R1 %s -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s -; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s -; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=ALL,MIPS32-R1-R2,MIPS32-GT-R1 %s +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,MIPS32-R1-R2,MIPS32-GT-R1 %s +; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefixes=ALL,MIPS32-R6,MIPS32-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefixes=ALL,MIPS4 %s +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS64 %s ; Prefixes: ; ALL - All @@ -21,6 +22,8 @@ entry: ; MIPS64-GT-R1: clz $2, $4 +; MICROMIPS64: clz $2, $4 + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) ret i32 %tmp1 } @@ -37,6 +40,8 @@ entry: ; MIPS64-GT-R1: clo $2, $4 +; MICROMIPS64: clo $2, $4 + %neg = xor i32 %X, -1 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) ret i32 %tmp1 @@ -58,6 +63,7 @@ entry: ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 ; MIPS64-GT-R1: dclz $2, $4 +; MICROMIPS64: dclz $2, $4 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) ret i64 %tmp1 @@ -83,6 +89,7 @@ entry: ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 ; MIPS64-GT-R1: dclo $2, $4 +; MICROMIPS64: dclo $2, $4 %neg = xor i64 %X, -1 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) diff --git a/test/CodeGen/Mips/cstmaterialization/stack.ll b/test/CodeGen/Mips/cstmaterialization/stack.ll new file mode 100644 index 000000000000..7266d00069cc --- /dev/null +++ b/test/CodeGen/Mips/cstmaterialization/stack.ll @@ -0,0 +1,54 @@ +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=CHECK-MIPS32 +; RUN: llc -march=mips64el -mcpu=mips64 < %s | \ +; RUN: FileCheck %s -check-prefix=CHECK-MIPS64 +; RUN: llc -march=mipsel -mcpu=mips64 -target-abi n32 < %s | \ +; RUN: FileCheck %s -check-prefix=CHECK-MIPSN32 + +; Test that the expansion of ADJCALLSTACKDOWN and ADJCALLSTACKUP generate +; (d)subu and (d)addu rather than just (d)addu. The (d)subu sequences are +; generally shorter as the constant that has to be materialized is smaller. + +define i32 @main() { +entry: + %z = alloca [1048576 x i8], align 1 + %arraydecay = getelementptr inbounds [1048576 x i8], [1048576 x i8]* %z, i32 0, i32 0 + %call = call i32 @foo(i8* %arraydecay) + ret i32 0 +; CHECK-LABEL: main + +; CHECK-MIPS32: lui $[[R0:[0-9]+]], 16 +; CHECK-MIPS32: addiu $[[R0]], $[[R0]], 24 +; CHECK-MIPS32: subu $sp, $sp, $[[R0]] + +; CHECK-MIPS32: lui $[[R1:[0-9]+]], 16 +; CHECK-MIPS32: addiu $[[R1]], $[[R1]], 24 +; CHECK-MIPS32: addu $sp, $sp, $[[R1]] + +; CHECK-MIPS64: lui $[[R0:[0-9]+]], 1 +; CHECK-MIPS64: daddiu $[[R0]], $[[R0]], 32 +; CHECK-MIPS64: dsubu $sp, $sp, $[[R0]] + +; FIXME: +; These are here to match other lui's used in address computations. We need to +; investigate why address computations are not CSE'd. Or implement it. + +; CHECK-MIPS64: lui +; CHECK-MIPS64: lui +; CHECK-MIPS64: lui +; CHECK-MIPS64: lui + +; CHECK-MIPS64: lui $[[R1:[0-9]+]], 16 +; CHECK-MIPS64: daddiu $[[R1]], $[[R1]], 32 +; CHECK-MIPS64: daddu $sp, $sp, $[[R1]] + +; CHECK-MIPSN32: lui $[[R0:[0-9]+]], 16 +; CHECK-MIPSN32: addiu $[[R0]], $[[R0]], 16 +; CHECK-MIPSN32: subu $sp, $sp, $[[R0]] + +; CHECK-MIPSN32: lui $[[R1:[0-9]+]], 16 +; CHECK-MIPSN32: addiu $[[R1]], $[[R1]], 16 +; CHECK-MIPSN32: addu $sp, $sp, $[[R1]] + +} + +declare i32 @foo(i8*) diff --git a/test/CodeGen/Mips/divrem.ll b/test/CodeGen/Mips/divrem.ll index 918db053f5b6..7703a8cecf5c 100644 --- a/test/CodeGen/Mips/divrem.ll +++ b/test/CodeGen/Mips/divrem.ll @@ -1,16 +1,16 @@ -; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC32 -check-prefix=ACC32-TRAP -; RUN: llc -march=mips -mcpu=mips32r2 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC32 -check-prefix=ACC32-TRAP -; RUN: llc -march=mips -mcpu=mips32r6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=GPR32-TRAP -; RUN: llc -march=mips64 -mcpu=mips64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC64 -check-prefix=ACC64-TRAP -; RUN: llc -march=mips64 -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC64 -check-prefix=ACC64-TRAP -; RUN: llc -march=mips64 -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=GPR64-TRAP +; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP +; RUN: llc -march=mips -mcpu=mips32r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP +; RUN: llc -march=mips -mcpu=mips32r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,GPR32-TRAP +; RUN: llc -march=mips64 -mcpu=mips64 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP +; RUN: llc -march=mips64 -mcpu=mips64r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP +; RUN: llc -march=mips64 -mcpu=mips64r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP -; RUN: llc -march=mips -mcpu=mips32 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC32 -check-prefix=NOCHECK -; RUN: llc -march=mips -mcpu=mips32r2 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC32 -check-prefix=NOCHECK -; RUN: llc -march=mips -mcpu=mips32r6 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NOCHECK -; RUN: llc -march=mips64 -mcpu=mips64 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC64 -check-prefix=NOCHECK -; RUN: llc -march=mips64 -mcpu=mips64r2 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC64 -check-prefix=NOCHECK -; RUN: llc -march=mips64 -mcpu=mips64r6 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=NOCHECK +; RUN: llc -march=mips -mcpu=mips32 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK +; RUN: llc -march=mips -mcpu=mips32r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK +; RUN: llc -march=mips -mcpu=mips32r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,NOCHECK +; RUN: llc -march=mips64 -mcpu=mips64 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK +; RUN: llc -march=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK +; RUN: llc -march=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK ; FileCheck Prefixes: ; ALL - All targets @@ -81,7 +81,7 @@ entry: ret i32 %rem } -define i32 @udiv1(i32 zeroext %a0, i32 zeroext %a1) nounwind readnone { +define i32 @udiv1(i32 signext %a0, i32 signext %a1) nounwind readnone { entry: ; ALL-LABEL: udiv1: @@ -107,7 +107,7 @@ entry: ret i32 %div } -define i32 @urem1(i32 zeroext %a0, i32 zeroext %a1) nounwind readnone { +define i32 @urem1(i32 signext %a0, i32 signext %a1) nounwind readnone { entry: ; ALL-LABEL: urem1: @@ -152,20 +152,20 @@ entry: ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sw $[[R0]], 0(${{[0-9]+}}) -; GPR32: mod $[[R0:[0-9]+]], $4, $5 +; GPR32-DAG: div $2, $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR32: sw $[[R0]], 0(${{[0-9]+}}) -; GPR32-DAG: div $2, $4, $5 +; GPR32-DAG: mod $[[R0:[0-9]+]], $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 +; GPR32: sw $[[R0]], 0(${{[0-9]+}}) -; GPR64: mod $[[R0:[0-9]+]], $4, $5 +; GPR64-DAG: div $2, $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR64: sw $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: div $2, $4, $5 +; GPR64-DAG: mod $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR64: sw $[[R0]], 0(${{[0-9]+}}) ; ALL: .end sdivrem1 @@ -175,7 +175,7 @@ entry: ret i32 %div } -define i32 @udivrem1(i32 zeroext %a0, i32 zeroext %a1, i32* nocapture %r) nounwind { +define i32 @udivrem1(i32 signext %a0, i32 signext %a1, i32* nocapture %r) nounwind { entry: ; ALL-LABEL: udivrem1: @@ -193,21 +193,21 @@ entry: ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sw $[[R0]], 0(${{[0-9]+}}) -; GPR32: modu $[[R0:[0-9]+]], $4, $5 +; GPR32-DAG: divu $2, $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR32: sw $[[R0]], 0(${{[0-9]+}}) -; GPR32-DAG: divu $2, $4, $5 +; GPR32-DAG: modu $[[R0:[0-9]+]], $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR32: sw $[[R0]], 0(${{[0-9]+}}) -; GPR64: modu $[[R0:[0-9]+]], $4, $5 +; GPR64-DAG: divu $2, $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR64: sw $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: divu $2, $4, $5 +; GPR64-DAG: modu $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR64: sw $[[R0]], 0(${{[0-9]+}}) ; ALL: .end udivrem1 @@ -335,14 +335,14 @@ entry: ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64: dmod $[[R0:[0-9]+]], $4, $5 +; GPR64-DAG: ddiv $2, $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: ddiv $2, $4, $5 +; GPR64-DAG: dmod $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR64: sd $[[R0]], 0(${{[0-9]+}}) ; ALL: .end sdivrem2 @@ -370,14 +370,14 @@ entry: ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64: dmodu $[[R0:[0-9]+]], $4, $5 +; GPR64-DAG: ddivu $2, $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: ddivu $2, $4, $5 +; GPR64: dmodu $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR64: sd $[[R0]], 0(${{[0-9]+}}) ; ALL: .end udivrem2 diff --git a/test/CodeGen/Mips/dsp-r1.ll b/test/CodeGen/Mips/dsp-r1.ll index fbd970399640..edd6258270a0 100644 --- a/test/CodeGen/Mips/dsp-r1.ll +++ b/test/CodeGen/Mips/dsp-r1.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp < %s | FileCheck %s +; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \ +; RUN: FileCheck %s define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind { entry: diff --git a/test/CodeGen/Mips/dynamic-stack-realignment.ll b/test/CodeGen/Mips/dynamic-stack-realignment.ll index 777930a37ad5..2ee1ca2e0dfc 100644 --- a/test/CodeGen/Mips/dynamic-stack-realignment.ll +++ b/test/CodeGen/Mips/dynamic-stack-realignment.ll @@ -1,21 +1,21 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N64 -; RUN: llc < %s -march=mips64 -mcpu=mips3 -target-abi n32 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N32 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -target-abi n32 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N32 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -target-abi n32 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N32 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N64 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -target-abi n32 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N32 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N32 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -target-abi n32 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N32 ; Check dynamic stack realignment in functions without variable-sized objects. diff --git a/test/CodeGen/Mips/eh-dwarf-cfa.ll b/test/CodeGen/Mips/eh-dwarf-cfa.ll index 6554974bf849..c4019c78d69e 100644 --- a/test/CodeGen/Mips/eh-dwarf-cfa.ll +++ b/test/CodeGen/Mips/eh-dwarf-cfa.ll @@ -13,6 +13,8 @@ entry: %0 = call i8* @llvm.eh.dwarf.cfa(i32 0) ret i8* %0 +; CHECK-LABEL: f1: + ; CHECK: addiu $sp, $sp, -32 ; CHECK: addiu $2, $sp, 32 } @@ -24,10 +26,12 @@ entry: %0 = call i8* @llvm.eh.dwarf.cfa(i32 0) ret i8* %0 +; CHECK-LABEL: f2: + ; check stack size (65536 + 8) -; CHECK: lui $[[R0:[a-z0-9]+]], 65535 -; CHECK: addiu $[[R0]], $[[R0]], -8 -; CHECK: addu $sp, $sp, $[[R0]] +; CHECK: lui $[[R0:[a-z0-9]+]], 1 +; CHECK: addiu $[[R0]], $[[R0]], 8 +; CHECK: subu $sp, $sp, $[[R0]] ; check return value ($sp + stack size) ; CHECK: lui $[[R1:[a-z0-9]+]], 1 @@ -46,6 +50,8 @@ entry: %add = add i32 %1, %3 ret i32 %add +; CHECK-LABEL: f3: + ; CHECK: addiu $sp, $sp, -40 ; check return value ($fp + stack size + $fp) @@ -60,6 +66,8 @@ entry: %0 = call i8* @llvm.eh.dwarf.cfa(i32 0) ret i8* %0 +; CHECK-LABEL: f4: + ; CHECK-MIPS64: daddiu $sp, $sp, -32 ; CHECK-MIPS64: daddiu $2, $sp, 32 } diff --git a/test/CodeGen/Mips/eh-return32.ll b/test/CodeGen/Mips/eh-return32.ll index 542c5bf4462e..a11a43cb406e 100644 --- a/test/CodeGen/Mips/eh-return32.ll +++ b/test/CodeGen/Mips/eh-return32.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6 -; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6 -; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6 +; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 declare void @llvm.eh.return.i32(i32, i8*) declare void @foo(...) diff --git a/test/CodeGen/Mips/eh-return64.ll b/test/CodeGen/Mips/eh-return64.ll index 2f8203d77c84..496e3abcf9c5 100644 --- a/test/CodeGen/Mips/eh-return64.ll +++ b/test/CodeGen/Mips/eh-return64.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips64el -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6 +; RUN: llc -march=mips64el -mcpu=mips4 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -march=mips64el -mcpu=mips64 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 declare void @llvm.eh.return.i64(i64, i8*) declare void @foo(...) diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll index 19f3d4d23d64..2f843d9da9a6 100644 --- a/test/CodeGen/Mips/eh.ll +++ b/test/CodeGen/Mips/eh.ll @@ -24,7 +24,7 @@ entry: lpad: ; preds = %entry ; CHECK-EL: # %lpad -; CHECK-EL: beq $5 +; CHECK-EL: bne $5 %exn.val = landingpad { i8*, i32 } cleanup diff --git a/test/CodeGen/Mips/ehframe-indirect.ll b/test/CodeGen/Mips/ehframe-indirect.ll index a51cfb7e0fcd..d6d47678590a 100644 --- a/test/CodeGen/Mips/ehframe-indirect.ll +++ b/test/CodeGen/Mips/ehframe-indirect.ll @@ -1,9 +1,9 @@ -; RUN: llc -mtriple=mipsel-linux-gnu < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=O32 %s -; RUN: llc -mtriple=mipsel-linux-android < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=O32 %s -; RUN: llc -mtriple=mips64el-linux-gnu -target-abi=n32 < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-android -target-abi=n32 < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-gnu < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=N64 %s -; RUN: llc -mtriple=mips64el-linux-android < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=N64 %s +; RUN: llc -mtriple=mipsel-linux-gnu < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-linux-android < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mips64el-linux-gnu -target-abi=n32 < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-android -target-abi=n32 < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-gnu < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-linux-android < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,N64 %s @_ZTISt9exception = external constant i8* @@ -42,9 +42,9 @@ declare void @foo() ; ALL: .hidden DW.ref.__gxx_personality_v0 ; ALL: .weak DW.ref.__gxx_personality_v0 ; ALL: .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat -; O32: .align 2 -; N32: .align 2 -; N64: .align 3 +; O32: .p2align 2 +; N32: .p2align 2 +; N64: .p2align 3 ; ALL: .type DW.ref.__gxx_personality_v0,@object ; O32: .size DW.ref.__gxx_personality_v0, 4 ; N32: .size DW.ref.__gxx_personality_v0, 4 diff --git a/test/CodeGen/Mips/elf_eflags.ll b/test/CodeGen/Mips/elf_eflags.ll index 00d8584fdad2..40910d8987d2 100644 --- a/test/CodeGen/Mips/elf_eflags.ll +++ b/test/CodeGen/Mips/elf_eflags.ll @@ -23,13 +23,13 @@ ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE32R2-MICROMIPS %s ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips %s -o - | FileCheck -check-prefix=CHECK-LE32R2-MICROMIPS_PIC %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64 %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 -target-abi n64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64 %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 -target-abi n64 %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64 %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64R2 %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 %s -o - | FileCheck -check-prefix=CHECK-LE64R2_PIC %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 -target-abi n64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64 %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 -target-abi n64 %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 -target-abi n64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64R2 %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 -target-abi n64 %s -o - | FileCheck -check-prefix=CHECK-LE64R2_PIC %s ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+mips16 -relocation-model=pic %s -o - | FileCheck -check-prefix=CHECK-LE32R2-MIPS16 %s diff --git a/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll b/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll index 54092b4e3ebe..a08b68149a70 100644 --- a/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll +++ b/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll @@ -1,5 +1,5 @@ ; Check that register scavenging spill slot is close to $fp. -; RUN: llc -march=mipsel -O0 < %s | FileCheck %s +; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s ; CHECK: sw ${{.*}}, 8($sp) ; CHECK: lw ${{.*}}, 8($sp) diff --git a/test/CodeGen/Mips/emutls_generic.ll b/test/CodeGen/Mips/emutls_generic.ll index a6cf23aa67ff..cda8dec7d12f 100644 --- a/test/CodeGen/Mips/emutls_generic.ll +++ b/test/CodeGen/Mips/emutls_generic.ll @@ -31,13 +31,13 @@ entry: ; MIPS_32-NOT: __emutls_t.external_x ; MIPS_32-NOT: __emutls_v.external_x: ; MIPS_32: .data -; MIPS_32: .align 2 +; MIPS_32: .p2align 2 ; MIPS_32-LABEL: __emutls_v.external_y: ; MIPS_32: .section .rodata, ; MIPS_32-LABEL: __emutls_t.external_y: ; MIPS_32-NEXT: .byte 7 ; MIPS_32: .data -; MIPS_32: .align 2 +; MIPS_32: .p2align 2 ; MIPS_32-LABEL: __emutls_v.internal_y: ; MIPS_32-NEXT: .4byte 8 ; MIPS_32-NEXT: .4byte 16 @@ -59,7 +59,7 @@ entry: ; MIPS_64-LABEL: __emutls_t.external_y: ; MIPS_64-NEXT: .byte 7 ; MIPS_64: .data -; MIPS_64: .align 3 +; MIPS_64: .p2align 3 ; MIPS_64-LABEL: __emutls_v.internal_y: ; MIPS_64-NEXT: .8byte 8 ; MIPS_64-NEXT: .8byte 16 diff --git a/test/CodeGen/Mips/fastcc.ll b/test/CodeGen/Mips/fastcc.ll index 299e0d696cbb..4b6191f9ae89 100644 --- a/test/CodeGen/Mips/fastcc.ll +++ b/test/CodeGen/Mips/fastcc.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=mipsel | FileCheck %s -; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu \ +; RUN: llc < %s -march=mipsel -relocation-model=pic | FileCheck %s +; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu -relocation-model=pic \ ; RUN: | FileCheck %s -check-prefix=CHECK-NACL -; RUN: llc < %s -march=mipsel -mcpu=mips32 -mattr=+nooddspreg | FileCheck %s -check-prefix=NOODDSPREG -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg | FileCheck %s -check-prefix=FP64-NOODDSPREG +; RUN: llc < %s -march=mipsel -mcpu=mips32 -mattr=+nooddspreg -relocation-model=pic | FileCheck %s -check-prefix=NOODDSPREG +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg -relocation-model=pic | FileCheck %s -check-prefix=FP64-NOODDSPREG @gi0 = external global i32 diff --git a/test/CodeGen/Mips/fcmp.ll b/test/CodeGen/Mips/fcmp.ll index aa1f09bf7aba..142ee1144bbe 100644 --- a/test/CodeGen/Mips/fcmp.ll +++ b/test/CodeGen/Mips/fcmp.ll @@ -1,21 +1,35 @@ ; RUN: llc < %s -march=mips -mcpu=mips32 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C +; RUN: FileCheck %s -check-prefixes=ALL,32-C ; RUN: llc < %s -march=mips -mcpu=mips32r2 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C +; RUN: FileCheck %s -check-prefixes=ALL,32-C ; RUN: llc < %s -march=mips -mcpu=mips32r6 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-CMP +; RUN: FileCheck %s -check-prefixes=ALL,32-CMP ; RUN: llc < %s -march=mips64 -mcpu=mips4 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: FileCheck %s -check-prefixes=ALL,64-C ; RUN: llc < %s -march=mips64 -mcpu=mips64 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: FileCheck %s -check-prefixes=ALL,64-C ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: FileCheck %s -check-prefixes=ALL,64-C ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMP +; RUN: FileCheck %s -check-prefixes=ALL,64-CMP +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6,MM32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6,MM64R6 define i32 @false_f32(float %a, float %b) nounwind { ; ALL-LABEL: false_f32: -; ALL: addiu $2, $zero, 0 +; 32-C: addiu $2, $zero, 0 + +; 32-CMP: addiu $2, $zero, 0 + +; 64-C: addiu $2, $zero, 0 + +; 64-CMP: addiu $2, $zero, 0 + +; MM-DAG: lui $2, 0 %1 = fcmp false float %a, %b %2 = zext i1 %1 to i32 @@ -41,6 +55,16 @@ define i32 @oeq_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.eq.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp oeq float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -65,6 +89,16 @@ define i32 @ogt_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ule.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ogt float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -89,6 +123,16 @@ define i32 @oge_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ult.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp oge float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -113,6 +157,16 @@ define i32 @olt_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.olt.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp olt float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -137,6 +191,16 @@ define i32 @ole_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ole.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ole float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -163,6 +227,17 @@ define i32 @one_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ueq.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp one float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -189,6 +264,17 @@ define i32 @ord_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.un.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp ord float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -213,6 +299,16 @@ define i32 @ueq_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ueq.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ueq float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -237,6 +333,16 @@ define i32 @ugt_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ole.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ugt float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -261,6 +367,16 @@ define i32 @uge_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.olt.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp uge float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -285,6 +401,15 @@ define i32 @ult_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ult.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 %1 = fcmp ult float %a, %b %2 = zext i1 %1 to i32 @@ -310,6 +435,16 @@ define i32 @ule_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ule.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ule float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -336,6 +471,17 @@ define i32 @une_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.eq.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp une float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -360,6 +506,16 @@ define i32 @uno_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.un.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp uno float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -367,7 +523,15 @@ define i32 @uno_f32(float %a, float %b) nounwind { define i32 @true_f32(float %a, float %b) nounwind { ; ALL-LABEL: true_f32: -; ALL: addiu $2, $zero, 1 +; 32-C: addiu $2, $zero, 1 + +; 32-CMP: addiu $2, $zero, 1 + +; 64-C: addiu $2, $zero, 1 + +; 64-CMP: addiu $2, $zero, 1 + +; MM-DAG: li16 $2, 1 %1 = fcmp true float %a, %b %2 = zext i1 %1 to i32 @@ -376,7 +540,15 @@ define i32 @true_f32(float %a, float %b) nounwind { define i32 @false_f64(double %a, double %b) nounwind { ; ALL-LABEL: false_f64: -; ALL: addiu $2, $zero, 0 +; 32-C: addiu $2, $zero, 0 + +; 32-CMP: addiu $2, $zero, 0 + +; 64-C: addiu $2, $zero, 0 + +; 64-CMP: addiu $2, $zero, 0 + +; MM-DAG: lui $2, 0 %1 = fcmp false double %a, %b %2 = zext i1 %1 to i32 @@ -402,6 +574,16 @@ define i32 @oeq_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.eq.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp oeq double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -426,6 +608,16 @@ define i32 @ogt_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ule.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ogt double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -450,6 +642,16 @@ define i32 @oge_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ult.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp oge double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -474,6 +676,16 @@ define i32 @olt_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.olt.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp olt double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -498,6 +710,16 @@ define i32 @ole_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ole.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ole double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -524,6 +746,17 @@ define i32 @one_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ueq.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp one double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -550,6 +783,17 @@ define i32 @ord_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.un.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp ord double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -574,6 +818,16 @@ define i32 @ueq_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ueq.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ueq double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -598,6 +852,16 @@ define i32 @ugt_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ole.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ugt double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -622,6 +886,16 @@ define i32 @uge_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.olt.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp uge double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -646,6 +920,16 @@ define i32 @ult_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ult.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ult double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -670,6 +954,16 @@ define i32 @ule_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ule.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ule double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -696,6 +990,17 @@ define i32 @une_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.eq.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp une double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -720,6 +1025,16 @@ define i32 @uno_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.un.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp uno double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -727,7 +1042,15 @@ define i32 @uno_f64(double %a, double %b) nounwind { define i32 @true_f64(double %a, double %b) nounwind { ; ALL-LABEL: true_f64: -; ALL: addiu $2, $zero, 1 +; 32-C: addiu $2, $zero, 1 + +; 32-CMP: addiu $2, $zero, 1 + +; 64-C: addiu $2, $zero, 1 + +; 64-CMP: addiu $2, $zero, 1 + +; MM-DAG: li16 $2, 1 %1 = fcmp true double %a, %b %2 = zext i1 %1 to i32 @@ -750,7 +1073,7 @@ entry: ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 -; 32-CMP-DAG: bnez $[[T4]], +; 32-CMP-DAG: bnezc $[[T4]], ; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)( @@ -763,7 +1086,32 @@ entry: ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 -; 64-CMP-DAG: bnez $[[T4]], +; 64-CMP-DAG: bnezc $[[T4]], + +; MM32R3-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12 +; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0) +; MM32R3-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]]) +; MM32R3-DAG: c.ole.s $[[T0]], $[[T2]] +; MM32R3-DAG: bc1t + +; MM32R6-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12 +; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0) +; MM32R6-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]]) +; MM32R6-DAG: cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]] +; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3:f[0-9]+]] +; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 +; MM32R6-DAG: bnez $[[T5]], + +; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f32))) +; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25 +; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32))) +; MM64R6-DAG: add.s $[[T3:f[0-9]+]], $f13, $f12 +; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI32_0)($[[T2]]) +; MM64R6-DAG: lwc1 $[[T5:f[0-9]+]], %got_ofst($CPI32_0)($[[T4]]) +; MM64R6-DAG: cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]] +; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]] +; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1 +; MM64R6-DAG: bnez $[[T8]], %add = fadd fast float %at, %angle %cmp = fcmp ogt float %add, 1.000000e+00 @@ -794,7 +1142,7 @@ entry: ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 -; 32-CMP-DAG: bnez $[[T4]], +; 32-CMP-DAG: bnezc $[[T4]], ; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)( @@ -807,7 +1155,32 @@ entry: ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 -; 64-CMP-DAG: bnez $[[T4]], +; 64-CMP-DAG: bnezc $[[T4]], + +; MM32R3-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12 +; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0) +; MM32R3-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]]) +; MM32R3-DAG: c.ole.d $[[T0]], $[[T2]] +; MM32R3-DAG: bc1t + +; MM32R6-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12 +; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0) +; MM32R6-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]]) +; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]] +; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]] +; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 +; MM32R6-DAG: bnez $[[T5]], + +; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f64))) +; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25 +; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64))) +; MM64R6-DAG: add.d $[[T3:f[0-9]+]], $f13, $f12 +; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI33_0)($[[T2]]) +; MM64R6-DAG: ldc1 $[[T5:f[0-9]+]], %got_ofst($CPI33_0)($[[T4]]) +; MM64R6-DAG: cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]] +; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]] +; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1 +; MM64R6-DAG: bnez $[[T8]], %add = fadd fast double %at, %angle %cmp = fcmp ogt double %add, 1.000000e+00 diff --git a/test/CodeGen/Mips/fcopysign-f32-f64.ll b/test/CodeGen/Mips/fcopysign-f32-f64.ll index 860bc79956fc..b1f065af0745 100644 --- a/test/CodeGen/Mips/fcopysign-f32-f64.ll +++ b/test/CodeGen/Mips/fcopysign-f32-f64.ll @@ -1,6 +1,9 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=64R2 +; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | \ +; RUN: FileCheck %s -check-prefixes=ALL,64 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | \ +; RUN: FileCheck %s -check-prefixes=ALL,64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R2 declare double @copysign(double, double) nounwind readnone @@ -8,7 +11,8 @@ declare float @copysignf(float, float) nounwind readnone define float @func2(float %d, double %f) nounwind readnone { entry: -; 64: func2 +; ALL-LABEL: func2: + ; 64-DAG: lui $[[T0:[0-9]+]], 32767 ; 64-DAG: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 ; 64-DAG: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] @@ -18,7 +22,7 @@ entry: ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]] ; 64: mtc1 $[[OR]], $f0 -; 64R2: dext ${{[0-9]+}}, ${{[0-9]+}}, 63, 1 +; 64R2: dextu ${{[0-9]+}}, ${{[0-9]+}}, 63, 1 ; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1 ; 64R2: mtc1 $[[INS]], $f0 @@ -30,17 +34,18 @@ entry: define double @func3(double %d, float %f) nounwind readnone { entry: +; ALL-LABEL: func3: -; 64: func3 -; 64-DAG: daddiu $[[T0:[0-9]+]], $zero, 1 -; 64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 63 -; 64-DAG: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1 -; 64-DAG: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] -; 64-DAG: srl $[[SRL:[0-9]+]], ${{[0-9]+}}, 31 -; 64-DAG: sll $[[SLL:[0-9]+]], $[[SRL]], 0 -; 64-DAG: dsll $[[DSLL:[0-9]+]], $[[SLL]], 63 -; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]] -; 64: dmtc1 $[[OR]], $f0 +; 64-DAG: mfc1 $[[MFC:[0-9]+]], $f13 +; 64-DAG: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31 +; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63 +; 64-DAG: daddiu $[[R1:[0-9]+]], $zero, 1 +; 64-DAG: dsll $[[R2:[0-9]+]], $[[R1]], 63 +; 64-DAG: daddiu $[[R3:[0-9]+]], $[[R2]], -1 +; 64-DAG: dmfc1 $[[R0:[0-9]+]], ${{.*}} +; 64: and $[[AND0:[0-9]+]], $[[R0]], $[[R3]] +; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]] +; 64: dmtc1 $[[OR]], $f0 ; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1 ; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1 @@ -51,4 +56,3 @@ entry: %call = tail call double @copysign(double %add, double %conv) nounwind readnone ret double %call } - diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll index 6928f2fe507f..ffc72a12f23d 100644 --- a/test/CodeGen/Mips/fcopysign.ll +++ b/test/CodeGen/Mips/fcopysign.ll @@ -27,7 +27,7 @@ entry: ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] ; 64: dmtc1 $[[OR]], $f0 -; 64R2: dext $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1 +; 64R2: dextu $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1 ; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1 ; 64R2: dmtc1 $[[INS]], $f0 diff --git a/test/CodeGen/Mips/fmadd1.ll b/test/CodeGen/Mips/fmadd1.ll index 99d99fada1cf..c155eedd62c4 100644 --- a/test/CodeGen/Mips/fmadd1.ll +++ b/test/CodeGen/Mips/fmadd1.ll @@ -5,18 +5,18 @@ ; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only ; available when -enable-no-nans-fp-math is given. -; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32 -check-prefix=32-NONAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NONAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NONAN -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64 -check-prefix=64-NONAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NONAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NONAN -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32 -check-prefix=32-NAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NAN -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64 -check-prefix=64-NAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NAN +; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32,32-NONAN +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6,32R6-NONAN +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6,64R6-NONAN +; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32,32-NAN +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6,32R6-NAN +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6,64R6-NAN define float @FOO0float(float %a, float %b, float %c) nounwind readnone { entry: diff --git a/test/CodeGen/Mips/fp-indexed-ls.ll b/test/CodeGen/Mips/fp-indexed-ls.ll index 219ca99d3f94..87fb248e56fd 100644 --- a/test/CodeGen/Mips/fp-indexed-ls.ll +++ b/test/CodeGen/Mips/fp-indexed-ls.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R1 -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R2 -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R6 -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4 -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4 -; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4 -; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64R6 +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R1 +; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R2 +; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R6 +; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 +; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 +; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS64R6 ; Check that [ls][dwu]xc1 are not emitted for nacl. ; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-NACL diff --git a/test/CodeGen/Mips/fp-spill-reload.ll b/test/CodeGen/Mips/fp-spill-reload.ll index 4a53ad8c8e13..431389ae9acb 100644 --- a/test/CodeGen/Mips/fp-spill-reload.ll +++ b/test/CodeGen/Mips/fp-spill-reload.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s ; check that $fp is not reserved. define void @foo0(i32* nocapture %b) nounwind { diff --git a/test/CodeGen/Mips/fp16-promote.ll b/test/CodeGen/Mips/fp16-promote.ll index 2ac46e028072..f060f6ab03ee 100644 --- a/test/CodeGen/Mips/fp16-promote.ll +++ b/test/CodeGen/Mips/fp16-promote.ll @@ -1,4 +1,4 @@ -; RUN: llc -asm-verbose=false -mtriple=mipsel-linux-gnueabi < %s | FileCheck %s -check-prefix=CHECK-LIBCALL +; RUN: llc -asm-verbose=false -mtriple=mipsel-linux-gnueabi -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-LIBCALL ; CHECK-LIBCALL-LABEL: test_fadd: ; CHECK-LIBCALL: %call16(__gnu_h2f_ieee) diff --git a/test/CodeGen/Mips/fp64a.ll b/test/CodeGen/Mips/fp64a.ll index fadce5cb748b..528a0c816842 100644 --- a/test/CodeGen/Mips/fp64a.ll +++ b/test/CodeGen/Mips/fp64a.ll @@ -11,14 +11,14 @@ ; incorrectly using this case. We should fix those test cases then add ; this check here. -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-BE -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-LE -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-BE +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-LE +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A -; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NO-FP64A +; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A ; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A -; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NO-FP64A +; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A ; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A ; 64-FP64A: LLVM ERROR: -mattr=+nooddspreg requires the O32 ABI. diff --git a/test/CodeGen/Mips/fpbr.ll b/test/CodeGen/Mips/fpbr.ll index 27d7094376e6..bf1b045dbf28 100644 --- a/test/CodeGen/Mips/fpbr.ll +++ b/test/CodeGen/Mips/fpbr.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR -; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR +; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR define void @func0(float %f2, float %f3) nounwind { entry: @@ -18,7 +18,8 @@ entry: ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; FIXME: We ought to be able to transform not+bnez -> beqz ; GPR: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], $BB0_2 +; 32-GPR: bnez $[[GPRCC]], $BB0_2 +; 64-GPR: bnezc $[[GPRCC]], $BB0_2 %cmp = fcmp oeq float %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -51,7 +52,8 @@ entry: ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], $BB1_2 +; 32-GPR: bnez $[[GPRCC]], $BB1_2 +; 64-GPR: bnezc $[[GPRCC]], $BB1_2 %cmp = fcmp olt float %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -80,7 +82,8 @@ entry: ; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: beqz $[[GPRCC]], $BB2_2 +; 32-GPR: beqz $[[GPRCC]], $BB2_2 +; 64-GPR: beqzc $[[GPRCC]], $BB2_2 %cmp = fcmp ugt float %f2, %f3 br i1 %cmp, label %if.else, label %if.then @@ -110,7 +113,8 @@ entry: ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; FIXME: We ought to be able to transform not+bnez -> beqz ; GPR: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], $BB3_2 +; 32-GPR: bnez $[[GPRCC]], $BB3_2 +; 64-GPR: bnezc $[[GPRCC]], $BB3_2 %cmp = fcmp oeq double %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -139,7 +143,8 @@ entry: ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], $BB4_2 +; 32-GPR: bnez $[[GPRCC]], $BB4_2 +; 64-GPR: bnezc $[[GPRCC]], $BB4_2 %cmp = fcmp olt double %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -168,7 +173,8 @@ entry: ; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: beqz $[[GPRCC]], $BB5_2 +; 32-GPR: beqz $[[GPRCC]], $BB5_2 +; 64-GPR: beqzc $[[GPRCC]], $BB5_2 %cmp = fcmp ugt double %f2, %f3 br i1 %cmp, label %if.else, label %if.then diff --git a/test/CodeGen/Mips/fpxx.ll b/test/CodeGen/Mips/fpxx.ll index 5b42ecec53e8..6fdb95efe8ec 100644 --- a/test/CodeGen/Mips/fpxx.ll +++ b/test/CodeGen/Mips/fpxx.ll @@ -1,20 +1,20 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-NOFPXX -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-FPXX +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32-NOFPXX +; RUN: llc -march=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32-FPXX -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NOFPXX -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FPXX +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32R2-NOFPXX +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32R2-FPXX -; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-NOFPXX +; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,4-NOFPXX ; RUN: not llc -march=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX -; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NOFPXX +; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,64-NOFPXX ; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-NOFPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-FPXX +; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,4-O32-NOFPXX +; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,4-O32-FPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-NOFPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-FPXX +; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,64-O32-NOFPXX +; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,64-O32-FPXX declare double @dbl(); diff --git a/test/CodeGen/Mips/gpreg-lazy-binding.ll b/test/CodeGen/Mips/gpreg-lazy-binding.ll index 800a74f5358f..98849ded7070 100644 --- a/test/CodeGen/Mips/gpreg-lazy-binding.ll +++ b/test/CodeGen/Mips/gpreg-lazy-binding.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -disable-mips-delay-filler < %s | FileCheck %s +; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck %s @g = external global i32 diff --git a/test/CodeGen/Mips/hf16call32.ll b/test/CodeGen/Mips/hf16call32.ll index 9fc94cac5175..5159477f2c69 100644 --- a/test/CodeGen/Mips/hf16call32.ll +++ b/test/CodeGen/Mips/hf16call32.ll @@ -820,7 +820,7 @@ declare void @v_df_df(double, double) #1 declare float @sf_v() #1 ; stel: .section .mips16.call.fp.sf_v,"ax",@progbits ; stel: .ent __call_stub_fp_sf_v -; stel: move $18, $31 +; stel: move $18, $ra ; stel: jal sf_v ; stel: mfc1 $2, $f0 ; stel: jr $18 @@ -898,7 +898,7 @@ declare float @sf_df_df(double, double) #1 declare double @df_v() #1 ; stel: .section .mips16.call.fp.df_v,"ax",@progbits ; stel: .ent __call_stub_fp_df_v -; stel: move $18, $31 +; stel: move $18, $ra ; stel: jal df_v ; stel: mfc1 $2, $f0 ; stel: mfc1 $3, $f1 @@ -983,7 +983,7 @@ declare double @df_df_df(double, double) #1 declare { float, float } @sc_v() #1 ; stel: .section .mips16.call.fp.sc_v,"ax",@progbits ; stel: .ent __call_stub_fp_sc_v -; stel: move $18, $31 +; stel: move $18, $ra ; stel: jal sc_v ; stel: mfc1 $2, $f0 ; stel: mfc1 $3, $f2 @@ -1004,7 +1004,7 @@ declare { float, float } @sc_sf(float) #1 declare { double, double } @dc_v() #1 ; stel: .section .mips16.call.fp.dc_v,"ax",@progbits ; stel: .ent __call_stub_fp_dc_v -; stel: move $18, $31 +; stel: move $18, $ra ; stel: jal dc_v ; stel: mfc1 $4, $f2 ; stel: mfc1 $5, $f3 diff --git a/test/CodeGen/Mips/hf16call32_body.ll b/test/CodeGen/Mips/hf16call32_body.ll index 1a04fd46f8bd..49ce181b015a 100644 --- a/test/CodeGen/Mips/hf16call32_body.ll +++ b/test/CodeGen/Mips/hf16call32_body.ll @@ -20,7 +20,8 @@ entry: } ; stel: .section .mips16.fn.v_sf,"ax",@progbits ; stel: .ent __fn_stub_v_sf -; stel: la $25, v_sf +; stel: lui $25, %hi(v_sf) +; stel: addiu $25, $25, %lo(v_sf) ; stel: mfc1 $4, $f12 ; stel: jr $25 ; stel: __fn_local_v_sf = v_sf @@ -40,7 +41,8 @@ entry: ; stel: .section .mips16.fn.v_df,"ax",@progbits ; stel: .ent __fn_stub_v_df -; stel: la $25, v_df +; stel: lui $25, %hi(v_df) +; stel: addiu $25, $25, %lo(v_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: jr $25 @@ -63,7 +65,8 @@ entry: ; stel: .section .mips16.fn.v_sf_sf,"ax",@progbits ; stel: .ent __fn_stub_v_sf_sf -; stel: la $25, v_sf_sf +; stel: lui $25, %hi(v_sf_sf) +; stel: addiu $25, $25, %lo(v_sf_sf) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f14 ; stel: jr $25 @@ -86,7 +89,8 @@ entry: ; stel: .section .mips16.fn.v_sf_df,"ax",@progbits ; stel: .ent __fn_stub_v_sf_df -; stel: la $25, v_sf_df +; stel: lui $25, %hi(v_sf_df) +; stel: addiu $25, $25, %lo(v_sf_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $6, $f14 ; stel: mfc1 $7, $f15 @@ -110,7 +114,8 @@ entry: ; stel: .section .mips16.fn.v_df_sf,"ax",@progbits ; stel: .ent __fn_stub_v_df_sf -; stel: la $25, v_df_sf +; stel: lui $25, %hi(v_df_sf) +; stel: addiu $25, $25, %lo(v_df_sf) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: mfc1 $6, $f14 @@ -134,7 +139,8 @@ entry: ; stel: .section .mips16.fn.v_df_df,"ax",@progbits ; stel: .ent __fn_stub_v_df_df -; stel: la $25, v_df_df +; stel: lui $25, %hi(v_df_df) +; stel: addiu $25, $25, %lo(v_df_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: mfc1 $6, $f14 @@ -164,7 +170,8 @@ entry: ; stel: .section .mips16.fn.sf_sf,"ax",@progbits ; stel: .ent __fn_stub_sf_sf -; stel: la $25, sf_sf +; stel: lui $25, %hi(sf_sf) +; stel: addiu $25, $25, %lo(sf_sf) ; stel: mfc1 $4, $f12 ; stel: jr $25 ; stel: __fn_local_sf_sf = sf_sf @@ -184,7 +191,8 @@ entry: ; stel: .section .mips16.fn.sf_df,"ax",@progbits ; stel: .ent __fn_stub_sf_df -; stel: la $25, sf_df +; stel: lui $25, %hi(sf_df) +; stel: addiu $25, $25, %lo(sf_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: jr $25 @@ -208,7 +216,8 @@ entry: ; stel: .section .mips16.fn.sf_sf_sf,"ax",@progbits ; stel: .ent __fn_stub_sf_sf_sf -; stel: la $25, sf_sf_sf +; stel: lui $25, %hi(sf_sf_sf) +; stel: addiu $25, $25, %lo(sf_sf_sf) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f14 ; stel: jr $25 @@ -232,7 +241,8 @@ entry: ; stel: .section .mips16.fn.sf_sf_df,"ax",@progbits ; stel: .ent __fn_stub_sf_sf_df -; stel: la $25, sf_sf_df +; stel: lui $25, %hi(sf_sf_df) +; stel: addiu $25, $25, %lo(sf_sf_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $6, $f14 ; stel: mfc1 $7, $f15 @@ -257,7 +267,8 @@ entry: ; stel: .section .mips16.fn.sf_df_sf,"ax",@progbits ; stel: .ent __fn_stub_sf_df_sf -; stel: la $25, sf_df_sf +; stel: lui $25, %hi(sf_df_sf) +; stel: addiu $25, $25, %lo(sf_df_sf) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: mfc1 $6, $f14 @@ -282,7 +293,8 @@ entry: ; stel: .section .mips16.fn.sf_df_df,"ax",@progbits ; stel: .ent __fn_stub_sf_df_df -; stel: la $25, sf_df_df +; stel: lui $25, %hi(sf_df_df) +; stel: addiu $25, $25, %lo(sf_df_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: mfc1 $6, $f14 diff --git a/test/CodeGen/Mips/hf1_body.ll b/test/CodeGen/Mips/hf1_body.ll index adf45109d69a..b6469716176f 100644 --- a/test/CodeGen/Mips/hf1_body.ll +++ b/test/CodeGen/Mips/hf1_body.ll @@ -1,4 +1,11 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=picfp16 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: -relocation-model=pic -no-integrated-as < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,GAS + +; The integrated assembler expands assembly macros before printing. +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,IAS @x = external global float @@ -11,11 +18,13 @@ entry: store float %0, float* @x, align 4 ret void } -; picfp16: .ent __fn_stub_v_sf -; picfp16: .cpload $25 -; picfp16: .set reorder -; picfp16: .reloc 0, R_MIPS_NONE, v_sf -; picfp16: la $25, $__fn_local_v_sf -; picfp16: mfc1 $4, $f12 -; picfp16: jr $25 -; picfp16: .end __fn_stub_v_sf +; ALL-LABEL: .ent __fn_stub_v_sf +; ALL: .cpload $25 +; ALL: .set reorder +; ALL: .reloc 0, R_MIPS_NONE, v_sf +; GAS: la $25, $__fn_local_v_sf +; IAS: lw $25, %got($$__fn_local_v_sf)($gp) +; IAS: addiu $25, $25, %lo($$__fn_local_v_sf) +; ALL: mfc1 $4, $f12 +; ALL: jr $25 +; ALL: .end __fn_stub_v_sf diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll index 5b2d13518035..22a0c1f51f7d 100644 --- a/test/CodeGen/Mips/i64arg.ll +++ b/test/CodeGen/Mips/i64arg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips -relocation-model=pic < %s | FileCheck %s define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { entry: diff --git a/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll b/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll new file mode 100644 index 000000000000..a99cb976eaa9 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll @@ -0,0 +1,36 @@ +; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s --check-prefixes=ALL,R6 +; RUN: llc -march=mips -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck %s --check-prefixes=ALL,R6 +; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,PRER6 +; RUN: llc -march=mips -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s --check-prefixes=ALL,PRER6 + + +%struct.anon = type { [63 x i32], i32, i32 } + +define i32 @Atomic() { +; CHECK-LABEL: Atomic: +entry: + %s = alloca %struct.anon, align 4 + %0 = bitcast %struct.anon* %s to i8* + %count = getelementptr inbounds %struct.anon, %struct.anon* %s, i64 0, i32 1 + store i32 0, i32* %count, align 4 +; R6: addiu $[[R0:[0-9a-z]+]], $sp, {{[0-9]+}} + +; ALL: #APP + +; R6: ll ${{[0-9a-z]+}}, 0($[[R0]]) +; R6: sc ${{[0-9a-z]+}}, 0($[[R0]]) + +; PRER6: ll ${{[0-9a-z]+}}, {{[0-9]+}}(${{[0-9a-z]+}}) +; PRER6: sc ${{[0-9a-z]+}}, {{[0-9]+}}(${{[0-9a-z]+}}) + +; ALL: #NO_APP + + %1 = call { i32, i32 } asm sideeffect ".set push\0A.set noreorder\0A1:\0All $0, $2\0Aaddu $1, $0, $3\0Asc $1, $2\0Abeqz $1, 1b\0Aaddu $1, $0, $3\0A.set pop\0A", "=&r,=&r,=*^ZC,Ir,*^ZC,~{memory},~{$1}"(i32* %count, i32 10, i32* %count) + %asmresult1.i = extractvalue { i32, i32 } %1, 1 + %cmp = icmp ne i32 %asmresult1.i, 10 + %conv = zext i1 %cmp to i32 + %call2 = call i32 @f(i32 signext %conv) + ret i32 %call2 +} + +declare i32 @f(i32 signext) diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll index 6d41385d18de..6b46884e9af7 100644 --- a/test/CodeGen/Mips/inlineasm-operand-code.ll +++ b/test/CodeGen/Mips/inlineasm-operand-code.ll @@ -1,9 +1,15 @@ ; Positive test for inline register constraints ; -; RUN: llc -no-integrated-as -march=mipsel < %s | \ -; RUN: FileCheck -check-prefix=ALL -check-prefix=LE32 -check-prefix=GAS %s -; RUN: llc -no-integrated-as -march=mips < %s | \ -; RUN: FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=GAS %s +; RUN: llc -no-integrated-as -march=mipsel -relocation-model=pic < %s | \ +; RUN: FileCheck -check-prefixes=ALL,LE32,GAS %s +; RUN: llc -no-integrated-as -march=mips -relocation-model=pic < %s | \ +; RUN: FileCheck -check-prefixes=ALL,BE32,GAS %s + +; IAS might not print in the same way since it parses the assembly. +; RUN: llc -march=mipsel -relocation-model=pic < %s | \ +; RUN: FileCheck -check-prefixes=ALL,LE32,IAS %s +; RUN: llc -march=mips -relocation-model=pic < %s | \ +; RUN: FileCheck -check-prefixes=ALL,BE32,IAS %s %union.u_tag = type { i64 } %struct.anon = type { i32, i32 } @@ -15,6 +21,7 @@ entry: ; ALL-LABEL: constraint_X: ; ALL: #APP ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd +; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 ; ALL: #NO_APP tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ; ret i32 0 @@ -26,6 +33,9 @@ entry: ; ALL-LABEL: constraint_x: ; ALL: #APP ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd +; This is _also_ -3 because uimm16 values are silently coerced to simm16 when +; it would otherwise fail to match. +; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 ; ALL: #NO_APP tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ; ret i32 0 @@ -54,39 +64,66 @@ entry: } ; z with -3 -define i32 @constraint_z() nounwind { +define void @constraint_z_0() nounwind { entry: -; ALL-LABEL: constraint_z: +; ALL-LABEL: constraint_z_0: ; ALL: #APP ; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 ; ALL: #NO_APP tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ; + ret void +} ; z with 0 +define void @constraint_z_1() nounwind { +entry: +; ALL-LABEL: constraint_z_1: ; ALL: #APP -; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0 +; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, $0 +; IAS: move ${{[0-9]+}}, ${{[0-9]+}} ; ALL: #NO_APP - tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind + tail call i32 asm sideeffect "addu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind + ret void +} ; z with non-zero and the "r"(register) and "J"(integer zero) constraints +define void @constraint_z_2() nounwind { +entry: +; ALL-LABEL: constraint_z_2: ; ALL: #APP ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} ; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind + ret void +} ; z with zero and the "r"(register) and "J"(integer zero) constraints +define void @constraint_z_3() nounwind { +entry: +; ALL-LABEL: constraint_z_3: ; ALL: #APP -; ALL: mtc0 $0, ${{[0-9]+}} +; GAS: mtc0 $0, ${{[0-9]+}} +; IAS: mtc0 $zero, ${{[0-9]+}}, 0 ; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind + ret void +} ; z with non-zero and just the "r"(register) constraint +define void @constraint_z_4() nounwind { +entry: +; ALL-LABEL: constraint_z_4: ; ALL: #APP ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} ; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind + ret void +} ; z with zero and just the "r"(register) constraint +define void @constraint_z_5() nounwind { +entry: +; ALL-LABEL: constraint_z_5: ; FIXME: Check for $0, instead of other registers. ; We should be using $0 directly in this case, not real registers. ; When the materialization of 0 gets fixed, this test will fail. @@ -94,7 +131,7 @@ entry: ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} ; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind - ret i32 0 + ret void } ; A long long in 32 bit mode (use to assert) diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll index a6ac07182ff5..164d28f733e4 100644 --- a/test/CodeGen/Mips/inlineasm_constraint.ll +++ b/test/CodeGen/Mips/inlineasm_constraint.ll @@ -1,5 +1,6 @@ ; RUN: llc -no-integrated-as -march=mipsel < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=GAS +; RUN: FileCheck %s -check-prefixes=ALL,GAS +; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=ALL,IAS define void @constraint_I() nounwind { ; First I with short @@ -31,6 +32,7 @@ define void @constraint_K() nounwind { ; Now K with 64 ; ALL: #APP ; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, 64 +; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 64 ; ALL: #NO_APP tail call i16 asm sideeffect "addu $0, $1, $2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind ret void diff --git a/test/CodeGen/Mips/inlineasm_constraint_R.ll b/test/CodeGen/Mips/inlineasm_constraint_R.ll index c4105ae6b22c..9c7611ba81d5 100644 --- a/test/CodeGen/Mips/inlineasm_constraint_R.ll +++ b/test/CodeGen/Mips/inlineasm_constraint_R.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s @data = global [8193 x i32] zeroinitializer diff --git a/test/CodeGen/Mips/inlineasm_constraint_ZC.ll b/test/CodeGen/Mips/inlineasm_constraint_ZC.ll index c1746a67564f..59778df3b423 100644 --- a/test/CodeGen/Mips/inlineasm_constraint_ZC.ll +++ b/test/CodeGen/Mips/inlineasm_constraint_ZC.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=09BIT -; RUN: llc -march=mipsel -mattr=+micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=12BIT -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=ALL -check-prefix=16BIT +; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,09BIT +; RUN: llc -march=mipsel -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,12BIT +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,16BIT @data = global [8193 x i32] zeroinitializer diff --git a/test/CodeGen/Mips/inlineasm_constraint_m.ll b/test/CodeGen/Mips/inlineasm_constraint_m.ll index 00053ad3c105..11ef8341cbdb 100644 --- a/test/CodeGen/Mips/inlineasm_constraint_m.ll +++ b/test/CodeGen/Mips/inlineasm_constraint_m.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s @data = global [8193 x i32] zeroinitializer diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll index bdf3ae55b802..61cbf93e667b 100644 --- a/test/CodeGen/Mips/inlineasmmemop.ll +++ b/test/CodeGen/Mips/inlineasmmemop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s ; Simple memory @g1 = external global i32 diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll index 2b4a0397f45f..b6b1c96c5f3b 100644 --- a/test/CodeGen/Mips/internalfunc.ll +++ b/test/CodeGen/Mips/internalfunc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mipsel | FileCheck %s +; RUN: llc < %s -march=mipsel -relocation-model=pic | FileCheck %s @caller.sf1 = internal unnamed_addr global void (...)* null, align 4 @gf1 = external global void (...)* diff --git a/test/CodeGen/Mips/interrupt-attr-64-error.ll b/test/CodeGen/Mips/interrupt-attr-64-error.ll index 830c199d91d9..9626bda45f51 100644 --- a/test/CodeGen/Mips/interrupt-attr-64-error.ll +++ b/test/CodeGen/Mips/interrupt-attr-64-error.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mcpu=mips64r6 -march=mipsel -relocation-model=static < %s 2>%t +; RUN: not llc -mcpu=mips64r6 -march=mipsel -target-abi n64 -relocation-model=static < %s 2>%t ; RUN: FileCheck %s < %t ; CHECK: LLVM ERROR: "interrupt" attribute is only supported for the O32 ABI on MIPS32R2+ at the present time. diff --git a/test/CodeGen/Mips/largeimm1.ll b/test/CodeGen/Mips/largeimm1.ll index 06c4d6bd9603..b4d15f9e1e8c 100644 --- a/test/CodeGen/Mips/largeimm1.ll +++ b/test/CodeGen/Mips/largeimm1.ll @@ -1,13 +1,19 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -; CHECK: lui ${{[0-9]+}}, 49152 -; CHECK: lui ${{[0-9]+}}, 16384 define void @f() nounwind { entry: %a1 = alloca [1073741824 x i8], align 1 %arrayidx = getelementptr inbounds [1073741824 x i8], [1073741824 x i8]* %a1, i32 0, i32 1048676 call void @f2(i8* %arrayidx) nounwind ret void +; CHECK-LABEL: f: + +; CHECK: lui $[[R0:[a-z0-9]+]], 16384 +; CHECK: addiu $[[R1:[a-z0-9]+]], $[[R0]], 24 +; CHECK: subu $sp, $sp, $[[R1]] + +; CHECK: lui $[[R2:[a-z0-9]+]], 16384 +; CHECK: addu ${{[0-9]+}}, $sp, $[[R2]] } declare void @f2(i8*) diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll index a53a953a7883..f27e11425b97 100644 --- a/test/CodeGen/Mips/largeimmprinting.ll +++ b/test/CodeGen/Mips/largeimmprinting.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32 -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | \ +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32 +; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | \ +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=64 %struct.S1 = type { [65536 x i8] } @@ -10,21 +10,19 @@ define void @f() nounwind { entry: -; 32: lui $[[R0:[0-9]+]], 65535 -; 32: addiu $[[R0]], $[[R0]], -24 -; 32: addu $sp, $sp, $[[R0]] -; 32: lui $[[R1:[0-9]+]], 1 -; 32: addu $[[R1]], $sp, $[[R1]] -; 32: sw $ra, 20($[[R1]]) -; 64: daddiu $[[R0:[0-9]+]], $zero, 1 -; 64: dsll $[[R0]], $[[R0]], 48 -; 64: daddiu $[[R0]], $[[R0]], -1 -; 64: dsll $[[R0]], $[[R0]], 16 -; 64: daddiu $[[R0]], $[[R0]], -32 -; 64: daddu $sp, $sp, $[[R0]] -; 64: lui $[[R1:[0-9]+]], 1 -; 64: daddu $[[R1]], $sp, $[[R1]] -; 64: sd $ra, 24($[[R1]]) +; 32: lui $[[R0:[0-9]+]], 1 +; 32: addiu $[[R0]], $[[R0]], 24 +; 32: subu $sp, $sp, $[[R0]] +; 32: lui $[[R1:[0-9]+]], 1 +; 32: addu $[[R1]], $sp, $[[R1]] +; 32: sw $ra, 20($[[R1]]) + +; 64: lui $[[R0:[0-9]+]], 1 +; 64: daddiu $[[R0]], $[[R0]], 32 +; 64: dsubu $sp, $sp, $[[R0]] +; 64: lui $[[R1:[0-9]+]], 1 +; 64: daddu $[[R1]], $sp, $[[R1]] +; 64: sd $ra, 24($[[R1]]) %agg.tmp = alloca %struct.S1, align 1 %tmp = getelementptr inbounds %struct.S1, %struct.S1* %agg.tmp, i32 0, i32 0, i32 0 diff --git a/test/CodeGen/Mips/lazy-binding.ll b/test/CodeGen/Mips/lazy-binding.ll index 839155adad9a..87040cc2b3ac 100644 --- a/test/CodeGen/Mips/lazy-binding.ll +++ b/test/CodeGen/Mips/lazy-binding.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s ; CHECK-LABEL: foo6: ; CHECK: %while.body diff --git a/test/CodeGen/Mips/lcb5.ll b/test/CodeGen/Mips/lcb5.ll index ec4c3da6515c..83f5fa0fb1c2 100644 --- a/test/CodeGen/Mips/lcb5.ll +++ b/test/CodeGen/Mips/lcb5.ll @@ -212,7 +212,7 @@ if.end: ; preds = %if.then, %entry ; ci: btnez $BB7_1 # 16 bit inst ; ci: jal $BB7_2 # branch ; ci: nop -; ci: .align 2 +; ci: .p2align 2 ; ci: $BB7_1: ; ci: .end z4 diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll index 6cccc7df19f9..7a60585d8fbf 100644 --- a/test/CodeGen/Mips/llvm-ir/add.ll +++ b/test/CodeGen/Mips/llvm-ir/add.ll @@ -1,37 +1,51 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @add_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: add_i1: - ; ALL: addu $[[T0:[0-9]+]], $4, $5 - ; ALL: sll $[[T0]], $[[T0]], 31 - ; ALL: sra $2, $[[T0]], 31 + ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 31 + ; NOT-R2-R6: sra $2, $[[T0]], 31 + + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: sll $[[T0]], $[[T0]], 31 + ; R2-R6: sra $2, $[[T0]], 31 + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 + ; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR6: sra $2, $[[T1]], 31 %r = add i1 %a, %b ret i1 %r @@ -45,8 +59,11 @@ entry: ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24 ; NOT-R2-R6: sra $2, $[[T0]], 24 - ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 - ; R2-R6: seb $2, $[[T0:[0-9]+]] + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seb $2, $[[T0:[0-9]+]] + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 + ; MMR6: seb $2, $[[T0]] %r = add i8 %a, %b ret i8 %r @@ -60,8 +77,11 @@ entry: ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16 ; NOT-R2-R6: sra $2, $[[T0]], 16 - ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 - ; R2-R6: seh $2, $[[T0:[0-9]+]] + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seh $2, $[[T0]] + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 + ; MMR6: seh $2, $[[T0]] %r = add i16 %a, %b ret i16 %r @@ -71,7 +91,10 @@ define signext i32 @add_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: add_i32: - ; ALL: addu $2, $4, $5 + ; NOT-R2-R6: addu $2, $4, $5 + ; R2-R6: addu $2, $4, $5 + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 %r = add i32 %a, %b ret i32 %r @@ -88,6 +111,13 @@ entry: ; GP64: daddu $2, $4, $5 + ; MM32: addu $3, $5, $7 + ; MM32: sltu $[[T0:[0-9]+]], $3, $7 + ; MM32: addu $[[T1:[0-9]+]], $[[T0]], $6 + ; MM32: addu $2, $4, $[[T1]] + + ; MM64: daddu $2, $4, $5 + %r = add i64 %a, %b ret i64 %r } @@ -102,13 +132,13 @@ entry: ; GP32: lw $[[T3:[0-9]+]], 24($sp) ; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]] - ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] + ; GP32: lw $[[T6:[0-9]+]], 16($sp) ; GP32: lw $[[T7:[0-9]+]], 20($sp) - ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] - ; GP32: lw $[[T9:[0-9]+]], 16($sp) + ; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]] + ; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]] ; GP32: addu $3, $5, $[[T8]] ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]] - ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]] + ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T6]] ; GP32: addu $2, $4, $[[T11]] ; GP32: move $4, $[[T5]] ; GP32: move $5, $[[T1]] @@ -118,6 +148,285 @@ entry: ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 ; GP64: daddu $2, $4, $[[T1]] + ; MM32: lw $[[T0:[0-9]+]], 28($sp) + ; MM32: addu $[[T1:[0-9]+]], $7, $[[T0]] + ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MM32: lw $[[T3:[0-9]+]], 24($sp) + ; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]] + ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] + ; MM32: lw $[[T7:[0-9]+]], 20($sp) + ; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] + ; MM32: addu $[[T9:[0-9]+]], $5, $[[T8]] + ; MM32: lw $[[T10:[0-9]+]], 16($sp) + ; MM32: sltu $[[T11:[0-9]+]], $[[T9]], $[[T7]] + ; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T10]] + ; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]] + ; MM32: move $4, $[[T5]] + ; MM32: move $5, $[[T1]] + + ; MM64: daddu $3, $5, $7 + ; MM64: sltu $[[T0:[0-9]+]], $3, $7 + ; MM64: daddu $[[T1:[0-9]+]], $[[T0]], $6 + ; MM64: daddu $2, $4, $[[T1]] + %r = add i128 %a, %b ret i128 %r } + +define signext i1 @add_i1_4(i1 signext %a) { +; ALL-LABEL: add_i1_4: + + ; ALL: move $2, $4 + + %r = add i1 4, %a + ret i1 %r +} + +define signext i8 @add_i8_4(i8 signext %a) { +; ALL-LABEL: add_i8_4: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 24 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 1024 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 24 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 4 + ; R2-R6: seb $2, $[[T0]] + + ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM32: seb $2, $[[T0]] + + ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM64: seb $2, $[[T0]] + + %r = add i8 4, %a + ret i8 %r +} + +define signext i16 @add_i16_4(i16 signext %a) { +; ALL-LABEL: add_i16_4: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 16 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 4 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 16 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 4 + ; R2-R6: seh $2, $[[T0]] + + ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM32: seh $2, $[[T0]] + + ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM64: seh $2, $[[T0]] + + %r = add i16 4, %a + ret i16 %r +} + +define signext i32 @add_i32_4(i32 signext %a) { +; ALL-LABEL: add_i32_4: + + ; GP32: addiu $2, $4, 4 + + ; GP64: addiu $2, $4, 4 + + ; MM32: addiur2 $2, $4, 4 + + ; MM64: addiur2 $2, $4, 4 + + %r = add i32 4, %a + ret i32 %r +} + +define signext i64 @add_i64_4(i64 signext %a) { +; ALL-LABEL: add_i64_4: + + ; GP32: addiu $[[T0:[0-9]+]], $5, 4 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 4 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $2, $4, $[[T1]] + + ; GP64: daddiu $2, $4, 4 + + ; MM32: addiu $[[T0:[0-9]+]], $5, 4 + ; MM32: li16 $[[T1:[0-9]+]], 4 + ; MM32: sltu $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; MM32: addu $2, $4, $[[T2]] + + ; MM64: daddiu $2, $4, 4 + + %r = add i64 4, %a + ret i64 %r +} + +define signext i128 @add_i128_4(i128 signext %a) { +; ALL-LABEL: add_i128_4: + + ; GP32: addiu $[[T0:[0-9]+]], $7, 4 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 4 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; GP32: sltu $[[T1]], $[[T2]], $zero + ; GP32: addu $[[T3:[0-9]+]], $5, $[[T1]] + ; GP32: sltu $[[T1]], $[[T3]], $zero + ; GP32: addu $[[T1]], $4, $[[T1]] + ; GP32: move $4, $[[T2]] + ; GP32: move $5, $[[T0]] + + ; GP64: daddiu $[[T0:[0-9]+]], $5, 4 + ; GP64: daddiu $[[T1:[0-9]+]], $zero, 4 + ; GP64: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP64: daddu $2, $4, $[[T1]] + + ; MM32: addiu $[[T0:[0-9]+]], $7, 4 + ; MM32: li16 $[[T1:[0-9]+]], 4 + ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; MM32: lui $[[T1]], 0 + ; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; MM32: addu $[[T3]], $5, $[[T3]] + ; MM32: sltu $[[T1]], $[[T3]], $[[T1]] + ; MM32: addu $[[T1]], $4, $[[T1]] + ; MM32: move $4, $[[T2]] + ; MM32: move $5, $[[T0]] + + ; MM64: daddiu $[[T0:[0-9]+]], $5, 4 + ; MM64: daddiu $[[T1:[0-9]+]], $zero, 4 + ; MM64: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM64: daddu $2, $4, $[[T1]] + + %r = add i128 4, %a + ret i128 %r +} + +define signext i1 @add_i1_3(i1 signext %a) { +; ALL-LABEL: add_i1_3: + + ; ALL: sll $[[T0:[0-9]+]], $4, 31 + ; ALL: lui $[[T1:[0-9]+]], 32768 + + ; GP32: addu $[[T0]], $[[T0]], $[[T1]] + ; GP32: sra $[[T1]], $[[T0]], 31 + + ; GP64: addu $[[T0]], $[[T0]], $[[T1]] + ; GP64: sra $[[T1]], $[[T0]], 31 + + ; MMR6: addu16 $[[T0]], $[[T0]], $[[T1]] + ; MMR6: sra $[[T0]], $[[T0]], 31 + + %r = add i1 3, %a + ret i1 %r +} + +define signext i8 @add_i8_3(i8 signext %a) { +; ALL-LABEL: add_i8_3: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 24 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 768 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 24 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 3 + ; R2-R6: seb $2, $[[T0]] + + ; MMR6: addius5 $[[T0:[0-9]+]], 3 + ; MMR6: seb $2, $[[T0]] + + %r = add i8 3, %a + ret i8 %r +} + +define signext i16 @add_i16_3(i16 signext %a) { +; ALL-LABEL: add_i16_3: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 16 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 3 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 16 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 3 + ; R2-R6: seh $2, $[[T0]] + + ; MMR6: addius5 $[[T0:[0-9]+]], 3 + ; MMR6: seh $2, $[[T0]] + + %r = add i16 3, %a + ret i16 %r +} + +define signext i32 @add_i32_3(i32 signext %a) { +; ALL-LABEL: add_i32_3: + + ; NOT-R2-R6: addiu $2, $4, 3 + + ; R2-R6: addiu $2, $4, 3 + + ; MMR6: addius5 $[[T0:[0-9]+]], 3 + ; MMR6: move $2, $[[T0]] + + %r = add i32 3, %a + ret i32 %r +} + +define signext i64 @add_i64_3(i64 signext %a) { +; ALL-LABEL: add_i64_3: + + ; GP32: addiu $[[T0:[0-9]+]], $5, 3 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 3 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $2, $4, $[[T1]] + + ; GP64: daddiu $2, $4, 3 + + ; MM32: addiu $[[T0:[0-9]+]], $5, 3 + ; MM32: li16 $[[T1:[0-9]+]], 3 + ; MM32: sltu $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; MM32: addu $2, $4, $[[T2]] + + ; MM64: daddiu $2, $4, 3 + + %r = add i64 3, %a + ret i64 %r +} + +define signext i128 @add_i128_3(i128 signext %a) { +; ALL-LABEL: add_i128_3: + + ; GP32: addiu $[[T0:[0-9]+]], $7, 3 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 3 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; GP32: sltu $[[T3:[0-9]+]], $[[T2]], $zero + ; GP32: addu $[[T4:[0-9]+]], $5, $[[T3]] + ; GP32: sltu $[[T5:[0-9]+]], $[[T4]], $zero + ; GP32: addu $[[T5]], $4, $[[T5]] + ; GP32: move $4, $[[T2]] + ; GP32: move $5, $[[T0]] + + ; GP64: daddiu $[[T0:[0-9]+]], $5, 3 + ; GP64: daddiu $[[T1:[0-9]+]], $zero, 3 + ; GP64: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP64: daddu $2, $4, $[[T1]] + + ; MM32: addiu $[[T0:[0-9]+]], $7, 3 + ; MM32: li16 $[[T1:[0-9]+]], 3 + ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; MM32: lui $[[T3:[0-9]+]], 0 + ; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; MM32: addu $[[T4]], $5, $[[T4]] + ; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]] + ; MM32: addu $[[T5]], $4, $[[T5]] + ; MM32: move $4, $[[T2]] + ; MM32: move $5, $[[T0]] + + ; MM64: daddiu $[[T0:[0-9]+]], $5, 3 + ; MM64: daddiu $[[T1:[0-9]+]], $zero, 3 + ; MM64: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM64: daddu $2, $4, $[[T1]] + + %r = add i128 3, %a + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll index c4121701ec15..d320ce60f291 100644 --- a/test/CodeGen/Mips/llvm-ir/and.ll +++ b/test/CodeGen/Mips/llvm-ir/and.ll @@ -1,35 +1,46 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @and_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: and_i1: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MM: and16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = and i1 %a, %b ret i1 %r @@ -39,7 +50,12 @@ define signext i8 @and_i8(i8 signext %a, i8 signext %b) { entry: ; ALL-LABEL: and_i8: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MM: and16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = and i8 %a, %b ret i8 %r @@ -49,7 +65,12 @@ define signext i16 @and_i16(i16 signext %a, i16 signext %b) { entry: ; ALL-LABEL: and_i16: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MM: and16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = and i16 %a, %b ret i16 %r @@ -64,6 +85,12 @@ entry: ; GP64: and $[[T0:[0-9]+]], $4, $5 ; GP64: sll $2, $[[T0]], 0 + ; MM32: and16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: and $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = and i32 %a, %b ret i32 %r } @@ -77,6 +104,13 @@ entry: ; GP64: and $2, $4, $5 + ; MM32: and16 $[[T0:[0-9]+]], $6 + ; MM32: and16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: and $2, $4, $5 + %r = and i64 %a, %b ret i64 %r } @@ -97,6 +131,573 @@ entry: ; GP64: and $2, $4, $6 ; GP64: and $3, $5, $7 + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: and16 $[[T1]], $4 + ; MM32: and16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: and16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: and16 $[[T3]], $7 + + ; MM64: and $2, $4, $6 + ; MM64: and $3, $5, $7 + %r = and i128 %a, %b ret i128 %r } + +define signext i1 @and_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_4: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i1 4, %b + ret i1 %r +} + +define signext i8 @and_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MM: andi16 $2, $4, 4 + + %r = and i8 4, %b + ret i8 %r +} + +define signext i16 @and_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MM: andi16 $2, $4, 4 + + %r = and i16 4, %b + ret i16 %r +} + +define signext i32 @and_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MM: andi16 $2, $4, 4 + + %r = and i32 4, %b + ret i32 %r +} + +define signext i64 @and_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_4: + + ; GP32: andi $3, $5, 4 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 4 + + ; MM32: andi16 $3, $5, 4 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 4 + + %r = and i64 4, %b + ret i64 %r +} + +define signext i128 @and_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_4: + + ; GP32: andi $5, $7, 4 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 4 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 4 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 4 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 4, %b + ret i128 %r +} + +define signext i1 @and_i1_31(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_31: + + ; ALL: move $2, $4 + + %r = and i1 31, %b + ret i1 %r +} + +define signext i8 @and_i8_31(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MM: andi16 $2, $4, 31 + + %r = and i8 31, %b + ret i8 %r +} + +define signext i16 @and_i16_31(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MM: andi16 $2, $4, 31 + + %r = and i16 31, %b + ret i16 %r +} + +define signext i32 @and_i32_31(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MM: andi16 $2, $4, 31 + + %r = and i32 31, %b + ret i32 %r +} + +define signext i64 @and_i64_31(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_31: + + ; GP32: andi $3, $5, 31 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 31 + + ; MM32: andi16 $3, $5, 31 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 31 + + %r = and i64 31, %b + ret i64 %r +} + +define signext i128 @and_i128_31(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_31: + + ; GP32: andi $5, $7, 31 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 31 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 31 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 31 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 31, %b + ret i128 %r +} + +define signext i1 @and_i1_255(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_255: + + ; ALL: move $2, $4 + + %r = and i1 255, %b + ret i1 %r +} + +define signext i8 @and_i8_255(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_255: + + ; ALL: move $2, $4 + + %r = and i8 255, %b + ret i8 %r +} + +define signext i16 @and_i16_255(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_255: + + ; GP32: andi $2, $4, 255 + + ; GP64: andi $2, $4, 255 + + ; MM: andi16 $2, $4, 255 + + %r = and i16 255, %b + ret i16 %r +} + +define signext i32 @and_i32_255(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_255: + + ; GP32: andi $2, $4, 255 + + ; GP64: andi $2, $4, 255 + + ; MM: andi16 $2, $4, 255 + + %r = and i32 255, %b + ret i32 %r +} + +define signext i64 @and_i64_255(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_255: + + ; GP32: andi $3, $5, 255 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 255 + + ; MM32: andi16 $3, $5, 255 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 255 + + %r = and i64 255, %b + ret i64 %r +} + +define signext i128 @and_i128_255(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_255: + + ; GP32: andi $5, $7, 255 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 255 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 255 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 255 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 255, %b + ret i128 %r +} + +define signext i1 @and_i1_32768(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_32768: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i1 32768, %b + ret i1 %r +} + +define signext i8 @and_i8_32768(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_32768: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i8 32768, %b + ret i8 %r +} + +define signext i16 @and_i16_32768(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_32768: + + ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP32: and $2, $4, $[[T0]] + + ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP64: and $2, $4, $[[T0]] + + ; MM: addiu $2, $zero, -32768 + ; MM: and16 $2, $4 + + %r = and i16 32768, %b + ret i16 %r +} + +define signext i32 @and_i32_32768(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_32768: + + ; GP32: andi $2, $4, 32768 + + ; GP64: andi $2, $4, 32768 + + ; MM: andi16 $2, $4, 32768 + + %r = and i32 32768, %b + ret i32 %r +} + +define signext i64 @and_i64_32768(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_32768: + + ; GP32: andi $3, $5, 32768 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 32768 + + ; MM32: andi16 $3, $5, 32768 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 32768 + + %r = and i64 32768, %b + ret i64 %r +} + +define signext i128 @and_i128_32768(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_32768: + + ; GP32: andi $5, $7, 32768 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 32768 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 32768 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 32768 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 32768, %b + ret i128 %r +} + +define signext i1 @and_i1_65(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_65: + + ; ALL: move $2, $4 + + %r = and i1 65, %b + ret i1 %r +} + +define signext i8 @and_i8_65(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_65: + + ; ALL: andi $2, $4, 65 + + %r = and i8 65, %b + ret i8 %r +} + +define signext i16 @and_i16_65(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_65: + + ; ALL: andi $2, $4, 65 + + %r = and i16 65, %b + ret i16 %r +} + +define signext i32 @and_i32_65(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_65: + + ; ALL: andi $2, $4, 65 + + %r = and i32 65, %b + ret i32 %r +} + +define signext i64 @and_i64_65(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_65: + + ; GP32: andi $3, $5, 65 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 65 + + ; MM32: andi $3, $5, 65 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 65 + + %r = and i64 65, %b + ret i64 %r +} + +define signext i128 @and_i128_65(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_65: + + ; GP32: andi $5, $7, 65 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 65 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi $5, $7, 65 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 65 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 65, %b + ret i128 %r +} + +define signext i1 @and_i1_256(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_256: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i1 256, %b + ret i1 %r +} + +define signext i8 @and_i8_256(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_256: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i8 256, %b + ret i8 %r +} + +define signext i16 @and_i16_256(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_256: + + ; ALL: andi $2, $4, 256 + + %r = and i16 256, %b + ret i16 %r +} + +define signext i32 @and_i32_256(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_256: + + ; ALL: andi $2, $4, 256 + + %r = and i32 256, %b + ret i32 %r +} + +define signext i64 @and_i64_256(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_256: + + ; GP32: andi $3, $5, 256 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 256 + + ; MM32: andi $3, $5, 256 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 256 + + %r = and i64 256, %b + ret i64 %r +} + +define signext i128 @and_i128_256(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_256: + + ; GP32: andi $5, $7, 256 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 256 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi $5, $7, 256 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 256 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 256, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll index cad4a39d7743..af9b81f9203f 100644 --- a/test/CodeGen/Mips/llvm-ir/ashr.ll +++ b/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -1,42 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=M2 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,M2 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) { entry: @@ -53,7 +44,9 @@ entry: ; ALL-LABEL: ashr_i8: ; FIXME: The andi instruction is redundant. - ; ALL: andi $[[T0:[0-9]+]], $5, 255 + ; GP32: andi $[[T0:[0-9]+]], $5, 255 + ; GP64: andi $[[T0:[0-9]+]], $5, 255 + ; MM: andi16 $[[T0:[0-9]+]], $5, 255 ; ALL: srav $2, $4, $[[T0]] %r = ashr i8 %a, %b @@ -65,7 +58,9 @@ entry: ; ALL-LABEL: ashr_i16: ; FIXME: The andi instruction is redundant. - ; ALL: andi $[[T0:[0-9]+]], $5, 65535 + ; GP32: andi $[[T0:[0-9]+]], $5, 65535 + ; GP64: andi $[[T0:[0-9]+]], $5, 65535 + ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 ; ALL: srav $2, $4, $[[T0]] %r = ashr i16 %a, %b @@ -133,6 +128,32 @@ entry: ; GP64: dsrav $2, $4, $5 + ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 + ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1 + ; MMR3: not16 $[[T2:[0-9]+]], $7 + ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR3: srav $[[T5:[0-9]+]], $4, $7 + ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 + ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; MMR3: sra $[[T8:[0-9]+]], $4, 31 + ; MMR3: movn $2, $[[T8]], $[[T6]] + + ; MMR6: srav $[[T0:[0-9]+]], $4, $7 + ; MMR6: andi16 $[[T1:[0-9]+]], $7, 32 + ; MMR6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; MMR6: sra $[[T3:[0-9]+]], $4, 31 + ; MMR6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] + ; MMR6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] + ; MMR6: srlv $[[T6:[0-9]+]], $5, $7 + ; MMR6: sll16 $[[T7:[0-9]+]], $4, 1 + ; MMR6: not16 $[[T8:[0-9]+]], $7 + ; MMR6: sllv $[[T9:[0-9]+]], $[[T7]], $[[T8]] + ; MMR6: or16 $[[T10:[0-9]+]], $[[T6]] + ; MMR6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] + ; MMR6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] + ; MMR6: or $3, $[[T12]], $[[T11]] + %r = ashr i64 %a, %b ret i64 %r } @@ -192,6 +213,8 @@ entry: ; 64R6: jr $ra ; 64R6: or $3, $[[T13]], $[[T12]] + ; MM: lw $25, %call16(__ashrti3)($2) + %r = ashr i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll index a4b03405f72b..0d524d439600 100644 --- a/test/CodeGen/Mips/llvm-ir/call.ll +++ b/test/CodeGen/Mips/llvm-ir/call.ll @@ -1,18 +1,18 @@ ; Test the 'call' instruction and the tailcall variant. ; FIXME: We should remove the need for -enable-mips-tail-calls -; RUN: llc -march=mips -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 +; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,R6C +; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,R6C +; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,R6C declare void @extern_void_void() declare i32 @extern_i32_void() @@ -25,9 +25,11 @@ define i32 @call_void_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp) -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] call void @extern_void_void() +; R6C: jrc $ra ret i32 0 } @@ -38,10 +40,12 @@ define i32 @call_i32_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp) -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] %1 = call i32 @extern_i32_void() %2 = add i32 %1, 1 +; R6C: jrc $ra ret i32 %2 } @@ -55,12 +59,13 @@ define float @call_float_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp) -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] -; O32: move $gp, $[[GP]] %1 = call float @extern_float_void() %2 = fadd float %1, 1.0 +; R6C: jrc $ra ret float %2 } @@ -71,8 +76,7 @@ define void @musttail_call_void_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp) -; NOT-R6: jr $[[TGT]] -; R6: r6.jr $[[TGT]] +; ALL: jr $[[TGT]] musttail call void @extern_void_void() ret void @@ -85,8 +89,7 @@ define i32 @musttail_call_i32_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp) -; NOT-R6: jr $[[TGT]] -; R6: r6.jr $[[TGT]] +; ALL: jr $[[TGT]] %1 = musttail call i32 @extern_i32_void() ret i32 %1 @@ -99,8 +102,7 @@ define float @musttail_call_float_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp) -; NOT-R6: jr $[[TGT]] -; R6: r6.jr $[[TGT]] +; ALL: jr $[[TGT]] %1 = musttail call float @extern_float_void() ret float %1 @@ -110,9 +112,11 @@ define i32 @indirect_call_void_void(void ()* %addr) { ; ALL-LABEL: indirect_call_void_void: ; ALL: move $25, $4 -; ALL: jalr $25 +; NOT-R6C: jalr $25 +; R6C: jalrc $25 call void %addr() +; R6C: jrc $ra ret i32 0 } @@ -120,10 +124,13 @@ define i32 @indirect_call_i32_void(i32 ()* %addr) { ; ALL-LABEL: indirect_call_i32_void: ; ALL: move $25, $4 -; ALL: jalr $25 +; NOT-R6C: jalr $25 +; R6C: jalrc $25 + %1 = call i32 %addr() %2 = add i32 %1, 1 +; R6C: jrc $ra ret i32 %2 } @@ -131,10 +138,13 @@ define float @indirect_call_float_void(float ()* %addr) { ; ALL-LABEL: indirect_call_float_void: ; ALL: move $25, $4 -; ALL: jalr $25 +; NOT-R6C: jalr $25 +; R6C: jalrc $25 + %1 = call float %addr() %2 = fadd float %1, 1.0 +; R6C: jrc $ra ret float %2 } @@ -178,7 +188,8 @@ define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr a ; ALL-LABEL: thunk_undef_double: ; O32: # implicit-def: %A2 ; O32: # implicit-def: %A3 -; ALL: jr $25 +; ALL: jr $25 + tail call void @undef_double(i32 undef, double undef) #8 ret void } @@ -190,10 +201,12 @@ define i32 @jal_only_allows_symbols() { ; ALL-NOT: {{jal }} ; ALL: addiu $[[TGT:[0-9]+]], $zero, 1234 ; ALL-NOT: {{jal }} -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] ; ALL-NOT: {{jal }} call void () inttoptr (i32 1234 to void ()*)() +; R6C: jrc $ra ret i32 0 } diff --git a/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/test/CodeGen/Mips/llvm-ir/indirectbr.ll index debfeb35b213..d982b570d7c2 100644 --- a/test/CodeGen/Mips/llvm-ir/indirectbr.ll +++ b/test/CodeGen/Mips/llvm-ir/indirectbr.ll @@ -1,30 +1,33 @@ ; Test all important variants of the unconditional 'br' instruction. -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6 -; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6 +; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C +; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6 define i32 @br(i8 *%addr) { ; ALL-LABEL: br: ; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR -; R6: jr $4 # <MCInst #{{[0-9]+}} JALR +; R6C: jrc $4 # <MCInst #{{[0-9]+}} JIC + ; ALL: $BB0_1: # %L1 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR ; ALL: addiu $2, $zero, 0 ; ALL: $BB0_2: # %L2 ; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR ; ALL: addiu $2, $zero, 1 entry: diff --git a/test/CodeGen/Mips/llvm-ir/lh_lhu.ll b/test/CodeGen/Mips/llvm-ir/lh_lhu.ll new file mode 100644 index 000000000000..fadcfdb0fb4f --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/lh_lhu.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s + +@us = global i16 0, align 2 + +define i32 @lhfunc() { +entry: +; CHECK-LABEL: lhfunc +; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}}) + %0 = load i16, i16* @us, align 2 + %conv = sext i16 %0 to i32 + ret i32 %conv +} + +define i16 @lhfunc_atomic() { +entry: +; CHECK-LABEL: lhfunc_atomic +; CHECK: lh $[[REG1:[0-9]+]], 0(${{[0-9]+}}) + %0 = load atomic i16, i16* @us acquire, align 2 + ret i16 %0 +} + +define i32 @lhufunc() { +entry: +; CHECK-LABEL: lhufunc +; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) + %0 = load i16, i16* @us, align 2 + %conv = zext i16 %0 to i32 + ret i32 %conv +} diff --git a/test/CodeGen/Mips/llvm-ir/load-atomic.ll b/test/CodeGen/Mips/llvm-ir/load-atomic.ll index a44b00bff586..baf9a74a2c54 100644 --- a/test/CodeGen/Mips/llvm-ir/load-atomic.ll +++ b/test/CodeGen/Mips/llvm-ir/load-atomic.ll @@ -1,9 +1,9 @@ ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL ; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 +; RUN: FileCheck %s -check-prefixes=ALL,M64 ; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 +; RUN: FileCheck %s -check-prefixes=ALL,M64 define i8 @load_i8(i8* %ptr) { ; ALL-LABEL: load_i8 diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll index 3a7029fa5b7a..10748b9c803a 100644 --- a/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -1,42 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=M2 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,M2 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6 define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) { entry: @@ -53,7 +44,9 @@ entry: ; ALL-LABEL: lshr_i8: ; ALL: srlv $[[T0:[0-9]+]], $4, $5 - ; ALL: andi $2, $[[T0]], 255 + ; GP32: andi $2, $[[T0]], 255 + ; GP64: andi $2, $[[T0]], 255 + ; MM: andi16 $2, $[[T0]], 255 %r = lshr i8 %a, %b ret i8 %r @@ -64,7 +57,9 @@ entry: ; ALL-LABEL: lshr_i16: ; ALL: srlv $[[T0:[0-9]+]], $4, $5 - ; ALL: andi $2, $[[T0]], 65535 + ; GP32: andi $2, $[[T0]], 65535 + ; GP64: andi $2, $[[T0]], 65535 + ; MM: andi16 $2, $[[T0]], 65535 %r = lshr i16 %a, %b ret i16 %r @@ -127,6 +122,29 @@ entry: ; GP64: dsrlv $2, $4, $5 + ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 + ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1 + ; MMR3: not16 $[[T2:[0-9]+]], $7 + ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR3: srlv $[[T5:[0-9]+]], $4, $7 + ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 + ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; MMR3: lui $[[T8:[0-9]+]], 0 + ; MMR3: movn $2, $[[T8]], $[[T6]] + + ; MMR6: srlv $[[T0:[0-9]+]], $5, $7 + ; MMR6: sll16 $[[T1:[0-9]+]], $4, 1 + ; MMR6: not16 $[[T2:[0-9]+]], $7 + ; MMR6: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 + ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] + ; MMR6: srlv $[[T7:[0-9]+]], $4, $7 + ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] + ; MMR6: or $3, $[[T8]], $[[T6]] + ; MMR6: seleqz $2, $[[T7]], $[[T5]] + %r = lshr i64 %a, %b ret i64 %r } @@ -182,6 +200,8 @@ entry: ; 64R6: jr $ra ; 64R6: seleqz $2, $[[T9]], $[[T7]] + ; MM: lw $25, %call16(__lshrti3)($2) + %r = lshr i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll index a7582805dd74..8d63e496806c 100644 --- a/test/CodeGen/Mips/llvm-ir/mul.ll +++ b/test/CodeGen/Mips/llvm-ir/mul.ll @@ -1,27 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=M2 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=32R1-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=32R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=M4 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=64R1-R5 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,M2,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1-R5,32R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R6,GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,M4,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=MM32,MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefixes=MM32,MM32R6 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \ +; RUN: FileCheck %s -check-prefix=64R6 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { entry: @@ -53,6 +59,10 @@ entry: ; 64R6: sll $[[T0]], $[[T0]], 31 ; 64R6: sra $2, $[[T0]], 31 + ; MM32: mul $[[T0:[0-9]+]], $4, $5 + ; MM32: sll $[[T0]], $[[T0]], 31 + ; MM32: sra $2, $[[T0]], 31 + %r = mul i1 %a, %b ret i1 %r } @@ -90,6 +100,10 @@ entry: ; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: seb $2, $[[T0]] + + ; MM32: mul $[[T0:[0-9]+]], $4, $5 + ; MM32: seb $2, $[[T0]] + %r = mul i8 %a, %b ret i8 %r } @@ -127,6 +141,10 @@ entry: ; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: seh $2, $[[T0]] + + ; MM32: mul $[[T0:[0-9]+]], $4, $5 + ; MM32: seh $2, $[[T0]] + %r = mul i16 %a, %b ret i16 %r } @@ -143,6 +161,9 @@ entry: ; 64R1-R5: mul $2, $4, $5 ; 64R6: mul $2, $4, $5 + + ; MM32: mul $2, $4, $5 + %r = mul i32 %a, %b ret i32 %r } @@ -169,12 +190,12 @@ entry: ; 32R1-R5: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]] ; 32R1-R5: addu $2, $[[T0]], $[[T1]] - ; 32R6: mul $[[T0:[0-9]+]], $5, $6 - ; 32R6: muhu $[[T1:[0-9]+]], $5, $7 - ; 32R6: addu $[[T0]], $[[T1]], $[[T0]] - ; 32R6: mul $[[T2:[0-9]+]], $4, $7 - ; 32R6: addu $2, $[[T0]], $[[T2]] - ; 32R6: mul $3, $5, $7 + ; 32R6-DAG: mul $3, $5, $7 + ; 32R6-DAG: mul $[[T0:[0-9]+]], $4, $7 + ; 32R6-DAG: mul $[[T1:[0-9]+]], $5, $6 + ; 32R6: muhu $[[T2:[0-9]+]], $5, $7 + ; 32R6: addu $[[T1]], $[[T2]], $[[T1]] + ; 32R6: addu $2, $[[T1]], $[[T0]] ; M4: dmult $4, $5 ; M4: mflo $2 @@ -184,6 +205,21 @@ entry: ; 64R6: dmul $2, $4, $5 + ; MM32R3: multu $[[T0:[0-9]+]], $7 + ; MM32R3: mflo $[[T1:[0-9]+]] + ; MM32R3: mfhi $[[T2:[0-9]+]] + ; MM32R3: mul $[[T3:[0-9]+]], $4, $7 + ; MM32R3: mul $[[T0]], $[[T0]], $6 + ; MM32R3: addu16 $[[T2]], $[[T2]], $[[T0]] + ; MM32R3: addu16 $2, $[[T2]], $[[T3]] + + ; MM32R6: mul $[[T0:[0-9]+]], $5, $7 + ; MM32R6: mul $[[T1:[0-9]+]], $4, $7 + ; MM32R6: mul $[[T2:[0-9]+]], $5, $6 + ; MM32R6: muhu $[[T3:[0-9]+]], $5, $7 + ; MM32R6: addu16 $[[T2]], $[[T3]], $[[T2]] + ; MM32R6: addu16 $2, $[[T2]], $[[T1]] + %r = mul i64 %a, %b ret i64 %r } @@ -204,12 +240,14 @@ entry: ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]] - ; 64R6: dmul $[[T0:[0-9]+]], $5, $6 - ; 64R6: dmuhu $[[T1:[0-9]+]], $5, $7 - ; 64R6: daddu $[[T2:[0-9]+]], $[[T1]], $[[T0]] - ; 64R6: dmul $[[T3:[0-9]+]], $4, $7 - ; 64R6: daddu $2, $[[T2]], $[[T3]] - ; 64R6: dmul $3, $5, $7 + ; 64R6-DAG: dmul $3, $5, $7 + ; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7 + ; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6 + ; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7 + ; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 64R6: daddu $2, $[[T1]], $[[T0]] + + ; MM32: lw $25, %call16(__multi3)($2) %r = mul i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/not.ll b/test/CodeGen/Mips/llvm-ir/not.ll new file mode 100644 index 000000000000..5f7374f6dfbb --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/not.ll @@ -0,0 +1,239 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM64 + +define signext i1 @not_i1(i1 signext %a) { +entry: +; ALL-LABEL: not_i1: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MM: not16 $2, $4 + + %r = xor i1 %a, -1 + ret i1 %r +} + +define signext i8 @not_i8(i8 signext %a) { +entry: +; ALL-LABEL: not_i8: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MM: not16 $2, $4 + + %r = xor i8 %a, -1 + ret i8 %r +} + +define signext i16 @not_i16(i16 signext %a) { +entry: +; ALL-LABEL: not_i16: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MM: not16 $2, $4 + + %r = xor i16 %a, -1 + ret i16 %r +} + +define signext i32 @not_i32(i32 signext %a) { +entry: +; ALL-LABEL: not_i32: + + ; GP32: not $2, $4 + + ; GP64: not $2, $4 + + ; MM: not16 $2, $4 + + %r = xor i32 %a, -1 + ret i32 %r +} + +define signext i64 @not_i64(i64 signext %a) { +entry: +; ALL-LABEL: not_i64: + + ; GP32: not $2, $4 + ; GP32: not $3, $5 + + ; GP64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; GP64: xor $2, $4, $[[T0]] + + ; MM32: not16 $2, $4 + ; MM32: not16 $3, $5 + + ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; MM64: xor $2, $4, $[[T0]] + + %r = xor i64 %a, -1 + ret i64 %r +} + +define signext i128 @not_i128(i128 signext %a) { +entry: +; ALL-LABEL: not_i128: + + ; GP32: not $2, $4 + ; GP32: not $3, $5 + ; GP32: not $4, $6 + ; GP32: not $5, $7 + + ; GP64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; GP64: xor $2, $4, $[[T0]] + ; GP64: xor $3, $5, $[[T0]] + + ; MM32: not16 $2, $4 + ; MM32: not16 $3, $5 + ; MM32: not16 $4, $6 + ; MM32: not16 $5, $7 + + ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; MM64: xor $2, $4, $[[T0]] + ; MM64: xor $3, $5, $[[T0]] + + %r = xor i128 %a, -1 + ret i128 %r +} + +define signext i1 @nor_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: nor_i1: + + ; ALL: nor $2, $5, $4 + + %or = or i1 %b, %a + %r = xor i1 %or, -1 + ret i1 %r +} + +define signext i8 @nor_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: nor_i8: + + ; ALL: nor $2, $5, $4 + + %or = or i8 %b, %a + %r = xor i8 %or, -1 + ret i8 %r +} + +define signext i16 @nor_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: nor_i16: + + ; ALL: nor $2, $5, $4 + + %or = or i16 %b, %a + %r = xor i16 %or, -1 + ret i16 %r +} + +define signext i32 @nor_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: nor_i32: + + ; GP32: nor $2, $5, $4 + + ; GP64: or $[[T0:[0-9]+]], $5, $4 + ; GP64: sll $[[T1:[0-9]+]], $[[T0]], 0 + ; GP64: not $2, $[[T1]] + + ; MM32: nor $2, $5, $4 + + ; MM64: or $[[T0:[0-9]+]], $5, $4 + ; MM64: sll $[[T1:[0-9]+]], $[[T0]], 0 + ; MM64: not16 $2, $[[T1]] + + %or = or i32 %b, %a + %r = xor i32 %or, -1 + ret i32 %r +} + + +define signext i64 @nor_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: nor_i64: + + ; GP32: nor $2, $6, $4 + ; GP32: nor $3, $7, $5 + + ; GP64: nor $2, $5, $4 + + ; MM32: nor $2, $6, $4 + ; MM32: nor $3, $7, $5 + + ; MM64: nor $2, $5, $4 + + %or = or i64 %b, %a + %r = xor i64 %or, -1 + ret i64 %r +} + +define signext i128 @nor_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: nor_i128: + + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: nor $2, $[[T2]], $4 + ; GP32: nor $3, $[[T1]], $5 + ; GP32: nor $4, $[[T0]], $6 + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: nor $5, $[[T3]], $7 + + ; GP64: nor $2, $6, $4 + ; GP64: nor $3, $7, $5 + + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: nor $2, $[[T1]], $4 + ; MM32: nor $3, $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: nor $4, $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: nor $5, $[[T3]], $7 + + ; MM64: nor $2, $6, $4 + ; MM64: nor $3, $7, $5 + + %or = or i128 %b, %a + %r = xor i128 %or, -1 + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll index 8509d6ce93f3..192e5de62301 100644 --- a/test/CodeGen/Mips/llvm-ir/or.ll +++ b/test/CodeGen/Mips/llvm-ir/or.ll @@ -1,35 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @or_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: or_i1: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MM: or16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = or i1 %a, %b ret i1 %r @@ -39,7 +37,12 @@ define signext i8 @or_i8(i8 signext %a, i8 signext %b) { entry: ; ALL-LABEL: or_i8: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MM: or16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = or i8 %a, %b ret i8 %r @@ -49,7 +52,12 @@ define signext i16 @or_i16(i16 signext %a, i16 signext %b) { entry: ; ALL-LABEL: or_i16: - ; ALL: or $2, $4, $5 + ; GP32: or $2, $4, $5 + + ; GP64: or $2, $4, $5 + + ; MM: or16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = or i16 %a, %b ret i16 %r @@ -59,12 +67,18 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: or_i32: - ; GP32: or $2, $4, $5 + ; GP32: or $2, $4, $5 - ; GP64: or $[[T0:[0-9]+]], $4, $5 + ; GP64: or $[[T0:[0-9]+]], $4, $5 ; FIXME: The sll instruction below is redundant. ; GP64: sll $2, $[[T0]], 0 + ; MM32: or16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: or $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = or i32 %a, %b ret i32 %r } @@ -73,10 +87,17 @@ define signext i64 @or_i64(i64 signext %a, i64 signext %b) { entry: ; ALL-LABEL: or_i64: - ; GP32: or $2, $4, $6 - ; GP32: or $3, $5, $7 + ; GP32: or $2, $4, $6 + ; GP32: or $3, $5, $7 + + ; GP64: or $2, $4, $5 - ; GP64: or $2, $4, $5 + ; MM32: or16 $[[T0:[0-9]+]], $6 + ; MM32: or16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: or $2, $4, $5 %r = or i64 %a, %b ret i64 %r @@ -86,18 +107,557 @@ define signext i128 @or_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: or_i128: - ; GP32: lw $[[T0:[0-9]+]], 24($sp) - ; GP32: lw $[[T1:[0-9]+]], 20($sp) - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: or $2, $4, $[[T2]] - ; GP32: or $3, $5, $[[T1]] - ; GP32: or $4, $6, $[[T0]] - ; GP32: lw $[[T3:[0-9]+]], 28($sp) - ; GP32: or $5, $7, $[[T3]] + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: or $2, $4, $[[T2]] + ; GP32: or $3, $5, $[[T1]] + ; GP32: or $4, $6, $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: or $5, $7, $[[T3]] + + ; GP64: or $2, $4, $6 + ; GP64: or $3, $5, $7 + + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: or16 $[[T1]], $4 + ; MM32: or16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: or16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: or16 $[[T3]], $7 - ; GP64: or $2, $4, $6 - ; GP64: or $3, $5, $7 + ; MM64: or $2, $4, $6 + ; MM64: or $3, $5, $7 %r = or i128 %a, %b ret i128 %r } + +define signext i1 @or_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_4: + + ; ALL: move $2, $4 + + %r = or i1 4, %b + ret i1 %r +} + +define signext i8 @or_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_4: + + ; ALL: ori $2, $4, 4 + + %r = or i8 4, %b + ret i8 %r +} + +define signext i16 @or_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_4: + + ; ALL: ori $2, $4, 4 + + %r = or i16 4, %b + ret i16 %r +} + +define signext i32 @or_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_4: + + ; ALL: ori $2, $4, 4 + + %r = or i32 4, %b + ret i32 %r +} + +define signext i64 @or_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_4: + + ; GP32: ori $3, $5, 4 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 4 + + ; MM32: ori $3, $5, 4 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 4 + + %r = or i64 4, %b + ret i64 %r +} + +define signext i128 @or_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_4: + + ; GP32: ori $[[T0:[0-9]+]], $7, 4 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 4 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 4 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 4 + ; MM64: move $2, $4 + + %r = or i128 4, %b + ret i128 %r +} + +define signext i1 @or_i1_31(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_31: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MM: li16 $2, -1 + + %r = or i1 31, %b + ret i1 %r +} + +define signext i8 @or_i8_31(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_31: + + ; ALL: ori $2, $4, 31 + + %r = or i8 31, %b + ret i8 %r +} + +define signext i16 @or_i16_31(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_31: + + ; ALL: ori $2, $4, 31 + + %r = or i16 31, %b + ret i16 %r +} + +define signext i32 @or_i32_31(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_31: + + ; ALL: ori $2, $4, 31 + + %r = or i32 31, %b + ret i32 %r +} + +define signext i64 @or_i64_31(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_31: + + ; GP32: ori $3, $5, 31 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 31 + + ; MM32: ori $3, $5, 31 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 31 + + %r = or i64 31, %b + ret i64 %r +} + +define signext i128 @or_i128_31(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_31: + + ; GP32: ori $[[T0:[0-9]+]], $7, 31 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 31 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 31 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 31 + ; MM64: move $2, $4 + + %r = or i128 31, %b + ret i128 %r +} + +define signext i1 @or_i1_255(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_255: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MM: li16 $2, -1 + + %r = or i1 255, %b + ret i1 %r +} + +define signext i8 @or_i8_255(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_255: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MM: li16 $2, -1 + + %r = or i8 255, %b + ret i8 %r +} + +define signext i16 @or_i16_255(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_255: + + ; ALL: ori $2, $4, 255 + + %r = or i16 255, %b + ret i16 %r +} + +define signext i32 @or_i32_255(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_255: + + ; ALL: ori $2, $4, 255 + + %r = or i32 255, %b + ret i32 %r +} + +define signext i64 @or_i64_255(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_255: + + ; GP32: ori $3, $5, 255 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 255 + + ; MM32: ori $3, $5, 255 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 255 + + %r = or i64 255, %b + ret i64 %r +} + +define signext i128 @or_i128_255(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_255: + + ; GP32: ori $[[T0:[0-9]+]], $7, 255 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 255 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 255 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 255 + ; MM64: move $2, $4 + + %r = or i128 255, %b + ret i128 %r +} + +define signext i1 @or_i1_32768(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_32768: + + ; ALL: move $2, $4 + + %r = or i1 32768, %b + ret i1 %r +} + +define signext i8 @or_i8_32768(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_32768: + + ; ALL: move $2, $4 + + %r = or i8 32768, %b + ret i8 %r +} + +define signext i16 @or_i16_32768(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_32768: + + ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP32: or $2, $4, $[[T0]] + + ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP64: or $2, $4, $[[T0]] + + ; MM: addiu $2, $zero, -32768 + ; MM: or16 $2, $4 + + %r = or i16 32768, %b + ret i16 %r +} + +define signext i32 @or_i32_32768(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_32768: + + ; ALL: ori $2, $4, 32768 + + %r = or i32 32768, %b + ret i32 %r +} + +define signext i64 @or_i64_32768(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_32768: + + ; GP32: ori $3, $5, 32768 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 32768 + + ; MM32: ori $3, $5, 32768 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 32768 + + %r = or i64 32768, %b + ret i64 %r +} + +define signext i128 @or_i128_32768(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_32768: + + ; GP32: ori $[[T0:[0-9]+]], $7, 32768 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 32768 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 32768 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 32768 + ; MM64: move $2, $4 + + %r = or i128 32768, %b + ret i128 %r +} + +define signext i1 @or_i1_65(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_65: + + ; GP32: addiu $2, $zero, -1 + + ; GP64: addiu $2, $zero, -1 + + ; MM: li16 $2, -1 + + %r = or i1 65, %b + ret i1 %r +} + +define signext i8 @or_i8_65(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_65: + + ; ALL: ori $2, $4, 65 + + %r = or i8 65, %b + ret i8 %r +} + +define signext i16 @or_i16_65(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_65: + + ; ALL: ori $2, $4, 65 + + %r = or i16 65, %b + ret i16 %r +} + +define signext i32 @or_i32_65(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_65: + + ; ALL: ori $2, $4, 65 + + %r = or i32 65, %b + ret i32 %r +} + +define signext i64 @or_i64_65(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_65: + + ; GP32: ori $3, $5, 65 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 65 + + ; MM32: ori $3, $5, 65 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 65 + + %r = or i64 65, %b + ret i64 %r +} + +define signext i128 @or_i128_65(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_65: + + ; GP32: ori $[[T0:[0-9]+]], $7, 65 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 65 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 65 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 65 + ; MM64: move $2, $4 + + %r = or i128 65, %b + ret i128 %r +} + +define signext i1 @or_i1_256(i1 signext %b) { +entry: +; ALL-LABEL: or_i1_256: + + ; ALL: move $2, $4 + + %r = or i1 256, %b + ret i1 %r +} + +define signext i8 @or_i8_256(i8 signext %b) { +entry: +; ALL-LABEL: or_i8_256: + + ; ALL: move $2, $4 + + %r = or i8 256, %b + ret i8 %r +} + +define signext i16 @or_i16_256(i16 signext %b) { +entry: +; ALL-LABEL: or_i16_256: + + ; ALL: ori $2, $4, 256 + + %r = or i16 256, %b + ret i16 %r +} + +define signext i32 @or_i32_256(i32 signext %b) { +entry: +; ALL-LABEL: or_i32_256: + + ; ALL: ori $2, $4, 256 + + %r = or i32 256, %b + ret i32 %r +} + +define signext i64 @or_i64_256(i64 signext %b) { +entry: +; ALL-LABEL: or_i64_256: + + ; GP32: ori $3, $5, 256 + ; GP32: move $2, $4 + + ; GP64: ori $2, $4, 256 + + ; MM32: ori $3, $5, 256 + ; MM32: move $2, $4 + + ; MM64: ori $2, $4, 256 + + %r = or i64 256, %b + ret i64 %r +} + +define signext i128 @or_i128_256(i128 signext %b) { +entry: +; ALL-LABEL: or_i128_256: + + ; GP32: ori $[[T0:[0-9]+]], $7, 256 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: ori $3, $5, 256 + ; GP64: move $2, $4 + + ; MM32: ori $[[T0:[0-9]+]], $7, 256 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: ori $3, $5, 256 + ; MM64: move $2, $4 + + %r = or i128 256, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/ret.ll b/test/CodeGen/Mips/llvm-ir/ret.ll index 0561c24219ce..9be80dc200fa 100644 --- a/test/CodeGen/Mips/llvm-ir/ret.ll +++ b/test/CodeGen/Mips/llvm-ir/ret.ll @@ -7,23 +7,30 @@ ; affects it and it's undesirable to repeat the non-pointer returns for each ; relocation model. -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6 -; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6 +; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,NO-MTHC1,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C +; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6 + +; FIXME: for the test ret_double_0x0, the delay slot of jr cannot be filled +; as mthc1 has unmodeled side effects. This is an artifact of our backend. +; Force the delay slot filler off to check that the sequence jr $ra; nop is +; turned into jic 0, $ra. + +; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C define void @ret_void() { ; ALL-LABEL: ret_void: ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC ret void } @@ -173,6 +180,7 @@ define float @ret_float_0x3() { ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC ; float constants are written as double constants ret float 0x36b8000000000000 @@ -191,6 +199,7 @@ define double @ret_double_0x0() { ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC ret double 0x0000000000000000 } @@ -204,6 +213,7 @@ define double @ret_double_0x3() { ; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR +; R6C-DAG: jrc $ra # <MCInst #{{[0-9]+}} JIC ret double 0x0000000000000003 } diff --git a/test/CodeGen/Mips/llvm-ir/sdiv.ll b/test/CodeGen/Mips/llvm-ir/sdiv.ll index 929ee88bb7f7..2d2b8ff12c04 100644 --- a/test/CodeGen/Mips/llvm-ir/sdiv.ll +++ b/test/CodeGen/Mips/llvm-ir/sdiv.ll @@ -1,29 +1,37 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=R6 -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R6,GP32 + +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,NOT-R2-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,R2-R5,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R6,64R6 + +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR3,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) { entry: @@ -42,6 +50,17 @@ entry: ; R6: sll $[[T1:[0-9]+]], $[[T0]], 31 ; R6: sra $2, $[[T1]], 31 + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $[[T0:[0-9]+]] + ; MMR3: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR3: sra $2, $[[T1]], 31 + + ; MMR6: div $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR6: sra $2, $[[T1]], 31 + %r = sdiv i1 %a, %b ret i1 %r } @@ -68,6 +87,15 @@ entry: ; FIXME: This instruction is redundant. ; R6: seb $2, $[[T0]] + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $[[T0:[0-9]+]] + ; MMR3: seb $2, $[[T0]] + + ; MMR6: div $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: seb $2, $[[T0]] + %r = sdiv i8 %a, %b ret i8 %r } @@ -94,6 +122,15 @@ entry: ; FIXME: This is instruction is redundant since div is signed. ; R6: seh $2, $[[T0]] + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $[[T0:[0-9]+]] + ; MMR3: seh $2, $[[T0]] + + ; MMR6: div $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: seh $2, $[[T0]] + %r = sdiv i16 %a, %b ret i16 %r } @@ -109,6 +146,13 @@ entry: ; R6: div $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $2 + + ; MMR6: div $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = sdiv i32 %a, %b ret i32 %r } @@ -126,6 +170,11 @@ entry: ; 64R6: ddiv $2, $4, $5 ; 64R6: teq $5, $zero, 7 + ; MM32: lw $25, %call16(__divdi3)($2) + + ; MM64: ddiv $2, $4, $5 + ; MM64: teq $5, $zero, 7 + %r = sdiv i64 %a, %b ret i64 %r } @@ -134,11 +183,15 @@ define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: sdiv_i128: - ; GP32: lw $25, %call16(__divti3)($gp) + ; GP32: lw $25, %call16(__divti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) + ; 64R6: ld $25, %call16(__divti3)($gp) + + ; MM32: lw $25, %call16(__divti3)($2) - ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) - ; 64R6: ld $25, %call16(__divti3)($gp) + ; MM64: ld $25, %call16(__divti3)($2) - %r = sdiv i128 %a, %b - ret i128 %r + %r = sdiv i128 %a, %b + ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/test/CodeGen/Mips/llvm-ir/select-dbl.ll new file mode 100644 index 000000000000..1ca5b4e054ba --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/select-dbl.ll @@ -0,0 +1,358 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M2,M2-M3 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL-32,32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M3,M2-M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL-64,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM32R6,SEL-32 + +define double @tst_select_i1_double(i1 signext %s, double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_i1_double: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: ldc1 $f0, 16($sp) + ; M2: jr $ra + ; M2: nop + ; M2: $[[BB0]]: + ; M2: mtc1 $7, $f0 + ; M2: jr $ra + ; M2: mtc1 $6, $f1 + + ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]] + ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}} + ; CMOV-32R2-R5: mthc1 $6, $[[F0]] + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: ldc1 $f0, 16($sp) + ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]] + + ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]] + ; SEL-32: mthc1 $6, $[[F0]] + ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp) + ; SEL-32: mtc1 $4, $f0 + ; SEL-32: sel.d $f0, $[[F1]], $[[F0]] + + ; M3: andi $[[T0:[0-9]+]], $4, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: mov.d $f13, $f14 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: mov.d $f0, $f13 + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn.d $f14, $f13, $[[T0]] + ; CMOV-64: mov.d $f0, $f14 + + ; SEL-64: mtc1 $4, $f0 + ; SEL-64: sel.d $f0, $f14, $f13 + + ; MM32R3: mtc1 $7, $[[F0:f[0-9]+]] + ; MM32R3: mthc1 $6, $[[F0]] + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: ldc1 $f0, 16($sp) + ; MM32R3: movn.d $f0, $[[F0]], $[[T0]] + + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_i1_double_reordered(double %x, double %y, + i1 signext %s) { +entry: + ; ALL-LABEL: tst_select_i1_double_reordered: + + ; M2: lw $[[T0:[0-9]+]], 16($sp) + ; M2: andi $[[T1:[0-9]+]], $[[T0]], 1 + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.d $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.d $f0, $f12 + + ; CMOV-32: lw $[[T0:[0-9]+]], 16($sp) + ; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1 + ; CMOV-32: movn.d $f14, $f12, $[[T1]] + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: lw $[[T0:[0-9]+]], 16($sp) + ; SEL-32: mtc1 $[[T0]], $f0 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; M3: andi $[[T0:[0-9]+]], $6, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: mov.d $f12, $f13 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: mov.d $f0, $f12 + + ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-64: movn.d $f13, $f12, $[[T0]] + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: mtc1 $6, $f0 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: lw $[[T0:[0-9]+]], 16($sp) + ; MM32R3: andi16 $[[T1:[0-9]+]], $[[T0:[0-9]+]], 1 + ; MM32R3: movn.d $f14, $f12, $[[T1]] + ; MM32R3: mov.d $f0, $f14 + + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_olt_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_olt_double: + + ; M2: c.olt.d $f12, $f14 + ; M3: c.olt.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.olt.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.lt.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.olt.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.lt.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.olt.d $f12, $f14 + ; MM32R3: movt.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp olt double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_ole_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ole_double: + + ; M2: c.ole.d $f12, $f14 + ; M3: c.ole.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ole.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.le.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ole.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.le.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ole.d $f12, $f14 + ; MM32R3: movt.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp ole double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_ogt_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ogt_double: + + ; M2: c.ule.d $f12, $f14 + ; M3: c.ule.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ule.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.lt.d $f0, $f14, $f12 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ule.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.lt.d $f0, $f13, $f12 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ule.d $f12, $f14 + ; MM32R3: movf.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp ogt double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_oge_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oge_double: + + ; M2: c.ult.d $f12, $f14 + ; M3: c.ult.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ult.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.le.d $f0, $f14, $f12 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ult.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.le.d $f0, $f13, $f12 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ult.d $f12, $f14 + ; MM32R3: movf.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp oge double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_oeq_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oeq_double: + + ; M2: c.eq.d $f12, $f14 + ; M3: c.eq.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.eq.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.eq.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.eq.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.eq.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.eq.d $f12, $f14 + ; MM32R3: movt.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp oeq double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_one_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_one_double: + + ; M2: c.ueq.d $f12, $f14 + ; M3: c.ueq.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ueq.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.ueq.d $f0, $f12, $f14 + ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: not $[[T0]], $[[T0]] + ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ueq.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.ueq.d $f0, $f12, $f13 + ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: not $[[T0]], $[[T0]] + ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: sel.d $f0, $f13, $f12 + + ; MM32R3: c.ueq.d $f12, $f14 + ; MM32R3: movf.d $f14, $f12, $fcc0 + ; MM32R3: mov.d $f0, $f14 + + %s = fcmp one double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} diff --git a/test/CodeGen/Mips/llvm-ir/select-flt.ll b/test/CodeGen/Mips/llvm-ir/select-flt.ll new file mode 100644 index 000000000000..6a0334da4833 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/select-flt.ll @@ -0,0 +1,335 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M2,M2-M3 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL-32,32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M3,M2-M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL-64,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM32R6,SEL-32 + +define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_i1_float: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: jr $ra + ; M2: mtc1 $6, $f0 + ; M3: mov.s $f13, $f14 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2: mtc1 $5, $f0 + ; M3: mov.s $f0, $f13 + + ; CMOV-32: mtc1 $6, $f0 + ; CMOV-32: mtc1 $5, $f1 + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: movn.s $f0, $f1, $[[T0]] + + ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]] + ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]] + ; SEL-32: mtc1 $4, $f0 + ; SEL-32: sel.s $f0, $[[F1]], $[[F0]] + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn.s $f14, $f13, $[[T0]] + ; CMOV-64: mov.s $f0, $f14 + + ; SEL-64: mtc1 $4, $f0 + ; SEL-64: sel.s $f0, $f14, $f13 + + ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]] + ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]] + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn.s $f0, $[[F1]], $[[T0]] + + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_i1_float_reordered(float %x, float %y, + i1 signext %s) { +entry: + ; ALL-LABEL: tst_select_i1_float_reordered: + + ; M2-M3: andi $[[T0:[0-9]+]], $6, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-32: movn.s $f14, $f12, $[[T0]] + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: mtc1 $6, $f0 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-64: movn.s $f13, $f12, $[[T0]] + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: mtc1 $6, $f0 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: andi16 $[[T0:[0-9]+]], $6, 1 + ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]] + ; MM32R3: mov.s $f0, $[[F0]] + + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_olt_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_olt_float: + + ; M2: c.olt.s $f12, $f14 + ; M3: c.olt.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.olt.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.lt.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.olt.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.lt.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.olt.s $f12, $f14 + ; MM32R3: movt.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp olt float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_ole_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ole_float: + + ; M2: c.ole.s $f12, $f14 + ; M3: c.ole.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ole.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.le.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ole.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.le.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ole.s $f12, $f14 + ; MM32R3: movt.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp ole float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_ogt_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ogt_float: + + ; M2: c.ule.s $f12, $f14 + ; M3: c.ule.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ule.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.lt.s $f0, $f14, $f12 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ule.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.lt.s $f0, $f13, $f12 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ule.s $f12, $f14 + ; MM32R3: movf.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp ogt float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_oge_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oge_float: + + ; M2: c.ult.s $f12, $f14 + ; M3: c.ult.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ult.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.le.s $f0, $f14, $f12 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ult.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.le.s $f0, $f13, $f12 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ult.s $f12, $f14 + ; MM32R3: movf.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp oge float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_oeq_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oeq_float: + + ; M2: c.eq.s $f12, $f14 + ; M3: c.eq.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.eq.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.eq.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.eq.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.eq.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.eq.s $f12, $f14 + ; MM32R3: movt.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp oeq float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_one_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_one_float: + + ; M2: c.ueq.s $f12, $f14 + ; M3: c.ueq.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ueq.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.ueq.s $f0, $f12, $f14 + ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: not $[[T0]], $[[T0]] + ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ueq.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.ueq.s $f0, $f12, $f13 + ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: not $[[T0]], $[[T0]] + ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: sel.s $f0, $f13, $f12 + + ; MM32R3: c.ueq.s $f12, $f14 + ; MM32R3: movf.s $f14, $f12, $fcc0 + ; MM32R3: mov.s $f0, $f14 + + %s = fcmp one float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} diff --git a/test/CodeGen/Mips/llvm-ir/select-int.ll b/test/CodeGen/Mips/llvm-ir/select-int.ll new file mode 100644 index 000000000000..e8f78ffdcb6a --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/select-int.ll @@ -0,0 +1,270 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M2,M2-M3 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL,SEL-32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,M3,M2-M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefixes=ALL,CMOV,CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefixes=ALL,SEL,SEL-64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32R6 + +define signext i1 @tst_select_i1_i1(i1 signext %s, + i1 signext %x, i1 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i1: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: move $2, $[[T1]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; MMR6: or $2, $[[T2]], $[[T1]] + + %r = select i1 %s, i1 %x, i1 %y + ret i1 %r +} + +define signext i8 @tst_select_i1_i8(i1 signext %s, + i8 signext %x, i8 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i8: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: move $2, $[[T1]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; MMR6: or $2, $[[T2]], $[[T1]] + + %r = select i1 %s, i8 %x, i8 %y + ret i8 %r +} + +define signext i32 @tst_select_i1_i32(i1 signext %s, + i32 signext %x, i32 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i32: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: move $2, $[[T1]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; MMR6: or $2, $[[T2]], $[[T1]] + + %r = select i1 %s, i32 %x, i32 %y + ret i32 %r +} + +define signext i64 @tst_select_i1_i64(i1 signext %s, + i64 signext %x, i64 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i64: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: lw $[[T1:[0-9]+]], 16($sp) + ; M2: $[[BB0]]: + ; FIXME: This branch is redundant + ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]] + ; M2: nop + ; M2: lw $[[T2:[0-9]+]], 20($sp) + ; M2: $[[BB1]]: + ; M2: move $2, $[[T1]] + ; M2: jr $ra + ; M2: move $3, $[[T2]] + + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: lw $2, 16($sp) + ; CMOV-32: movn $2, $6, $[[T0]] + ; CMOV-32: lw $3, 20($sp) + ; CMOV-32: movn $3, $7, $[[T0]] + + ; SEL-32: andi $[[T0:[0-9]+]], $4, 1 + ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL-32: lw $[[T2:[0-9]+]], 16($sp) + ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]] + ; SEL-32: or $2, $[[T1]], $[[T3]] + ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]] + ; SEL-32: lw $[[T5:[0-9]+]], 20($sp) + ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]] + ; SEL-32: or $3, $[[T4]], $[[T6]] + + ; M3: andi $[[T0:[0-9]+]], $4, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: move $5, $6 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: move $2, $5 + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn $6, $5, $[[T0]] + ; CMOV-64: move $2, $6 + + ; SEL-64: andi $[[T0:[0-9]+]], $4, 1 + ; FIXME: This shift is redundant + ; SEL-64: sll $[[T0]], $[[T0]], 0 + ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL-64: selnez $[[T0]], $5, $[[T0]] + ; SEL-64: or $2, $[[T0]], $[[T1]] + + ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: lw $2, 16($sp) + ; MM32R3: movn $2, $6, $[[T0]] + ; MM32R3: lw $3, 20($sp) + ; MM32R3: movn $3, $7, $[[T0]] + + ; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R6: lw $[[T1:[0-9]+]], 16($sp) + ; MM32R6: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MM32R6: selnez $[[T3:[0-9]+]], $6, $[[T0]] + ; MM32R6: or $2, $[[T3]], $[[T2]] + ; MM32R6: lw $[[T4:[0-9]+]], 20($sp) + ; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]] + ; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]] + ; MM32R6: or $3, $[[T6]], $[[T5]] + + %r = select i1 %s, i64 %x, i64 %y + ret i64 %r +} + +define i8* @tst_select_word_cst(i8* %a, i8* %b) { + ; ALL-LABEL: tst_select_word_cst: + + ; M2: addiu $[[T0:[0-9]+]], $zero, -1 + ; M2: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; M2: bnez $[[T2]], $[[BB0:BB[0-9_]+]] + ; M2: addiu $2, $zero, 0 + ; M2: move $2, $4 + ; M2: $[[BB0]]: + ; M2: jr $ra + + ; M3: daddiu $[[T0:[0-9]+]], $zero, -1 + ; M3: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; M3: bnez $[[T2]], $[[BB0:BB[0-9_]+]] + ; M3: daddiu $2, $zero, 0 + ; M3: move $2, $4 + ; M3: $[[BB0]]: + ; M3: jr $ra + + ; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1 + ; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]] + ; CMOV-32: jr $ra + ; CMOV-32: move $2, $[[T2]] + + ; SEL-32: addiu $[[T0:[0-9]+]], $zero, -1 + ; SEL-32: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; SEL-32: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; SEL-32: jr $ra + ; SEL-32: seleqz $2, $4, $[[T2]] + + ; CMOV-64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; CMOV-64: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; CMOV-64: movn $[[T2:[0-9]+]], $zero, $[[T1]] + ; CMOV-64: move $2, $[[T2]] + + ; SEL-64: daddiu $[[T0:[0-9]+]], $zero, -1 + ; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; FIXME: This shift is redundant. + ; SEL-64: sll $[[T2]], $[[T2]], 0 + ; SEL-64: seleqz $2, $4, $[[T2]] + + ; MM32R3: li16 $[[T0:[0-9]+]], -1 + ; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R3: lui $[[T2:[0-9]+]], 0 + ; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; MM32R3: move $2, $[[T3]] + + ; MM32R6: li16 $[[T0:[0-9]+]], -1 + ; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]] + ; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]] + ; MM32R6: seleqz $2, $4, $[[T2]] + + %cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*) + %r = select i1 %cmp, i8* %a, i8* null + ret i8* %r +} diff --git a/test/CodeGen/Mips/llvm-ir/select.ll b/test/CodeGen/Mips/llvm-ir/select.ll deleted file mode 100644 index f17670adca33..000000000000 --- a/test/CodeGen/Mips/llvm-ir/select.ll +++ /dev/null @@ -1,712 +0,0 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV \ -; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV \ -; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV \ -; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV \ -; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64 - -define signext i1 @tst_select_i1_i1(i1 signext %s, - i1 signext %x, i1 signext %y) { -entry: - ; ALL-LABEL: tst_select_i1_i1: - - ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2-M3: move $5, $6 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: move $2, $5 - - ; CMOV: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV: movn $6, $5, $[[T0]] - ; CMOV: move $2, $6 - - ; SEL: andi $[[T0:[0-9]+]], $4, 1 - ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] - ; SEL: or $2, $[[T2]], $[[T1]] - %r = select i1 %s, i1 %x, i1 %y - ret i1 %r -} - -define signext i8 @tst_select_i1_i8(i1 signext %s, - i8 signext %x, i8 signext %y) { -entry: - ; ALL-LABEL: tst_select_i1_i8: - - ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2-M3: move $5, $6 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: move $2, $5 - - ; CMOV: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV: movn $6, $5, $[[T0]] - ; CMOV: move $2, $6 - - ; SEL: andi $[[T0:[0-9]+]], $4, 1 - ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] - ; SEL: or $2, $[[T2]], $[[T1]] - %r = select i1 %s, i8 %x, i8 %y - ret i8 %r -} - -define signext i32 @tst_select_i1_i32(i1 signext %s, - i32 signext %x, i32 signext %y) { -entry: - ; ALL-LABEL: tst_select_i1_i32: - - ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2-M3: move $5, $6 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: move $2, $5 - - ; CMOV: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV: movn $6, $5, $[[T0]] - ; CMOV: move $2, $6 - - ; SEL: andi $[[T0:[0-9]+]], $4, 1 - ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] - ; SEL: or $2, $[[T2]], $[[T1]] - %r = select i1 %s, i32 %x, i32 %y - ret i32 %r -} - -define signext i64 @tst_select_i1_i64(i1 signext %s, - i64 signext %x, i64 signext %y) { -entry: - ; ALL-LABEL: tst_select_i1_i64: - - ; M2: andi $[[T0:[0-9]+]], $4, 1 - ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2: nop - ; M2: lw $[[T1:[0-9]+]], 16($sp) - ; M2: $[[BB0]]: - ; FIXME: This branch is redundant - ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]] - ; M2: nop - ; M2: lw $[[T2:[0-9]+]], 20($sp) - ; M2: $[[BB1]]: - ; M2: move $2, $[[T1]] - ; M2: jr $ra - ; M2: move $3, $[[T2]] - - ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-32: lw $2, 16($sp) - ; CMOV-32: movn $2, $6, $[[T0]] - ; CMOV-32: lw $3, 20($sp) - ; CMOV-32: movn $3, $7, $[[T0]] - - ; SEL-32: andi $[[T0:[0-9]+]], $4, 1 - ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL-32: lw $[[T2:[0-9]+]], 16($sp) - ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]] - ; SEL-32: or $2, $[[T1]], $[[T3]] - ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]] - ; SEL-32: lw $[[T5:[0-9]+]], 20($sp) - ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]] - ; SEL-32: or $3, $[[T4]], $[[T6]] - - ; M3: andi $[[T0:[0-9]+]], $4, 1 - ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M3: nop - ; M3: move $5, $6 - ; M3: $[[BB0]]: - ; M3: jr $ra - ; M3: move $2, $5 - - ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-64: movn $6, $5, $[[T0]] - ; CMOV-64: move $2, $6 - - ; SEL-64: andi $[[T0:[0-9]+]], $4, 1 - ; FIXME: This shift is redundant - ; SEL-64: sll $[[T0]], $[[T0]], 0 - ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL-64: selnez $[[T0]], $5, $[[T0]] - ; SEL-64: or $2, $[[T0]], $[[T1]] - %r = select i1 %s, i64 %x, i64 %y - ret i64 %r -} - -define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_i1_float: - - ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: jr $ra - ; M2: mtc1 $6, $f0 - ; M3: mov.s $f13, $f14 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2: mtc1 $5, $f0 - ; M3: mov.s $f0, $f13 - - ; CMOV-32: mtc1 $6, $f0 - ; CMOV-32: mtc1 $5, $f1 - ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-32: movn.s $f0, $f1, $[[T0]] - - ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]] - ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]] - ; SEL-32: mtc1 $4, $f0 - ; SEL-32: sel.s $f0, $[[F1]], $[[F0]] - - ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-64: movn.s $f14, $f13, $[[T0]] - ; CMOV-64: mov.s $f0, $f14 - - ; SEL-64: mtc1 $4, $f0 - ; SEL-64: sel.s $f0, $f14, $f13 - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_i1_float_reordered(float %x, float %y, - i1 signext %s) { -entry: - ; ALL-LABEL: tst_select_i1_float_reordered: - - ; M2-M3: andi $[[T0:[0-9]+]], $6, 1 - ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1 - ; CMOV-32: movn.s $f14, $f12, $[[T0]] - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: mtc1 $6, $f0 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 - ; CMOV-64: movn.s $f13, $f12, $[[T0]] - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: mtc1 $6, $f0 - ; SEL-64: sel.s $f0, $f13, $f12 - %r = select i1 %s, float %x, float %y - ret float %r -} - -define double @tst_select_i1_double(i1 signext %s, double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_i1_double: - - ; M2: andi $[[T0:[0-9]+]], $4, 1 - ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M2: nop - ; M2: ldc1 $f0, 16($sp) - ; M2: jr $ra - ; M2: nop - ; M2: $[[BB0]]: - ; M2: mtc1 $7, $f0 - ; M2: jr $ra - ; M2: mtc1 $6, $f1 - - ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]] - ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}} - ; CMOV-32R2-R5: mthc1 $6, $[[F0]] - ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-32: ldc1 $f0, 16($sp) - ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]] - - ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]] - ; SEL-32: mthc1 $6, $[[F0]] - ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp) - ; SEL-32: mtc1 $4, $f0 - ; SEL-32: sel.d $f0, $[[F1]], $[[F0]] - - ; M3: andi $[[T0:[0-9]+]], $4, 1 - ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M3: nop - ; M3: mov.d $f13, $f14 - ; M3: $[[BB0]]: - ; M3: jr $ra - ; M3: mov.d $f0, $f13 - - ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 - ; CMOV-64: movn.d $f14, $f13, $[[T0]] - ; CMOV-64: mov.d $f0, $f14 - - ; SEL-64: mtc1 $4, $f0 - ; SEL-64: sel.d $f0, $f14, $f13 - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_i1_double_reordered(double %x, double %y, - i1 signext %s) { -entry: - ; ALL-LABEL: tst_select_i1_double_reordered: - - ; M2: lw $[[T0:[0-9]+]], 16($sp) - ; M2: andi $[[T1:[0-9]+]], $[[T0]], 1 - ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] - ; M2: nop - ; M2: mov.d $f12, $f14 - ; M2: $[[BB0]]: - ; M2: jr $ra - ; M2: mov.d $f0, $f12 - - ; CMOV-32: lw $[[T0:[0-9]+]], 16($sp) - ; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1 - ; CMOV-32: movn.d $f14, $f12, $[[T1]] - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: lw $[[T0:[0-9]+]], 16($sp) - ; SEL-32: mtc1 $[[T0]], $f0 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; M3: andi $[[T0:[0-9]+]], $6, 1 - ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] - ; M3: nop - ; M3: mov.d $f12, $f13 - ; M3: $[[BB0]]: - ; M3: jr $ra - ; M3: mov.d $f0, $f12 - - ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 - ; CMOV-64: movn.d $f13, $f12, $[[T0]] - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: mtc1 $6, $f0 - ; SEL-64: sel.d $f0, $f13, $f12 - %r = select i1 %s, double %x, double %y - ret double %r -} - -define float @tst_select_fcmp_olt_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_olt_float: - - ; M2: c.olt.s $f12, $f14 - ; M3: c.olt.s $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.olt.s $f12, $f14 - ; CMOV-32: movt.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.lt.s $f0, $f12, $f14 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.olt.s $f12, $f13 - ; CMOV-64: movt.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.lt.s $f0, $f12, $f13 - ; SEL-64: sel.s $f0, $f13, $f12 - %s = fcmp olt float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_fcmp_ole_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_ole_float: - - ; M2: c.ole.s $f12, $f14 - ; M3: c.ole.s $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.ole.s $f12, $f14 - ; CMOV-32: movt.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.le.s $f0, $f12, $f14 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.ole.s $f12, $f13 - ; CMOV-64: movt.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.le.s $f0, $f12, $f13 - ; SEL-64: sel.s $f0, $f13, $f12 - %s = fcmp ole float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_fcmp_ogt_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_ogt_float: - - ; M2: c.ule.s $f12, $f14 - ; M3: c.ule.s $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.ule.s $f12, $f14 - ; CMOV-32: movf.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.lt.s $f0, $f14, $f12 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.ule.s $f12, $f13 - ; CMOV-64: movf.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.lt.s $f0, $f13, $f12 - ; SEL-64: sel.s $f0, $f13, $f12 - %s = fcmp ogt float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_fcmp_oge_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_oge_float: - - ; M2: c.ult.s $f12, $f14 - ; M3: c.ult.s $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.ult.s $f12, $f14 - ; CMOV-32: movf.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.le.s $f0, $f14, $f12 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.ult.s $f12, $f13 - ; CMOV-64: movf.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.le.s $f0, $f13, $f12 - ; SEL-64: sel.s $f0, $f13, $f12 - %s = fcmp oge float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_fcmp_oeq_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_oeq_float: - - ; M2: c.eq.s $f12, $f14 - ; M3: c.eq.s $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.eq.s $f12, $f14 - ; CMOV-32: movt.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.eq.s $f0, $f12, $f14 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.eq.s $f12, $f13 - ; CMOV-64: movt.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.eq.s $f0, $f12, $f13 - ; SEL-64: sel.s $f0, $f13, $f12 - %s = fcmp oeq float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define float @tst_select_fcmp_one_float(float %x, float %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_one_float: - - ; M2: c.ueq.s $f12, $f14 - ; M3: c.ueq.s $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.s $f12, $f14 - ; M3: mov.s $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.s $f0, $f12 - - ; CMOV-32: c.ueq.s $f12, $f14 - ; CMOV-32: movf.s $f14, $f12, $fcc0 - ; CMOV-32: mov.s $f0, $f14 - - ; SEL-32: cmp.ueq.s $f0, $f12, $f14 - ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 - ; SEL-32: not $[[T0]], $[[T0]] - ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 - ; SEL-32: sel.s $f0, $f14, $f12 - - ; CMOV-64: c.ueq.s $f12, $f13 - ; CMOV-64: movf.s $f13, $f12, $fcc0 - ; CMOV-64: mov.s $f0, $f13 - - ; SEL-64: cmp.ueq.s $f0, $f12, $f13 - ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 - ; SEL-64: not $[[T0]], $[[T0]] - ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 - ; SEL-64: sel.s $f0, $f13, $f12 - - %s = fcmp one float %x, %y - %r = select i1 %s, float %x, float %y - ret float %r -} - -define double @tst_select_fcmp_olt_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_olt_double: - - ; M2: c.olt.d $f12, $f14 - ; M3: c.olt.d $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.olt.d $f12, $f14 - ; CMOV-32: movt.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.lt.d $f0, $f12, $f14 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.olt.d $f12, $f13 - ; CMOV-64: movt.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.lt.d $f0, $f12, $f13 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp olt double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_fcmp_ole_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_ole_double: - - ; M2: c.ole.d $f12, $f14 - ; M3: c.ole.d $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.ole.d $f12, $f14 - ; CMOV-32: movt.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.le.d $f0, $f12, $f14 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.ole.d $f12, $f13 - ; CMOV-64: movt.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.le.d $f0, $f12, $f13 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp ole double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_fcmp_ogt_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_ogt_double: - - ; M2: c.ule.d $f12, $f14 - ; M3: c.ule.d $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.ule.d $f12, $f14 - ; CMOV-32: movf.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.lt.d $f0, $f14, $f12 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.ule.d $f12, $f13 - ; CMOV-64: movf.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.lt.d $f0, $f13, $f12 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp ogt double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_fcmp_oge_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_oge_double: - - ; M2: c.ult.d $f12, $f14 - ; M3: c.ult.d $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.ult.d $f12, $f14 - ; CMOV-32: movf.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.le.d $f0, $f14, $f12 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.ult.d $f12, $f13 - ; CMOV-64: movf.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.le.d $f0, $f13, $f12 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp oge double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_fcmp_oeq_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_oeq_double: - - ; M2: c.eq.d $f12, $f14 - ; M3: c.eq.d $f12, $f13 - ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.eq.d $f12, $f14 - ; CMOV-32: movt.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.eq.d $f0, $f12, $f14 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.eq.d $f12, $f13 - ; CMOV-64: movt.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.eq.d $f0, $f12, $f13 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp oeq double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} - -define double @tst_select_fcmp_one_double(double %x, double %y) { -entry: - ; ALL-LABEL: tst_select_fcmp_one_double: - - ; M2: c.ueq.d $f12, $f14 - ; M3: c.ueq.d $f12, $f13 - ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] - ; M2-M3: nop - ; M2: mov.d $f12, $f14 - ; M3: mov.d $f12, $f13 - ; M2-M3: $[[BB0]]: - ; M2-M3: jr $ra - ; M2-M3: mov.d $f0, $f12 - - ; CMOV-32: c.ueq.d $f12, $f14 - ; CMOV-32: movf.d $f14, $f12, $fcc0 - ; CMOV-32: mov.d $f0, $f14 - - ; SEL-32: cmp.ueq.d $f0, $f12, $f14 - ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 - ; SEL-32: not $[[T0]], $[[T0]] - ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 - ; SEL-32: sel.d $f0, $f14, $f12 - - ; CMOV-64: c.ueq.d $f12, $f13 - ; CMOV-64: movf.d $f13, $f12, $fcc0 - ; CMOV-64: mov.d $f0, $f13 - - ; SEL-64: cmp.ueq.d $f0, $f12, $f13 - ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 - ; SEL-64: not $[[T0]], $[[T0]] - ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 - ; SEL-64: sel.d $f0, $f13, $f12 - %s = fcmp one double %x, %y - %r = select i1 %s, double %x, double %y - ret double %r -} diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll index bba34c47ea82..fa43840a8b7b 100644 --- a/test/CodeGen/Mips/llvm-ir/shl.ll +++ b/test/CodeGen/Mips/llvm-ir/shl.ll @@ -1,42 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R6 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=64R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,M2,NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,NOT-R2-R6,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5,R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R6,R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,M3,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6,R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,64R6,R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6 define signext i1 @shl_i1(i1 signext %a, i1 signext %b) { entry: @@ -61,6 +52,10 @@ entry: ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] ; R2-R6: seb $2, $[[T1]] + ; MM: andi16 $[[T0:[0-9]+]], $5, 255 + ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; MM: seb $2, $[[T1]] + %r = shl i8 %a, %b ret i8 %r } @@ -78,6 +73,10 @@ entry: ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] ; R2-R6: seh $2, $[[T1]] + ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 + ; MM: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; MM: seh $2, $[[T1]] + %r = shl i16 %a, %b ret i16 %r } @@ -139,6 +138,29 @@ entry: ; GP64: dsllv $2, $4, $5 + ; MMR3: sllv $[[T0:[0-9]+]], $4, $7 + ; MMR3: srl16 $[[T1:[0-9]+]], $5, 1 + ; MMR3: not16 $[[T2:[0-9]+]], $7 + ; MMR3: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR3: sllv $[[T5:[0-9]+]], $5, $7 + ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 + ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; MMR3: lui $[[T8:[0-9]+]], 0 + ; MMR3: movn $3, $[[T8]], $[[T6]] + + ; MMR6: sllv $[[T0:[0-9]+]], $4, $7 + ; MMR6: srl16 $[[T1:[0-9]+]], $5, 1 + ; MMR6: not16 $[[T2:[0-9]+]], $7 + ; MMR6: srlv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR6: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR6: andi16 $[[T5:[0-9]+]], $7, 32 + ; MMR6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T5]] + ; MMR6: sllv $[[T7:[0-9]+]], $5, $7 + ; MMR6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] + ; MMR6: or $2, $[[T8]], $[[T6]] + ; MMR6: seleqz $3, $[[T7]], $[[T5]] + %r = shl i64 %a, %b ret i64 %r } @@ -194,6 +216,8 @@ entry: ; 64R6: jr $ra ; 64R6: seleqz $3, $[[T9]], $[[T7]] + ; MM: lw $25, %call16(__ashlti3)($2) + %r = shl i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/srem.ll b/test/CodeGen/Mips/llvm-ir/srem.ll index ceb53ee7033a..3431922b6c58 100644 --- a/test/CodeGen/Mips/llvm-ir/srem.ll +++ b/test/CodeGen/Mips/llvm-ir/srem.ll @@ -1,32 +1,37 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R6,R2-R6 + +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,64R6,R6,R2-R6 + +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR3,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) { entry: @@ -43,6 +48,17 @@ entry: ; R6: sll $[[T3:[0-9]+]], $[[T0]], 31 ; R6: sra $2, $[[T3]], 31 + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mfhi $[[T0:[0-9]+]] + ; MMR3: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR3: sra $2, $[[T1]], 31 + + ; MMR6: mod $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR6: sra $2, $[[T1]], 31 + %r = srem i1 %a, %b ret i1 %r } @@ -66,6 +82,15 @@ entry: ; R6: teq $5, $zero, 7 ; R6: seb $2, $[[T0]] + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mfhi $[[T0:[0-9]+]] + ; MMR3: seb $2, $[[T0]] + + ; MMR6: mod $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: seb $2, $[[T0]] + %r = srem i8 %a, %b ret i8 %r } @@ -83,12 +108,21 @@ entry: ; R2-R5: div $zero, $4, $5 ; R2-R5: teq $5, $zero, 7 ; R2-R5: mfhi $[[T0:[0-9]+]] - ; R2-R5: seh $2, $[[T1]] + ; R2-R5: seh $2, $[[T0]] ; R6: mod $[[T0:[0-9]+]], $4, $5 ; R6: teq $5, $zero, 7 ; R6: seh $2, $[[T0]] + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mfhi $[[T0:[0-9]+]] + ; MMR3: seh $2, $[[T0]] + + ; MMR6: mod $[[T0:[0-9]+]], $4, $5 + ; MMR6: teq $5, $zero, 7 + ; MMR6: seh $2, $[[T0]] + %r = srem i16 %a, %b ret i16 %r } @@ -104,6 +138,13 @@ entry: ; R6: mod $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: div $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mfhi $2 + + ; MMR6: mod $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = srem i32 %a, %b ret i32 %r } @@ -121,6 +162,11 @@ entry: ; 64R6: dmod $2, $4, $5 ; 64R6: teq $5, $zero, 7 + ; MM32: lw $25, %call16(__moddi3)($2) + + ; MM64: dmod $2, $4, $5 + ; MM64: teq $5, $zero, 7 + %r = srem i64 %a, %b ret i64 %r } @@ -132,7 +178,11 @@ entry: ; GP32: lw $25, %call16(__modti3)($gp) ; GP64-NOT-R6: ld $25, %call16(__modti3)($gp) - ; 64-R6: ld $25, %call16(__modti3)($gp) + ; 64R6: ld $25, %call16(__modti3)($gp) + + ; MM32: lw $25, %call16(__modti3)($2) + + ; MM64: ld $25, %call16(__modti3)($2) %r = srem i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/store-atomic.ll b/test/CodeGen/Mips/llvm-ir/store-atomic.ll index 6b33f2685d17..8624cf6c1c66 100644 --- a/test/CodeGen/Mips/llvm-ir/store-atomic.ll +++ b/test/CodeGen/Mips/llvm-ir/store-atomic.ll @@ -1,9 +1,9 @@ ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL ; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL ; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 +; RUN: FileCheck %s -check-prefixes=ALL,M64 ; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 +; RUN: FileCheck %s -check-prefixes=ALL,M64 define void @store_i8(i8* %ptr, i8 signext %v) { ; ALL-LABEL: store_i8 diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll index 164975844d73..33757657ad91 100644 --- a/test/CodeGen/Mips/llvm-ir/sub.ll +++ b/test/CodeGen/Mips/llvm-ir/sub.ll @@ -1,37 +1,47 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=GP32-MM,GP32,MM +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=GP32-MM,GP32,MM ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=GP64,MM define signext i1 @sub_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: sub_i1: - ; ALL: subu $[[T0:[0-9]+]], $4, $5 - ; ALL: sll $[[T0]], $[[T0]], 31 - ; ALL: sra $2, $[[T0]], 31 + ; NOT-MM: subu $[[T0:[0-9]+]], $4, $5 + ; NOT-MM: sll $[[T0]], $[[T0]], 31 + ; NOT-MM: sra $2, $[[T0]], 31 + + ; MM: subu16 $[[T0:[0-9]+]], $4, $5 + ; MM: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MM: sra $[[T0]], $[[T1]], 31 %r = sub i1 %a, %b ret i1 %r @@ -48,6 +58,9 @@ entry: ; R2-R6: subu $[[T0:[0-9]+]], $4, $5 ; R2-R6: seb $2, $[[T0:[0-9]+]] + ; MM: subu16 $[[T0:[0-9]+]], $4, $5 + ; MM: seb $[[T0]], $[[T0]] + %r = sub i8 %a, %b ret i8 %r } @@ -63,6 +76,9 @@ entry: ; R2-R6: subu $[[T0:[0-9]+]], $4, $5 ; R2-R6: seh $2, $[[T0:[0-9]+]] + ; MM: subu16 $[[T0:[0-9]+]], $4, $5 + ; MM: seh $[[T0]], $[[T0]] + %r = sub i16 %a, %b ret i16 %r } @@ -71,7 +87,9 @@ define signext i32 @sub_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: sub_i32: - ; ALL: subu $2, $4, $5 + ; NOT-MM: subu $2, $4, $5 + + ; MM: subu16 $2, $4, $5 %r = sub i32 %a, %b ret i32 %r @@ -96,26 +114,42 @@ define signext i128 @sub_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: sub_i128: - ; GP32: lw $[[T0:[0-9]+]], 20($sp) - ; GP32: sltu $[[T1:[0-9]+]], $5, $[[T0]] - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]] - ; GP32: lw $[[T4:[0-9]+]], 24($sp) - ; GP32: lw $[[T5:[0-9]+]], 28($sp) - ; GP32: subu $[[T6:[0-9]+]], $7, $[[T5]] - ; GP32: subu $2, $4, $[[T3]] - ; GP32: sltu $[[T8:[0-9]+]], $6, $[[T4]] - ; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]] - ; GP32: subu $3, $5, $[[T9]] - ; GP32: sltu $[[T10:[0-9]+]], $7, $[[T5]] - ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]] - ; GP32: subu $4, $6, $[[T11]] - ; GP32: move $5, $[[T6]] + ; GP32-NOT-MM: lw $[[T0:[0-9]+]], 20($sp) + ; GP32-NOT-MM: sltu $[[T1:[0-9]+]], $5, $[[T0]] + ; GP32-NOT-MM: lw $[[T2:[0-9]+]], 16($sp) + ; GP32-NOT-MM: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; GP32-NOT-MM: lw $[[T4:[0-9]+]], 24($sp) + ; GP32-NOT-MM: lw $[[T5:[0-9]+]], 28($sp) + ; GP32-NOT-MM: subu $[[T6:[0-9]+]], $7, $[[T5]] + ; GP32-NOT-MM: subu $2, $4, $[[T3]] + ; GP32-NOT-MM: sltu $[[T8:[0-9]+]], $6, $[[T4]] + ; GP32-NOT-MM: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]] + ; GP32-NOT-MM: subu $3, $5, $[[T9]] + ; GP32-NOT-MM: sltu $[[T10:[0-9]+]], $7, $[[T5]] + ; GP32-NOT-MM: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]] + ; GP32-NOT-MM: subu $4, $6, $[[T11]] + ; GP32-NOT-MM: move $5, $[[T6]] + + ; GP32-MM: lw $[[T0:[0-9]+]], 20($sp) + ; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]] + ; GP32-MM: lw $[[T3:[0-9]+]], 16($sp) + ; GP32-MM: addu $[[T3]], $[[T1]], $[[T3]] + ; GP32-MM: lw $[[T4:[0-9]+]], 28($sp) + ; GP32-MM: subu $[[T1]], $7, $[[T4]] + ; GP32-MM: subu $[[T3]], $[[T5:[0-9]+]], $[[T3]] + ; GP32-MM: lw $[[T5]], 24($sp) + ; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]] + ; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]] + ; GP32-MM: subu $[[T0]], $5, $[[T0]] + ; GP32-MM: sltu $[[T2]], $7, $[[T4]] + ; GP32-MM: addu $[[T5]], $[[T2]], $[[T5]] + ; GP32-MM: subu $[[T5]], $6, $[[T5]] + ; GP32-MM: move $[[T2]], $[[T1]] - ; GP64: dsubu $3, $5, $7 - ; GP64: sltu $[[T0:[0-9]+]], $5, $7 - ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 - ; GP64: dsubu $2, $4, $[[T1]] + ; GP64: dsubu $3, $5, $7 + ; GP64: sltu $[[T0:[0-9]+]], $5, $7 + ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 + ; GP64: dsubu $2, $4, $[[T1]] %r = sub i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/udiv.ll b/test/CodeGen/Mips/llvm-ir/udiv.ll index a7cafe52d1ac..6f4dcb5d7bb5 100644 --- a/test/CodeGen/Mips/llvm-ir/udiv.ll +++ b/test/CodeGen/Mips/llvm-ir/udiv.ll @@ -1,29 +1,37 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=R6 -check-prefix=GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=R6 -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R6,GP32 + +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,NOT-R6,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R6,64R6 + +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR3,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) { entry: @@ -36,6 +44,13 @@ entry: ; R6: divu $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: divu $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $2 + + ; MMR6: divu $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = udiv i1 %a, %b ret i1 %r } @@ -51,6 +66,13 @@ entry: ; R6: divu $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: divu $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $2 + + ; MMR6: divu $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = udiv i8 %a, %b ret i8 %r } @@ -66,6 +88,13 @@ entry: ; R6: divu $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: divu $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $2 + + ; MMR6: divu $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = udiv i16 %a, %b ret i16 %r } @@ -81,6 +110,13 @@ entry: ; R6: divu $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: divu $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mflo $2 + + ; MMR6: divu $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = udiv i32 %a, %b ret i32 %r } @@ -98,6 +134,11 @@ entry: ; 64R6: ddivu $2, $4, $5 ; 64R6: teq $5, $zero, 7 + ; MM32: lw $25, %call16(__udivdi3)($2) + + ; MM64: ddivu $2, $4, $5 + ; MM64: teq $5, $zero, 7 + %r = udiv i64 %a, %b ret i64 %r } @@ -111,6 +152,10 @@ entry: ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp) ; 64-R6: ld $25, %call16(__udivti3)($gp) + ; MM32: lw $25, %call16(__udivti3)($2) + + ; MM64: ld $25, %call16(__udivti3)($2) + %r = udiv i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/urem.ll b/test/CodeGen/Mips/llvm-ir/urem.ll index d5a231c8dfca..69b13ba7fee6 100644 --- a/test/CodeGen/Mips/llvm-ir/urem.ll +++ b/test/CodeGen/Mips/llvm-ir/urem.ll @@ -1,32 +1,37 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ -; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R2-R5,R2-R6,NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,R6,R2-R6 + +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64-NOT-R6,NOT-R6,NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,R2-R5,R2-R6,GP64-NOT-R6,NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,64R6,R6,R2-R6 + +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR3,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @urem_i1(i1 signext %a, i1 signext %b) { entry: @@ -47,6 +52,21 @@ entry: ; R6: sll $[[T3:[0-9]+]], $[[T2]], 31 ; R6: sra $2, $[[T3]], 31 + ; MMR3: andi16 $[[T0:[0-9]+]], $5, 1 + ; MMR3: andi16 $[[T1:[0-9]+]], $4, 1 + ; MMR3: divu $zero, $[[T1]], $[[T0]] + ; MMR3: teq $[[T0]], $zero, 7 + ; MMR3: mfhi $[[T2:[0-9]+]] + ; MMR3: sll $[[T3:[0-9]+]], $[[T2]], 31 + ; MMR3: sra $2, $[[T3]], 31 + + ; MMR6: andi16 $[[T0:[0-9]+]], $5, 1 + ; MMR6: andi16 $[[T1:[0-9]+]], $4, 1 + ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MMR6: teq $[[T0]], $zero, 7 + ; MMR6: sll $[[T3:[0-9]+]], $[[T2]], 31 + ; MMR6: sra $2, $[[T3]], 31 + %r = urem i1 %a, %b ret i1 %r } @@ -76,6 +96,19 @@ entry: ; R6: teq $[[T0]], $zero, 7 ; R6: seb $2, $[[T2]] + ; MMR3: andi16 $[[T0:[0-9]+]], $5, 255 + ; MMR3: andi16 $[[T1:[0-9]+]], $4, 255 + ; MMR3: divu $zero, $[[T1]], $[[T0]] + ; MMR3: teq $[[T0]], $zero, 7 + ; MMR3: mfhi $[[T2:[0-9]+]] + ; MMR3: seb $2, $[[T2]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $5, 255 + ; MMR6: andi16 $[[T1:[0-9]+]], $4, 255 + ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MMR6: teq $[[T0]], $zero, 7 + ; MMR6: seb $2, $[[T2]] + %r = urem i8 %a, %b ret i8 %r } @@ -105,6 +138,19 @@ entry: ; R6: teq $[[T0]], $zero, 7 ; R6: seh $2, $[[T2]] + ; MMR3: andi16 $[[T0:[0-9]+]], $5, 65535 + ; MMR3: andi16 $[[T1:[0-9]+]], $4, 65535 + ; MMR3: divu $zero, $[[T1]], $[[T0]] + ; MMR3: teq $[[T0]], $zero, 7 + ; MMR3: mfhi $[[T2:[0-9]+]] + ; MMR3: seh $2, $[[T2]] + + ; MMR6: andi16 $[[T0:[0-9]+]], $5, 65535 + ; MMR6: andi16 $[[T1:[0-9]+]], $4, 65535 + ; MMR6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MMR6: teq $[[T0]], $zero, 7 + ; MMR6: seh $2, $[[T2]] + %r = urem i16 %a, %b ret i16 %r } @@ -120,6 +166,13 @@ entry: ; R6: modu $2, $4, $5 ; R6: teq $5, $zero, 7 + ; MMR3: divu $zero, $4, $5 + ; MMR3: teq $5, $zero, 7 + ; MMR3: mfhi $2 + + ; MMR6: modu $2, $4, $5 + ; MMR6: teq $5, $zero, 7 + %r = urem i32 %a, %b ret i32 %r } @@ -137,6 +190,11 @@ entry: ; 64R6: dmodu $2, $4, $5 ; 64R6: teq $5, $zero, 7 + ; MM32: lw $25, %call16(__umoddi3)($2) + + ; MM64: dmodu $2, $4, $5 + ; MM64: teq $5, $zero, 7 + %r = urem i64 %a, %b ret i64 %r } @@ -145,10 +203,14 @@ define signext i128 @urem_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: urem_i128: - ; GP32: lw $25, %call16(__umodti3)($gp) + ; GP32: lw $25, %call16(__umodti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) + ; 64R6: ld $25, %call16(__umodti3)($gp) + + ; MM32: lw $25, %call16(__umodti3)($2) - ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) - ; 64-R6: ld $25, %call16(__umodti3)($gp) + ; MM64: ld $25, %call16(__umodti3)($2) %r = urem i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll index d3cc57484895..0ba696fbc339 100644 --- a/test/CodeGen/Mips/llvm-ir/xor.ll +++ b/test/CodeGen/Mips/llvm-ir/xor.ll @@ -1,35 +1,44 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: xor_i1: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MM: xor16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = xor i1 %a, %b ret i1 %r @@ -39,7 +48,12 @@ define signext i8 @xor_i8(i8 signext %a, i8 signext %b) { entry: ; ALL-LABEL: xor_i8: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MM: xor16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = xor i8 %a, %b ret i8 %r @@ -49,7 +63,12 @@ define signext i16 @xor_i16(i16 signext %a, i16 signext %b) { entry: ; ALL-LABEL: xor_i16: - ; ALL: xor $2, $4, $5 + ; GP32: xor $2, $4, $5 + + ; GP64: xor $2, $4, $5 + + ; MM: xor16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = xor i16 %a, %b ret i16 %r @@ -64,6 +83,12 @@ entry: ; GP64: xor $[[T0:[0-9]+]], $4, $5 ; GP64: sll $2, $[[T0]], 0 + ; MM32: xor16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: xor $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = xor i32 %a, %b ret i32 %r } @@ -77,6 +102,13 @@ entry: ; GP64: xor $2, $4, $5 + ; MM32: xor16 $[[T0:[0-9]+]], $6 + ; MM32: xor16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: xor $2, $4, $5 + %r = xor i64 %a, %b ret i64 %r } @@ -97,6 +129,102 @@ entry: ; GP64: xor $2, $4, $6 ; GP64: xor $3, $5, $7 + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: xor16 $[[T1]], $4 + ; MM32: xor16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: xor16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: xor16 $[[T3]], $7 + + ; MM64: xor $2, $4, $6 + ; MM64: xor $3, $5, $7 + %r = xor i128 %a, %b ret i128 %r } + +define signext i1 @xor_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: xor_i1_4: + + ; ALL: move $2, $4 + + %r = xor i1 4, %b + ret i1 %r +} + +define signext i8 @xor_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: xor_i8_4: + + ; ALL: xori $2, $4, 4 + + %r = xor i8 4, %b + ret i8 %r +} + +define signext i16 @xor_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: xor_i16_4: + + ; ALL: xori $2, $4, 4 + + %r = xor i16 4, %b + ret i16 %r +} + +define signext i32 @xor_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: xor_i32_4: + + ; ALL: xori $2, $4, 4 + + %r = xor i32 4, %b + ret i32 %r +} + +define signext i64 @xor_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: xor_i64_4: + + ; GP32: xori $3, $5, 4 + ; GP32: move $2, $4 + + ; GP64: xori $2, $4, 4 + + ; MM32: xori $3, $5, 4 + ; MM32: move $2, $4 + + ; MM64: xori $2, $4, 4 + + %r = xor i64 4, %b + ret i64 %r +} + +define signext i128 @xor_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: xor_i128_4: + + ; GP32: xori $[[T0:[0-9]+]], $7, 4 + ; GP32: move $2, $4 + ; GP32: move $3, $5 + ; GP32: move $4, $6 + ; GP32: move $5, $[[T0]] + + ; GP64: xori $3, $5, 4 + ; GP64: move $2, $4 + + ; MM32: xori $[[T0:[0-9]+]], $7, 4 + ; MM32: move $2, $4 + ; MM32: move $3, $5 + ; MM32: move $4, $6 + ; MM32: move $5, $[[T0]] + + ; MM64: xori $3, $5, 4 + ; MM64: move $2, $4 + + %r = xor i128 4, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/load-store-left-right.ll b/test/CodeGen/Mips/load-store-left-right.ll index a01d246ae460..3bd924a81200 100644 --- a/test/CodeGen/Mips/load-store-left-right.ll +++ b/test/CodeGen/Mips/load-store-left-right.ll @@ -1,17 +1,17 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32 -check-prefix=MIPS32-EL %s -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32 -check-prefix=MIPS32-EB %s -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32 -check-prefix=MIPS32-EL %s -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32 -check-prefix=MIPS32-EB %s -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32R6 -check-prefix=MIPS32R6-EL %s -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32R6 -check-prefix=MIPS32R6-EB %s -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s -; RUN: llc -march=mips64 -mcpu=mips4 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s -; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s -; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EL %s -; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 -check-prefix=MIPS64-EB %s -; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64R6 -check-prefix=MIPS64R6-EL %s -; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64R6 -check-prefix=MIPS64R6-EB %s +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EL %s +; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EB %s +; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EL %s +; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32,MIPS32-EB %s +; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32R6,MIPS32R6-EL %s +; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS32R6,MIPS32R6-EB %s +; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s +; RUN: llc -march=mips64 -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s +; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s +; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EL %s +; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s +; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EL %s +; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EB %s %struct.SLL = type { i64 } %struct.SI = type { i32 } diff --git a/test/CodeGen/Mips/longbranch.ll b/test/CodeGen/Mips/longbranch.ll index 9f5b7417b859..06eda11e7888 100644 --- a/test/CodeGen/Mips/longbranch.ll +++ b/test/CodeGen/Mips/longbranch.ll @@ -1,13 +1,17 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -; RUN: llc -march=mipsel -force-mips-long-branch -O3 < %s \ +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -force-mips-long-branch -O3 -relocation-model=pic < %s \ ; RUN: | FileCheck %s -check-prefix=O32 -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 \ +; RUN: llc -march=mipsel -mcpu=mips32r6 -force-mips-long-branch -O3 \ +; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=O32-R6 +; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ ; RUN: < %s | FileCheck %s -check-prefix=N64 -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 \ +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ ; RUN: < %s | FileCheck %s -check-prefix=N64 +; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -force-mips-long-branch -O3 \ +; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=N64-R6 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \ -; RUN: -force-mips-long-branch -O3 < %s | FileCheck %s -check-prefix=MICROMIPS -; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 < %s \ +; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPS +; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s \ ; RUN: | FileCheck %s -check-prefix=NACL @@ -72,6 +76,10 @@ end: ; O32: jr $ra ; O32: nop +; In MIPS32R6 JR is an alias to JALR with $rd=0. As everything else remains the +; same with the O32 prefix, we use -asm-show-inst in order to make sure that +; the opcode of the MachineInst is a JALR. +; O32-R6: JALR ; Check the MIPS64 version. @@ -101,6 +109,11 @@ end: ; N64: jr $ra ; N64: nop +; In MIPS64R6 JR is an alias to JALR with $rd=0. As everything else remains the +; same with the N64 prefix, we use -asm-show-inst in order to make sure that +; the opcode of the MachineInst is a JALR. +; N64-R6: JALR64 + ; Check the microMIPS version. @@ -155,7 +168,7 @@ end: ; NACL: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) ; NACL: addiu $[[R2:[0-9]+]], $zero, 1 ; NACL: sw $[[R2]], 0($[[R1]]) -; NACL: .align 4 +; NACL: .p2align 4 ; NACL-NEXT: $[[BB2]]: ; NACL: jr $ra ; NACL: nop diff --git a/test/CodeGen/Mips/lw16-base-reg.ll b/test/CodeGen/Mips/lw16-base-reg.ll new file mode 100644 index 000000000000..09150421a960 --- /dev/null +++ b/test/CodeGen/Mips/lw16-base-reg.ll @@ -0,0 +1,26 @@ +; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \ +; RUN: -relocation-model=pic -O3 -o - | FileCheck %s +; RUN: llc %s -march=mips64 -mcpu=mips64r6 -mattr=micromips -filetype=asm \ +; RUN: -relocation-model=pic -O3 -o - | FileCheck %s + +; The purpose of this test is to check whether the CodeGen selects +; LW16 instruction with the base register in a range of $2-$7, $16, $17. + +%struct.T = type { i32 } + +$_ZN1TaSERKS_ = comdat any + +define linkonce_odr void @_ZN1TaSERKS_(%struct.T* %this, %struct.T* dereferenceable(4) %t) #0 comdat align 2 { +entry: + %this.addr = alloca %struct.T*, align 4 + %t.addr = alloca %struct.T*, align 4 + %this1 = load %struct.T*, %struct.T** %this.addr, align 4 + %0 = load %struct.T*, %struct.T** %t.addr, align 4 + %V3 = getelementptr inbounds %struct.T, %struct.T* %0, i32 0, i32 0 + %1 = load i32, i32* %V3, align 4 + %V4 = getelementptr inbounds %struct.T, %struct.T* %this1, i32 0, i32 0 + store i32 %1, i32* %V4, align 4 + ret void +} + +; CHECK: lw16 ${{[0-9]+}}, 0(${{[2-7]|16|17}}) diff --git a/test/CodeGen/Mips/madd-msub.ll b/test/CodeGen/Mips/madd-msub.ll index 667676de5f33..7baba005a072 100644 --- a/test/CodeGen/Mips/madd-msub.ll +++ b/test/CodeGen/Mips/madd-msub.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32 -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32 -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R6 +; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32 +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32 +; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,32R6 ; RUN: llc -march=mips -mcpu=mips32 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP -; RUN: llc -march=mips -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64 -; RUN: llc -march=mips -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64 -; RUN: llc -march=mips -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64R6 +; RUN: llc -march=mips -mcpu=mips64 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64 +; RUN: llc -march=mips -mcpu=mips64r2 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64 +; RUN: llc -march=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64R6 ; FIXME: The MIPS16 test should check its output ; RUN: llc -march=mips -mattr=mips16 < %s diff --git a/test/CodeGen/Mips/micromips-addiu.ll b/test/CodeGen/Mips/micromips-addiu.ll index e0743c9c088b..84ebc4349e1f 100644 --- a/test/CodeGen/Mips/micromips-addiu.ll +++ b/test/CodeGen/Mips/micromips-addiu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @x = global i32 65504, align 4 diff --git a/test/CodeGen/Mips/micromips-atomic1.ll b/test/CodeGen/Mips/micromips-atomic1.ll index 37c3d7682e4f..d7c66c27b6e2 100644 --- a/test/CodeGen/Mips/micromips-atomic1.ll +++ b/test/CodeGen/Mips/micromips-atomic1.ll @@ -1,6 +1,5 @@ ; RUN: llc -march=mipsel -filetype=obj --disable-machine-licm -mattr=micromips < %s -o - \ -; RUN: | llvm-objdump -no-show-raw-insn -arch mipsel -mcpu=mips32r2 -mattr=micromips -d - \ -; RUN: | FileCheck %s -check-prefix=MICROMIPS +; RUN: | llvm-objdump -no-show-raw-insn -d - | FileCheck %s -check-prefix=MICROMIPS ; Use llvm-objdump to check wheter the encodings of microMIPS atomic instructions are correct. ; While emitting assembly files directly when in microMIPS mode, it is possible to emit a mips32r2 diff --git a/test/CodeGen/Mips/micromips-delay-slot.ll b/test/CodeGen/Mips/micromips-delay-slot.ll index ef6546232835..5c6aa36a4130 100644 --- a/test/CodeGen/Mips/micromips-delay-slot.ll +++ b/test/CodeGen/Mips/micromips-delay-slot.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=static -O2 < %s | FileCheck %s +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \ +; RUN: -relocation-model=static -O2 < %s | FileCheck %s -check-prefix=CHECK-MMR6 ; Function Attrs: nounwind define i32 @foo(i32 signext %a) #0 { @@ -16,3 +18,5 @@ declare i32 @bar(i32 signext) #1 ; CHECK: jals ; CHECK-NEXT: sll16 +; CHECK-MMR6: jal +; CHECK-MMR6-NOT: sll16 diff --git a/test/CodeGen/Mips/micromips-lwc1-swc1.ll b/test/CodeGen/Mips/micromips-lwc1-swc1.ll new file mode 100644 index 000000000000..a1a10a5de259 --- /dev/null +++ b/test/CodeGen/Mips/micromips-lwc1-swc1.ll @@ -0,0 +1,50 @@ +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips \ +; RUN: -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM32 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \ +; RUN: -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM32 +; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \ +; RUN: -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM64 + +@gf0 = external global float + +define float @test_lwc1() { +entry: +; CHECK-LABEL: test_lwc1 +; MM32: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM32: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM32: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]]) +; MM32: lwc1 $f0, 0($[[R3]]) + +; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1))) +; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25 +; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1))) +; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]]) +; MM64: lwc1 $f0, 0($[[R3]]) + + %0 = load float, float* @gf0, align 4 + ret float %0 +} + +define void @test_swc1(float %a) { +entry: +; CHECK-LABEL: test_swc1 +; MM32: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM32: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM32: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]]) +; MM32: swc1 $f12, 0($[[R3]]) + +; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1))) +; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25 +; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1))) +; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]]) +; MM64: swc1 $f12, 0($[[R3]]) + + store float %a, float* @gf0, align 4 + ret void +} + diff --git a/test/CodeGen/Mips/micromips-or16.ll b/test/CodeGen/Mips/micromips-or16.ll index 82ea9c687df4..ae2c53884ef7 100644 --- a/test/CodeGen/Mips/micromips-or16.ll +++ b/test/CodeGen/Mips/micromips-or16.ll @@ -1,18 +1,23 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s +; RUN: llc -O0 -march=mips -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -asm-show-inst < %s | FileCheck %s -define i32 @main() { -entry: - %retval = alloca i32, align 4 - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - store i32 0, i32* %retval - %0 = load i32, i32* %b, align 4 - %1 = load i32, i32* %c, align 4 - %or = or i32 %0, %1 - store i32 %or, i32* %a, align 4 - ret i32 0 +; Branch instruction added to enable FastISel::selectOperator +; to select OR instruction +define i32 @f1(i32 signext %a, i32 signext %b) { +; CHECK-LABEL: f1 +; CHECK-NOT: OR16_MMR6 + %1 = or i32 %a, %b + br label %b1 +b1: + ret i32 %1 } +define i32 @f2(i32 signext %a, i32 signext %b) { +entry: +; CHECK-LABEL: f2 ; CHECK: or16 + %0 = or i32 %a, %b + ret i32 %0 +} diff --git a/test/CodeGen/Mips/micromips-shift.ll b/test/CodeGen/Mips/micromips-shift.ll index ed1bcbbf0831..a4f8ffe9408d 100644 --- a/test/CodeGen/Mips/micromips-shift.ll +++ b/test/CodeGen/Mips/micromips-shift.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s @a = global i32 10, align 4 @b = global i32 0, align 4 diff --git a/test/CodeGen/Mips/micromips-zero-mat-uses.ll b/test/CodeGen/Mips/micromips-zero-mat-uses.ll deleted file mode 100644 index b38747a2d2c2..000000000000 --- a/test/CodeGen/Mips/micromips-zero-mat-uses.ll +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips,+nooddspreg -O0 < %s | FileCheck %s - -; CHECK: addiu $[[R0:[0-9]+]], $zero, 0 -; CHECK: subu16 $2, $[[R0]], ${{[0-9]+}} -define i32 @foo() { - %1 = sub i32 0, undef - ret i32 %1 -} diff --git a/test/CodeGen/Mips/mips-shf-gprel.s b/test/CodeGen/Mips/mips-shf-gprel.s new file mode 100644 index 000000000000..9caaf00394a3 --- /dev/null +++ b/test/CodeGen/Mips/mips-shf-gprel.s @@ -0,0 +1,27 @@ +# Check that .sdata and .sbss sections have SHF_MIPS_GPREL flags +# and proper section types. + +# RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o - \ +# RUN: | llvm-readobj -s | FileCheck %s + + .sdata + .word 0 + + .sbss + .zero 4 + +# CHECK: Name: .sdata +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK-NEXT: Flags [ (0x10000003) +# CHECK-NEXT: SHF_ALLOC +# CHECK-NEXT: SHF_MIPS_GPREL +# CHECK-NEXT: SHF_WRITE +# CHECK-NEXT: ] + +# CHECK: Name: .sbss +# CHECK-NEXT: Type: SHT_NOBITS +# CHECK-NEXT: Flags [ (0x10000003) +# CHECK-NEXT: SHF_ALLOC +# CHECK-NEXT: SHF_MIPS_GPREL +# CHECK-NEXT: SHF_WRITE +# CHECK-NEXT: ] diff --git a/test/CodeGen/Mips/mips16fpe.ll b/test/CodeGen/Mips/mips16fpe.ll index 16695e45265a..b8f1d945f356 100644 --- a/test/CodeGen/Mips/mips16fpe.ll +++ b/test/CodeGen/Mips/mips16fpe.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16hf +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 \ +; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=16hf @x = global float 5.000000e+00, align 4 @y = global float 1.500000e+01, align 4 diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll index d9c93810438f..2b1c154f095b 100644 --- a/test/CodeGen/Mips/mips64-f128.ll +++ b/test/CodeGen/Mips/mips64-f128.ll @@ -1,11 +1,11 @@ ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips4 -mattr=+soft-float -O1 \ -; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT +; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64 -mattr=+soft-float -O1 \ -; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT +; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r2 -mattr=+soft-float -O1 \ -; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=C_CC_FMT +; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,C_CC_FMT,PRER6 ; RUN: llc -mtriple=mips64el-unknown-unknown -mcpu=mips64r6 -mattr=+soft-float -O1 \ -; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=ALL -check-prefix=CMP_CC_FMT +; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,CMP_CC_FMT,R6 @gld0 = external global fp128 @gld1 = external global fp128 @@ -544,10 +544,11 @@ entry: } ; ALL-LABEL: load_LD_float: -; ALL: ld $[[R0:[0-9]+]], %got_disp(gf1) -; ALL: lw $4, 0($[[R0]]) -; ALL: ld $25, %call16(__extendsftf2) -; ALL: jalr $25 +; ALL: ld $[[R0:[0-9]+]], %got_disp(gf1) +; ALL: lw $4, 0($[[R0]]) +; ALL: ld $25, %call16(__extendsftf2) +; PRER6: jalr $25 +; R6: jalrc $25 define fp128 @load_LD_float() { entry: @@ -557,10 +558,11 @@ entry: } ; ALL-LABEL: load_LD_double: -; ALL: ld $[[R0:[0-9]+]], %got_disp(gd1) -; ALL: ld $4, 0($[[R0]]) -; ALL: ld $25, %call16(__extenddftf2) -; ALL: jalr $25 +; ALL: ld $[[R0:[0-9]+]], %got_disp(gd1) +; ALL: ld $4, 0($[[R0]]) +; ALL: ld $25, %call16(__extenddftf2) +; PRER6: jalr $25 +; R6: jalrc $25 define fp128 @load_LD_double() { entry: @@ -585,13 +587,14 @@ entry: } ; ALL-LABEL: store_LD_float: -; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1) -; ALL: ld $4, 0($[[R0]]) -; ALL: ld $5, 8($[[R0]]) -; ALL: ld $25, %call16(__trunctfsf2) -; ALL: jalr $25 -; ALL: ld $[[R1:[0-9]+]], %got_disp(gf1) -; ALL: sw $2, 0($[[R1]]) +; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1) +; ALL: ld $4, 0($[[R0]]) +; ALL: ld $5, 8($[[R0]]) +; ALL: ld $25, %call16(__trunctfsf2) +; PRER6: jalr $25 +; R6: jalrc $25 +; ALL: ld $[[R1:[0-9]+]], %got_disp(gf1) +; ALL: sw $2, 0($[[R1]]) define void @store_LD_float() { entry: @@ -602,13 +605,14 @@ entry: } ; ALL-LABEL: store_LD_double: -; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1) -; ALL: ld $4, 0($[[R0]]) -; ALL: ld $5, 8($[[R0]]) -; ALL: ld $25, %call16(__trunctfdf2) -; ALL: jalr $25 -; ALL: ld $[[R1:[0-9]+]], %got_disp(gd1) -; ALL: sd $2, 0($[[R1]]) +; ALL: ld $[[R0:[0-9]+]], %got_disp(gld1) +; ALL: ld $4, 0($[[R0]]) +; ALL: ld $5, 8($[[R0]]) +; ALL: ld $25, %call16(__trunctfdf2) +; PRER6: jalr $25 +; R6: jalrc $25 +; ALL: ld $[[R1:[0-9]+]], %got_disp(gd1) +; ALL: sd $2, 0($[[R1]]) define void @store_LD_double() { entry: @@ -648,7 +652,8 @@ entry: ; ALL: move $[[R2:[0-9]+]], $9 ; ALL: move $[[R3:[0-9]+]], $8 ; ALL: ld $25, %call16(__gttf2)($gp) -; ALL: jalr $25 +; PRER6: jalr $25 +; R6: jalrc $25 ; C_CC_FMT: slti $[[CC:[0-9]+]], $2, 1 ; C_CC_FMT: movz $[[R1]], $[[R3]], $[[CC]] diff --git a/test/CodeGen/Mips/mips64extins.ll b/test/CodeGen/Mips/mips64extins.ll index 211cd5f8e7fd..7876266fb856 100644 --- a/test/CodeGen/Mips/mips64extins.ll +++ b/test/CodeGen/Mips/mips64extins.ll @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s define i64 @dext(i64 %i) nounwind readnone { entry: +; CHECK-LABEL: dext: ; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10 %shr = lshr i64 %i, 5 %and = and i64 %shr, 1023 @@ -10,7 +11,8 @@ entry: define i64 @dextm(i64 %i) nounwind readnone { entry: -; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34 +; CHECK-LABEL: dextm: +; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34 %shr = lshr i64 %i, 5 %and = and i64 %shr, 17179869183 ret i64 %and @@ -18,7 +20,8 @@ entry: define i64 @dextu(i64 %i) nounwind readnone { entry: -; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6 +; CHECK-LABEL: dextu: +; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6 %shr = lshr i64 %i, 34 %and = and i64 %shr, 63 ret i64 %and @@ -26,6 +29,7 @@ entry: define i64 @dins(i64 %i, i64 %j) nounwind readnone { entry: +; CHECK-LABEL: dins: ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10 %shl2 = shl i64 %j, 8 %and = and i64 %shl2, 261888 @@ -36,6 +40,7 @@ entry: define i64 @dinsm(i64 %i, i64 %j) nounwind readnone { entry: +; CHECK-LABEL: dinsm: ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 10, 33 %shl4 = shl i64 %j, 10 %and = and i64 %shl4, 8796093021184 @@ -46,6 +51,7 @@ entry: define i64 @dinsu(i64 %i, i64 %j) nounwind readnone { entry: +; CHECK-LABEL: dinsu: ; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13 %shl4 = shl i64 %j, 40 %and = and i64 %shl4, 9006099743113216 diff --git a/test/CodeGen/Mips/mips64fpldst.ll b/test/CodeGen/Mips/mips64fpldst.ll index 55d5c775cbba..564ffdd2f691 100644 --- a/test/CodeGen/Mips/mips64fpldst.ll +++ b/test/CodeGen/Mips/mips64fpldst.ll @@ -1,7 +1,9 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 @f0 = common global float 0.000000e+00, align 4 @d0 = common global double 0.000000e+00, align 8 @@ -12,10 +14,10 @@ define float @funcfl1() nounwind readonly { entry: ; CHECK-N64: funcfl1 ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0) -; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]]) +; CHECK-N64: lwc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfl1 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0) -; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]]) +; CHECK-N32: lwc1 $f{{[0-9]+}}, 0($[[R0]]) %0 = load float, float* @f0, align 4 ret float %0 } @@ -24,11 +26,11 @@ define double @funcfl2() nounwind readonly { entry: ; CHECK-N64: funcfl2 ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0) -; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]]) +; CHECK-N64: ldc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfl2 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0) -; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]]) - %0 = load double, double* @d0, align 8 +; CHECK-N32: ldc1 $f{{[0-9]+}}, 0($[[R0]]) + %0 = load double, double* @d0, align 8 ret double %0 } @@ -36,12 +38,12 @@ define void @funcfs1() nounwind { entry: ; CHECK-N64: funcfs1 ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(f0) -; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]]) +; CHECK-N64: swc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfs1 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(f0) -; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]]) - %0 = load float, float* @f1, align 4 - store float %0, float* @f0, align 4 +; CHECK-N32: swc1 $f{{[0-9]+}}, 0($[[R0]]) + %0 = load float, float* @f1, align 4 + store float %0, float* @f0, align 4 ret void } @@ -49,12 +51,12 @@ define void @funcfs2() nounwind { entry: ; CHECK-N64: funcfs2 ; CHECK-N64: ld $[[R0:[0-9]+]], %got_disp(d0) -; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]]) +; CHECK-N64: sdc1 $f{{[0-9]+}}, 0($[[R0]]) ; CHECK-N32: funcfs2 ; CHECK-N32: lw $[[R0:[0-9]+]], %got_disp(d0) -; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]]) - %0 = load double, double* @d1, align 8 - store double %0, double* @d0, align 8 +; CHECK-N32: sdc1 $f{{[0-9]+}}, 0($[[R0]]) + %0 = load double, double* @d1, align 8 + store double %0, double* @d0, align 8 ret void } diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll index d64cdceb6b81..8f124c89db4b 100644 --- a/test/CodeGen/Mips/mips64instrs.ll +++ b/test/CodeGen/Mips/mips64instrs.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 -check-prefix=ACCMULDIV %s -; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s -; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s -; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=GPRMULDIV %s +; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,MIPS4,ACCMULDIV %s +; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s +; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,ACCMULDIV %s +; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,HAS-DCLO,GPRMULDIV %s @gll0 = common global i64 0, align 8 @gll1 = common global i64 0, align 8 diff --git a/test/CodeGen/Mips/mips64intldst.ll b/test/CodeGen/Mips/mips64intldst.ll index 658ab88481c4..0abe192de117 100644 --- a/test/CodeGen/Mips/mips64intldst.ll +++ b/test/CodeGen/Mips/mips64intldst.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=CHECK-N64 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 @c = common global i8 0, align 4 @s = common global i16 0, align 4 diff --git a/test/CodeGen/Mips/mips64muldiv.ll b/test/CodeGen/Mips/mips64muldiv.ll index 32d05a9da369..d1292be504e6 100644 --- a/test/CodeGen/Mips/mips64muldiv.ll +++ b/test/CodeGen/Mips/mips64muldiv.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC -; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC -; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR +; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,ACC +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,ACC +; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,ACC +; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR ; FileCheck prefixes: ; ALL - All targets diff --git a/test/CodeGen/Mips/mips64r6/compatibility.ll b/test/CodeGen/Mips/mips64r6/compatibility.ll index 429f68d784bb..174f4ce1771a 100644 --- a/test/CodeGen/Mips/mips64r6/compatibility.ll +++ b/test/CodeGen/Mips/mips64r6/compatibility.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mcpu=mips64r6 < %s | FileCheck %s -; RUN: not llc -march=mipsel -mcpu=mips64r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s +; RUN: llc -march=mipsel -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s +; RUN: not llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s ; CHECK: foo: ; DSP: MIPS64r6 is not compatible with the DSP ASE diff --git a/test/CodeGen/Mips/mips64shift.ll b/test/CodeGen/Mips/mips64shift.ll index 52c6f9066392..e93140f18c9b 100644 --- a/test/CodeGen/Mips/mips64shift.ll +++ b/test/CodeGen/Mips/mips64shift.ll @@ -1,64 +1,65 @@ -; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s +; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS %s +; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS %s define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: dsllv +; ALL: dsllv %shl = shl i64 %a0, %a1 ret i64 %shl } define i64 @f1(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: dsrav +; ALL: dsrav %shr = ashr i64 %a0, %a1 ret i64 %shr } define i64 @f2(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: dsrlv +; ALL: dsrlv %shr = lshr i64 %a0, %a1 ret i64 %shr } define i64 @f3(i64 %a0) nounwind readnone { entry: -; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10 +; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10 %shl = shl i64 %a0, 10 ret i64 %shl } define i64 @f4(i64 %a0) nounwind readnone { entry: -; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10 +; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10 %shr = ashr i64 %a0, 10 ret i64 %shr } define i64 @f5(i64 %a0) nounwind readnone { entry: -; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10 +; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10 %shr = lshr i64 %a0, 10 ret i64 %shr } define i64 @f6(i64 %a0) nounwind readnone { entry: -; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40 +; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40 %shl = shl i64 %a0, 40 ret i64 %shl } define i64 @f7(i64 %a0) nounwind readnone { entry: -; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40 +; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40 %shr = ashr i64 %a0, 40 ret i64 %shr } define i64 @f8(i64 %a0) nounwind readnone { entry: -; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40 +; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40 %shr = lshr i64 %a0, 40 ret i64 %shr } @@ -66,7 +67,7 @@ entry: define i64 @f9(i64 %a0, i64 %a1) nounwind readnone { entry: ; CHECK-NOT: sll -; CHECK: drotrv +; ALL: drotrv %shr = lshr i64 %a0, %a1 %sub = sub i64 64, %a1 %shl = shl i64 %a0, %sub @@ -77,7 +78,7 @@ entry: define i64 @f10(i64 %a0, i64 %a1) nounwind readnone { entry: ; CHECK-NOT: sll -; CHECK: drotrv +; ALL: drotrv %shl = shl i64 %a0, %a1 %sub = sub i64 64, %a1 %shr = lshr i64 %a0, %sub @@ -87,7 +88,7 @@ entry: define i64 @f11(i64 %a0) nounwind readnone { entry: -; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10 +; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10 %shr = lshr i64 %a0, 10 %shl = shl i64 %a0, 54 %or = or i64 %shr, %shl @@ -96,7 +97,7 @@ entry: define i64 @f12(i64 %a0) nounwind readnone { entry: -; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54 +; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54 %shl = shl i64 %a0, 10 %shr = lshr i64 %a0, 54 %or = or i64 %shl, %shr diff --git a/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/test/CodeGen/Mips/mno-ldc1-sdc1.ll index c7eda3320bc6..9663138d4c81 100644 --- a/test/CodeGen/Mips/mno-ldc1-sdc1.ll +++ b/test/CodeGen/Mips/mno-ldc1-sdc1.ll @@ -1,52 +1,63 @@ ; Check that [sl]dc1 are normally emitted. MIPS32r2 should have [sl]dxc1 too. -; RUN: llc -march=mipsel -mcpu=mips32 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1-LDC1 -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2-LDXC1 -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6-LDC1 +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1-LDC1 +; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R2-LDXC1 +; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R6-LDC1 +; RUN: llc -march=mipsel -mcpu=mips32r3 -mattr=+micromips \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MM +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MM ; Check that -mno-ldc1-sdc1 disables [sl]dc1 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \ -; RUN: -check-prefix=32R1-LE -check-prefix=32R1-LE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R1,32R1-LE,32R1-LE-PIC ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \ -; RUN: -check-prefix=32R2-LE -check-prefix=32R2-LE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R2,32R2-LE,32R2-LE-PIC ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \ -; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-PIC +; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \ +; RUN: -mattr=+micromips < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-LE-PIC +; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \ +; RUN: -mattr=+micromips < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-LE-PIC ; Check again for big-endian ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \ -; RUN: -check-prefix=32R1-BE -check-prefix=32R1-BE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R1,32R1-BE,32R1-BE-PIC ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \ -; RUN: -check-prefix=32R2-BE -check-prefix=32R2-BE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R2,32R2-BE,32R2-BE-PIC ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \ -; RUN: -check-prefix=32R6-BE -check-prefix=32R6-BE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-BE,32R6-BE-PIC +; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \ +; RUN: -mattr=+micromips < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-BE-PIC +; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \ +; RUN: -mattr=+micromips < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-BE-PIC ; Check again for the static relocation model ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \ -; RUN: -check-prefix=32R1-LE -check-prefix=32R1-LE-STATIC +; RUN: FileCheck %s -check-prefixes=ALL,32R1,32R1-LE,32R1-LE-STATIC ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \ -; RUN: -check-prefix=32R2-LE -check-prefix=32R2-LE-STATIC +; RUN: FileCheck %s -check-prefixes=ALL,32R2,32R2-LE,32R2-LE-STATIC ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \ -; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-STATIC +; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-STATIC +; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r3 \ +; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC_PIC +; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \ +; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC-PIC @g0 = common global double 0.000000e+00, align 8 @@ -109,6 +120,26 @@ ; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}}) +; MM: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM: lw $[[R3:[0-9]+]], %got(g0)($[[R2]]) +; MM: ldc1 $f0, 0($[[R3]]) + +; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM-MNO-PIC: lw $[[R3:[0-9]+]], %got(g0)($[[R2]]) +; MM-MNO-PIC: lw16 $[[R4:[0-9]+]], 0($[[R3]]) +; MM-MNO-PIC: lw16 $[[R5:[0-9]+]], 4($[[R3]]) +; MM-MNO-LE-PIC: mtc1 $[[R4]], $f0 +; MM-MNO-LE-PIC: mthc1 $[[R5]], $f0 +; MM-MNO-BE-PIC: mtc1 $[[R5]], $f0 +; MM-MNO-BE-PIC: mthc1 $[[R4]], $f0 + +; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0) +; MM-STATIC-PIC: ldc1 $f0, %lo(g0)($[[R0]]) + define double @test_ldc1() { entry: %0 = load double, double* @g0, align 8 @@ -174,6 +205,26 @@ entry: ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) +; MM: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM: lw $[[R3:[0-9]+]], %got(g0)($[[R2]]) +; MM: sdc1 $f12, 0($[[R3]]) + +; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM-MNO-LE-PIC: mfc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-BE-PIC: mfhc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-PIC: lw $[[R4:[0-9]+]], %got(g0)($[[R2]]) +; MM-MNO-PIC: sw16 $[[R3]], 0($[[R4]]) +; MM-MNO-LE-PIC: mfhc1 $[[R5:[0-9]+]], $f12 +; MM-MNO-BE-PIC: mfc1 $[[R5:[0-9]+]], $f12 +; MM-MNO-PIC: sw16 $[[R5]], 4($[[R4]]) + +; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0) +; MM-STATIC-PIC: sdc1 $f12, %lo(g0)($[[R0]]) + define void @test_sdc1(double %a) { entry: store double %a, double* @g0, align 8 @@ -210,6 +261,23 @@ entry: ; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}}) +; MM: sll16 $[[R0:[0-9]+]], $5, 3 +; MM: addu16 $[[R1:[0-9]+]], $4, $[[R0]] +; MM: ldc1 $f0, 0($[[R1]]) + +; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $5, 3 +; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]] +; MM-MNO-PIC: lw16 $[[R2:[0-9]+]], 0($[[R1]]) +; MM-MNO-PIC: lw16 $[[R3:[0-9]+]], 4($[[R1]]) +; MM-MNO-LE-PIC: mtc1 $[[R2]], $f0 +; MM-MNO-LE-PIC: mthc1 $[[R3]], $f0 +; MM-MNO-BE-PIC: mtc1 $[[R3]], $f0 +; MM-MNO-BE-PIC: mthc1 $[[R2]], $f0 + +; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $5, 3 +; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]] +; MM-STATIC-PIC: ldc1 $f0, 0($[[R1]]) + define double @test_ldxc1(double* nocapture readonly %a, i32 %i) { entry: %arrayidx = getelementptr inbounds double, double* %a, i32 %i @@ -241,6 +309,23 @@ entry: ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) +; MM: sll16 $[[R0:[0-9]+]], $7, 3 +; MM: addu16 $[[R1:[0-9]+]], $6, $[[R0]] +; MM: sdc1 $f12, 0($[[R1]]) + +; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3 +; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]] +; MM-MNO-LE-PIC: mfc1 $[[R2:[0-9]+]], $f12 +; MM-MNO-BE-PIC: mfhc1 $[[R2:[0-9]+]], $f12 +; MM-MNO-PIC: sw16 $[[R2]], 0($[[R1]]) +; MM-MNO-LE-PIC: mfhc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-BE-PIC: mfc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-PIC: sw16 $[[R3]], 4($[[R1]]) + +; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $7, 3 +; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]] +; MM-STATIC-PIC: sdc1 $f12, 0($[[R1]]) + define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) { entry: %arrayidx = getelementptr inbounds double, double* %a, i32 %i diff --git a/test/CodeGen/Mips/msa/2r.ll b/test/CodeGen/Mips/msa/2r.ll index 501936c76e73..0abd73f180a0 100644 --- a/test/CodeGen/Mips/msa/2r.ll +++ b/test/CodeGen/Mips/msa/2r.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_nloc_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_nloc_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/test/CodeGen/Mips/msa/2r_vector_scalar.ll index ddcd3cf757d9..db0eb5ad5a43 100644 --- a/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -1,14 +1,14 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format and ; convert scalars to vectors. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_fill_b_ARG1 = global i32 23, align 16 @llvm_mips_fill_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 @@ -97,4 +97,4 @@ declare <2 x i64> @llvm.mips.fill.d(i64) nounwind ; MIPS64-DAG: ld [[RD:\$[0-9]+]], %got_disp(llvm_mips_fill_d_RES) ; MIPS64-DAG: st.d [[WD]], 0([[RD]]) ; MIPS-ANY: .size llvm_mips_fill_d_test -;
\ No newline at end of file +; diff --git a/test/CodeGen/Mips/msa/2rf.ll b/test/CodeGen/Mips/msa/2rf.ll index 1dbfbda1b612..885e2c64bcfc 100644 --- a/test/CodeGen/Mips/msa/2rf.ll +++ b/test/CodeGen/Mips/msa/2rf.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_flog2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_flog2_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 diff --git a/test/CodeGen/Mips/msa/2rf_float_int.ll b/test/CodeGen/Mips/msa/2rf_float_int.ll index 369015814b0e..44861caf4650 100644 --- a/test/CodeGen/Mips/msa/2rf_float_int.ll +++ b/test/CodeGen/Mips/msa/2rf_float_int.ll @@ -1,8 +1,8 @@ ; Test the MSA integer to floating point conversion intrinsics that are encoded ; with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 @llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 diff --git a/test/CodeGen/Mips/msa/2rf_int_float.ll b/test/CodeGen/Mips/msa/2rf_int_float.ll index 77d1404f9cfa..f845f3ddd740 100644 --- a/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -2,8 +2,8 @@ ; 2RF instruction format. This includes conversions but other instructions such ; as fclass are also here. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_fclass_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 @llvm_mips_fclass_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 diff --git a/test/CodeGen/Mips/msa/3r-a.ll b/test/CodeGen/Mips/msa/3r-a.ll index db772f918614..8feb928a8add 100644 --- a/test/CodeGen/Mips/msa/3r-a.ll +++ b/test/CodeGen/Mips/msa/3r-a.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s ; It should fail to compile without fp64. ; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \ diff --git a/test/CodeGen/Mips/msa/3r-b.ll b/test/CodeGen/Mips/msa/3r-b.ll index 2ecdc4290067..1c4f14814a2a 100644 --- a/test/CodeGen/Mips/msa/3r-b.ll +++ b/test/CodeGen/Mips/msa/3r-b.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'b' -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclr_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_bclr_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/test/CodeGen/Mips/msa/3r-s.ll b/test/CodeGen/Mips/msa/3r-s.ll index d04c5ff165f2..fe4365110366 100644 --- a/test/CodeGen/Mips/msa/3r-s.ll +++ b/test/CodeGen/Mips/msa/3r-s.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 's' -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_sld_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_sld_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/test/CodeGen/Mips/msa/3r_splat.ll b/test/CodeGen/Mips/msa/3r_splat.ll index 56d26b030de9..78c485f4f868 100644 --- a/test/CodeGen/Mips/msa/3r_splat.ll +++ b/test/CodeGen/Mips/msa/3r_splat.ll @@ -1,9 +1,9 @@ ; Test the MSA splat intrinsics that are encoded with the 3R instruction ; format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s @llvm_mips_splat_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 diff --git a/test/CodeGen/Mips/msa/basic_operations.ll b/test/CodeGen/Mips/msa/basic_operations.ll index 2efec2911935..5d253d7af253 100644 --- a/test/CodeGen/Mips/msa/basic_operations.ll +++ b/test/CodeGen/Mips/msa/basic_operations.ll @@ -1,9 +1,21 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-BE %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-LE %s -; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-BE %s -; RUN: llc -march=mips64el -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-LE %s -; RUN: llc -march=mips64 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-BE %s -; RUN: llc -march=mips64el -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-LE %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-BE %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-LE %s +; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 \ +; RUN: -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,N32,MIPS64,ALL-BE %s +; RUN: llc -march=mips64el -target-abi n32 -mattr=+msa,+fp64 \ +; RUN: -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,N32,MIPS64,ALL-LE %s +; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,N64,MIPS64,ALL-BE %s +; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,N64,MIPS64,ALL-LE %s @v4i8 = global <4 x i8> <i8 0, i8 0, i8 0, i8 0> @v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> diff --git a/test/CodeGen/Mips/msa/basic_operations_float.ll b/test/CodeGen/Mips/msa/basic_operations_float.ll index f19cb9b7c2e5..d714b3eec1f2 100644 --- a/test/CodeGen/Mips/msa/basic_operations_float.ll +++ b/test/CodeGen/Mips/msa/basic_operations_float.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s -; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s -; RUN: llc -march=mips64 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 %s -; RUN: llc -march=mips64el -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,O32 %s +; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N64 %s @v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0> @v2f64 = global <2 x double> <double 0.0, double 0.0> diff --git a/test/CodeGen/Mips/msa/elm_copy.ll b/test/CodeGen/Mips/msa/elm_copy.ll index 251b535fd76c..8befecbdd65a 100644 --- a/test/CodeGen/Mips/msa/elm_copy.ll +++ b/test/CodeGen/Mips/msa/elm_copy.ll @@ -1,14 +1,14 @@ ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are element extraction operations. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_copy_s_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_copy_s_b_RES = global i32 0, align 16 diff --git a/test/CodeGen/Mips/msa/elm_cxcmsa.ll b/test/CodeGen/Mips/msa/elm_cxcmsa.ll index 8d6b0ee20ab8..b96499c15235 100644 --- a/test/CodeGen/Mips/msa/elm_cxcmsa.ll +++ b/test/CodeGen/Mips/msa/elm_cxcmsa.ll @@ -1,8 +1,8 @@ ; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM ; instruction format). -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s define i32 @msa_ir_cfcmsa_test() nounwind { entry: diff --git a/test/CodeGen/Mips/msa/elm_insv.ll b/test/CodeGen/Mips/msa/elm_insv.ll index 46e6289189df..6458b6dc23db 100644 --- a/test/CodeGen/Mips/msa/elm_insv.ll +++ b/test/CodeGen/Mips/msa/elm_insv.ll @@ -1,14 +1,14 @@ ; Test the MSA element insertion intrinsics that are encoded with the ELM ; instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_insert_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_insert_b_ARG3 = global i32 27, align 16 diff --git a/test/CodeGen/Mips/msa/frameindex.ll b/test/CodeGen/Mips/msa/frameindex.ll index afd28ae184dd..f903381f9ef0 100644 --- a/test/CodeGen/Mips/msa/frameindex.ll +++ b/test/CodeGen/Mips/msa/frameindex.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-BE %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-LE %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefixes=MIPS32-AE,MIPS32-BE %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefixes=MIPS32-AE,MIPS32-LE %s define void @loadstore_v16i8_near() nounwind { ; MIPS32-AE: loadstore_v16i8_near: diff --git a/test/CodeGen/Mips/msa/i5-b.ll b/test/CodeGen/Mips/msa/i5-b.ll index 40ab095f6809..c588c8b2407e 100644 --- a/test/CodeGen/Mips/msa/i5-b.ll +++ b/test/CodeGen/Mips/msa/i5-b.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'b' -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclri_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_bclri_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/test/CodeGen/Mips/msa/i8.ll b/test/CodeGen/Mips/msa/i8.ll index 4af9c588fdef..5f8b4663c387 100644 --- a/test/CodeGen/Mips/msa/i8.ll +++ b/test/CodeGen/Mips/msa/i8.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I8 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 diff --git a/test/CodeGen/Mips/msa/vec.ll b/test/CodeGen/Mips/msa/vec.ll index 8790923ce727..f206975990af 100644 --- a/test/CodeGen/Mips/msa/vec.ll +++ b/test/CodeGen/Mips/msa/vec.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the VEC instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ANYENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ANYENDIAN %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefix=ANYENDIAN %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefix=ANYENDIAN %s @llvm_mips_and_v_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 @llvm_mips_and_v_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16 diff --git a/test/CodeGen/Mips/nacl-align.ll b/test/CodeGen/Mips/nacl-align.ll index 8191c7dec6f2..74b6286648dd 100644 --- a/test/CodeGen/Mips/nacl-align.ll +++ b/test/CodeGen/Mips/nacl-align.ll @@ -7,8 +7,8 @@ define void @test0() { ret void -; CHECK: .align 4 -; CHECK-NOT: .align +; CHECK: .p2align 4 +; CHECK-NOT: .p2align ; CHECK-LABEL: test0: } @@ -40,18 +40,18 @@ default: ; CHECK-LABEL: test1: -; CHECK: .align 4 +; CHECK: .p2align 4 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 111 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 555 -; CHECK-NEXT: .align 4 +; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 222 -; CHECK-NEXT: .align 4 +; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 333 @@ -81,12 +81,12 @@ bb2: ; Note that there are two consecutive labels - one temporary and one for ; basic block. -; CHECK: .align 4 +; CHECK: .p2align 4 ; CHECK-NEXT: ${{[a-zA-Z0-9]+}}: ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 111 -; CHECK-NEXT: .align 4 +; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: ${{[a-zA-Z0-9]+}}: ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra diff --git a/test/CodeGen/Mips/no-odd-spreg-msa.ll b/test/CodeGen/Mips/no-odd-spreg-msa.ll index 7213044a2300..603a99e267f6 100644 --- a/test/CodeGen/Mips/no-odd-spreg-msa.ll +++ b/test/CodeGen/Mips/no-odd-spreg-msa.ll @@ -1,9 +1,9 @@ ; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,-nooddspreg \ -; RUN: -no-integrated-as < %s | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=ODDSPREG +; RUN: -no-integrated-as -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,ODDSPREG ; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,+nooddspreg \ -; RUN: -no-integrated-as < %s | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=NOODDSPREG +; RUN: -no-integrated-as -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,NOODDSPREG @v4f32 = global <4 x float> zeroinitializer diff --git a/test/CodeGen/Mips/no-odd-spreg.ll b/test/CodeGen/Mips/no-odd-spreg.ll index 572e940bc467..411441a7bd94 100644 --- a/test/CodeGen/Mips/no-odd-spreg.ll +++ b/test/CodeGen/Mips/no-odd-spreg.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG -check-prefix=ODDSPREG-NO-EMIT -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOODDSPREG -; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG -check-prefix=ODDSPREG-NO-EMIT -; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64,+nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOODDSPREG -; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fpxx,-nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG -check-prefix=ODDSPREG-EMIT +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT +; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+nooddspreg < %s | FileCheck %s -check-prefixes=ALL,NOODDSPREG +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64,+nooddspreg < %s | FileCheck %s -check-prefixes=ALL,NOODDSPREG +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fpxx,-nooddspreg < %s | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-EMIT ; We don't emit a directive unless we need to. This is to support versions of ; GAS which do not support the directive. diff --git a/test/CodeGen/Mips/o32_cc.ll b/test/CodeGen/Mips/o32_cc.ll index c28f9abcadcd..cef1290a75bd 100644 --- a/test/CodeGen/Mips/o32_cc.ll +++ b/test/CodeGen/Mips/o32_cc.ll @@ -1,8 +1,7 @@ ; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=ALL %s -; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck -check-prefix=ALL %s -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=NO-MFHC1 %s -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-MFHC1 %s -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-MFHC1 %s +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=ALL,NO-MFHC1 %s +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s ; $f12, $f14 ; ALL-LABEL: testlowercall0: diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index 108c663ab1cd..33431dba43c4 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s %0 = type { i8, i16, i32, i64, double, i32, [4 x i8] } %struct.S1 = type { i8, i16, i32, i64, double, i32 } diff --git a/test/CodeGen/Mips/octeon.ll b/test/CodeGen/Mips/octeon.ll index 499ce3c1ddbf..b441274cec6b 100644 --- a/test/CodeGen/Mips/octeon.ll +++ b/test/CodeGen/Mips/octeon.ll @@ -1,5 +1,5 @@ -; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=ALL -check-prefix=OCTEON -; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64 +; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON +; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 define i64 @addi64(i64 %a, i64 %b) nounwind { entry: diff --git a/test/CodeGen/Mips/octeon_popcnt.ll b/test/CodeGen/Mips/octeon_popcnt.ll index 3432b3992984..13488ed59504 100644 --- a/test/CodeGen/Mips/octeon_popcnt.ll +++ b/test/CodeGen/Mips/octeon_popcnt.ll @@ -21,7 +21,7 @@ define i16 @cnt16(i16 %x) nounwind readnone { ; MIPS64-NOT: pop } -define i32 @cnt32(i32 zeroext %x) nounwind readnone { +define i32 @cnt32(i32 signext %x) nounwind readnone { %cnt = tail call i32 @llvm.ctpop.i32(i32 %x) ret i32 %cnt ; OCTEON-LABEL: cnt32: diff --git a/test/CodeGen/Mips/optimize-pic-o0.ll b/test/CodeGen/Mips/optimize-pic-o0.ll index 454bc851484d..8790b8e92b74 100644 --- a/test/CodeGen/Mips/optimize-pic-o0.ll +++ b/test/CodeGen/Mips/optimize-pic-o0.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -O0 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -O0 -relocation-model=pic < %s | FileCheck %s ; Function Attrs: nounwind define i32 @main() { diff --git a/test/CodeGen/Mips/prevent-hoisting.ll b/test/CodeGen/Mips/prevent-hoisting.ll index 81b14d7441b3..200848ac5485 100644 --- a/test/CodeGen/Mips/prevent-hoisting.ll +++ b/test/CodeGen/Mips/prevent-hoisting.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -O3 < %s | FileCheck %s +; RUN: llc -march=mipsel -O3 -relocation-model=pic < %s | FileCheck %s ; MIPS direct branches implicitly define register $at. This test makes sure that @@ -11,12 +11,12 @@ ; CHECK-LABEL: readLumaCoeff8x8_CABAC ; The check for first "addiu" instruction is added so that we can match the correct "b" instruction. -; CHECK: addiu ${{[0-9]+}}, $zero, -1 +; CHECK: andi ; CHECK: b $[[BB0:BB[0-9_]+]] -; CHECK-NEXT: addiu ${{[0-9]+}}, $zero, 0 +; CHECK-NEXT: sll ; Check that at the start of a fallthrough block there is a instruction that writes to $1. -; CHECK-NEXT: {{BB[0-9_#]+}}: +; CHECK-NEXT: {{BB[0-9_#]+}}: ; CHECK-NEXT: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]]) ; CHECK-NEXT: sll $1, $[[R0:[0-9]+]], 4 diff --git a/test/CodeGen/Mips/private-addr.ll b/test/CodeGen/Mips/private-addr.ll new file mode 100644 index 000000000000..37dd6fe53c40 --- /dev/null +++ b/test/CodeGen/Mips/private-addr.ll @@ -0,0 +1,14 @@ +; RUN: llc -mtriple=mips-pc-linux -relocation-model=pic < %s | FileCheck %s + +define private void @bar() { + ret void +} + +define void()* @foo() { +; CHECK: foo: +; CHECK: lw $[[REG:.*]], %got($bar)($1) +; CHECK-NEXT: jr $ra +; CHECK-NEXT: addiu $2, $[[REG]], %lo($bar) + + ret void()* @bar +} diff --git a/test/CodeGen/Mips/private.ll b/test/CodeGen/Mips/private.ll index 5907dbd644ae..07affbf30c38 100644 --- a/test/CodeGen/Mips/private.ll +++ b/test/CodeGen/Mips/private.ll @@ -1,6 +1,6 @@ ; Test to make sure that the 'private' is used correctly. ; -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips -relocation-model=pic < %s | FileCheck %s define private void @foo() { ; CHECK-LABEL: foo: diff --git a/test/CodeGen/Mips/return-vector.ll b/test/CodeGen/Mips/return-vector.ll index 3870fe092156..08eddf370096 100644 --- a/test/CodeGen/Mips/return-vector.ll +++ b/test/CodeGen/Mips/return-vector.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s ; Check that function accesses vector return value from stack in cases when diff --git a/test/CodeGen/Mips/rotate.ll b/test/CodeGen/Mips/rotate.ll index 70eff6e224d0..77936b7bef9b 100644 --- a/test/CodeGen/Mips/rotate.ll +++ b/test/CodeGen/Mips/rotate.ll @@ -1,8 +1,15 @@ ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16 +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips < %s | FileCheck %s \ +; RUN: -check-prefix=MM32 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips < %s | FileCheck %s \ +; RUN: -check-prefix=MM32 ; CHECK: rotrv $2, $4 ; mips16: .ent rot0 +; MM32: li16 $2, 32 +; MM32: subu16 $2, $2, $5 +; MM32: rotrv $2, $4, $2 define i32 @rot0(i32 %a, i32 %b) nounwind readnone { entry: %shl = shl i32 %a, %b @@ -14,6 +21,7 @@ entry: ; CHECK: rotr $2, $4, 22 ; mips16: .ent rot1 +; MM32: rotr $2, $4, 22 define i32 @rot1(i32 %a) nounwind readnone { entry: %shl = shl i32 %a, 10 @@ -24,6 +32,7 @@ entry: ; CHECK: rotrv $2, $4, $5 ; mips16: .ent rot2 +; MM32: rotrv $2, $4, $5 define i32 @rot2(i32 %a, i32 %b) nounwind readnone { entry: %shr = lshr i32 %a, %b @@ -35,6 +44,7 @@ entry: ; CHECK: rotr $2, $4, 10 ; mips16: .ent rot3 +; MM32: rotr $2, $4, 10 define i32 @rot3(i32 %a) nounwind readnone { entry: %shr = lshr i32 %a, 10 diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll index 96bd3782c058..0ef8f36333f2 100644 --- a/test/CodeGen/Mips/select.ll +++ b/test/CodeGen/Mips/select.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32 -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32 +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R2 +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R2 +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6 @d2 = external global double @d3 = external global double diff --git a/test/CodeGen/Mips/selectcc.ll b/test/CodeGen/Mips/selectcc.ll index 9790a0a3e411..865e4b38acad 100644 --- a/test/CodeGen/Mips/selectcc.ll +++ b/test/CodeGen/Mips/selectcc.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s -; RUN: llc -march=mipsel -mcpu=mips32 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s -; RUN: llc -march=mipsel -mcpu=mips32r2 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s +; RUN: llc -march=mipsel -mcpu=mips32 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED +; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s +; RUN: llc -march=mipsel -mcpu=mips32r2 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED @gf0 = external global float @gf1 = external global float diff --git a/test/CodeGen/Mips/selectiondag-optlevel.ll b/test/CodeGen/Mips/selectiondag-optlevel.ll new file mode 100644 index 000000000000..999361131745 --- /dev/null +++ b/test/CodeGen/Mips/selectiondag-optlevel.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=mips -fast-isel=false -O0 < %s 2>&1 | FileCheck %s -check-prefix=O0 +; RUN: llc -march=mips -fast-isel=false -O2 < %s 2>&1 | FileCheck %s -check-prefix=O2 + +; At -O0, DAGCombine won't try to merge these consecutive loads but it will at +; -O2. + +define void @foo() nounwind { +entry: + %0 = alloca [2 x i8], align 32 + %1 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 0 + store i8 1, i8* %1 + %2 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 1 + store i8 1, i8* %2 + ret void +} + +; O0: addiu $[[REG:[0-9]+]], $zero, 1 +; O0-DAG: sb $[[REG]], 0($sp) +; O0-DAG: sb $[[REG]], 1($sp) + +; O2: addiu $[[REG:[0-9]+]], $zero, 257 +; O2: sh $[[REG]], 0($sp) diff --git a/test/CodeGen/Mips/stackcoloring.ll b/test/CodeGen/Mips/stackcoloring.ll index 5516b5a3c023..817caee2f275 100644 --- a/test/CodeGen/Mips/stackcoloring.ll +++ b/test/CodeGen/Mips/stackcoloring.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s @g1 = external global i32* diff --git a/test/CodeGen/Mips/start-asm-file.ll b/test/CodeGen/Mips/start-asm-file.ll index 60c047a4e8cc..6d0a5425230a 100644 --- a/test/CodeGen/Mips/start-asm-file.ll +++ b/test/CodeGen/Mips/start-asm-file.ll @@ -3,53 +3,53 @@ ; ### O32 ABI ### ; RUN: llc -filetype=asm -mtriple mips-unknown-linux -mcpu=mips32 \ ; RUN: -relocation-model=static %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-O32 -check-prefix=CHECK-STATIC-O32-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-O32,CHECK-STATIC-O32-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips-unknown-linux -mcpu=mips32 \ ; RUN: -relocation-model=pic %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-O32 -check-prefix=CHECK-PIC-O32-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-O32,CHECK-PIC-O32-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips-unknown-linux -mcpu=mips32 \ ; RUN: -relocation-model=static -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-O32 -check-prefix=CHECK-STATIC-O32-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-O32,CHECK-STATIC-O32-N2008 %s ; RUN: llc -filetype=asm -mtriple mips-unknown-linux -mcpu=mips32 \ ; RUN: -relocation-model=pic -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-O32 -check-prefix=CHECK-PIC-O32-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-O32,CHECK-PIC-O32-N2008 %s ; ### N32 ABI ### ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=static -target-abi n32 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-N32 -check-prefix=CHECK-STATIC-N32-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-N32,CHECK-STATIC-N32-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=pic -target-abi n32 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-N32 -check-prefix=CHECK-PIC-N32-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-N32,CHECK-PIC-N32-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=static -target-abi n32 -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-N32 -check-prefix=CHECK-STATIC-N32-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-N32,CHECK-STATIC-N32-N2008 %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=pic -target-abi n32 -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-N32 -check-prefix=CHECK-PIC-N32-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-N32,CHECK-PIC-N32-N2008 %s ; ### N64 ABI ### ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=static -target-abi n64 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-N64 -check-prefix=CHECK-STATIC-N64-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-N64,CHECK-STATIC-N64-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=pic -target-abi n64 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-N64 -check-prefix=CHECK-PIC-N64-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-N64,CHECK-PIC-N64-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=static -target-abi n64 -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-N64 -check-prefix=CHECK-STATIC-N64-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-N64,CHECK-STATIC-N64-N2008 %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=pic -target-abi n64 -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-N64 -check-prefix=CHECK-PIC-N64-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-N64,CHECK-PIC-N64-N2008 %s ; CHECK-STATIC-O32: .abicalls ; CHECK-STATIC-O32: .option pic0 diff --git a/test/CodeGen/Mips/stchar.ll b/test/CodeGen/Mips/stchar.ll index 4b3c8fb79315..34493e9ae338 100644 --- a/test/CodeGen/Mips/stchar.ll +++ b/test/CodeGen/Mips/stchar.ll @@ -5,32 +5,8 @@ @sp = common global i16* null, align 4 @cp = common global i8* null, align 4 -define void @p1(i16 signext %s, i8 signext %c) nounwind { -entry: - %conv = sext i16 %s to i32 - %conv1 = sext i8 %c to i32 - %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv, i32 %conv1) nounwind - ret void -} - declare i32 @printf(i8* nocapture, ...) nounwind -define void @p2() nounwind { -entry: - %0 = load i16*, i16** @sp, align 4 - %1 = load i16, i16* %0, align 2 - %2 = load i8*, i8** @cp, align 4 - %3 = load i8, i8* %2, align 1 - %conv.i = sext i16 %1 to i32 - %conv1.i = sext i8 %3 to i32 - %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind - %4 = load i16*, i16** @sp, align 4 - store i16 32, i16* %4, align 2 - %5 = load i8*, i8** @cp, align 4 - store i8 97, i8* %5, align 1 - ret void -} - define void @test() nounwind { entry: %s = alloca i16, align 4 @@ -58,32 +34,6 @@ entry: ; 16_h: lh ${{[0-9]+}}, [[offset2]](${{[0-9]+}}) } -define i32 @main() nounwind { -entry: - %s.i = alloca i16, align 4 - %c.i = alloca i8, align 4 - %0 = bitcast i16* %s.i to i8* - call void @llvm.lifetime.start(i64 -1, i8* %0) nounwind - call void @llvm.lifetime.start(i64 -1, i8* %c.i) nounwind - store i16 16, i16* %s.i, align 4 - store i8 99, i8* %c.i, align 4 - store i16* %s.i, i16** @sp, align 4 - store i8* %c.i, i8** @cp, align 4 - %call.i.i.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 16, i32 99) nounwind - %1 = load i16*, i16** @sp, align 4 - store i16 32, i16* %1, align 2 - %2 = load i8*, i8** @cp, align 4 - store i8 97, i8* %2, align 1 - %3 = load i16, i16* %s.i, align 4 - %4 = load i8, i8* %c.i, align 4 - %conv.i.i = sext i16 %3 to i32 - %conv1.i.i = sext i8 %4 to i32 - %call.i.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv.i.i, i32 %conv1.i.i) nounwind - call void @llvm.lifetime.end(i64 -1, i8* %0) nounwind - call void @llvm.lifetime.end(i64 -1, i8* %c.i) nounwind - ret i32 0 -} - declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind diff --git a/test/CodeGen/Mips/stldst.ll b/test/CodeGen/Mips/stldst.ll index 8aecca4aed67..62d5f1f92b45 100644 --- a/test/CodeGen/Mips/stldst.ll +++ b/test/CodeGen/Mips/stldst.ll @@ -33,9 +33,9 @@ entry: %call7 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind ret i32 0 } -; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill -; 16: lw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Reload -; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill -; 16: lw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Reload +; 16: sw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Spill +; 16: lw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Reload +; 16: sw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Spill +; 16: lw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Reload declare i32 @printf(i8* nocapture, ...) nounwind diff --git a/test/CodeGen/Mips/tailcall.ll b/test/CodeGen/Mips/tailcall.ll index b0868255053a..61f8e508f40d 100644 --- a/test/CodeGen/Mips/tailcall.ll +++ b/test/CodeGen/Mips/tailcall.ll @@ -1,11 +1,12 @@ -; RUN: llc -march=mipsel -relocation-model=pic -enable-mips-tail-calls < %s | \ -; RUN: FileCheck %s -check-prefix=PIC32 -; RUN: llc -march=mipsel -relocation-model=static \ -; RUN: -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=STATIC32 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+n64 -enable-mips-tail-calls \ -; RUN: < %s | FileCheck %s -check-prefix=N64 +; RUN: llc -march=mipsel -relocation-model=pic -enable-mips-tail-calls \ +; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=PIC32 +; RUN: llc -march=mipsel -relocation-model=static -enable-mips-tail-calls \ +; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=STATIC32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -enable-mips-tail-calls \ +; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=N64 ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic \ -; RUN: -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=PIC16 +; RUN: -enable-mips-tail-calls -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefix=PIC16 @g0 = common global i32 0, align 4 @g1 = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/thread-pointer.ll b/test/CodeGen/Mips/thread-pointer.ll new file mode 100644 index 000000000000..60bee3d03031 --- /dev/null +++ b/test/CodeGen/Mips/thread-pointer.ll @@ -0,0 +1,12 @@ +; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips64 < %s | FileCheck %s +; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mips64el < %s | FileCheck %s + +declare i8* @llvm.thread.pointer() nounwind readnone + +define i8* @thread_pointer() { +; CHECK: rdhwr $3, $29 + %1 = tail call i8* @llvm.thread.pointer() + ret i8* %1 +} diff --git a/test/CodeGen/Mips/tls-models.ll b/test/CodeGen/Mips/tls-models.ll index 1a958dceaa28..ca3c7fde19d4 100644 --- a/test/CodeGen/Mips/tls-models.ll +++ b/test/CodeGen/Mips/tls-models.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=CHECK-PIC %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck -check-prefix=CHECK-PIC %s ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck -check-prefix=CHECK-NONPIC %s @external_gd = external thread_local global i32 diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll index 97e270fc59a6..8968567cb423 100644 --- a/test/CodeGen/Mips/tls.ll +++ b/test/CodeGen/Mips/tls.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -disable-mips-delay-filler < %s | \ -; RUN: FileCheck %s -check-prefix=PIC -check-prefix=CHECK +; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=PIC,CHECK ; RUN: llc -march=mipsel -relocation-model=static -disable-mips-delay-filler < \ -; RUN: %s | FileCheck %s -check-prefix=STATIC -check-prefix=CHECK +; RUN: %s | FileCheck %s -check-prefixes=STATIC,CHECK ; RUN: llc -march=mipsel -relocation-model=static -disable-mips-delay-filler \ ; RUN: -mips-fix-global-base-reg=false < %s | \ -; RUN: FileCheck %s -check-prefix=STATICGP -check-prefix=CHECK +; RUN: FileCheck %s -check-prefixes=STATICGP,CHECK @t1 = thread_local global i32 0, align 4 diff --git a/test/CodeGen/Mips/unalignedload.ll b/test/CodeGen/Mips/unalignedload.ll index 9e453a6e794b..ba476b6c4554 100644 --- a/test/CodeGen/Mips/unalignedload.ll +++ b/test/CodeGen/Mips/unalignedload.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32-EL -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32-EB -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32-EL -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32-EB -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32R6-EL -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32R6-EB +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32-EL +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32-EB +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32-EL +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32-EB +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32R6-EL +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32R6-EB %struct.S2 = type { %struct.S1, %struct.S1 } %struct.S1 = type { i8, i8 } %struct.S4 = type { [7 x i8] } diff --git a/test/CodeGen/Mips/zeroreg.ll b/test/CodeGen/Mips/zeroreg.ll index 6baf9d4fbff2..c024d04a39b0 100644 --- a/test/CodeGen/Mips/zeroreg.ll +++ b/test/CodeGen/Mips/zeroreg.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -; RUN: llc < %s -march=mipsel -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6 +; RUN: llc < %s -march=mipsel -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc < %s -march=mipsel -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc < %s -march=mipsel -mcpu=mips64r2 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6 @g1 = external global i32 |