diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2015-12-30 11:46:15 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-12-30 11:46:15 +0000 |
| commit | dd58ef019b700900793a1eb48b52123db01b654e (patch) | |
| tree | fcfbb4df56a744f4ddc6122c50521dd3f1c5e196 /test/CodeGen/PowerPC/stack-realign.ll | |
| parent | 2fe5752e3a7c345cdb59e869278d36af33c13fa4 (diff) | |
Notes
Diffstat (limited to 'test/CodeGen/PowerPC/stack-realign.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/stack-realign.ll | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/test/CodeGen/PowerPC/stack-realign.ll b/test/CodeGen/PowerPC/stack-realign.ll index e91b563af72e..1c93d665c16d 100644 --- a/test/CodeGen/PowerPC/stack-realign.ll +++ b/test/CodeGen/PowerPC/stack-realign.ll @@ -29,7 +29,7 @@ entry: ; CHECK-LABEL: @goo -; CHECK-DAG: mflr 0 +; CHECK-DAG: mflr {{[0-9]+}} ; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-DAG: std 30, -16(1) ; CHECK-DAG: mr 30, 1 @@ -44,14 +44,14 @@ entry: ; CHECK: std 3, 48(30) ; CHECK: ld 1, 0(1) -; CHECK-DAG: ld 0, 16(1) +; CHECK-DAG: ld [[SR:[0-9]+]], 16(1) ; CHECK-DAG: ld 30, -16(1) -; CHECK-DAG: mtlr 0 +; CHECK-DAG: mtlr [[SR]] ; CHECK: blr ; CHECK-FP-LABEL: @goo -; CHECK-FP-DAG: mflr 0 +; CHECK-FP-DAG: mflr {{[0-9]+}} ; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-FP-DAG: std 31, -8(1) ; CHECK-FP-DAG: std 30, -16(1) @@ -70,14 +70,14 @@ entry: ; CHECK-FP: std 3, 48(30) ; CHECK-FP: ld 1, 0(1) -; CHECK-FP-DAG: ld 0, 16(1) +; CHECK-FP-DAG: ld [[SR:[0-9]+]], 16(1) ; CHECK-FP-DAG: ld 31, -8(1) ; CHECK-FP-DAG: ld 30, -16(1) -; CHECK-FP-DAG: mtlr 0 +; CHECK-FP-DAG: mtlr [[SR]] ; CHECK-FP: blr ; CHECK-32-LABEL: @goo -; CHECK-32-DAG: mflr 0 +; CHECK-32-DAG: mflr {{[0-9]+}} ; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27 ; CHECK-32-DAG: stw 30, -8(1) ; CHECK-32-DAG: mr 30, 1 @@ -86,7 +86,7 @@ entry: ; CHECK-32: stwux 1, 1, 0 ; CHECK-32-PIC-LABEL: @goo -; CHECK-32-PIC-DAG: mflr 0 +; CHECK-32-PIC-DAG: mflr {{[0-9]+}} ; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27 ; CHECK-32-PIC-DAG: stw 29, -12(1) ; CHECK-32-PIC-DAG: mr 29, 1 @@ -114,7 +114,7 @@ entry: ; CHECK-DAG: lis [[REG1:[0-9]+]], -13 ; CHECK-DAG: clrldi [[REG3:[0-9]+]], 1, 59 -; CHECK-DAG: mflr 0 +; CHECK-DAG: mflr {{[0-9]+}} ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808 ; CHECK-DAG: std 30, -16(1) ; CHECK-DAG: mr 30, 1 @@ -130,7 +130,7 @@ entry: ; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13 ; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27 -; CHECK-32-DAG: mflr 0 +; CHECK-32-DAG: mflr {{[0-9]+}} ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904 ; CHECK-32-DAG: stw 30, -8(1) ; CHECK-32-DAG: mr 30, 1 @@ -144,7 +144,7 @@ entry: ; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13 ; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27 -; CHECK-32-PIC-DAG: mflr 0 +; CHECK-32-PIC-DAG: mflr {{[0-9]+}} ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904 ; CHECK-32-PIC-DAG: stw 29, -12(1) ; CHECK-32-PIC-DAG: mr 29, 1 @@ -174,7 +174,7 @@ entry: ; CHECK-LABEL: @loo -; CHECK-DAG: mflr 0 +; CHECK-DAG: mflr {{[0-9]+}} ; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-DAG: std 30, -32(1) ; CHECK-DAG: mr 30, 1 @@ -190,7 +190,7 @@ entry: ; CHECK-FP-LABEL: @loo -; CHECK-FP-DAG: mflr 0 +; CHECK-FP-DAG: mflr {{[0-9]+}} ; CHECK-FP-DAG: clrldi [[REG:[0-9]+]], 1, 59 ; CHECK-FP-DAG: std 31, -24(1) ; CHECK-FP-DAG: std 30, -32(1) |