vendor/llvm/llvm-release_371-r255217

10 files changed, 2466 insertions, 0 deletions

diff --git a/test/CodeGen/PowerPC/ctr-loop-tls-const.ll b/test/CodeGen/PowerPC/ctr-loop-tls-const.ll
new file mode 100644
index 000000000000..01f837cb9933
--- /dev/null
+++ b/test/CodeGen/PowerPC/ctr-loop-tls-const.ll
@@ -0,0 +1,40 @@
+; RUN: llc -mcpu=pwr7 -relocation-model=pic < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+@x = thread_local global [1600 x i32] zeroinitializer, align 4
+
+; Function Attrs: nounwind
+define void @foo(i32 signext %v) #0 {
+entry:
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %entry
+  %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
+  %induction5 = or i64 %index, 1
+  %0 = getelementptr inbounds [1600 x i32], [1600 x i32]* @x, i64 0, i64 %index
+  %1 = getelementptr inbounds [1600 x i32], [1600 x i32]* @x, i64 0, i64 %induction5
+  %2 = load i32, i32* %0, align 4
+  %3 = load i32, i32* %1, align 4
+  %4 = add nsw i32 %2, %v
+  %5 = add nsw i32 %3, %v
+  store i32 %4, i32* %0, align 4
+  store i32 %5, i32* %1, align 4
+  %index.next = add i64 %index, 2
+  %6 = icmp eq i64 %index.next, 1600
+  br i1 %6, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup:                                 ; preds = %vector.body
+  ret void
+}
+
+; CHECK-LABEL: @foo
+; CHECK-NOT: mtctr
+; CHECK: __tls_get_addr
+
+attributes #0 = { nounwind }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 1, !"PIC Level", i32 2}
+
diff --git a/test/CodeGen/PowerPC/ctrloop-intrin.ll b/test/CodeGen/PowerPC/ctrloop-intrin.ll
new file mode 100644
index 000000000000..7c781cd15e41
--- /dev/null
+++ b/test/CodeGen/PowerPC/ctrloop-intrin.ll
@@ -0,0 +1,349 @@
+; RUN: llc < %s
+; ModuleID = 'new.bc'
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le--linux-gnu"
+
+@.str.87 = external hidden unnamed_addr constant [5 x i8], align 1
+@.str.1.88 = external hidden unnamed_addr constant [4 x i8], align 1
+@.str.2.89 = external hidden unnamed_addr constant [5 x i8], align 1
+@.str.3.90 = external hidden unnamed_addr constant [4 x i8], align 1
+@.str.4.91 = external hidden unnamed_addr constant [14 x i8], align 1
+@.str.5.92 = external hidden unnamed_addr constant [13 x i8], align 1
+@.str.6.93 = external hidden unnamed_addr constant [10 x i8], align 1
+@.str.7.94 = external hidden unnamed_addr constant [9 x i8], align 1
+@.str.8.95 = external hidden unnamed_addr constant [2 x i8], align 1
+@.str.9.96 = external hidden unnamed_addr constant [2 x i8], align 1
+@.str.10.97 = external hidden unnamed_addr constant [3 x i8], align 1
+@.str.11.98 = external hidden unnamed_addr constant [3 x i8], align 1
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.start(i64, i8* nocapture) #0
+
+; Function Attrs: nounwind
+declare void @llvm.lifetime.end(i64, i8* nocapture) #0
+
+; Function Attrs: nounwind
+declare i8* @halide_string_to_string(i8*, i8*, i8*) #1
+
+; Function Attrs: nounwind
+declare i8* @halide_int64_to_string(i8*, i8*, i64, i32) #1
+
+; Function Attrs: nounwind
+define weak i8* @halide_double_to_string(i8* %dst, i8* %end, double %arg, i32 %scientific) #1 {
+entry:
+  %arg.addr = alloca double, align 8
+  %bits = alloca i64, align 8
+  %buf = alloca [512 x i8], align 1
+  store double %arg, double* %arg.addr, align 8, !tbaa !4
+  %0 = bitcast i64* %bits to i8*
+  call void @llvm.lifetime.start(i64 8, i8* %0) #0
+  store i64 0, i64* %bits, align 8, !tbaa !8
+  %1 = bitcast double* %arg.addr to i8*
+  %call = call i8* @memcpy(i8* %0, i8* %1, i64 8) #2
+  %2 = load i64, i64* %bits, align 8, !tbaa !8
+  %and = and i64 %2, 4503599627370495
+  %shr = lshr i64 %2, 52
+  %shr.tr = trunc i64 %shr to i32
+  %conv = and i32 %shr.tr, 2047
+  %shr2 = lshr i64 %2, 63
+  %conv3 = trunc i64 %shr2 to i32
+  %cmp = icmp eq i32 %conv, 2047
+  br i1 %cmp, label %if.then, label %if.else.15
+
+if.then:                                          ; preds = %entry
+  %tobool = icmp eq i64 %and, 0
+  %tobool5 = icmp ne i32 %conv3, 0
+  br i1 %tobool, label %if.else.9, label %if.then.4
+
+if.then.4:                                        ; preds = %if.then
+  br i1 %tobool5, label %if.then.6, label %if.else
+
+if.then.6:                                        ; preds = %if.then.4
+  %call7 = call i8* @halide_string_to_string(i8* %dst, i8* %end, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str.87, i64 0, i64 0)) #3
+  br label %cleanup.148
+
+if.else:                                          ; preds = %if.then.4
+  %call8 = call i8* @halide_string_to_string(i8* %dst, i8* %end, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.1.88, i64 0, i64 0)) #3
+  br label %cleanup.148
+
+if.else.9:                                        ; preds = %if.then
+  br i1 %tobool5, label %if.then.11, label %if.else.13
+
+if.then.11:                                       ; preds = %if.else.9
+  %call12 = call i8* @halide_string_to_string(i8* %dst, i8* %end, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str.2.89, i64 0, i64 0)) #3
+  br label %cleanup.148
+
+if.else.13:                                       ; preds = %if.else.9
+  %call14 = call i8* @halide_string_to_string(i8* %dst, i8* %end, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str.3.90, i64 0, i64 0)) #3
+  br label %cleanup.148
+
+if.else.15:                                       ; preds = %entry
+  %cmp16 = icmp eq i32 %conv, 0
+  %cmp17 = icmp eq i64 %and, 0
+  %or.cond = and i1 %cmp17, %cmp16
+  br i1 %or.cond, label %if.then.18, label %if.end.32
+
+if.then.18:                                       ; preds = %if.else.15
+  %tobool19 = icmp eq i32 %scientific, 0
+  %tobool21 = icmp ne i32 %conv3, 0
+  br i1 %tobool19, label %if.else.26, label %if.then.20
+
+if.then.20:                                       ; preds = %if.then.18
+  br i1 %tobool21, label %if.then.22, label %if.else.24
+
+if.then.22:                                       ; preds = %if.then.20
+  %call23 = call i8* @halide_string_to_string(i8* %dst, i8* %end, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str.4.91, i64 0, i64 0)) #3
+  br label %cleanup.148
+
+if.else.24:                                       ; preds = %if.then.20
+  %call25 = call i8* @halide_string_to_string(i8* %dst, i8* %end, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.5.92, i64 0, i64 0)) #3
+  br label %cleanup.148
+
+if.else.26:                                       ; preds = %if.then.18
+  br i1 %tobool21, label %if.then.28, label %if.else.30
+
+if.then.28:                                       ; preds = %if.else.26
+  %call29 = call i8* @halide_string_to_string(i8* %dst, i8* %end, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str.6.93, i64 0, i64 0)) #3
+  br label %cleanup.148
+
+if.else.30:                                       ; preds = %if.else.26
+  %call31 = call i8* @halide_string_to_string(i8* %dst, i8* %end, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str.7.94, i64 0, i64 0)) #3
+  br label %cleanup.148
+
+if.end.32:                                        ; preds = %if.else.15
+  %tobool33 = icmp eq i32 %conv3, 0
+  br i1 %tobool33, label %if.end.37, label %if.then.34
+
+if.then.34:                                       ; preds = %if.end.32
+  %call35 = call i8* @halide_string_to_string(i8* %dst, i8* %end, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.8.95, i64 0, i64 0)) #3
+  %sub36 = fsub double -0.000000e+00, %arg
+  store double %sub36, double* %arg.addr, align 8, !tbaa !4
+  br label %if.end.37
+
+if.end.37:                                        ; preds = %if.then.34, %if.end.32
+  %.pr = phi double [ %sub36, %if.then.34 ], [ %arg, %if.end.32 ]
+  %dst.addr.0 = phi i8* [ %call35, %if.then.34 ], [ %dst, %if.end.32 ]
+  %tobool38 = icmp eq i32 %scientific, 0
+  br i1 %tobool38, label %if.else.62, label %while.condthread-pre-split
+
+while.condthread-pre-split:                       ; preds = %if.end.37
+  %cmp40.261 = fcmp olt double %.pr, 1.000000e+00
+  br i1 %cmp40.261, label %while.body, label %while.cond.41thread-pre-split
+
+while.body:                                       ; preds = %while.body, %while.condthread-pre-split
+  %exponent_base_10.0262 = phi i32 [ %dec, %while.body ], [ 0, %while.condthread-pre-split ]
+  %3 = phi double [ %mul, %while.body ], [ %.pr, %while.condthread-pre-split ]
+  %mul = fmul double %3, 1.000000e+01
+  %dec = add nsw i32 %exponent_base_10.0262, -1
+  %cmp40 = fcmp olt double %mul, 1.000000e+00
+  br i1 %cmp40, label %while.body, label %while.cond.while.cond.41thread-pre-split_crit_edge
+
+while.cond.while.cond.41thread-pre-split_crit_edge: ; preds = %while.body
+  store double %mul, double* %arg.addr, align 8, !tbaa !4
+  br label %while.cond.41thread-pre-split
+
+while.cond.41thread-pre-split:                    ; preds = %while.cond.while.cond.41thread-pre-split_crit_edge, %while.condthread-pre-split
+  %.pr246 = phi double [ %mul, %while.cond.while.cond.41thread-pre-split_crit_edge ], [ %.pr, %while.condthread-pre-split ]
+  %exponent_base_10.0.lcssa = phi i32 [ %dec, %while.cond.while.cond.41thread-pre-split_crit_edge ], [ 0, %while.condthread-pre-split ]
+  %cmp42.257 = fcmp ult double %.pr246, 1.000000e+01
+  br i1 %cmp42.257, label %while.end.44, label %while.body.43
+
+while.body.43:                                    ; preds = %while.body.43, %while.cond.41thread-pre-split
+  %exponent_base_10.1258 = phi i32 [ %inc, %while.body.43 ], [ %exponent_base_10.0.lcssa, %while.cond.41thread-pre-split ]
+  %4 = phi double [ %div, %while.body.43 ], [ %.pr246, %while.cond.41thread-pre-split ]
+  %div = fdiv double %4, 1.000000e+01
+  %inc = add nsw i32 %exponent_base_10.1258, 1
+  %cmp42 = fcmp ult double %div, 1.000000e+01
+  br i1 %cmp42, label %while.cond.41.while.end.44_crit_edge, label %while.body.43
+
+while.cond.41.while.end.44_crit_edge:             ; preds = %while.body.43
+  store double %div, double* %arg.addr, align 8, !tbaa !4
+  br label %while.end.44
+
+while.end.44:                                     ; preds = %while.cond.41.while.end.44_crit_edge, %while.cond.41thread-pre-split
+  %exponent_base_10.1.lcssa = phi i32 [ %inc, %while.cond.41.while.end.44_crit_edge ], [ %exponent_base_10.0.lcssa, %while.cond.41thread-pre-split ]
+  %.lcssa = phi double [ %div, %while.cond.41.while.end.44_crit_edge ], [ %.pr246, %while.cond.41thread-pre-split ]
+  %mul45 = fmul double %.lcssa, 1.000000e+06
+  %add = fadd double %mul45, 5.000000e-01
+  %conv46 = fptoui double %add to i64
+  %div47 = udiv i64 %conv46, 1000000
+  %5 = mul i64 %div47, -1000000
+  %sub49 = add i64 %conv46, %5
+  %call50 = call i8* @halide_int64_to_string(i8* %dst.addr.0, i8* %end, i64 %div47, i32 1) #3
+  %call51 = call i8* @halide_string_to_string(i8* %call50, i8* %end, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.9.96, i64 0, i64 0)) #3
+  %call52 = call i8* @halide_int64_to_string(i8* %call51, i8* %end, i64 %sub49, i32 6) #3
+  %cmp53 = icmp sgt i32 %exponent_base_10.1.lcssa, -1
+  br i1 %cmp53, label %if.then.54, label %if.else.56
+
+if.then.54:                                       ; preds = %while.end.44
+  %call55 = call i8* @halide_string_to_string(i8* %call52, i8* %end, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str.10.97, i64 0, i64 0)) #3
+  br label %if.end.59
+
+if.else.56:                                       ; preds = %while.end.44
+  %call57 = call i8* @halide_string_to_string(i8* %call52, i8* %end, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str.11.98, i64 0, i64 0)) #3
+  %sub58 = sub nsw i32 0, %exponent_base_10.1.lcssa
+  br label %if.end.59
+
+if.end.59:                                        ; preds = %if.else.56, %if.then.54
+  %exponent_base_10.2 = phi i32 [ %exponent_base_10.1.lcssa, %if.then.54 ], [ %sub58, %if.else.56 ]
+  %dst.addr.1 = phi i8* [ %call55, %if.then.54 ], [ %call57, %if.else.56 ]
+  %conv60 = sext i32 %exponent_base_10.2 to i64
+  %call61 = call i8* @halide_int64_to_string(i8* %dst.addr.1, i8* %end, i64 %conv60, i32 2) #3
+  br label %cleanup.148
+
+if.else.62:                                       ; preds = %if.end.37
+  br i1 %cmp16, label %if.then.64, label %if.end.66
+
+if.then.64:                                       ; preds = %if.else.62
+  %call65 = call i8* @halide_double_to_string(i8* %dst.addr.0, i8* %end, double 0.000000e+00, i32 0) #3
+  br label %cleanup.148
+
+if.end.66:                                        ; preds = %if.else.62
+  %add68 = or i64 %and, 4503599627370496
+  %sub70 = add nsw i32 %conv, -1075
+  %cmp71 = icmp ult i32 %conv, 1075
+  br i1 %cmp71, label %if.then.72, label %if.end.105
+
+if.then.72:                                       ; preds = %if.end.66
+  %cmp73 = icmp slt i32 %sub70, -52
+  br i1 %cmp73, label %if.end.84, label %if.else.76
+
+if.else.76:                                       ; preds = %if.then.72
+  %sub77 = sub nsw i32 1075, %conv
+  %sh_prom = zext i32 %sub77 to i64
+  %shr78 = lshr i64 %add68, %sh_prom
+  %shl81 = shl i64 %shr78, %sh_prom
+  %sub82 = sub i64 %add68, %shl81
+  br label %if.end.84
+
+if.end.84:                                        ; preds = %if.else.76, %if.then.72
+  %integer_part.0 = phi i64 [ %shr78, %if.else.76 ], [ 0, %if.then.72 ]
+  %f.0.in = phi i64 [ %sub82, %if.else.76 ], [ %add68, %if.then.72 ]
+  %f.0 = uitofp i64 %f.0.in to double
+  %conv85.244 = zext i32 %sub70 to i64
+  %shl86 = shl i64 %conv85.244, 52
+  %add88 = add i64 %shl86, 4696837146684686336
+  %6 = bitcast i64 %add88 to double
+  %mul90 = fmul double %6, %f.0
+  %add91 = fadd double %mul90, 5.000000e-01
+  %conv92 = fptoui double %add91 to i64
+  %conv93 = uitofp i64 %conv92 to double
+  %and96 = and i64 %conv92, 1
+  %notlhs = fcmp oeq double %conv93, %add91
+  %notrhs = icmp ne i64 %and96, 0
+  %not.or.cond245 = and i1 %notrhs, %notlhs
+  %dec99 = sext i1 %not.or.cond245 to i64
+  %fractional_part.0 = add i64 %dec99, %conv92
+  %cmp101 = icmp eq i64 %fractional_part.0, 1000000
+  %inc103 = zext i1 %cmp101 to i64
+  %inc103.integer_part.0 = add i64 %inc103, %integer_part.0
+  %.fractional_part.0 = select i1 %cmp101, i64 0, i64 %fractional_part.0
+  br label %if.end.105
+
+if.end.105:                                       ; preds = %if.end.84, %if.end.66
+  %integer_part.2 = phi i64 [ %inc103.integer_part.0, %if.end.84 ], [ %add68, %if.end.66 ]
+  %integer_exponent.0 = phi i32 [ 0, %if.end.84 ], [ %sub70, %if.end.66 ]
+  %fractional_part.2 = phi i64 [ %.fractional_part.0, %if.end.84 ], [ 0, %if.end.66 ]
+  %7 = bitcast [512 x i8]* %buf to i8*
+  call void @llvm.lifetime.start(i64 512, i8* %7) #0
+  %add.ptr = getelementptr inbounds [512 x i8], [512 x i8]* %buf, i64 0, i64 512
+  %add.ptr106 = getelementptr inbounds [512 x i8], [512 x i8]* %buf, i64 0, i64 480
+  %call109 = call i8* @halide_int64_to_string(i8* %add.ptr106, i8* %add.ptr, i64 %integer_part.2, i32 1) #3
+  %cmp110.252 = icmp sgt i32 %integer_exponent.0, 0
+  br i1 %cmp110.252, label %for.cond.112.preheader, label %for.cond.cleanup
+
+for.cond.112.preheader:                           ; preds = %if.end.138, %if.end.105
+  %i.0255 = phi i32 [ %inc140, %if.end.138 ], [ 0, %if.end.105 ]
+  %int_part_ptr.0253 = phi i8* [ %int_part_ptr.1, %if.end.138 ], [ %add.ptr106, %if.end.105 ]
+  %int_part_ptr.02534 = ptrtoint i8* %int_part_ptr.0253 to i64
+  %cmp114.249 = icmp eq i8* %call109, %int_part_ptr.0253
+  br i1 %cmp114.249, label %if.end.138, label %for.body.116.preheader
+
+for.body.116.preheader:                           ; preds = %for.cond.112.preheader
+  %8 = sub i64 0, %int_part_ptr.02534
+  %scevgep5 = getelementptr i8, i8* %call109, i64 %8
+  %scevgep56 = ptrtoint i8* %scevgep5 to i64
+  call void @llvm.ppc.mtctr.i64(i64 %scevgep56)
+  br label %for.body.116
+
+for.cond.cleanup:                                 ; preds = %if.end.138, %if.end.105
+  %int_part_ptr.0.lcssa = phi i8* [ %add.ptr106, %if.end.105 ], [ %int_part_ptr.1, %if.end.138 ]
+  %9 = bitcast [512 x i8]* %buf to i8*
+  %call142 = call i8* @halide_string_to_string(i8* %dst.addr.0, i8* %end, i8* %int_part_ptr.0.lcssa) #3
+  %call143 = call i8* @halide_string_to_string(i8* %call142, i8* %end, i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.9.96, i64 0, i64 0)) #3
+  %call144 = call i8* @halide_int64_to_string(i8* %call143, i8* %end, i64 %fractional_part.2, i32 6) #3
+  call void @llvm.lifetime.end(i64 512, i8* %9) #0
+  br label %cleanup.148
+
+for.cond.cleanup.115:                             ; preds = %for.body.116
+  br i1 %cmp125, label %if.then.136, label %if.end.138
+
+for.body.116:                                     ; preds = %for.body.116, %for.body.116.preheader
+  %call109.pn = phi i8* [ %p.0251, %for.body.116 ], [ %call109, %for.body.116.preheader ]
+  %carry.0250 = phi i32 [ %carry.1, %for.body.116 ], [ 0, %for.body.116.preheader ]
+  %call109.pn2 = ptrtoint i8* %call109.pn to i64
+  %p.0251 = getelementptr inbounds i8, i8* %call109.pn, i64 -1
+  %scevgep3 = getelementptr i8, i8* inttoptr (i64 -1 to i8*), i64 %call109.pn2
+  %10 = load i8, i8* %scevgep3, align 1, !tbaa !10
+  %sub118 = add i8 %10, -48
+  %conv120 = sext i8 %sub118 to i32
+  %mul121 = shl nsw i32 %conv120, 1
+  %add122 = or i32 %mul121, %carry.0250
+  %11 = trunc i32 %add122 to i8
+  %cmp125 = icmp sgt i8 %11, 9
+  %sub128 = add nsw i32 %add122, 246
+  %carry.1 = zext i1 %cmp125 to i32
+  %new_digit.0.in = select i1 %cmp125, i32 %sub128, i32 %add122
+  %add133 = add nsw i32 %new_digit.0.in, 48
+  %conv134 = trunc i32 %add133 to i8
+  %scevgep = getelementptr i8, i8* inttoptr (i64 -1 to i8*), i64 %call109.pn2
+  store i8 %conv134, i8* %scevgep, align 1, !tbaa !10
+  %12 = call i1 @llvm.ppc.is.decremented.ctr.nonzero()
+  br i1 %12, label %for.body.116, label %for.cond.cleanup.115
+
+if.then.136:                                      ; preds = %for.cond.cleanup.115
+  %incdec.ptr137 = getelementptr inbounds i8, i8* %int_part_ptr.0253, i64 -1
+  store i8 49, i8* %incdec.ptr137, align 1, !tbaa !10
+  br label %if.end.138
+
+if.end.138:                                       ; preds = %if.then.136, %for.cond.cleanup.115, %for.cond.112.preheader
+  %int_part_ptr.1 = phi i8* [ %incdec.ptr137, %if.then.136 ], [ %call109, %for.cond.112.preheader ], [ %int_part_ptr.0253, %for.cond.cleanup.115 ]
+  %inc140 = add nuw nsw i32 %i.0255, 1
+  %exitcond = icmp eq i32 %inc140, %integer_exponent.0
+  br i1 %exitcond, label %for.cond.cleanup, label %for.cond.112.preheader
+
+cleanup.148:                                      ; preds = %for.cond.cleanup, %if.then.64, %if.end.59, %if.else.30, %if.then.28, %if.else.24, %if.then.22, %if.else.13, %if.then.11, %if.else, %if.then.6
+  %retval.1 = phi i8* [ %call7, %if.then.6 ], [ %call8, %if.else ], [ %call12, %if.then.11 ], [ %call14, %if.else.13 ], [ %call23, %if.then.22 ], [ %call25, %if.else.24 ], [ %call29, %if.then.28 ], [ %call31, %if.else.30 ], [ %call65, %if.then.64 ], [ %call61, %if.end.59 ], [ %call144, %for.cond.cleanup ]
+  %13 = bitcast i64* %bits to i8*
+  call void @llvm.lifetime.end(i64 8, i8* %13) #0
+  ret i8* %retval.1
+}
+
+; Function Attrs: nounwind
+declare i8* @memcpy(i8*, i8* nocapture readonly, i64) #1
+
+; Function Attrs: nounwind
+declare void @llvm.ppc.mtctr.i64(i64) #0
+
+; Function Attrs: nounwind
+declare i1 @llvm.ppc.is.decremented.ctr.nonzero() #0
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind }
+attributes #3 = { nounwind }
+
+!llvm.ident = !{!0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0, !0}
+!llvm.module.flags = !{!1, !2, !3}
+
+!0 = !{!"clang version 3.7.0 (branches/release_37 246867) (llvm/branches/release_37 246866)"}
+!1 = !{i32 2, !"halide_use_soft_float_abi", i32 0}
+!2 = !{i32 2, !"halide_mcpu", !"pwr8"}
+!3 = !{i32 2, !"halide_mattrs", !"+altivec,+vsx,+power8-altivec,+direct-move"}
+!4 = !{!5, !5, i64 0}
+!5 = !{!"double", !6, i64 0}
+!6 = !{!"omnipotent char", !7, i64 0}
+!7 = !{!"Simple C/C++ TBAA"}
+!8 = !{!9, !9, i64 0}
+!9 = !{!"long long", !6, i64 0}
+!10 = !{!6, !6, i64 0}
diff --git a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
new file mode 100644
index 000000000000..5c998d09a3db
--- /dev/null
+++ b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
@@ -0,0 +1,92 @@
+# RUN: llc -start-after=dead-mi-elimination -stop-after=twoaddressinstruction -o /dev/null %s | FileCheck %s
+
+--- |
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+  
+  @d = global i32 15, align 4
+  @b = global i32* @d, align 8
+  @a = common global i32 0, align 4
+  
+  ; Function Attrs: nounwind
+  define signext i32 @main() #0 {
+  entry:
+    %0 = load i32*, i32** @b, align 8
+    %1 = load i32, i32* @a, align 4
+    %lnot = icmp eq i32 %1, 0
+    %lnot.ext = zext i1 %lnot to i32
+    %shr.i = lshr i32 2072, %lnot.ext
+    %call.lobit = lshr i32 %shr.i, 7
+    %2 = and i32 %call.lobit, 1
+    %3 = load i32, i32* %0, align 4
+    %or = or i32 %2, %3
+    store i32 %or, i32* %0, align 4
+    %4 = load i32, i32* @a, align 4
+    %lnot.1 = icmp eq i32 %4, 0
+    %lnot.ext.1 = zext i1 %lnot.1 to i32
+    %shr.i.1 = lshr i32 2072, %lnot.ext.1
+    %call.lobit.1 = lshr i32 %shr.i.1, 7
+    %5 = and i32 %call.lobit.1, 1
+    %or.1 = or i32 %5, %or
+    store i32 %or.1, i32* %0, align 4
+    ret i32 %or.1
+  }
+  
+  attributes #0 = { nounwind "target-cpu"="ppc64" }
+
+...
+---
+name:            main
+alignment:       2
+exposesReturnsTwice: false
+hasInlineAsm:    false
+isSSA:           true
+tracksRegLiveness: true
+tracksSubRegLiveness: false
+registers:       
+  - { id: 0, class: g8rc_and_g8rc_nox0 }
+  - { id: 1, class: g8rc_and_g8rc_nox0 }
+  - { id: 2, class: gprc }
+  - { id: 3, class: gprc }
+  - { id: 4, class: gprc }
+  - { id: 5, class: g8rc_and_g8rc_nox0 }
+  - { id: 6, class: g8rc_and_g8rc_nox0 }
+  - { id: 7, class: gprc }
+  - { id: 8, class: gprc }
+  - { id: 9, class: gprc }
+  - { id: 10, class: g8rc }
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.entry:
+    liveins: %x2
+
+    %0 = ADDIStocHA %x2, @b
+    %1 = LD target-flags(ppc-toc-lo) @b, killed %0 :: (load 8 from @b)
+    %2 = LWZ 0, %1 :: (load 4 from %ir.0)
+    %3 = LI 0
+    %4 = RLWIMI %3, killed %2, 0, 0, 31
+    ; CHECK-LABEL: name: main
+    ; CHECK: %[[REG1:[0-9]+]] = LI 0
+    ; CHECK: %[[REG2:[0-9]+]] = COPY %[[REG1]]
+    ; CHECK: %[[REG2]] = RLWIMI %[[REG2]], killed %2, 0, 0, 31
+    %8 = RLWIMI %3, %4, 0, 0, 31
+    STW %4, 0, %1 :: (store 4 into %ir.0)
+    %10 = EXTSW_32_64 %8
+    STW %8, 0, %1 :: (store 4 into %ir.0)
+    %x3 = COPY %10
+    BLR8 implicit %x3, implicit %lr8, implicit %rm
+
+...
diff --git a/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll b/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
new file mode 100644
index 000000000000..052f55644fe2
--- /dev/null
+++ b/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define <2 x i32> @test1(<4 x i32> %wide.vec) #0 {
+entry:
+  %strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
+  ret <2 x i32> %strided.vec
+
+; CHECK-LABEL: @test1
+; CHECK: vsldoi 2, 2, 2, 12
+; CHECK: blr
+}
+
+; Function Attrs: nounwind
+define <16 x i8> @test2(<16 x i8> %wide.vec) #0 {
+entry:
+  %strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 11>
+  ret <16 x i8> %strided.vec
+
+; CHECK-LABEL: @test2
+; CHECK: vsldoi 2, 2, 2, 12
+; CHECK: blr
+}
+
+attributes #0 = { nounwind "target-cpu"="pwr7" }
+
diff --git a/test/CodeGen/PowerPC/pr24546.ll b/test/CodeGen/PowerPC/pr24546.ll
new file mode 100644
index 000000000000..3bb638af2343
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr24546.ll
@@ -0,0 +1,116 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s
+
+; Verify that we no longer crash in VSX swap removal when debug values
+; are in the code stream.
+
+@php_intpow10.powers = external unnamed_addr constant [23 x double], align 8
+
+; Function Attrs: nounwind
+define double @_php_math_round(double %value, i32 signext %places, i32 signext %mode) #0 {
+entry:
+  br i1 undef, label %if.then, label %if.else, !dbg !32
+
+if.then:                                          ; preds = %entry
+  %conv = sitofp i32 undef to double, !dbg !34
+  br i1 undef, label %if.then.i, label %if.end.i, !dbg !36
+
+if.then.i:                                        ; preds = %if.then
+  %call.i = tail call double @pow(double 1.000000e+01, double undef) #3, !dbg !39
+  br label %php_intpow10.exit, !dbg !41
+
+if.end.i:                                         ; preds = %if.then
+  %0 = load double, double* undef, align 8, !dbg !42, !tbaa !43
+  br label %php_intpow10.exit, !dbg !47
+
+php_intpow10.exit:                                ; preds = %if.end.i, %if.then.i
+  %retval.0.i = phi double [ %call.i, %if.then.i ], [ %0, %if.end.i ], !dbg !48
+  tail call void @llvm.dbg.value(metadata double %retval.0.i, i64 0, metadata !15, metadata !49), !dbg !50
+  %div = fdiv double %conv, %retval.0.i, !dbg !51
+  br label %if.end.15, !dbg !52
+
+if.else:                                          ; preds = %entry
+  %mul = fmul double %value, undef, !dbg !53
+  br label %if.end.15
+
+if.end.15:                                        ; preds = %if.else, %php_intpow10.exit
+  %tmp_value.1 = phi double [ %div, %php_intpow10.exit ], [ %mul, %if.else ]
+  ret double %tmp_value.1, !dbg !57
+}
+
+declare signext i32 @php_intlog10abs(...) #1
+
+declare signext i32 @php_round_helper(...) #1
+
+; Function Attrs: nounwind
+declare double @pow(double, double) #0
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2
+
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!29, !30}
+!llvm.ident = !{!31}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.8.0 (git://github.com/llvm-mirror/clang.git e0848b6353721eb1b278a5bbea257bbf6316251e) (git://github.com/llvm-mirror/llvm.git 8724a428dfd5e78d7865bb01783708e83f9ed128)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !3, subprograms: !5, globals: !23)
+!1 = !DIFile(filename: "testcase.i", directory: "/tmp/glibc.build")
+!2 = !{}
+!3 = !{!4}
+!4 = !DIBasicType(name: "double", size: 64, align: 64, encoding: DW_ATE_float)
+!5 = !{!6, !18}
+!6 = !DISubprogram(name: "_php_math_round", scope: !1, file: !1, line: 15, type: !7, isLocal: false, isDefinition: true, scopeLine: 16, flags: DIFlagPrototyped, isOptimized: true, function: double (double, i32, i32)* @_php_math_round, variables: !10)
+!7 = !DISubroutineType(types: !8)
+!8 = !{!4, !4, !9, !9}
+!9 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
+!10 = !{!11, !12, !13, !14, !15, !16, !17}
+!11 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "value", arg: 1, scope: !6, file: !1, line: 15, type: !4)
+!12 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "places", arg: 2, scope: !6, file: !1, line: 15, type: !9)
+!13 = !DILocalVariable(tag: DW_TAG_arg_variable, name: "mode", arg: 3, scope: !6, file: !1, line: 15, type: !9)
+!14 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "f1", scope: !6, file: !1, line: 17, type: !4)
+!15 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "f2", scope: !6, file: !1, line: 17, type: !4)
+!16 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "tmp_value", scope: !6, file: !1, line: 18, type: !4)
+!17 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "precision_places", scope: !6, file: !1, line: 19, type: !9)
+!18 = !DISubprogram(name: "php_intpow10", scope: !1, file: !1, line: 1, type: !19, isLocal: true, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, variables: !21)
+!19 = !DISubroutineType(types: !20)
+!20 = !{!4, !9}
+!21 = !{!22}
+!22 = !DILocalVariable(tag: DW_TAG_auto_variable, name: "power", arg: 1, scope: !18, file: !1, line: 1, type: !9)
+!23 = !{!24}
+!24 = !DIGlobalVariable(name: "powers", scope: !18, file: !1, line: 3, type: !25, isLocal: true, isDefinition: true, variable: [23 x double]* @php_intpow10.powers)
+!25 = !DICompositeType(tag: DW_TAG_array_type, baseType: !26, size: 1472, align: 64, elements: !27)
+!26 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !4)
+!27 = !{!28}
+!28 = !DISubrange(count: 23)
+!29 = !{i32 2, !"Dwarf Version", i32 4}
+!30 = !{i32 2, !"Debug Info Version", i32 3}
+!31 = !{!"clang version 3.8.0 (git://github.com/llvm-mirror/clang.git e0848b6353721eb1b278a5bbea257bbf6316251e) (git://github.com/llvm-mirror/llvm.git 8724a428dfd5e78d7865bb01783708e83f9ed128)"}
+!32 = !DILocation(line: 21, column: 32, scope: !33)
+!33 = distinct !DILexicalBlock(scope: !6, file: !1, line: 21, column: 6)
+!34 = !DILocation(line: 22, column: 15, scope: !35)
+!35 = distinct !DILexicalBlock(scope: !33, file: !1, line: 21, column: 67)
+!36 = !DILocation(line: 8, column: 16, scope: !37, inlinedAt: !38)
+!37 = distinct !DILexicalBlock(scope: !18, file: !1, line: 8, column: 6)
+!38 = distinct !DILocation(line: 23, column: 8, scope: !35)
+!39 = !DILocation(line: 9, column: 10, scope: !40, inlinedAt: !38)
+!40 = distinct !DILexicalBlock(scope: !37, file: !1, line: 8, column: 31)
+!41 = !DILocation(line: 9, column: 3, scope: !40, inlinedAt: !38)
+!42 = !DILocation(line: 11, column: 9, scope: !18, inlinedAt: !38)
+!43 = !{!44, !44, i64 0}
+!44 = !{!"double", !45, i64 0}
+!45 = !{!"omnipotent char", !46, i64 0}
+!46 = !{!"Simple C/C++ TBAA"}
+!47 = !DILocation(line: 11, column: 2, scope: !18, inlinedAt: !38)
+!48 = !DILocation(line: 23, column: 8, scope: !35)
+!49 = !DIExpression()
+!50 = !DILocation(line: 17, column: 13, scope: !6)
+!51 = !DILocation(line: 24, column: 25, scope: !35)
+!52 = !DILocation(line: 25, column: 2, scope: !35)
+!53 = !DILocation(line: 27, column: 22, scope: !54)
+!54 = distinct !DILexicalBlock(scope: !55, file: !1, line: 26, column: 20)
+!55 = distinct !DILexicalBlock(scope: !56, file: !1, line: 26, column: 7)
+!56 = distinct !DILexicalBlock(scope: !33, file: !1, line: 25, column: 9)
+!57 = !DILocation(line: 32, column: 2, scope: !6)
diff --git a/test/CodeGen/PowerPC/pr25157.ll b/test/CodeGen/PowerPC/pr25157.ll
new file mode 100644
index 000000000000..7137d675a74a
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr25157.ll
@@ -0,0 +1,58 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; Verify correct generation of an lxsspx rather than an invalid optimization
+; to lxvdsx.  Bugpoint-reduced test from Eric Schweitz.
+
+%struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625 = type <{ [28 x i8] }>
+%struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626 = type <{ [64 x i8] }>
+
+@.BSS38 = external global %struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, align 32
+@_main1_2_ = external global %struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626, section ".comm", align 16
+
+define void @aercalc_() {
+L.entry:
+  br i1 undef, label %L.LB38_2426, label %L.LB38_2911
+
+L.LB38_2911:
+  br i1 undef, label %L.LB38_2140, label %L.LB38_2640
+
+L.LB38_2640:
+  unreachable
+
+L.LB38_2426:
+  br i1 undef, label %L.LB38_2438, label %L.LB38_2920
+
+L.LB38_2920:
+  br i1 undef, label %L.LB38_2438, label %L.LB38_2921
+
+L.LB38_2921:
+  br label %L.LB38_2140
+
+L.LB38_2140:
+  ret void
+
+L.LB38_2438:
+  br i1 undef, label %L.LB38_2451, label %L.LB38_2935
+
+L.LB38_2935:
+  br i1 undef, label %L.LB38_2451, label %L.LB38_2936
+
+L.LB38_2936:
+  unreachable
+
+L.LB38_2451:
+  br i1 undef, label %L.LB38_2452, label %L.LB38_2937
+
+L.LB38_2937:
+  unreachable
+
+L.LB38_2452:
+  %0 = load float, float* bitcast (i8* getelementptr inbounds (%struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625, %struct.BSS38.51.4488.9911.14348.16813.20264.24701.28152.31603.35054.39491.44914.45407.46393.46886.47872.49351.49844.50830.51323.52309.53295.53788.54281.55267.55760.59211.61625* @.BSS38, i64 0, i32 0, i64 16) to float*), align 16
+  %1 = fpext float %0 to double
+  %2 = insertelement <2 x double> undef, double %1, i32 1
+  store <2 x double> %2, <2 x double>* bitcast (i8* getelementptr inbounds (%struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626, %struct_main1_2_.491.4928.10351.14788.17253.20704.25141.28592.32043.35494.39931.45354.45847.46833.47326.48312.49791.50284.51270.51763.52749.53735.54228.54721.55707.56200.59651.61626* @_main1_2_, i64 0, i32 0, i64 32) to <2 x double>*), align 16
+  unreachable
+}
+
+; CHECK-LABEL: @aercalc_
+; CHECK: lxsspx
diff --git a/test/CodeGen/PowerPC/rlwimi-and-or-bits.ll b/test/CodeGen/PowerPC/rlwimi-and-or-bits.ll
new file mode 100644
index 000000000000..a74bc7273962
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwimi-and-or-bits.ll
@@ -0,0 +1,27 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+@m = external global i32, align 4
+
+; Function Attrs: nounwind
+define signext i32 @main() #0 {
+entry:
+
+; CHECK-LABEL: @main
+; CHECK-NOT: rlwimi
+; CHECK: andi
+
+  %0 = load i32, i32* @m, align 4
+  %or = or i32 %0, 250
+  store i32 %or, i32* @m, align 4
+  %and = and i32 %or, 249
+  %sub.i = sub i32 %and, 0
+  %sext = shl i32 %sub.i, 24
+  %conv = ashr exact i32 %sext, 24
+  ret i32 %conv
+}
+
+attributes #0 = { nounwind "target-cpu"="pwr7" }
+attributes #1 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/test/CodeGen/PowerPC/select-i1-vs-i1.ll
new file mode 100644
index 000000000000..6dabbaa4208b
--- /dev/null
+++ b/test/CodeGen/PowerPC/select-i1-vs-i1.ll
@@ -0,0 +1,1685 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; FIXME: We should check the operands to the cr* logical operation itself, but
+; unfortunately, FileCheck does not yet understand how to do arithmetic, so we
+; can't do so without introducing a register-allocation dependency.
+
+define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+entry:
+  %cmp1 = icmp eq i32 %c3, %c4
+  %cmp3tmp = icmp eq i32 %c1, %c2
+  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i32 %a1, i32 %a2
+  ret i32 %cond
+
+; CHECK-LABEL: @testi32slt
+; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+entry:
+  %cmp1 = icmp eq i32 %c3, %c4
+  %cmp3tmp = icmp eq i32 %c1, %c2
+  %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i32 %a1, i32 %a2
+  ret i32 %cond
+
+; CHECK-LABEL: @testi32ult
+; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+entry:
+  %cmp1 = icmp eq i32 %c3, %c4
+  %cmp3tmp = icmp eq i32 %c1, %c2
+  %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i32 %a1, i32 %a2
+  ret i32 %cond
+
+; CHECK-LABEL: @testi32sle
+; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+entry:
+  %cmp1 = icmp eq i32 %c3, %c4
+  %cmp3tmp = icmp eq i32 %c1, %c2
+  %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i32 %a1, i32 %a2
+  ret i32 %cond
+
+; CHECK-LABEL: @testi32ule
+; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+entry:
+  %cmp1 = icmp eq i32 %c3, %c4
+  %cmp3tmp = icmp eq i32 %c1, %c2
+  %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i32 %a1, i32 %a2
+  ret i32 %cond
+
+; CHECK-LABEL: @testi32eq
+; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
+; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+entry:
+  %cmp1 = icmp eq i32 %c3, %c4
+  %cmp3tmp = icmp eq i32 %c1, %c2
+  %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i32 %a1, i32 %a2
+  ret i32 %cond
+
+; CHECK-LABEL: @testi32sge
+; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+entry:
+  %cmp1 = icmp eq i32 %c3, %c4
+  %cmp3tmp = icmp eq i32 %c1, %c2
+  %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i32 %a1, i32 %a2
+  ret i32 %cond
+
+; CHECK-LABEL: @testi32uge
+; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+entry:
+  %cmp1 = icmp eq i32 %c3, %c4
+  %cmp3tmp = icmp eq i32 %c1, %c2
+  %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i32 %a1, i32 %a2
+  ret i32 %cond
+
+; CHECK-LABEL: @testi32sgt
+; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+entry:
+  %cmp1 = icmp eq i32 %c3, %c4
+  %cmp3tmp = icmp eq i32 %c1, %c2
+  %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i32 %a1, i32 %a2
+  ret i32 %cond
+
+; CHECK-LABEL: @testi32ugt
+; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
+entry:
+  %cmp1 = icmp eq i32 %c3, %c4
+  %cmp3tmp = icmp eq i32 %c1, %c2
+  %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i32 %a1, i32 %a2
+  ret i32 %cond
+
+; CHECK-LABEL: @testi32ne
+; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
+; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
+; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+entry:
+  %cmp1 = icmp eq i64 %c3, %c4
+  %cmp3tmp = icmp eq i64 %c1, %c2
+  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i64 %a1, i64 %a2
+  ret i64 %cond
+
+; CHECK-LABEL: @testi64slt
+; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
+; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+entry:
+  %cmp1 = icmp eq i64 %c3, %c4
+  %cmp3tmp = icmp eq i64 %c1, %c2
+  %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i64 %a1, i64 %a2
+  ret i64 %cond
+
+; CHECK-LABEL: @testi64ult
+; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
+; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+entry:
+  %cmp1 = icmp eq i64 %c3, %c4
+  %cmp3tmp = icmp eq i64 %c1, %c2
+  %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i64 %a1, i64 %a2
+  ret i64 %cond
+
+; CHECK-LABEL: @testi64sle
+; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
+; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+entry:
+  %cmp1 = icmp eq i64 %c3, %c4
+  %cmp3tmp = icmp eq i64 %c1, %c2
+  %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i64 %a1, i64 %a2
+  ret i64 %cond
+
+; CHECK-LABEL: @testi64ule
+; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
+; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+entry:
+  %cmp1 = icmp eq i64 %c3, %c4
+  %cmp3tmp = icmp eq i64 %c1, %c2
+  %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i64 %a1, i64 %a2
+  ret i64 %cond
+
+; CHECK-LABEL: @testi64eq
+; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
+; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
+; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+entry:
+  %cmp1 = icmp eq i64 %c3, %c4
+  %cmp3tmp = icmp eq i64 %c1, %c2
+  %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i64 %a1, i64 %a2
+  ret i64 %cond
+
+; CHECK-LABEL: @testi64sge
+; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
+; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+entry:
+  %cmp1 = icmp eq i64 %c3, %c4
+  %cmp3tmp = icmp eq i64 %c1, %c2
+  %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i64 %a1, i64 %a2
+  ret i64 %cond
+
+; CHECK-LABEL: @testi64uge
+; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
+; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+entry:
+  %cmp1 = icmp eq i64 %c3, %c4
+  %cmp3tmp = icmp eq i64 %c1, %c2
+  %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i64 %a1, i64 %a2
+  ret i64 %cond
+
+; CHECK-LABEL: @testi64sgt
+; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
+; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+entry:
+  %cmp1 = icmp eq i64 %c3, %c4
+  %cmp3tmp = icmp eq i64 %c1, %c2
+  %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i64 %a1, i64 %a2
+  ret i64 %cond
+
+; CHECK-LABEL: @testi64ugt
+; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
+; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
+entry:
+  %cmp1 = icmp eq i64 %c3, %c4
+  %cmp3tmp = icmp eq i64 %c1, %c2
+  %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, i64 %a1, i64 %a2
+  ret i64 %cond
+
+; CHECK-LABEL: @testi64ne
+; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
+; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
+; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: isel 3, 7, 8, [[REG1]]
+; CHECK: blr
+}
+
+define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, float %a1, float %a2
+  ret float %cond
+
+; CHECK-LABEL: @testfloatslt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define float @testfloatult(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, float %a1, float %a2
+  ret float %cond
+
+; CHECK-LABEL: @testfloatult
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, float %a1, float %a2
+  ret float %cond
+
+; CHECK-LABEL: @testfloatsle
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define float @testfloatule(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, float %a1, float %a2
+  ret float %cond
+
+; CHECK-LABEL: @testfloatule
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, float %a1, float %a2
+  ret float %cond
+
+; CHECK-LABEL: @testfloateq
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define float @testfloatsge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, float %a1, float %a2
+  ret float %cond
+
+; CHECK-LABEL: @testfloatsge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define float @testfloatuge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, float %a1, float %a2
+  ret float %cond
+
+; CHECK-LABEL: @testfloatuge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, float %a1, float %a2
+  ret float %cond
+
+; CHECK-LABEL: @testfloatsgt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define float @testfloatugt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, float %a1, float %a2
+  ret float %cond
+
+; CHECK-LABEL: @testfloatugt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, float %a1, float %a2
+  ret float %cond
+
+; CHECK-LABEL: @testfloatne
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define double @testdoubleslt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq double %c3, %c4
+  %cmp3tmp = fcmp oeq double %c1, %c2
+  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, double %a1, double %a2
+  ret double %cond
+
+; CHECK-LABEL: @testdoubleslt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define double @testdoubleult(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq double %c3, %c4
+  %cmp3tmp = fcmp oeq double %c1, %c2
+  %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, double %a1, double %a2
+  ret double %cond
+
+; CHECK-LABEL: @testdoubleult
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq double %c3, %c4
+  %cmp3tmp = fcmp oeq double %c1, %c2
+  %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, double %a1, double %a2
+  ret double %cond
+
+; CHECK-LABEL: @testdoublesle
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define double @testdoubleule(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq double %c3, %c4
+  %cmp3tmp = fcmp oeq double %c1, %c2
+  %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, double %a1, double %a2
+  ret double %cond
+
+; CHECK-LABEL: @testdoubleule
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq double %c3, %c4
+  %cmp3tmp = fcmp oeq double %c1, %c2
+  %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, double %a1, double %a2
+  ret double %cond
+
+; CHECK-LABEL: @testdoubleeq
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define double @testdoublesge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq double %c3, %c4
+  %cmp3tmp = fcmp oeq double %c1, %c2
+  %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, double %a1, double %a2
+  ret double %cond
+
+; CHECK-LABEL: @testdoublesge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define double @testdoubleuge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq double %c3, %c4
+  %cmp3tmp = fcmp oeq double %c1, %c2
+  %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, double %a1, double %a2
+  ret double %cond
+
+; CHECK-LABEL: @testdoubleuge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq double %c3, %c4
+  %cmp3tmp = fcmp oeq double %c1, %c2
+  %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, double %a1, double %a2
+  ret double %cond
+
+; CHECK-LABEL: @testdoublesgt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define double @testdoubleugt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq double %c3, %c4
+  %cmp3tmp = fcmp oeq double %c1, %c2
+  %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, double %a1, double %a2
+  ret double %cond
+
+; CHECK-LABEL: @testdoubleugt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq double %c3, %c4
+  %cmp3tmp = fcmp oeq double %c1, %c2
+  %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, double %a1, double %a2
+  ret double %cond
+
+; CHECK-LABEL: @testdoublene
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: fmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: fmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; FIXME: This test (and the other v4f32 tests) should use the same bclr
+; technique as the v2f64 tests below.
+
+; CHECK-LABEL: @testv4floatslt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
+; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: .LBB[[BB]]:
+; CHECK: xxlor 34, [[REG2]], [[REG2]]
+; CHECK: blr
+}
+
+define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testv4floatult
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
+; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: .LBB[[BB]]:
+; CHECK: xxlor 34, [[REG2]], [[REG2]]
+; CHECK: blr
+}
+
+define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testv4floatsle
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
+; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: .LBB[[BB]]:
+; CHECK: xxlor 34, [[REG2]], [[REG2]]
+; CHECK: blr
+}
+
+define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testv4floatule
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
+; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: .LBB[[BB]]:
+; CHECK: xxlor 34, [[REG2]], [[REG2]]
+; CHECK: blr
+}
+
+define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testv4floateq
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
+; CHECK-DAG: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: .LBB[[BB]]:
+; CHECK: xxlor 34, [[REG2]], [[REG2]]
+; CHECK: blr
+}
+
+define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testv4floatsge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
+; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: .LBB[[BB]]:
+; CHECK: xxlor 34, [[REG2]], [[REG2]]
+; CHECK: blr
+}
+
+define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testv4floatuge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
+; CHECK-DAG: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: .LBB[[BB]]:
+; CHECK: xxlor 34, [[REG2]], [[REG2]]
+; CHECK: blr
+}
+
+define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testv4floatsgt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
+; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: .LBB[[BB]]:
+; CHECK: xxlor 34, [[REG2]], [[REG2]]
+; CHECK: blr
+}
+
+define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testv4floatugt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
+; CHECK-DAG: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: .LBB[[BB]]:
+; CHECK: xxlor 34, [[REG2]], [[REG2]]
+; CHECK: blr
+}
+
+define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testv4floatne
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK-DAG: xxlor [[REG2:[0-9]+]], 34, 34
+; CHECK-DAG: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: xxlor [[REG2]], 35, 35
+; CHECK: .LBB[[BB]]:
+; CHECK: xxlor 34, [[REG2]], [[REG2]]
+; CHECK: blr
+}
+
+define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq ppc_fp128 %c3, %c4
+  %cmp3tmp = fcmp oeq ppc_fp128 %c1, %c2
+  %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, ppc_fp128 %a1, ppc_fp128 %a2
+  ret ppc_fp128 %cond
+
+; FIXME: Because of the way that the late SELECT_* pseudo-instruction expansion
+; works, we end up with two blocks with the same predicate. These could be
+; combined.
+
+; CHECK-LABEL: @testppc_fp128eq
+; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8
+; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7
+; CHECK-DAG: fcmpu {{[0-9]+}}, 2, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3
+; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: creqv [[REG3:[0-9]+]], [[REG2]], [[REG1]]
+; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]]
+; CHECK: fmr 9, 11
+; CHECK: .LBB[[BB1]]:
+; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]]
+; CHECK: fmr 10, 12
+; CHECK: .LBB[[BB2]]:
+; CHECK-DAG: fmr 1, 9
+; CHECK-DAG: fmr 2, 10
+; CHECK: blr
+}
+
+define <2 x double> @testv2doubleslt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
+  ret <2 x double> %cond
+
+; CHECK-LABEL: @testv2doubleslt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: vor 2, 3, 3
+; CHECK: blr
+}
+
+define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
+  ret <2 x double> %cond
+
+; CHECK-LABEL: @testv2doubleult
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: vor 2, 3, 3
+; CHECK: blr
+}
+
+define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
+  ret <2 x double> %cond
+
+; CHECK-LABEL: @testv2doublesle
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: vor 2, 3, 3
+; CHECK: blr
+}
+
+define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
+  ret <2 x double> %cond
+
+; CHECK-LABEL: @testv2doubleule
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: vor 2, 3, 3
+; CHECK: blr
+}
+
+define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
+  ret <2 x double> %cond
+
+; CHECK-LABEL: @testv2doubleeq
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: vor 2, 3, 3
+; CHECK: blr
+}
+
+define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
+  ret <2 x double> %cond
+
+; CHECK-LABEL: @testv2doublesge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: vor 2, 3, 3
+; CHECK: blr
+}
+
+define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
+  ret <2 x double> %cond
+
+; CHECK-LABEL: @testv2doubleuge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: vor 2, 3, 3
+; CHECK: blr
+}
+
+define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
+  ret <2 x double> %cond
+
+; CHECK-LABEL: @testv2doublesgt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: vor 2, 3, 3
+; CHECK: blr
+}
+
+define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
+  ret <2 x double> %cond
+
+; CHECK-LABEL: @testv2doubleugt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: vor 2, 3, 3
+; CHECK: blr
+}
+
+define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
+  ret <2 x double> %cond
+
+; CHECK-LABEL: @testv2doublene
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: vor 2, 3, 3
+; CHECK: blr
+}
+
+define <4 x double> @testqv4doubleslt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
+  ret <4 x double> %cond
+
+; CHECK-LABEL: @testqv4doubleslt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x double> @testqv4doubleult(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
+  ret <4 x double> %cond
+
+; CHECK-LABEL: @testqv4doubleult
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x double> @testqv4doublesle(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
+  ret <4 x double> %cond
+
+; CHECK-LABEL: @testqv4doublesle
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x double> @testqv4doubleule(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
+  ret <4 x double> %cond
+
+; CHECK-LABEL: @testqv4doubleule
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x double> @testqv4doubleeq(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
+  ret <4 x double> %cond
+
+; CHECK-LABEL: @testqv4doubleeq
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x double> @testqv4doublesge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
+  ret <4 x double> %cond
+
+; CHECK-LABEL: @testqv4doublesge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x double> @testqv4doubleuge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
+  ret <4 x double> %cond
+
+; CHECK-LABEL: @testqv4doubleuge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x double> @testqv4doublesgt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
+  ret <4 x double> %cond
+
+; CHECK-LABEL: @testqv4doublesgt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x double> @testqv4doubleugt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
+  ret <4 x double> %cond
+
+; CHECK-LABEL: @testqv4doubleugt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x double> @testqv4doublene(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
+  ret <4 x double> %cond
+
+; CHECK-LABEL: @testqv4doublene
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testqv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testqv4floatslt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testqv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testqv4floatult
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testqv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testqv4floatsle
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testqv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testqv4floatule
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testqv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testqv4floateq
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testqv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testqv4floatsge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testqv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testqv4floatuge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testqv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testqv4floatsgt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testqv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testqv4floatugt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x float> @testqv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
+  ret <4 x float> %cond
+
+; CHECK-LABEL: @testqv4floatne
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x i1> @testqv4i1slt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
+  ret <4 x i1> %cond
+
+; CHECK-LABEL: @testqv4i1slt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x i1> @testqv4i1ult(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
+  ret <4 x i1> %cond
+
+; CHECK-LABEL: @testqv4i1ult
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x i1> @testqv4i1sle(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
+  ret <4 x i1> %cond
+
+; CHECK-LABEL: @testqv4i1sle
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x i1> @testqv4i1ule(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
+  ret <4 x i1> %cond
+
+; CHECK-LABEL: @testqv4i1ule
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x i1> @testqv4i1eq(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
+  ret <4 x i1> %cond
+
+; CHECK-LABEL: @testqv4i1eq
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x i1> @testqv4i1sge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
+  ret <4 x i1> %cond
+
+; CHECK-LABEL: @testqv4i1sge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x i1> @testqv4i1uge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
+  ret <4 x i1> %cond
+
+; CHECK-LABEL: @testqv4i1uge
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x i1> @testqv4i1sgt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
+  ret <4 x i1> %cond
+
+; CHECK-LABEL: @testqv4i1sgt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x i1> @testqv4i1ugt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
+  ret <4 x i1> %cond
+
+; CHECK-LABEL: @testqv4i1ugt
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+define <4 x i1> @testqv4i1ne(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
+entry:
+  %cmp1 = fcmp oeq float %c3, %c4
+  %cmp3tmp = fcmp oeq float %c1, %c2
+  %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
+  %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
+  ret <4 x i1> %cond
+
+; CHECK-LABEL: @testqv4i1ne
+; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
+; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
+; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
+; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
+; CHECK: qvfmr 5, 6
+; CHECK: .LBB[[BB]]:
+; CHECK: qvfmr 1, 5
+; CHECK: blr
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="pwr7" }
+attributes #1 = { nounwind readnone "target-cpu"="a2q" }
+
diff --git a/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll b/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll
new file mode 100644
index 000000000000..a5b4474460c0
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsx-fma-mutate-trivial-copy.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @LSH_recall_init(float %d_min, float %W) #0 {
+entry:
+  br i1 undef, label %for.body.lr.ph, label %for.end
+
+; CHECK-LABEL: @LSH_recall_init
+; CHECK: xsnmsubadp
+
+for.body.lr.ph:                                   ; preds = %entry
+  %conv3 = fpext float %W to double
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %for.body.lr.ph
+  %div = fdiv fast float 0.000000e+00, 0.000000e+00
+  %add = fadd fast float %div, %d_min
+  %conv2 = fpext float %add to double
+  %0 = tail call double @llvm.sqrt.f64(double %conv2)
+  %div4 = fdiv fast double %conv3, %0
+  %call = tail call signext i32 bitcast (i32 (...)* @p_col_helper to i32 (double)*)(double %div4) #2
+  br label %for.body
+
+for.end:                                          ; preds = %entry
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare double @llvm.sqrt.f64(double) #1
+
+declare signext i32 @p_col_helper(...) #2
+
+attributes #0 = { nounwind "no-infs-fp-math"="true" "no-nans-fp-math"="true" "target-cpu"="pwr7" "unsafe-fp-math"="true" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+
diff --git a/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll b/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
new file mode 100644
index 000000000000..e3f4001aa1d3
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
@@ -0,0 +1,33 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @acosh_float8() #0 {
+entry:
+  br i1 undef, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  %0 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> undef, <4 x float> <float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000>, <4 x float> undef) #0
+  %astype.i.i.74.i = bitcast <4 x float> %0 to <4 x i32>
+  %and.i.i.76.i = and <4 x i32> %astype.i.i.74.i, undef
+  %or.i.i.79.i = or <4 x i32> %and.i.i.76.i, undef
+  %astype5.i.i.80.i = bitcast <4 x i32> %or.i.i.79.i to <4 x float>
+  %1 = shufflevector <4 x float> %astype5.i.i.80.i, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+  %2 = shufflevector <8 x float> undef, <8 x float> %1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
+  store <8 x float> %2, <8 x float>* undef, align 32
+  br label %if.end
+
+; CHECK-LABEL: @acosh_float8
+; CHECK: xvmaddasp
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+