diff options
| author | Ed Schouten <ed@FreeBSD.org> | 2009-06-02 17:52:33 +0000 |
|---|---|---|
| committer | Ed Schouten <ed@FreeBSD.org> | 2009-06-02 17:52:33 +0000 |
| commit | 009b1c42aa6266385f2c37e227516b24077e6dd7 (patch) | |
| tree | 64ba909838c23261cace781ece27d106134ea451 /test/CodeGen/PowerPC | |
Notes
Diffstat (limited to 'test/CodeGen/PowerPC')
219 files changed, 9674 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll b/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll new file mode 100644 index 000000000000..70f294a78d86 --- /dev/null +++ b/test/CodeGen/PowerPC/2004-11-29-ShrCrash.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +define void @test() { + %tr1 = lshr i32 1, 0 ; <i32> [#uses=0] + ret void +} + diff --git a/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll b/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll new file mode 100644 index 000000000000..93a91234b707 --- /dev/null +++ b/test/CodeGen/PowerPC/2004-11-30-shift-crash.ll @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + +define void @main() { + %tr4 = shl i64 1, 0 ; <i64> [#uses=0] + ret void +} + diff --git a/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll b/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll new file mode 100644 index 000000000000..1a1aca4b5d11 --- /dev/null +++ b/test/CodeGen/PowerPC/2004-11-30-shr-var-crash.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + +define void @main() { + %shamt = add i8 0, 1 ; <i8> [#uses=1] + %shift.upgrd.1 = zext i8 %shamt to i64 ; <i64> [#uses=1] + %tr2 = ashr i64 1, %shift.upgrd.1 ; <i64> [#uses=0] + ret void +} + diff --git a/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll b/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll new file mode 100644 index 000000000000..3e490b1dc7a2 --- /dev/null +++ b/test/CodeGen/PowerPC/2004-12-12-ZeroSizeCommon.ll @@ -0,0 +1,4 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep .comm.*X,0 + +@X = linkonce global { } zeroinitializer ; <{ }*> [#uses=0] + diff --git a/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll b/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll new file mode 100644 index 000000000000..f84caaf1d499 --- /dev/null +++ b/test/CodeGen/PowerPC/2005-01-14-SetSelectCrash.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + +define i32 @main() { + %setle = icmp sle i64 1, 0 ; <i1> [#uses=1] + %select = select i1 true, i1 %setle, i1 true ; <i1> [#uses=0] + ret i32 0 +} + diff --git a/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll b/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll new file mode 100644 index 000000000000..7b3e9b4f092f --- /dev/null +++ b/test/CodeGen/PowerPC/2005-01-14-UndefLong.ll @@ -0,0 +1,5 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + +define i64 @test() { + ret i64 undef +} diff --git a/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll b/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll new file mode 100644 index 000000000000..8e8fee2888fb --- /dev/null +++ b/test/CodeGen/PowerPC/2005-08-12-rlwimi-crash.ll @@ -0,0 +1,13 @@ +; this should not crash the ppc backend + +; RUN: llvm-as < %s | llc -march=ppc32 + + +define i32 @test(i32 %j.0.0.i) { + %tmp.85.i = and i32 %j.0.0.i, 7 ; <i32> [#uses=1] + %tmp.161278.i = bitcast i32 %tmp.85.i to i32 ; <i32> [#uses=1] + %tmp.5.i77.i = lshr i32 %tmp.161278.i, 3 ; <i32> [#uses=1] + ret i32 %tmp.5.i77.i +} + + diff --git a/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll b/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll new file mode 100644 index 000000000000..428dd0c3e3fd --- /dev/null +++ b/test/CodeGen/PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll @@ -0,0 +1,11 @@ +; This function should have exactly one call to fixdfdi, no more! + +; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | \ +; RUN: grep {bl .*fixdfdi} | count 1 + +define double @test2(double %tmp.7705) { + %mem_tmp.2.0.in = fptosi double %tmp.7705 to i64 ; <i64> [#uses=1] + %mem_tmp.2.0 = sitofp i64 %mem_tmp.2.0.in to double ; <double> [#uses=1] + ret double %mem_tmp.2.0 +} + diff --git a/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll b/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll new file mode 100644 index 000000000000..54f24c612660 --- /dev/null +++ b/test/CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll @@ -0,0 +1,11 @@ +; This was erroneously being turned into an rlwinm instruction. +; The sign bit does matter in this case. + +; RUN: llvm-as < %s | llc -march=ppc32 | grep srawi + +define i32 @test(i32 %X) { + %Y = and i32 %X, -2 ; <i32> [#uses=1] + %Z = ashr i32 %Y, 11 ; <i32> [#uses=1] + ret i32 %Z +} + diff --git a/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll b/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll new file mode 100644 index 000000000000..d56cffcf4ab1 --- /dev/null +++ b/test/CodeGen/PowerPC/2005-11-30-vastart-crash.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc + +target datalayout = "E-p:32:32" +target triple = "powerpc-apple-darwin8.2.0" + +define void @bar(i32 %G, i32 %E, i32 %F, i32 %A, i32 %B, i32 %C, i32 %D, i8* %fmt, ...) { + %ap = alloca i8* ; <i8**> [#uses=2] + %va.upgrd.1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1] + call void @llvm.va_start( i8* %va.upgrd.1 ) + %tmp.1 = load i8** %ap ; <i8*> [#uses=1] + %tmp.0 = call double @foo( i8* %tmp.1 ) ; <double> [#uses=0] + ret void +} + +declare void @llvm.va_start(i8*) + +declare double @foo(i8*) + diff --git a/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll b/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll new file mode 100644 index 000000000000..e2f06f5e69ae --- /dev/null +++ b/test/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc | not grep {, f1} + +target datalayout = "E-p:32:32" +target triple = "powerpc-apple-darwin8.2.0" + +; Dead argument should reserve an FP register. +define double @bar(double %DEAD, double %X, double %Y) { + %tmp.2 = add double %X, %Y ; <double> [#uses=1] + ret double %tmp.2 +} diff --git a/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll new file mode 100644 index 000000000000..86ad71861773 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-01-20-ShiftPartsCrash.ll @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc + +define void @iterative_hash_host_wide_int() { + %zero = alloca i32 ; <i32*> [#uses=2] + %b = alloca i32 ; <i32*> [#uses=1] + store i32 0, i32* %zero + %tmp = load i32* %zero ; <i32> [#uses=1] + %tmp5 = bitcast i32 %tmp to i32 ; <i32> [#uses=1] + %tmp6.u = add i32 %tmp5, 32 ; <i32> [#uses=1] + %tmp6 = bitcast i32 %tmp6.u to i32 ; <i32> [#uses=1] + %tmp7 = load i64* null ; <i64> [#uses=1] + %tmp6.upgrd.1 = trunc i32 %tmp6 to i8 ; <i8> [#uses=1] + %shift.upgrd.2 = zext i8 %tmp6.upgrd.1 to i64 ; <i64> [#uses=1] + %tmp8 = ashr i64 %tmp7, %shift.upgrd.2 ; <i64> [#uses=1] + %tmp8.upgrd.3 = trunc i64 %tmp8 to i32 ; <i32> [#uses=1] + store i32 %tmp8.upgrd.3, i32* %b + unreachable +} + diff --git a/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll b/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll new file mode 100644 index 000000000000..8500260fafce --- /dev/null +++ b/test/CodeGen/PowerPC/2006-04-01-FloatDoubleExtend.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + + +define double @CalcSpeed(float %tmp127) { + %tmp145 = fpext float %tmp127 to double ; <double> [#uses=1] + %tmp150 = call double asm "frsqrte $0,$1", "=f,f"( double %tmp145 ) ; <double> [#uses=1] + ret double %tmp150 +} + diff --git a/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll b/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll new file mode 100644 index 000000000000..a536fa162c03 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-04-05-splat-ish.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \ +; RUN: grep {vspltish v.*, 10} + +define void @test(<8 x i16>* %P) { + %tmp = load <8 x i16>* %P ; <<8 x i16>> [#uses=1] + %tmp1 = add <8 x i16> %tmp, < i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10 > ; <<8 x i16>> [#uses=1] + store <8 x i16> %tmp1, <8 x i16>* %P + ret void +} + diff --git a/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll b/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll new file mode 100644 index 000000000000..b79cce2ead00 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll @@ -0,0 +1,58 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; END. + +define void @test(i8* %stack) { +entry: + %tmp9 = icmp eq i32 0, 0 ; <i1> [#uses=1] + %tmp30 = icmp eq i32 0, 0 ; <i1> [#uses=1] + br i1 %tmp30, label %cond_next54, label %cond_true31 +cond_true860: ; preds = %bb855 + %tmp879 = tail call <4 x float> @llvm.ppc.altivec.vmaddfp( <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x float> zeroinitializer ) ; <<4 x float>> [#uses=1] + %tmp880 = bitcast <4 x float> %tmp879 to <4 x i32> ; <<4 x i32>> [#uses=2] + %tmp883 = shufflevector <4 x i32> %tmp880, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>> [#uses=1] + %tmp883.upgrd.1 = bitcast <4 x i32> %tmp883 to <4 x float> ; <<4 x float>> [#uses=1] + %tmp885 = shufflevector <4 x i32> %tmp880, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x i32>> [#uses=1] + %tmp885.upgrd.2 = bitcast <4 x i32> %tmp885 to <4 x float> ; <<4 x float>> [#uses=1] + br label %cond_next905 +cond_true31: ; preds = %entry + ret void +cond_next54: ; preds = %entry + br i1 %tmp9, label %cond_false385, label %bb279 +bb279: ; preds = %cond_next54 + ret void +cond_false385: ; preds = %cond_next54 + %tmp388 = icmp eq i32 0, 0 ; <i1> [#uses=1] + br i1 %tmp388, label %cond_next463, label %cond_true389 +cond_true389: ; preds = %cond_false385 + ret void +cond_next463: ; preds = %cond_false385 + %tmp1208107 = icmp ugt i8* null, %stack ; <i1> [#uses=1] + br i1 %tmp1208107, label %cond_true1209.preheader, label %bb1212 +cond_true498: ; preds = %cond_true1209.preheader + ret void +cond_true519: ; preds = %cond_true1209.preheader + %bothcond = or i1 false, false ; <i1> [#uses=1] + br i1 %bothcond, label %bb855, label %bb980 +cond_false548: ; preds = %cond_true1209.preheader + ret void +bb855: ; preds = %cond_true519 + %tmp859 = icmp eq i32 0, 0 ; <i1> [#uses=1] + br i1 %tmp859, label %cond_true860, label %cond_next905 +cond_next905: ; preds = %bb855, %cond_true860 + %vfpw2.4 = phi <4 x float> [ %tmp885.upgrd.2, %cond_true860 ], [ undef, %bb855 ] ; <<4 x float>> [#uses=0] + %vfpw1.4 = phi <4 x float> [ %tmp883.upgrd.1, %cond_true860 ], [ undef, %bb855 ] ; <<4 x float>> [#uses=0] + %tmp930 = bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>> [#uses=0] + ret void +bb980: ; preds = %cond_true519 + ret void +cond_true1209.preheader: ; preds = %cond_next463 + %tmp496 = and i32 0, 12288 ; <i32> [#uses=1] + switch i32 %tmp496, label %cond_false548 [ + i32 0, label %cond_true498 + i32 4096, label %cond_true519 + ] +bb1212: ; preds = %cond_next463 + ret void +} + +declare <4 x float> @llvm.ppc.altivec.vmaddfp(<4 x float>, <4 x float>, <4 x float>) diff --git a/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll b/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll new file mode 100644 index 000000000000..e1033c3f808a --- /dev/null +++ b/test/CodeGen/PowerPC/2006-05-12-rlwimi-crash.ll @@ -0,0 +1,55 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; END. + + %struct.attr_desc = type { i8*, %struct.attr_desc*, %struct.attr_value*, %struct.attr_value*, i32 } + %struct.attr_value = type { %struct.rtx_def*, %struct.attr_value*, %struct.insn_ent*, i32, i32 } + %struct.insn_def = type { %struct.insn_def*, %struct.rtx_def*, i32, i32, i32, i32, i32 } + %struct.insn_ent = type { %struct.insn_ent*, %struct.insn_def* } + %struct.rtx_def = type { i16, i8, i8, %struct.u } + %struct.u = type { [1 x i64] } + +define void @find_attr() { +entry: + %tmp26 = icmp eq %struct.attr_desc* null, null ; <i1> [#uses=1] + br i1 %tmp26, label %bb30, label %cond_true27 +cond_true27: ; preds = %entry + ret void +bb30: ; preds = %entry + %tmp67 = icmp eq %struct.attr_desc* null, null ; <i1> [#uses=1] + br i1 %tmp67, label %cond_next92, label %cond_true68 +cond_true68: ; preds = %bb30 + ret void +cond_next92: ; preds = %bb30 + %tmp173 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=2] + %tmp174 = load i32* %tmp173 ; <i32> [#uses=1] + %tmp177 = and i32 %tmp174, -9 ; <i32> [#uses=1] + store i32 %tmp177, i32* %tmp173 + %tmp180 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=1] + %tmp181 = load i32* %tmp180 ; <i32> [#uses=1] + %tmp185 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=2] + %tmp186 = load i32* %tmp185 ; <i32> [#uses=1] + %tmp183187 = shl i32 %tmp181, 1 ; <i32> [#uses=1] + %tmp188 = and i32 %tmp183187, 16 ; <i32> [#uses=1] + %tmp190 = and i32 %tmp186, -17 ; <i32> [#uses=1] + %tmp191 = or i32 %tmp190, %tmp188 ; <i32> [#uses=1] + store i32 %tmp191, i32* %tmp185 + %tmp193 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=1] + %tmp194 = load i32* %tmp193 ; <i32> [#uses=1] + %tmp198 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=2] + %tmp199 = load i32* %tmp198 ; <i32> [#uses=1] + %tmp196200 = shl i32 %tmp194, 2 ; <i32> [#uses=1] + %tmp201 = and i32 %tmp196200, 64 ; <i32> [#uses=1] + %tmp203 = and i32 %tmp199, -65 ; <i32> [#uses=1] + %tmp204 = or i32 %tmp203, %tmp201 ; <i32> [#uses=1] + store i32 %tmp204, i32* %tmp198 + %tmp206 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=1] + %tmp207 = load i32* %tmp206 ; <i32> [#uses=1] + %tmp211 = getelementptr %struct.attr_desc* null, i32 0, i32 4 ; <i32*> [#uses=2] + %tmp212 = load i32* %tmp211 ; <i32> [#uses=1] + %tmp209213 = shl i32 %tmp207, 1 ; <i32> [#uses=1] + %tmp214 = and i32 %tmp209213, 128 ; <i32> [#uses=1] + %tmp216 = and i32 %tmp212, -129 ; <i32> [#uses=1] + %tmp217 = or i32 %tmp216, %tmp214 ; <i32> [#uses=1] + store i32 %tmp217, i32* %tmp211 + ret void +} diff --git a/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll new file mode 100644 index 000000000000..33807ca012b5 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-07-07-ComputeMaskedBits.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin | grep extsw | count 2 + +@lens = external global i8* ; <i8**> [#uses=1] +@vals = external global i32* ; <i32**> [#uses=1] + +define i32 @test(i32 %i) { + %tmp = load i8** @lens ; <i8*> [#uses=1] + %tmp1 = getelementptr i8* %tmp, i32 %i ; <i8*> [#uses=1] + %tmp.upgrd.1 = load i8* %tmp1 ; <i8> [#uses=1] + %tmp2 = zext i8 %tmp.upgrd.1 to i32 ; <i32> [#uses=1] + %tmp3 = load i32** @vals ; <i32*> [#uses=1] + %tmp5 = sub i32 1, %tmp2 ; <i32> [#uses=1] + %tmp6 = getelementptr i32* %tmp3, i32 %tmp5 ; <i32*> [#uses=1] + %tmp7 = load i32* %tmp6 ; <i32> [#uses=1] + ret i32 %tmp7 +} + diff --git a/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll b/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll new file mode 100644 index 000000000000..c25cf215bc34 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + +define void @img2buf(i32 %symbol_size_in_bytes, i16* %ui16) { + %tmp93 = load i16* null ; <i16> [#uses=1] + %tmp99 = call i16 @llvm.bswap.i16( i16 %tmp93 ) ; <i16> [#uses=1] + store i16 %tmp99, i16* %ui16 + ret void +} + +declare i16 @llvm.bswap.i16(i16) + diff --git a/test/CodeGen/PowerPC/2006-08-11-RetVector.ll b/test/CodeGen/PowerPC/2006-08-11-RetVector.ll new file mode 100644 index 000000000000..1043e45efb11 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-08-11-RetVector.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsldoi +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vor + +define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) { + %tmp76 = shufflevector <4 x float> %fp0, <4 x float> %fp1, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>> [#uses=1] + ret <4 x float> %tmp76 +} + diff --git a/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll new file mode 100644 index 000000000000..aff4edeba54b --- /dev/null +++ b/test/CodeGen/PowerPC/2006-08-15-SelectionCrash.ll @@ -0,0 +1,30 @@ +; RUN: llvm-as < %s | llc + + %struct..0anon = type { i32 } + %struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] } + +define fastcc void @immed_double_const(i32 %i0, i32 %i1) { +entry: + %tmp1 = load i32* null ; <i32> [#uses=1] + switch i32 %tmp1, label %bb103 [ + i32 1, label %bb + i32 3, label %bb + ] +bb: ; preds = %entry, %entry + %tmp14 = icmp sgt i32 0, 31 ; <i1> [#uses=1] + br i1 %tmp14, label %cond_next77, label %cond_next17 +cond_next17: ; preds = %bb + ret void +cond_next77: ; preds = %bb + %tmp79.not = icmp ne i32 %i1, 0 ; <i1> [#uses=1] + %tmp84 = icmp slt i32 %i0, 0 ; <i1> [#uses=2] + %bothcond1 = or i1 %tmp79.not, %tmp84 ; <i1> [#uses=1] + br i1 %bothcond1, label %bb88, label %bb99 +bb88: ; preds = %cond_next77 + %bothcond2 = and i1 false, %tmp84 ; <i1> [#uses=0] + ret void +bb99: ; preds = %cond_next77 + ret void +bb103: ; preds = %entry + ret void +} diff --git a/test/CodeGen/PowerPC/2006-09-28-shift_64.ll b/test/CodeGen/PowerPC/2006-09-28-shift_64.ll new file mode 100644 index 000000000000..5210dd1cb1a8 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-09-28-shift_64.ll @@ -0,0 +1,25 @@ +; RUN: llvm-as < %s | llc -march=ppc64 + +target datalayout = "E-p:64:64" +target triple = "powerpc64-apple-darwin8" + +define void @glArrayElement_CompExec() { +entry: + %tmp3 = and i64 0, -8388609 ; <i64> [#uses=1] + br label %cond_true24 +cond_false: ; preds = %cond_true24 + ret void +cond_true24: ; preds = %cond_true24, %entry + %indvar.ph = phi i32 [ 0, %entry ], [ %indvar.next, %cond_true24 ] ; <i32> [#uses=1] + %indvar = add i32 0, %indvar.ph ; <i32> [#uses=2] + %code.0 = trunc i32 %indvar to i8 ; <i8> [#uses=1] + %tmp5 = add i8 %code.0, 16 ; <i8> [#uses=1] + %shift.upgrd.1 = zext i8 %tmp5 to i64 ; <i64> [#uses=1] + %tmp7 = lshr i64 %tmp3, %shift.upgrd.1 ; <i64> [#uses=1] + %tmp7.upgrd.2 = trunc i64 %tmp7 to i32 ; <i32> [#uses=1] + %tmp8 = and i32 %tmp7.upgrd.2, 1 ; <i32> [#uses=1] + %tmp8.upgrd.3 = icmp eq i32 %tmp8, 0 ; <i1> [#uses=1] + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1] + br i1 %tmp8.upgrd.3, label %cond_false, label %cond_true24 +} + diff --git a/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll b/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll new file mode 100644 index 000000000000..a58cd162b4e8 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-10-11-combiner-aa-regression.ll @@ -0,0 +1,24 @@ +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -combiner-alias-analysis | grep f5 + +target datalayout = "E-p:32:32" +target triple = "powerpc-apple-darwin8.2.0" + %struct.Point = type { double, double, double } + +define void @offset(%struct.Point* %pt, double %x, double %y, double %z) { +entry: + %tmp = getelementptr %struct.Point* %pt, i32 0, i32 0 ; <double*> [#uses=2] + %tmp.upgrd.1 = load double* %tmp ; <double> [#uses=1] + %tmp2 = add double %tmp.upgrd.1, %x ; <double> [#uses=1] + store double %tmp2, double* %tmp + %tmp6 = getelementptr %struct.Point* %pt, i32 0, i32 1 ; <double*> [#uses=2] + %tmp7 = load double* %tmp6 ; <double> [#uses=1] + %tmp9 = add double %tmp7, %y ; <double> [#uses=1] + store double %tmp9, double* %tmp6 + %tmp13 = getelementptr %struct.Point* %pt, i32 0, i32 2 ; <double*> [#uses=2] + %tmp14 = load double* %tmp13 ; <double> [#uses=1] + %tmp16 = add double %tmp14, %z ; <double> [#uses=1] + store double %tmp16, double* %tmp13 + ret void +} + diff --git a/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll new file mode 100644 index 000000000000..6621cec7f43e --- /dev/null +++ b/test/CodeGen/PowerPC/2006-10-13-Miscompile.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep IMPLICIT_DEF + +define void @foo(i64 %X) { +entry: + %tmp1 = and i64 %X, 3 ; <i64> [#uses=1] + %tmp = icmp sgt i64 %tmp1, 2 ; <i1> [#uses=1] + br i1 %tmp, label %UnifiedReturnBlock, label %cond_true +cond_true: ; preds = %entry + %tmp.upgrd.1 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + ret void +UnifiedReturnBlock: ; preds = %entry + ret void +} + +declare i32 @bar(...) + diff --git a/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll new file mode 100644 index 000000000000..313568c1e4be --- /dev/null +++ b/test/CodeGen/PowerPC/2006-10-17-brcc-miscompile.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep xor + +target datalayout = "E-p:32:32" +target triple = "powerpc-apple-darwin8.7.0" + +define void @foo(i32 %X) { +entry: + %tmp1 = and i32 %X, 3 ; <i32> [#uses=1] + %tmp2 = xor i32 %tmp1, 1 ; <i32> [#uses=1] + %tmp = icmp eq i32 %tmp2, 0 ; <i1> [#uses=1] + br i1 %tmp, label %UnifiedReturnBlock, label %cond_true +cond_true: ; preds = %entry + tail call i32 (...)* @bar( ) ; <i32>:0 [#uses=0] + ret void +UnifiedReturnBlock: ; preds = %entry + ret void +} + +declare i32 @bar(...) + diff --git a/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll b/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll new file mode 100644 index 000000000000..6dc1ff037eb3 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-10-17-ppc64-alloca.ll @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=ppc64 + +define i32* @foo(i32 %n) { + %A = alloca i32, i32 %n ; <i32*> [#uses=1] + ret i32* %A +} + diff --git a/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll b/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll new file mode 100644 index 000000000000..80ef479fb076 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwimi + +define void @test(i16 %div.0.i.i.i.i, i32 %L_num.0.i.i.i.i, i32 %tmp1.i.i206.i.i, i16* %P) { + %X = shl i16 %div.0.i.i.i.i, 1 ; <i16> [#uses=1] + %tmp28.i.i.i.i = shl i32 %L_num.0.i.i.i.i, 1 ; <i32> [#uses=1] + %tmp31.i.i.i.i = icmp slt i32 %tmp28.i.i.i.i, %tmp1.i.i206.i.i ; <i1> [#uses=1] + %tmp31.i.i.i.i.upgrd.1 = zext i1 %tmp31.i.i.i.i to i16 ; <i16> [#uses=1] + %tmp371.i.i.i.i1 = or i16 %tmp31.i.i.i.i.upgrd.1, %X ; <i16> [#uses=1] + %div.0.be.i.i.i.i = xor i16 %tmp371.i.i.i.i1, 1 ; <i16> [#uses=1] + store i16 %div.0.be.i.i.i.i, i16* %P + ret void +} + diff --git a/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll b/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll new file mode 100644 index 000000000000..7680c215c217 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-11-29-AltivecFPSplat.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 + +define void @glgRunProcessor15() { + %tmp26355.i = shufflevector <4 x float> zeroinitializer, <4 x float> < float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000, float 0x379FFFE000000000 >, <4 x i32> < i32 0, i32 1, i32 2, i32 7 >; <<4 x float>> [#uses=1] + %tmp3030030304.i = bitcast <4 x float> %tmp26355.i to <8 x i16> ; <<8 x i16>> [#uses=1] + %tmp30305.i = shufflevector <8 x i16> zeroinitializer, <8 x i16> %tmp3030030304.i, <8 x i32> < i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15 > ; <<8 x i16>> [#uses=1] + %tmp30305.i.upgrd.1 = bitcast <8 x i16> %tmp30305.i to <4 x i32> ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp30305.i.upgrd.1, <4 x i32>* null + ret void +} diff --git a/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll new file mode 100644 index 000000000000..be3b86308f13 --- /dev/null +++ b/test/CodeGen/PowerPC/2006-12-07-LargeAlloca.ll @@ -0,0 +1,24 @@ +; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llvm-as < %s | llc + +define void @bitap() { +entry: + %RMask.i = alloca [256 x i32], align 16 ; <[256 x i32]*> [#uses=1] + %buffer = alloca [147456 x i8], align 16 ; <[147456 x i8]*> [#uses=0] + br i1 false, label %bb19, label %bb.preheader +bb.preheader: ; preds = %entry + ret void +bb19: ; preds = %entry + br i1 false, label %bb12.i, label %cond_next39 +bb12.i: ; preds = %bb12.i, %bb19 + %i.0.i = phi i32 [ %tmp11.i, %bb12.i ], [ 0, %bb19 ] ; <i32> [#uses=2] + %gep.upgrd.1 = zext i32 %i.0.i to i64 ; <i64> [#uses=1] + %tmp9.i = getelementptr [256 x i32]* %RMask.i, i32 0, i64 %gep.upgrd.1 ; <i32*> [#uses=1] + store i32 0, i32* %tmp9.i + %tmp11.i = add i32 %i.0.i, 1 ; <i32> [#uses=1] + br label %bb12.i +cond_next39: ; preds = %bb19 + ret void +} + diff --git a/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll new file mode 100644 index 000000000000..058166ff93db --- /dev/null +++ b/test/CodeGen/PowerPC/2006-12-07-SelectCrash.ll @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=ppc64 +; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llvm-as < %s | llc + +@qsz.b = external global i1 ; <i1*> [#uses=1] + +define fastcc void @qst() { +entry: + br i1 true, label %cond_next71, label %cond_true +cond_true: ; preds = %entry + ret void +cond_next71: ; preds = %entry + %tmp73.b = load i1* @qsz.b ; <i1> [#uses=1] + %ii.4.ph = select i1 %tmp73.b, i64 4, i64 0 ; <i64> [#uses=1] + br label %bb139 +bb82: ; preds = %bb139 + ret void +bb139: ; preds = %bb139, %cond_next71 + %exitcond89 = icmp eq i64 0, %ii.4.ph ; <i1> [#uses=1] + br i1 %exitcond89, label %bb82, label %bb139 +} + diff --git a/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll b/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll new file mode 100644 index 000000000000..19fedf9f5962 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-01-04-ArgExtension.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep extsb +; RUN: llvm-as < %s | llc -march=ppc32 | grep extsh + +define i32 @p1(i8 %c, i16 %s) { +entry: + %tmp = sext i8 %c to i32 ; <i32> [#uses=1] + %tmp1 = sext i16 %s to i32 ; <i32> [#uses=1] + %tmp2 = add i32 %tmp1, %tmp ; <i32> [#uses=1] + ret i32 %tmp2 +} diff --git a/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll new file mode 100644 index 000000000000..d9374edfe865 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-01-15-AsmDialect.ll @@ -0,0 +1,27 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep cntlzw + +define i32 @foo() { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=2] + %temp = alloca i32, align 4 ; <i32*> [#uses=2] + %ctz_x = alloca i32, align 4 ; <i32*> [#uses=3] + %ctz_c = alloca i32, align 4 ; <i32*> [#uses=2] + "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i32 61440, i32* %ctz_x + %tmp = load i32* %ctz_x ; <i32> [#uses=1] + %tmp1 = sub i32 0, %tmp ; <i32> [#uses=1] + %tmp2 = load i32* %ctz_x ; <i32> [#uses=1] + %tmp3 = and i32 %tmp1, %tmp2 ; <i32> [#uses=1] + %tmp4 = call i32 asm "$(cntlz$|cntlzw$) $0,$1", "=r,r,~{dirflag},~{fpsr},~{flags}"( i32 %tmp3 ) ; <i32> [#uses=1] + store i32 %tmp4, i32* %ctz_c + %tmp5 = load i32* %ctz_c ; <i32> [#uses=1] + store i32 %tmp5, i32* %temp + %tmp6 = load i32* %temp ; <i32> [#uses=1] + store i32 %tmp6, i32* %retval + br label %return + +return: ; preds = %entry + %retval2 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval2 +} diff --git a/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll b/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll new file mode 100644 index 000000000000..f2c951ec21d5 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llvm-as < %s | llc -march=ppc64 + +define i16 @test(i8* %d1, i16* %d2) { + %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) ; <i16> [#uses=1] + ret i16 %tmp237 +} diff --git a/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll new file mode 100644 index 000000000000..d4764622af68 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll @@ -0,0 +1,24 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llvm-as < %s | llc -march=ppc64 + +; Test two things: 1) that a frameidx can be rewritten in an inline asm +; 2) that inline asms can handle reg+imm addr modes. + + %struct.A = type { i32, i32 } + + +define void @test1() { +entry: + %Out = alloca %struct.A, align 4 ; <%struct.A*> [#uses=1] + %tmp2 = getelementptr %struct.A* %Out, i32 0, i32 1 + %tmp5 = call i32 asm "lwbrx $0, $1", "=r,m"(i32* %tmp2 ) + ret void +} + +define void @test2() { +entry: + %Out = alloca %struct.A, align 4 ; <%struct.A*> [#uses=1] + %tmp2 = getelementptr %struct.A* %Out, i32 0, i32 0 ; <i32*> [#uses=1] + %tmp5 = call i32 asm "lwbrx $0, $2, $1", "=r,r,bO,m"( i8* null, i32 0, i32* %tmp2 ) ; <i32> [#uses=0] + ret void +} diff --git a/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll b/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll new file mode 100644 index 000000000000..97f6a018b30b --- /dev/null +++ b/test/CodeGen/PowerPC/2007-02-16-AlignPacked.ll @@ -0,0 +1,4 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | \ +; RUN: grep align.*3 + +@X = global <{i32, i32}> <{ i32 1, i32 123 }> diff --git a/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll b/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll new file mode 100644 index 000000000000..5a3d3b5d9c1c --- /dev/null +++ b/test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc + +target datalayout = "E-p:32:32" +target triple = "powerpc-apple-darwin8.8.0" + + +define void @blargh() { +entry: + %tmp4 = call i32 asm "rlwimi $0,$2,$3,$4,$5", "=r,0,r,n,n,n"( i32 0, i32 0, i32 0, i32 24, i32 31 ) ; <i32> [#uses=0] + unreachable +} diff --git a/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll b/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll new file mode 100644 index 000000000000..3eef9c551b75 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-02-23-lr-saved-twice.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc | grep mflr | count 1 + +target datalayout = "e-p:32:32" +target triple = "powerpc-apple-darwin8" +@str = internal constant [18 x i8] c"hello world!, %d\0A\00" ; <[18 x i8]*> [#uses=1] + + +define i32 @main() { +entry: + %tmp = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([18 x i8]* @str, i32 0, i32 0) ) ; <i32> [#uses=0] + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll new file mode 100644 index 000000000000..098e7484e173 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=ppc64 -mcpu=g5 | grep cntlzd + +define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) { + %tmp19 = load i64* %t + %tmp22 = tail call i64 @llvm.ctlz.i64( i64 %tmp19 ) ; <i64> [#uses=1] + %tmp23 = trunc i64 %tmp22 to i32 + %tmp89 = add i32 %tmp23, -64 ; <i32> [#uses=1] + %tmp90 = add i32 %tmp89, 0 ; <i32> [#uses=1] + ret i32 %tmp90 +} + +declare i64 @llvm.ctlz.i64(i64) diff --git a/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll b/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll new file mode 100644 index 000000000000..04ca3bbde1d3 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-03-30-SpillerCrash.ll @@ -0,0 +1,1801 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 + +define void @test(<4 x float>*, { { i16, i16, i32 } }*) { +xOperationInitMasks.exit: + %.sub7896 = getelementptr [4 x <4 x i32>]* null, i32 0, i32 0 ; <<4 x i32>*> [#uses=24] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 175, i32 3 ; <<4 x float>*>:2 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 174, i32 2 ; <<4 x float>*>:3 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 174, i32 3 ; <<4 x float>*>:4 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 1 ; <<4 x float>*>:5 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 2 ; <<4 x float>*>:6 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 3 ; <<4 x float>*>:7 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 1 ; <<4 x float>*>:8 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 2 ; <<4 x float>*>:9 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 3 ; <<4 x float>*>:10 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 1 ; <<4 x float>*>:11 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 2 ; <<4 x float>*>:12 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 171, i32 3 ; <<4 x float>*>:13 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 1 ; <<4 x float>*>:14 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 2 ; <<4 x float>*>:15 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 170, i32 3 ; <<4 x float>*>:16 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 1 ; <<4 x float>*>:17 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 2 ; <<4 x float>*>:18 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 169, i32 3 ; <<4 x float>*>:19 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 1 ; <<4 x float>*>:20 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 2 ; <<4 x float>*>:21 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 168, i32 3 ; <<4 x float>*>:22 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 1 ; <<4 x float>*>:23 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 2 ; <<4 x float>*>:24 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 167, i32 3 ; <<4 x float>*>:25 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 1 ; <<4 x float>*>:26 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 2 ; <<4 x float>*>:27 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 166, i32 3 ; <<4 x float>*>:28 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 1 ; <<4 x float>*>:29 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 2 ; <<4 x float>*>:30 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 165, i32 3 ; <<4 x float>*>:31 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 1 ; <<4 x float>*>:32 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 2 ; <<4 x float>*>:33 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 164, i32 3 ; <<4 x float>*>:34 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 1 ; <<4 x float>*>:35 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 2 ; <<4 x float>*>:36 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 163, i32 3 ; <<4 x float>*>:37 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 1 ; <<4 x float>*>:38 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 2 ; <<4 x float>*>:39 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 162, i32 3 ; <<4 x float>*>:40 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 1 ; <<4 x float>*>:41 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 2 ; <<4 x float>*>:42 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 161, i32 3 ; <<4 x float>*>:43 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 1 ; <<4 x float>*>:44 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 2 ; <<4 x float>*>:45 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 160, i32 3 ; <<4 x float>*>:46 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 1 ; <<4 x float>*>:47 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 2 ; <<4 x float>*>:48 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 159, i32 3 ; <<4 x float>*>:49 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 1 ; <<4 x float>*>:50 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 2 ; <<4 x float>*>:51 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 158, i32 3 ; <<4 x float>*>:52 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 1 ; <<4 x float>*>:53 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 2 ; <<4 x float>*>:54 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 157, i32 3 ; <<4 x float>*>:55 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 1 ; <<4 x float>*>:56 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 2 ; <<4 x float>*>:57 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 156, i32 3 ; <<4 x float>*>:58 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 1 ; <<4 x float>*>:59 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 2 ; <<4 x float>*>:60 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 155, i32 3 ; <<4 x float>*>:61 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 1 ; <<4 x float>*>:62 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 2 ; <<4 x float>*>:63 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 154, i32 3 ; <<4 x float>*>:64 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 1 ; <<4 x float>*>:65 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 2 ; <<4 x float>*>:66 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 153, i32 3 ; <<4 x float>*>:67 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 1 ; <<4 x float>*>:68 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 2 ; <<4 x float>*>:69 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 152, i32 3 ; <<4 x float>*>:70 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 1 ; <<4 x float>*>:71 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 2 ; <<4 x float>*>:72 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 151, i32 3 ; <<4 x float>*>:73 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 1 ; <<4 x float>*>:74 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 2 ; <<4 x float>*>:75 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 150, i32 3 ; <<4 x float>*>:76 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 1 ; <<4 x float>*>:77 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 2 ; <<4 x float>*>:78 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 149, i32 3 ; <<4 x float>*>:79 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 1 ; <<4 x float>*>:80 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 2 ; <<4 x float>*>:81 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 148, i32 3 ; <<4 x float>*>:82 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 1 ; <<4 x float>*>:83 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 2 ; <<4 x float>*>:84 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 147, i32 3 ; <<4 x float>*>:85 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 1 ; <<4 x float>*>:86 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 2 ; <<4 x float>*>:87 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 146, i32 3 ; <<4 x float>*>:88 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 145, i32 1 ; <<4 x float>*>:89 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 145, i32 2 ; <<4 x float>*>:90 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 145, i32 3 ; <<4 x float>*>:91 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 144, i32 1 ; <<4 x float>*>:92 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 144, i32 2 ; <<4 x float>*>:93 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 144, i32 3 ; <<4 x float>*>:94 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 143, i32 1 ; <<4 x float>*>:95 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 143, i32 2 ; <<4 x float>*>:96 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 143, i32 3 ; <<4 x float>*>:97 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 142, i32 1 ; <<4 x float>*>:98 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 142, i32 2 ; <<4 x float>*>:99 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 142, i32 3 ; <<4 x float>*>:100 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 141, i32 1 ; <<4 x float>*>:101 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 141, i32 2 ; <<4 x float>*>:102 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 141, i32 3 ; <<4 x float>*>:103 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 140, i32 1 ; <<4 x float>*>:104 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 140, i32 2 ; <<4 x float>*>:105 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 140, i32 3 ; <<4 x float>*>:106 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 139, i32 1 ; <<4 x float>*>:107 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 139, i32 2 ; <<4 x float>*>:108 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 139, i32 3 ; <<4 x float>*>:109 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 138, i32 1 ; <<4 x float>*>:110 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 138, i32 2 ; <<4 x float>*>:111 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 138, i32 3 ; <<4 x float>*>:112 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 137, i32 1 ; <<4 x float>*>:113 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 137, i32 2 ; <<4 x float>*>:114 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 137, i32 3 ; <<4 x float>*>:115 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 136, i32 1 ; <<4 x float>*>:116 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 136, i32 2 ; <<4 x float>*>:117 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 136, i32 3 ; <<4 x float>*>:118 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 135, i32 1 ; <<4 x float>*>:119 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 135, i32 2 ; <<4 x float>*>:120 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 135, i32 3 ; <<4 x float>*>:121 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 134, i32 1 ; <<4 x float>*>:122 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 134, i32 2 ; <<4 x float>*>:123 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 134, i32 3 ; <<4 x float>*>:124 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 133, i32 1 ; <<4 x float>*>:125 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 133, i32 2 ; <<4 x float>*>:126 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 133, i32 3 ; <<4 x float>*>:127 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 132, i32 1 ; <<4 x float>*>:128 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 132, i32 2 ; <<4 x float>*>:129 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 132, i32 3 ; <<4 x float>*>:130 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 131, i32 1 ; <<4 x float>*>:131 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 131, i32 2 ; <<4 x float>*>:132 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 131, i32 3 ; <<4 x float>*>:133 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 130, i32 1 ; <<4 x float>*>:134 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 130, i32 2 ; <<4 x float>*>:135 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 130, i32 3 ; <<4 x float>*>:136 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 1 ; <<4 x float>*>:137 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 2 ; <<4 x float>*>:138 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 129, i32 3 ; <<4 x float>*>:139 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 1 ; <<4 x float>*>:140 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 2 ; <<4 x float>*>:141 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 128, i32 3 ; <<4 x float>*>:142 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 1 ; <<4 x float>*>:143 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 2 ; <<4 x float>*>:144 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 127, i32 3 ; <<4 x float>*>:145 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 1 ; <<4 x float>*>:146 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 2 ; <<4 x float>*>:147 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 126, i32 3 ; <<4 x float>*>:148 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 1 ; <<4 x float>*>:149 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 2 ; <<4 x float>*>:150 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 125, i32 3 ; <<4 x float>*>:151 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 1 ; <<4 x float>*>:152 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 2 ; <<4 x float>*>:153 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 124, i32 3 ; <<4 x float>*>:154 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 1 ; <<4 x float>*>:155 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 2 ; <<4 x float>*>:156 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 123, i32 3 ; <<4 x float>*>:157 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 1 ; <<4 x float>*>:158 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 2 ; <<4 x float>*>:159 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 122, i32 3 ; <<4 x float>*>:160 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 1 ; <<4 x float>*>:161 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 2 ; <<4 x float>*>:162 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 121, i32 3 ; <<4 x float>*>:163 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 1 ; <<4 x float>*>:164 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 2 ; <<4 x float>*>:165 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 120, i32 3 ; <<4 x float>*>:166 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 1 ; <<4 x float>*>:167 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 2 ; <<4 x float>*>:168 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 119, i32 3 ; <<4 x float>*>:169 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 1 ; <<4 x float>*>:170 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 2 ; <<4 x float>*>:171 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 118, i32 3 ; <<4 x float>*>:172 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 1 ; <<4 x float>*>:173 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 2 ; <<4 x float>*>:174 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 117, i32 3 ; <<4 x float>*>:175 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 1 ; <<4 x float>*>:176 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 2 ; <<4 x float>*>:177 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 116, i32 3 ; <<4 x float>*>:178 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 1 ; <<4 x float>*>:179 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 2 ; <<4 x float>*>:180 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 115, i32 3 ; <<4 x float>*>:181 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 1 ; <<4 x float>*>:182 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 2 ; <<4 x float>*>:183 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 114, i32 3 ; <<4 x float>*>:184 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 1 ; <<4 x float>*>:185 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 2 ; <<4 x float>*>:186 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 113, i32 3 ; <<4 x float>*>:187 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 1 ; <<4 x float>*>:188 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 2 ; <<4 x float>*>:189 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 112, i32 3 ; <<4 x float>*>:190 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 1 ; <<4 x float>*>:191 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 2 ; <<4 x float>*>:192 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 111, i32 3 ; <<4 x float>*>:193 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 1 ; <<4 x float>*>:194 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 2 ; <<4 x float>*>:195 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 110, i32 3 ; <<4 x float>*>:196 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 1 ; <<4 x float>*>:197 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 2 ; <<4 x float>*>:198 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 109, i32 3 ; <<4 x float>*>:199 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 1 ; <<4 x float>*>:200 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 2 ; <<4 x float>*>:201 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 108, i32 3 ; <<4 x float>*>:202 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 1 ; <<4 x float>*>:203 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 2 ; <<4 x float>*>:204 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 107, i32 3 ; <<4 x float>*>:205 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 1 ; <<4 x float>*>:206 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 2 ; <<4 x float>*>:207 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 106, i32 3 ; <<4 x float>*>:208 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 1 ; <<4 x float>*>:209 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 2 ; <<4 x float>*>:210 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 105, i32 3 ; <<4 x float>*>:211 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 1 ; <<4 x float>*>:212 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 2 ; <<4 x float>*>:213 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 104, i32 3 ; <<4 x float>*>:214 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 1 ; <<4 x float>*>:215 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 2 ; <<4 x float>*>:216 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 103, i32 3 ; <<4 x float>*>:217 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 1 ; <<4 x float>*>:218 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 2 ; <<4 x float>*>:219 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 102, i32 3 ; <<4 x float>*>:220 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 1 ; <<4 x float>*>:221 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 2 ; <<4 x float>*>:222 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 101, i32 3 ; <<4 x float>*>:223 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 1 ; <<4 x float>*>:224 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 2 ; <<4 x float>*>:225 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 100, i32 3 ; <<4 x float>*>:226 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 1 ; <<4 x float>*>:227 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 2 ; <<4 x float>*>:228 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 99, i32 3 ; <<4 x float>*>:229 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 1 ; <<4 x float>*>:230 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 2 ; <<4 x float>*>:231 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 98, i32 3 ; <<4 x float>*>:232 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 1 ; <<4 x float>*>:233 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 2 ; <<4 x float>*>:234 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 97, i32 3 ; <<4 x float>*>:235 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 1 ; <<4 x float>*>:236 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 2 ; <<4 x float>*>:237 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 96, i32 3 ; <<4 x float>*>:238 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 1 ; <<4 x float>*>:239 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 2 ; <<4 x float>*>:240 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 95, i32 3 ; <<4 x float>*>:241 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 1 ; <<4 x float>*>:242 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 2 ; <<4 x float>*>:243 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 94, i32 3 ; <<4 x float>*>:244 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 1 ; <<4 x float>*>:245 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 2 ; <<4 x float>*>:246 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 93, i32 3 ; <<4 x float>*>:247 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 1 ; <<4 x float>*>:248 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 2 ; <<4 x float>*>:249 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 92, i32 3 ; <<4 x float>*>:250 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 1 ; <<4 x float>*>:251 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 2 ; <<4 x float>*>:252 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 91, i32 3 ; <<4 x float>*>:253 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 1 ; <<4 x float>*>:254 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 2 ; <<4 x float>*>:255 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 90, i32 3 ; <<4 x float>*>:256 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 1 ; <<4 x float>*>:257 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 2 ; <<4 x float>*>:258 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 89, i32 3 ; <<4 x float>*>:259 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 1 ; <<4 x float>*>:260 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 2 ; <<4 x float>*>:261 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 88, i32 3 ; <<4 x float>*>:262 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 1 ; <<4 x float>*>:263 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 2 ; <<4 x float>*>:264 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 87, i32 3 ; <<4 x float>*>:265 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 1 ; <<4 x float>*>:266 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 2 ; <<4 x float>*>:267 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 86, i32 3 ; <<4 x float>*>:268 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 85, i32 1 ; <<4 x float>*>:269 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 85, i32 2 ; <<4 x float>*>:270 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 85, i32 3 ; <<4 x float>*>:271 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 84, i32 1 ; <<4 x float>*>:272 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 84, i32 2 ; <<4 x float>*>:273 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 84, i32 3 ; <<4 x float>*>:274 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 83, i32 1 ; <<4 x float>*>:275 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 83, i32 2 ; <<4 x float>*>:276 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 83, i32 3 ; <<4 x float>*>:277 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 82, i32 1 ; <<4 x float>*>:278 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 82, i32 2 ; <<4 x float>*>:279 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 82, i32 3 ; <<4 x float>*>:280 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 81, i32 1 ; <<4 x float>*>:281 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 81, i32 2 ; <<4 x float>*>:282 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 81, i32 3 ; <<4 x float>*>:283 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 80, i32 1 ; <<4 x float>*>:284 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 80, i32 2 ; <<4 x float>*>:285 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 80, i32 3 ; <<4 x float>*>:286 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 79, i32 1 ; <<4 x float>*>:287 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 79, i32 2 ; <<4 x float>*>:288 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 79, i32 3 ; <<4 x float>*>:289 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 78, i32 1 ; <<4 x float>*>:290 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 78, i32 2 ; <<4 x float>*>:291 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 78, i32 3 ; <<4 x float>*>:292 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 77, i32 1 ; <<4 x float>*>:293 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 77, i32 2 ; <<4 x float>*>:294 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 77, i32 3 ; <<4 x float>*>:295 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 76, i32 1 ; <<4 x float>*>:296 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 76, i32 2 ; <<4 x float>*>:297 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 76, i32 3 ; <<4 x float>*>:298 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 75, i32 1 ; <<4 x float>*>:299 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 75, i32 2 ; <<4 x float>*>:300 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 75, i32 3 ; <<4 x float>*>:301 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 74, i32 1 ; <<4 x float>*>:302 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 74, i32 2 ; <<4 x float>*>:303 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 74, i32 3 ; <<4 x float>*>:304 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 73, i32 1 ; <<4 x float>*>:305 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 73, i32 2 ; <<4 x float>*>:306 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 73, i32 3 ; <<4 x float>*>:307 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 72, i32 1 ; <<4 x float>*>:308 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 72, i32 2 ; <<4 x float>*>:309 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 72, i32 3 ; <<4 x float>*>:310 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 71, i32 1 ; <<4 x float>*>:311 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 71, i32 2 ; <<4 x float>*>:312 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 71, i32 3 ; <<4 x float>*>:313 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 70, i32 1 ; <<4 x float>*>:314 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 70, i32 2 ; <<4 x float>*>:315 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 70, i32 3 ; <<4 x float>*>:316 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 69, i32 1 ; <<4 x float>*>:317 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 69, i32 2 ; <<4 x float>*>:318 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 69, i32 3 ; <<4 x float>*>:319 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 68, i32 1 ; <<4 x float>*>:320 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 68, i32 2 ; <<4 x float>*>:321 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 68, i32 3 ; <<4 x float>*>:322 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 67, i32 1 ; <<4 x float>*>:323 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 67, i32 2 ; <<4 x float>*>:324 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 67, i32 3 ; <<4 x float>*>:325 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 66, i32 1 ; <<4 x float>*>:326 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 66, i32 2 ; <<4 x float>*>:327 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 66, i32 3 ; <<4 x float>*>:328 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 65, i32 1 ; <<4 x float>*>:329 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 65, i32 2 ; <<4 x float>*>:330 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 65, i32 3 ; <<4 x float>*>:331 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 64, i32 1 ; <<4 x float>*>:332 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 64, i32 2 ; <<4 x float>*>:333 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 64, i32 3 ; <<4 x float>*>:334 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 63, i32 1 ; <<4 x float>*>:335 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 63, i32 2 ; <<4 x float>*>:336 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 63, i32 3 ; <<4 x float>*>:337 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 62, i32 1 ; <<4 x float>*>:338 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 62, i32 2 ; <<4 x float>*>:339 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 62, i32 3 ; <<4 x float>*>:340 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 61, i32 1 ; <<4 x float>*>:341 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 61, i32 2 ; <<4 x float>*>:342 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 61, i32 3 ; <<4 x float>*>:343 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 60, i32 1 ; <<4 x float>*>:344 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 60, i32 2 ; <<4 x float>*>:345 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 60, i32 3 ; <<4 x float>*>:346 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 59, i32 1 ; <<4 x float>*>:347 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 59, i32 2 ; <<4 x float>*>:348 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 59, i32 3 ; <<4 x float>*>:349 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 58, i32 1 ; <<4 x float>*>:350 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 58, i32 2 ; <<4 x float>*>:351 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 58, i32 3 ; <<4 x float>*>:352 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 57, i32 1 ; <<4 x float>*>:353 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 57, i32 2 ; <<4 x float>*>:354 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 57, i32 3 ; <<4 x float>*>:355 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 1 ; <<4 x float>*>:356 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 2 ; <<4 x float>*>:357 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 56, i32 3 ; <<4 x float>*>:358 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 1 ; <<4 x float>*>:359 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 2 ; <<4 x float>*>:360 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 55, i32 3 ; <<4 x float>*>:361 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 1 ; <<4 x float>*>:362 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 2 ; <<4 x float>*>:363 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 54, i32 3 ; <<4 x float>*>:364 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 1 ; <<4 x float>*>:365 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 2 ; <<4 x float>*>:366 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 53, i32 3 ; <<4 x float>*>:367 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 1 ; <<4 x float>*>:368 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 2 ; <<4 x float>*>:369 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 52, i32 3 ; <<4 x float>*>:370 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 1 ; <<4 x float>*>:371 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 2 ; <<4 x float>*>:372 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 51, i32 3 ; <<4 x float>*>:373 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 1 ; <<4 x float>*>:374 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 2 ; <<4 x float>*>:375 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 50, i32 3 ; <<4 x float>*>:376 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 1 ; <<4 x float>*>:377 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 2 ; <<4 x float>*>:378 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 49, i32 3 ; <<4 x float>*>:379 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 1 ; <<4 x float>*>:380 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 2 ; <<4 x float>*>:381 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 48, i32 3 ; <<4 x float>*>:382 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 1 ; <<4 x float>*>:383 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 2 ; <<4 x float>*>:384 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 47, i32 3 ; <<4 x float>*>:385 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 1 ; <<4 x float>*>:386 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 2 ; <<4 x float>*>:387 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 46, i32 3 ; <<4 x float>*>:388 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 1 ; <<4 x float>*>:389 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 2 ; <<4 x float>*>:390 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 45, i32 3 ; <<4 x float>*>:391 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 1 ; <<4 x float>*>:392 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 2 ; <<4 x float>*>:393 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 44, i32 3 ; <<4 x float>*>:394 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 1 ; <<4 x float>*>:395 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 2 ; <<4 x float>*>:396 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 43, i32 3 ; <<4 x float>*>:397 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 1 ; <<4 x float>*>:398 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 2 ; <<4 x float>*>:399 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 42, i32 3 ; <<4 x float>*>:400 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 1 ; <<4 x float>*>:401 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 2 ; <<4 x float>*>:402 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 41, i32 3 ; <<4 x float>*>:403 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 1 ; <<4 x float>*>:404 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 2 ; <<4 x float>*>:405 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 40, i32 3 ; <<4 x float>*>:406 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 1 ; <<4 x float>*>:407 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 2 ; <<4 x float>*>:408 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 39, i32 3 ; <<4 x float>*>:409 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 1 ; <<4 x float>*>:410 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 2 ; <<4 x float>*>:411 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 38, i32 3 ; <<4 x float>*>:412 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 1 ; <<4 x float>*>:413 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 2 ; <<4 x float>*>:414 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 37, i32 3 ; <<4 x float>*>:415 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 1 ; <<4 x float>*>:416 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 2 ; <<4 x float>*>:417 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 36, i32 3 ; <<4 x float>*>:418 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 1 ; <<4 x float>*>:419 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 2 ; <<4 x float>*>:420 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 35, i32 3 ; <<4 x float>*>:421 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 1 ; <<4 x float>*>:422 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 2 ; <<4 x float>*>:423 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 34, i32 3 ; <<4 x float>*>:424 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 1 ; <<4 x float>*>:425 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 2 ; <<4 x float>*>:426 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 33, i32 3 ; <<4 x float>*>:427 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 1 ; <<4 x float>*>:428 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 2 ; <<4 x float>*>:429 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 32, i32 3 ; <<4 x float>*>:430 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 1 ; <<4 x float>*>:431 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 2 ; <<4 x float>*>:432 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 31, i32 3 ; <<4 x float>*>:433 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 1 ; <<4 x float>*>:434 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 2 ; <<4 x float>*>:435 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 30, i32 3 ; <<4 x float>*>:436 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 1 ; <<4 x float>*>:437 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 2 ; <<4 x float>*>:438 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 29, i32 3 ; <<4 x float>*>:439 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 1 ; <<4 x float>*>:440 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 2 ; <<4 x float>*>:441 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 28, i32 3 ; <<4 x float>*>:442 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 1 ; <<4 x float>*>:443 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 2 ; <<4 x float>*>:444 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 27, i32 3 ; <<4 x float>*>:445 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 1 ; <<4 x float>*>:446 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 2 ; <<4 x float>*>:447 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 26, i32 3 ; <<4 x float>*>:448 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 25, i32 1 ; <<4 x float>*>:449 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 25, i32 2 ; <<4 x float>*>:450 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 25, i32 3 ; <<4 x float>*>:451 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 24, i32 1 ; <<4 x float>*>:452 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 24, i32 2 ; <<4 x float>*>:453 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 24, i32 3 ; <<4 x float>*>:454 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 23, i32 1 ; <<4 x float>*>:455 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 23, i32 2 ; <<4 x float>*>:456 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 23, i32 3 ; <<4 x float>*>:457 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 22, i32 1 ; <<4 x float>*>:458 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 22, i32 2 ; <<4 x float>*>:459 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 22, i32 3 ; <<4 x float>*>:460 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 21, i32 1 ; <<4 x float>*>:461 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 21, i32 2 ; <<4 x float>*>:462 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 21, i32 3 ; <<4 x float>*>:463 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 20, i32 1 ; <<4 x float>*>:464 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 20, i32 2 ; <<4 x float>*>:465 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 20, i32 3 ; <<4 x float>*>:466 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 19, i32 1 ; <<4 x float>*>:467 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 19, i32 2 ; <<4 x float>*>:468 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 19, i32 3 ; <<4 x float>*>:469 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 18, i32 1 ; <<4 x float>*>:470 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 18, i32 2 ; <<4 x float>*>:471 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 18, i32 3 ; <<4 x float>*>:472 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 17, i32 1 ; <<4 x float>*>:473 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 17, i32 2 ; <<4 x float>*>:474 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 17, i32 3 ; <<4 x float>*>:475 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 16, i32 1 ; <<4 x float>*>:476 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 16, i32 2 ; <<4 x float>*>:477 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 16, i32 3 ; <<4 x float>*>:478 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 15, i32 1 ; <<4 x float>*>:479 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 15, i32 2 ; <<4 x float>*>:480 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 15, i32 3 ; <<4 x float>*>:481 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 14, i32 1 ; <<4 x float>*>:482 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 14, i32 2 ; <<4 x float>*>:483 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 14, i32 3 ; <<4 x float>*>:484 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:485 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:486 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:487 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1 ; <<4 x float>*>:488 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 2 ; <<4 x float>*>:489 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 3 ; <<4 x float>*>:490 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 180, i32 1 ; <<4 x float>*>:491 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 180, i32 2 ; <<4 x float>*>:492 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 180, i32 3 ; <<4 x float>*>:493 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 181, i32 1 ; <<4 x float>*>:494 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 181, i32 2 ; <<4 x float>*>:495 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 181, i32 3 ; <<4 x float>*>:496 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 182, i32 1 ; <<4 x float>*>:497 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 182, i32 2 ; <<4 x float>*>:498 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 182, i32 3 ; <<4 x float>*>:499 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 183, i32 1 ; <<4 x float>*>:500 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 183, i32 2 ; <<4 x float>*>:501 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 183, i32 3 ; <<4 x float>*>:502 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 184, i32 1 ; <<4 x float>*>:503 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 184, i32 2 ; <<4 x float>*>:504 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 184, i32 3 ; <<4 x float>*>:505 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 185, i32 1 ; <<4 x float>*>:506 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 185, i32 2 ; <<4 x float>*>:507 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 185, i32 3 ; <<4 x float>*>:508 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 190, i32 1 ; <<4 x float>*>:509 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 190, i32 2 ; <<4 x float>*>:510 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 190, i32 3 ; <<4 x float>*>:511 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 9, i32 1 ; <<4 x float>*>:512 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 9, i32 2 ; <<4 x float>*>:513 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 9, i32 3 ; <<4 x float>*>:514 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 10, i32 1 ; <<4 x float>*>:515 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 10, i32 2 ; <<4 x float>*>:516 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 10, i32 3 ; <<4 x float>*>:517 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 11, i32 1 ; <<4 x float>*>:518 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 11, i32 2 ; <<4 x float>*>:519 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 11, i32 3 ; <<4 x float>*>:520 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 1 ; <<4 x float>*>:521 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 2 ; <<4 x float>*>:522 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 12, i32 3 ; <<4 x float>*>:523 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 13, i32 1 ; <<4 x float>*>:524 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 13, i32 2 ; <<4 x float>*>:525 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 13, i32 3 ; <<4 x float>*>:526 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1 ; <<4 x float>*>:527 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2 ; <<4 x float>*>:528 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3 ; <<4 x float>*>:529 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1 ; <<4 x float>*>:530 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:531 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:532 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1 ; <<4 x float>*>:533 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2 ; <<4 x float>*>:534 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3 ; <<4 x float>*>:535 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 1 ; <<4 x float>*>:536 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 2 ; <<4 x float>*>:537 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 6, i32 3 ; <<4 x float>*>:538 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 1 ; <<4 x float>*>:539 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 2 ; <<4 x float>*>:540 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 7, i32 3 ; <<4 x float>*>:541 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1 ; <<4 x float>*>:542 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2 ; <<4 x float>*>:543 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3 ; <<4 x float>*>:544 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 1 ; <<4 x float>*>:545 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 2 ; <<4 x float>*>:546 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 187, i32 3 ; <<4 x float>*>:547 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 1 ; <<4 x float>*>:548 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 2 ; <<4 x float>*>:549 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 8, i32 3 ; <<4 x float>*>:550 [#uses=0] + load <4 x float>* null ; <<4 x float>>:551 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 1 ; <<4 x float>*>:552 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 2 ; <<4 x float>*>:553 [#uses=1] + load <4 x float>* %553 ; <<4 x float>>:554 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 3 ; <<4 x float>*>:555 [#uses=0] + shufflevector <4 x float> %554, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:556 [#uses=1] + call <4 x i32> @llvm.ppc.altivec.vcmpgtfp( <4 x float> zeroinitializer, <4 x float> %556 ) ; <<4 x i32>>:557 [#uses=0] + bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>>:558 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0 ; <<4 x float>*>:559 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 2 ; <<4 x float>*>:560 [#uses=1] + store <4 x float> zeroinitializer, <4 x float>* %560 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3 ; <<4 x float>*>:561 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:562 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 2 ; <<4 x float>*>:563 [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:564 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:565 [#uses=1] + store <4 x float> %565, <4 x float>* null + icmp eq i32 0, 0 ; <i1>:566 [#uses=1] + br i1 %566, label %.critedge, label %xPIF.exit + +.critedge: ; preds = %xOperationInitMasks.exit + getelementptr [4 x <4 x i32>]* null, i32 0, i32 3 ; <<4 x i32>*>:567 [#uses=0] + and <4 x i32> zeroinitializer, zeroinitializer ; <<4 x i32>>:568 [#uses=0] + or <4 x i32> zeroinitializer, zeroinitializer ; <<4 x i32>>:569 [#uses=0] + icmp eq i32 0, 0 ; <i1>:570 [#uses=1] + br i1 %570, label %.critedge7898, label %xPBRK.exit + +.critedge7898: ; preds = %.critedge + br label %xPIF.exit + +xPIF.exit: ; preds = %.critedge7898, %xOperationInitMasks.exit + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 1 ; <<4 x float>*>:571 [#uses=0] + load <4 x float>* null ; <<4 x float>>:572 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:573 [#uses=0] + icmp eq i32 0, 0 ; <i1>:574 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1 ; <<4 x float>*>:575 [#uses=0] + load <4 x float>* %0 ; <<4 x float>>:576 [#uses=0] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:577 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 0 ; <<4 x float>*>:578 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1 ; <<4 x float>*>:579 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2 ; <<4 x float>*>:580 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3 ; <<4 x float>*>:581 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:582 [#uses=0] + load <4 x float>* null ; <<4 x float>>:583 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:584 [#uses=1] + load <4 x float>* %584 ; <<4 x float>>:585 [#uses=1] + load <4 x float>* null ; <<4 x float>>:586 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:587 [#uses=1] + load <4 x float>* %587 ; <<4 x float>>:588 [#uses=1] + shufflevector <4 x float> %583, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:589 [#uses=1] + shufflevector <4 x float> %585, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:590 [#uses=1] + shufflevector <4 x float> %588, <4 x float> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x float>>:591 [#uses=1] + mul <4 x float> zeroinitializer, %589 ; <<4 x float>>:592 [#uses=0] + mul <4 x float> zeroinitializer, %590 ; <<4 x float>>:593 [#uses=0] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:594 [#uses=1] + mul <4 x float> zeroinitializer, %591 ; <<4 x float>>:595 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0 ; <<4 x float>*>:596 [#uses=2] + load <4 x float>* %596 ; <<4 x float>>:597 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* %596 + load <4 x float>* null ; <<4 x float>>:598 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:599 [#uses=0] + shufflevector <4 x float> %594, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:600 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:601 [#uses=2] + load <4 x float>* %601 ; <<4 x float>>:602 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* %601 + load <4 x float>* null ; <<4 x float>>:603 [#uses=0] + load <4 x float>* null ; <<4 x float>>:604 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:605 [#uses=1] + load <4 x float>* %605 ; <<4 x float>>:606 [#uses=1] + sub <4 x float> zeroinitializer, %604 ; <<4 x float>>:607 [#uses=2] + sub <4 x float> zeroinitializer, %606 ; <<4 x float>>:608 [#uses=2] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:609 [#uses=0] + br i1 false, label %617, label %610 + +; <label>:610 ; preds = %xPIF.exit + load <4 x float>* null ; <<4 x float>>:611 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:612 [#uses=2] + load <4 x float>* %612 ; <<4 x float>>:613 [#uses=1] + shufflevector <4 x float> %607, <4 x float> %613, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:614 [#uses=1] + store <4 x float> %614, <4 x float>* %612 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:615 [#uses=2] + load <4 x float>* %615 ; <<4 x float>>:616 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* %615 + br label %xST.exit400 + +; <label>:617 ; preds = %xPIF.exit + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:618 [#uses=0] + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:619 [#uses=1] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %619, <4 x i32> zeroinitializer ) ; <i32>:620 [#uses=1] + icmp eq i32 %620, 0 ; <i1>:621 [#uses=1] + br i1 %621, label %625, label %622 + +; <label>:622 ; preds = %617 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:623 [#uses=0] + shufflevector <4 x float> %607, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:624 [#uses=0] + br label %625 + +; <label>:625 ; preds = %622, %617 + load <4 x i32>* %.sub7896 ; <<4 x i32>>:626 [#uses=0] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:627 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:628 [#uses=1] + load <4 x float>* %628 ; <<4 x float>>:629 [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:630 [#uses=0] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:631 [#uses=1] + icmp eq i32 %631, 0 ; <i1>:632 [#uses=1] + br i1 %632, label %xST.exit400, label %633 + +; <label>:633 ; preds = %625 + load <4 x float>* null ; <<4 x float>>:634 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> %634, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:635 [#uses=1] + store <4 x float> %635, <4 x float>* null + br label %xST.exit400 + +xST.exit400: ; preds = %633, %625, %610 + %.17218 = phi <4 x float> [ zeroinitializer, %610 ], [ %608, %633 ], [ %608, %625 ] ; <<4 x float>> [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 0 ; <<4 x float>*>:636 [#uses=1] + load <4 x float>* %636 ; <<4 x float>>:637 [#uses=0] + load <4 x float>* null ; <<4 x float>>:638 [#uses=2] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:639 [#uses=0] + load <4 x float>* null ; <<4 x float>>:640 [#uses=2] + mul <4 x float> %638, %638 ; <<4 x float>>:641 [#uses=1] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:642 [#uses=0] + mul <4 x float> %640, %640 ; <<4 x float>>:643 [#uses=2] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x float>>:644 [#uses=0] + shufflevector <4 x float> %643, <4 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x float>>:645 [#uses=1] + add <4 x float> %645, %643 ; <<4 x float>>:646 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x float>>:647 [#uses=1] + shufflevector <4 x float> %641, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x float>>:648 [#uses=1] + add <4 x float> zeroinitializer, %647 ; <<4 x float>>:649 [#uses=2] + add <4 x float> zeroinitializer, %648 ; <<4 x float>>:650 [#uses=0] + add <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:651 [#uses=2] + call <4 x float> @llvm.ppc.altivec.vrsqrtefp( <4 x float> %649 ) ; <<4 x float>>:652 [#uses=1] + mul <4 x float> %652, %649 ; <<4 x float>>:653 [#uses=1] + call <4 x float> @llvm.ppc.altivec.vrsqrtefp( <4 x float> %651 ) ; <<4 x float>>:654 [#uses=1] + mul <4 x float> %654, %651 ; <<4 x float>>:655 [#uses=0] + icmp eq i32 0, 0 ; <i1>:656 [#uses=1] + br i1 %656, label %665, label %657 + +; <label>:657 ; preds = %xST.exit400 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0 ; <<4 x float>*>:658 [#uses=0] + shufflevector <4 x float> %653, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:659 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:660 [#uses=1] + load <4 x float>* %660 ; <<4 x float>>:661 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:662 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:663 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:664 [#uses=0] + br label %xST.exit402 + +; <label>:665 ; preds = %xST.exit400 + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:666 [#uses=0] + br i1 false, label %669, label %667 + +; <label>:667 ; preds = %665 + load <4 x float>* null ; <<4 x float>>:668 [#uses=0] + br label %669 + +; <label>:669 ; preds = %667, %665 + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:670 [#uses=0] + br label %xST.exit402 + +xST.exit402: ; preds = %669, %657 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0 ; <<4 x float>*>:671 [#uses=0] + load <4 x float>* null ; <<4 x float>>:672 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:673 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:674 [#uses=1] + load <4 x float>* %674 ; <<4 x float>>:675 [#uses=1] + load <4 x float>* null ; <<4 x float>>:676 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:677 [#uses=1] + shufflevector <4 x float> %675, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:678 [#uses=1] + mul <4 x float> zeroinitializer, %677 ; <<4 x float>>:679 [#uses=0] + mul <4 x float> zeroinitializer, %678 ; <<4 x float>>:680 [#uses=0] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:681 [#uses=1] + icmp eq i32 0, 0 ; <i1>:682 [#uses=1] + br i1 %682, label %689, label %683 + +; <label>:683 ; preds = %xST.exit402 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1 ; <<4 x float>*>:684 [#uses=1] + load <4 x float>* %684 ; <<4 x float>>:685 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2 ; <<4 x float>*>:686 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3 ; <<4 x float>*>:687 [#uses=0] + shufflevector <4 x float> %681, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:688 [#uses=0] + br label %xST.exit405 + +; <label>:689 ; preds = %xST.exit402 + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:690 [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:691 [#uses=1] + shufflevector <4 x i32> %691, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:692 [#uses=1] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %692, <4 x i32> zeroinitializer ) ; <i32>:693 [#uses=1] + icmp eq i32 %693, 0 ; <i1>:694 [#uses=0] + br label %xST.exit405 + +xST.exit405: ; preds = %689, %683 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:695 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:696 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:697 [#uses=0] + load <4 x float>* null ; <<4 x float>>:698 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2 ; <<4 x float>*>:699 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:700 [#uses=1] + add <4 x float> zeroinitializer, %700 ; <<4 x float>>:701 [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:702 [#uses=1] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %702, <4 x i32> zeroinitializer ) ; <i32>:703 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1 ; <<4 x float>*>:704 [#uses=2] + load <4 x float>* %704 ; <<4 x float>>:705 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* %704 + load <4 x float>* null ; <<4 x float>>:706 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* null + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:707 [#uses=2] + load <4 x float>* %707 ; <<4 x float>>:708 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* %707 + load <4 x float>* null ; <<4 x float>>:709 [#uses=0] + load <4 x float>* null ; <<4 x float>>:710 [#uses=0] + load <4 x float>* null ; <<4 x float>>:711 [#uses=1] + shufflevector <4 x float> %711, <4 x float> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x float>>:712 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:713 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:714 [#uses=1] + load <4 x float>* %714 ; <<4 x float>>:715 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:716 [#uses=0] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:717 [#uses=1] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:718 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 0 ; <<4 x float>*>:719 [#uses=1] + store <4 x float> zeroinitializer, <4 x float>* %719 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 1 ; <<4 x float>*>:720 [#uses=1] + shufflevector <4 x float> %717, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:721 [#uses=1] + store <4 x float> %721, <4 x float>* %720 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2 ; <<4 x float>*>:722 [#uses=1] + load <4 x float>* %722 ; <<4 x float>>:723 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> %723, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:724 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3 ; <<4 x float>*>:725 [#uses=1] + store <4 x float> zeroinitializer, <4 x float>* %725 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 2 ; <<4 x float>*>:726 [#uses=1] + load <4 x float>* %726 ; <<4 x float>>:727 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 5, i32 3 ; <<4 x float>*>:728 [#uses=1] + load <4 x float>* %728 ; <<4 x float>>:729 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0 ; <<4 x float>*>:730 [#uses=1] + load <4 x float>* %730 ; <<4 x float>>:731 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:732 [#uses=1] + load <4 x float>* %732 ; <<4 x float>>:733 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:734 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:735 [#uses=1] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:736 [#uses=1] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:737 [#uses=1] + mul <4 x float> zeroinitializer, %735 ; <<4 x float>>:738 [#uses=1] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:739 [#uses=1] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:740 [#uses=1] + icmp eq i32 %740, 0 ; <i1>:741 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 0 ; <<4 x float>*>:742 [#uses=2] + load <4 x float>* %742 ; <<4 x float>>:743 [#uses=1] + shufflevector <4 x float> %736, <4 x float> %743, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:744 [#uses=1] + store <4 x float> %744, <4 x float>* %742 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:745 [#uses=1] + load <4 x float>* %745 ; <<4 x float>>:746 [#uses=1] + shufflevector <4 x float> %737, <4 x float> %746, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:747 [#uses=0] + shufflevector <4 x float> %738, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:748 [#uses=1] + store <4 x float> %748, <4 x float>* null + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:749 [#uses=1] + load <4 x float>* %749 ; <<4 x float>>:750 [#uses=1] + shufflevector <4 x float> %739, <4 x float> %750, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:751 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0 ; <<4 x float>*>:752 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1 ; <<4 x float>*>:753 [#uses=1] + load <4 x float>* %753 ; <<4 x float>>:754 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:755 [#uses=0] + load <4 x float>* null ; <<4 x float>>:756 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:757 [#uses=1] + shufflevector <4 x float> %756, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:758 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:759 [#uses=1] + load <4 x float>* %759 ; <<4 x float>>:760 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:761 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:762 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:763 [#uses=1] + add <4 x float> %757, zeroinitializer ; <<4 x float>>:764 [#uses=0] + add <4 x float> %758, %763 ; <<4 x float>>:765 [#uses=0] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:766 [#uses=1] + br i1 false, label %773, label %767 + +; <label>:767 ; preds = %xST.exit405 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:768 [#uses=0] + load <4 x float>* null ; <<4 x float>>:769 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> %769, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:770 [#uses=1] + store <4 x float> %770, <4 x float>* null + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:771 [#uses=1] + load <4 x float>* %771 ; <<4 x float>>:772 [#uses=0] + br label %xST.exit422 + +; <label>:773 ; preds = %xST.exit405 + br label %xST.exit422 + +xST.exit422: ; preds = %773, %767 + %.07267 = phi <4 x float> [ %766, %767 ], [ undef, %773 ] ; <<4 x float>> [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:774 [#uses=0] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:775 [#uses=0] + icmp eq i32 0, 0 ; <i1>:776 [#uses=1] + br i1 %776, label %780, label %777 + +; <label>:777 ; preds = %xST.exit422 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:778 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:779 [#uses=0] + br label %xST.exit431 + +; <label>:780 ; preds = %xST.exit422 + load <4 x i32>* %.sub7896 ; <<4 x i32>>:781 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:782 [#uses=2] + load <4 x float>* %782 ; <<4 x float>>:783 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* %782 + load <4 x i32>* %.sub7896 ; <<4 x i32>>:784 [#uses=1] + shufflevector <4 x i32> %784, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:785 [#uses=0] + icmp eq i32 0, 0 ; <i1>:786 [#uses=0] + br label %xST.exit431 + +xST.exit431: ; preds = %780, %777 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:787 [#uses=0] + load <4 x float>* null ; <<4 x float>>:788 [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:789 [#uses=2] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %789, <4 x i32> zeroinitializer ) ; <i32>:790 [#uses=1] + icmp eq i32 %790, 0 ; <i1>:791 [#uses=0] + shufflevector <4 x i32> %789, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:792 [#uses=1] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %792, <4 x i32> zeroinitializer ) ; <i32>:793 [#uses=1] + icmp eq i32 %793, 0 ; <i1>:794 [#uses=1] + br i1 %794, label %797, label %795 + +; <label>:795 ; preds = %xST.exit431 + load <4 x float>* null ; <<4 x float>>:796 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* null + br label %797 + +; <label>:797 ; preds = %795, %xST.exit431 + %.07332 = phi <4 x float> [ zeroinitializer, %795 ], [ undef, %xST.exit431 ] ; <<4 x float>> [#uses=0] + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:798 [#uses=0] + br i1 false, label %xST.exit434, label %799 + +; <label>:799 ; preds = %797 + load <4 x float>* null ; <<4 x float>>:800 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* null + br label %xST.exit434 + +xST.exit434: ; preds = %799, %797 + load <4 x i32>* %.sub7896 ; <<4 x i32>>:801 [#uses=1] + shufflevector <4 x i32> %801, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x i32>>:802 [#uses=0] + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:803 [#uses=0] + icmp eq i32 0, 0 ; <i1>:804 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 0 ; <<4 x float>*>:805 [#uses=1] + load <4 x float>* %805 ; <<4 x float>>:806 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:807 [#uses=1] + load <4 x float>* %807 ; <<4 x float>>:808 [#uses=0] + load <4 x float>* null ; <<4 x float>>:809 [#uses=0] + load <4 x float>* null ; <<4 x float>>:810 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0 ; <<4 x float>*>:811 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:812 [#uses=1] + load <4 x float>* %812 ; <<4 x float>>:813 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:814 [#uses=1] + load <4 x float>* %814 ; <<4 x float>>:815 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:816 [#uses=0] + unreachable + +xPBRK.exit: ; preds = %.critedge + store <4 x i32> < i32 -1, i32 -1, i32 -1, i32 -1 >, <4 x i32>* %.sub7896 + store <4 x i32> zeroinitializer, <4 x i32>* null + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1 ; <<4 x float>*>:817 [#uses=1] + load <4 x float>* %817 ; <<4 x float>>:818 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2 ; <<4 x float>*>:819 [#uses=1] + load <4 x float>* %819 ; <<4 x float>>:820 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3 ; <<4 x float>*>:821 [#uses=1] + load <4 x float>* %821 ; <<4 x float>>:822 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:823 [#uses=1] + shufflevector <4 x float> %818, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:824 [#uses=1] + shufflevector <4 x float> %820, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:825 [#uses=1] + shufflevector <4 x float> %822, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:826 [#uses=1] + shufflevector <4 x float> %823, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:827 [#uses=0] + shufflevector <4 x float> %824, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:828 [#uses=1] + store <4 x float> %828, <4 x float>* null + load <4 x float>* null ; <<4 x float>>:829 [#uses=1] + shufflevector <4 x float> %825, <4 x float> %829, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:830 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3 ; <<4 x float>*>:831 [#uses=2] + load <4 x float>* %831 ; <<4 x float>>:832 [#uses=1] + shufflevector <4 x float> %826, <4 x float> %832, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:833 [#uses=1] + store <4 x float> %833, <4 x float>* %831 + br label %xLS.exit449 + +xLS.exit449: ; preds = %1215, %xPBRK.exit + %.27464 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.17463, %1215 ] ; <<4 x float>> [#uses=2] + %.27469 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.17468, %1215 ] ; <<4 x float>> [#uses=2] + %.27474 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=1] + %.17482 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0] + %.17486 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0] + %.17490 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07489, %1215 ] ; <<4 x float>> [#uses=2] + %.17494 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0] + %.27504 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0] + %.17513 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0] + %.17517 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0] + %.17552 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07551, %1215 ] ; <<4 x float>> [#uses=2] + %.17556 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07555, %1215 ] ; <<4 x float>> [#uses=2] + %.17560 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0] + %.17583 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07582, %1215 ] ; <<4 x float>> [#uses=2] + %.17591 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07590, %1215 ] ; <<4 x float>> [#uses=2] + %.17599 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0] + %.17618 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07617, %1215 ] ; <<4 x float>> [#uses=2] + %.17622 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07621, %1215 ] ; <<4 x float>> [#uses=2] + %.17626 = phi <4 x float> [ undef, %xPBRK.exit ], [ zeroinitializer, %1215 ] ; <<4 x float>> [#uses=0] + %.17653 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07652, %1215 ] ; <<4 x float>> [#uses=2] + %.17657 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07656, %1215 ] ; <<4 x float>> [#uses=2] + %.17661 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07660, %1215 ] ; <<4 x float>> [#uses=2] + %.17665 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07664, %1215 ] ; <<4 x float>> [#uses=2] + %.17723 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07722, %1215 ] ; <<4 x float>> [#uses=2] + %.17727 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07726, %1215 ] ; <<4 x float>> [#uses=2] + %.17731 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07730, %1215 ] ; <<4 x float>> [#uses=2] + %.17735 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07734, %1215 ] ; <<4 x float>> [#uses=2] + %.17770 = phi <4 x float> [ undef, %xPBRK.exit ], [ %.07769, %1215 ] ; <<4 x float>> [#uses=2] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 0 ; <<4 x float>*>:834 [#uses=0] + load <4 x float>* null ; <<4 x float>>:835 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2 ; <<4 x float>*>:836 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3 ; <<4 x float>*>:837 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:838 [#uses=0] + shufflevector <4 x float> %835, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:839 [#uses=1] + getelementptr <4 x float>* null, i32 878 ; <<4 x float>*>:840 [#uses=1] + load <4 x float>* %840 ; <<4 x float>>:841 [#uses=0] + call <4 x float> @llvm.ppc.altivec.vcfsx( <4 x i32> zeroinitializer, i32 0 ) ; <<4 x float>>:842 [#uses=1] + shufflevector <4 x float> %842, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:843 [#uses=2] + call <4 x i32> @llvm.ppc.altivec.vcmpgtfp( <4 x float> %843, <4 x float> %839 ) ; <<4 x i32>>:844 [#uses=1] + bitcast <4 x i32> %844 to <4 x float> ; <<4 x float>>:845 [#uses=1] + call <4 x i32> @llvm.ppc.altivec.vcmpgtfp( <4 x float> %843, <4 x float> zeroinitializer ) ; <<4 x i32>>:846 [#uses=0] + bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>>:847 [#uses=1] + icmp eq i32 0, 0 ; <i1>:848 [#uses=1] + br i1 %848, label %854, label %849 + +; <label>:849 ; preds = %xLS.exit449 + shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:850 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:851 [#uses=1] + store <4 x float> zeroinitializer, <4 x float>* %851 + shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:852 [#uses=1] + store <4 x float> %852, <4 x float>* null + shufflevector <4 x float> %847, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:853 [#uses=0] + br label %xST.exit451 + +; <label>:854 ; preds = %xLS.exit449 + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:855 [#uses=0] + br i1 false, label %859, label %856 + +; <label>:856 ; preds = %854 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0 ; <<4 x float>*>:857 [#uses=2] + load <4 x float>* %857 ; <<4 x float>>:858 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* %857 + br label %859 + +; <label>:859 ; preds = %856, %854 + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:860 [#uses=0] + br i1 false, label %864, label %861 + +; <label>:861 ; preds = %859 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:862 [#uses=1] + shufflevector <4 x float> %845, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:863 [#uses=1] + store <4 x float> %863, <4 x float>* %862 + br label %864 + +; <label>:864 ; preds = %861, %859 + load <4 x i32>* %.sub7896 ; <<4 x i32>>:865 [#uses=1] + shufflevector <4 x i32> %865, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x i32>>:866 [#uses=0] + br i1 false, label %868, label %867 + +; <label>:867 ; preds = %864 + store <4 x float> zeroinitializer, <4 x float>* null + br label %868 + +; <label>:868 ; preds = %867, %864 + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:869 [#uses=0] + br label %xST.exit451 + +xST.exit451: ; preds = %868, %849 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0 ; <<4 x float>*>:870 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:871 [#uses=0] + load <4 x float>* null ; <<4 x float>>:872 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:873 [#uses=1] + bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:874 [#uses=1] + xor <4 x i32> %874, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>>:875 [#uses=0] + bitcast <4 x float> %873 to <4 x i32> ; <<4 x i32>>:876 [#uses=1] + xor <4 x i32> %876, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>>:877 [#uses=0] + bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:878 [#uses=1] + xor <4 x i32> %878, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>>:879 [#uses=1] + bitcast <4 x i32> %879 to <4 x float> ; <<4 x float>>:880 [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:881 [#uses=1] + icmp eq i32 0, 0 ; <i1>:882 [#uses=1] + br i1 %882, label %888, label %883 + +; <label>:883 ; preds = %xST.exit451 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 0 ; <<4 x float>*>:884 [#uses=1] + store <4 x float> zeroinitializer, <4 x float>* %884 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:885 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:886 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3 ; <<4 x float>*>:887 [#uses=0] + br label %xST.exit453 + +; <label>:888 ; preds = %xST.exit451 + shufflevector <4 x i32> %881, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:889 [#uses=0] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:890 [#uses=0] + br i1 false, label %894, label %891 + +; <label>:891 ; preds = %888 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:892 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:893 [#uses=1] + store <4 x float> %893, <4 x float>* %892 + br label %894 + +; <label>:894 ; preds = %891, %888 + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:895 [#uses=1] + icmp eq i32 %895, 0 ; <i1>:896 [#uses=1] + br i1 %896, label %898, label %897 + +; <label>:897 ; preds = %894 + br label %898 + +; <label>:898 ; preds = %897, %894 + load <4 x i32>* %.sub7896 ; <<4 x i32>>:899 [#uses=0] + br i1 false, label %xST.exit453, label %900 + +; <label>:900 ; preds = %898 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3 ; <<4 x float>*>:901 [#uses=1] + load <4 x float>* %901 ; <<4 x float>>:902 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> %902, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:903 [#uses=0] + br label %xST.exit453 + +xST.exit453: ; preds = %900, %898, %883 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 1 ; <<4 x float>*>:904 [#uses=0] + load <4 x float>* null ; <<4 x float>>:905 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 189, i32 3 ; <<4 x float>*>:906 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:907 [#uses=1] + shufflevector <4 x float> %905, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:908 [#uses=1] + bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:909 [#uses=0] + bitcast <4 x float> %908 to <4 x i32> ; <<4 x i32>>:910 [#uses=0] + bitcast <4 x float> %907 to <4 x i32> ; <<4 x i32>>:911 [#uses=0] + bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:912 [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:913 [#uses=0] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 2, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:914 [#uses=0] + br i1 false, label %915, label %xPIF.exit455 + +; <label>:915 ; preds = %xST.exit453 + load <4 x i32>* %.sub7896 ; <<4 x i32>>:916 [#uses=0] + getelementptr [4 x <4 x i32>]* null, i32 0, i32 3 ; <<4 x i32>*>:917 [#uses=1] + store <4 x i32> zeroinitializer, <4 x i32>* %917 + load <4 x i32>* %.sub7896 ; <<4 x i32>>:918 [#uses=1] + and <4 x i32> %918, zeroinitializer ; <<4 x i32>>:919 [#uses=0] + br label %.critedge7899 + +.critedge7899: ; preds = %.critedge7899, %915 + or <4 x i32> zeroinitializer, zeroinitializer ; <<4 x i32>>:920 [#uses=1] + br i1 false, label %.critedge7899, label %xPBRK.exit456 + +xPBRK.exit456: ; preds = %.critedge7899 + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 2, <4 x i32> %920, <4 x i32> zeroinitializer ) ; <i32>:921 [#uses=0] + unreachable + +xPIF.exit455: ; preds = %xST.exit453 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 0 ; <<4 x float>*>:922 [#uses=1] + load <4 x float>* %922 ; <<4 x float>>:923 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 1 ; <<4 x float>*>:924 [#uses=1] + load <4 x float>* %924 ; <<4 x float>>:925 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 2 ; <<4 x float>*>:926 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 186, i32 3 ; <<4 x float>*>:927 [#uses=0] + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:928 [#uses=0] + bitcast { { i16, i16, i32 } }* %1 to <4 x float>* ; <<4 x float>*>:929 [#uses=0] + bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:930 [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:931 [#uses=0] + icmp eq i32 0, 0 ; <i1>:932 [#uses=1] + br i1 %932, label %934, label %933 + +; <label>:933 ; preds = %xPIF.exit455 + store <4 x float> zeroinitializer, <4 x float>* null + br label %934 + +; <label>:934 ; preds = %933, %xPIF.exit455 + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:935 [#uses=0] + icmp eq i32 0, 0 ; <i1>:936 [#uses=1] + br i1 %936, label %xST.exit459, label %937 + +; <label>:937 ; preds = %934 + br label %xST.exit459 + +xST.exit459: ; preds = %937, %934 + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x i32>>:938 [#uses=1] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %938, <4 x i32> zeroinitializer ) ; <i32>:939 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 188, i32 2 ; <<4 x float>*>:940 [#uses=1] + store <4 x float> zeroinitializer, <4 x float>* %940 + load <4 x float>* null ; <<4 x float>>:941 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> %941, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:942 [#uses=1] + store <4 x float> %942, <4 x float>* null + shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:943 [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:944 [#uses=0] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:945 [#uses=0] + br i1 false, label %947, label %946 + +; <label>:946 ; preds = %xST.exit459 + br label %947 + +; <label>:947 ; preds = %946, %xST.exit459 + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:948 [#uses=0] + icmp eq i32 0, 0 ; <i1>:949 [#uses=1] + br i1 %949, label %952, label %950 + +; <label>:950 ; preds = %947 + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:951 [#uses=1] + call void @llvm.ppc.altivec.stvewx( <4 x i32> %951, i8* null ) + br label %952 + +; <label>:952 ; preds = %950, %947 + br i1 false, label %955, label %953 + +; <label>:953 ; preds = %952 + getelementptr [4 x <4 x i32>]* null, i32 0, i32 2 ; <<4 x i32>*>:954 [#uses=0] + br label %955 + +; <label>:955 ; preds = %953, %952 + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:956 [#uses=0] + icmp eq i32 0, 0 ; <i1>:957 [#uses=1] + br i1 %957, label %xStoreDestAddressWithMask.exit461, label %958 + +; <label>:958 ; preds = %955 + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:959 [#uses=1] + call void @llvm.ppc.altivec.stvewx( <4 x i32> %959, i8* null ) + br label %xStoreDestAddressWithMask.exit461 + +xStoreDestAddressWithMask.exit461: ; preds = %958, %955 + load <4 x float>* %0 ; <<4 x float>>:960 [#uses=0] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:961 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 0 ; <<4 x float>*>:962 [#uses=0] + br i1 false, label %968, label %xST.exit463 + +xST.exit463: ; preds = %xStoreDestAddressWithMask.exit461 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 1 ; <<4 x float>*>:963 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 2 ; <<4 x float>*>:964 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 3, i32 3 ; <<4 x float>*>:965 [#uses=0] + load <4 x float>* %0 ; <<4 x float>>:966 [#uses=3] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:967 [#uses=0] + br i1 false, label %972, label %969 + +; <label>:968 ; preds = %xStoreDestAddressWithMask.exit461 + unreachable + +; <label>:969 ; preds = %xST.exit463 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 1 ; <<4 x float>*>:970 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 2 ; <<4 x float>*>:971 [#uses=1] + store <4 x float> %966, <4 x float>* %971 + store <4 x float> %966, <4 x float>* null + br label %xST.exit465 + +; <label>:972 ; preds = %xST.exit463 + call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <<4 x i32>>:973 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* null + store <4 x float> zeroinitializer, <4 x float>* null + load <4 x float>* null ; <<4 x float>>:974 [#uses=0] + bitcast <4 x float> %966 to <4 x i32> ; <<4 x i32>>:975 [#uses=1] + call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> zeroinitializer, <4 x i32> %975, <4 x i32> zeroinitializer ) ; <<4 x i32>>:976 [#uses=1] + bitcast <4 x i32> %976 to <4 x float> ; <<4 x float>>:977 [#uses=1] + store <4 x float> %977, <4 x float>* null + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 2, i32 3 ; <<4 x float>*>:978 [#uses=0] + bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:979 [#uses=1] + call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> %979, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <<4 x i32>>:980 [#uses=1] + bitcast <4 x i32> %980 to <4 x float> ; <<4 x float>>:981 [#uses=0] + br label %xST.exit465 + +xST.exit465: ; preds = %972, %969 + load <4 x float>* %0 ; <<4 x float>>:982 [#uses=3] + icmp eq i32 0, 0 ; <i1>:983 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 0 ; <<4 x float>*>:984 [#uses=1] + br i1 %983, label %989, label %985 + +; <label>:985 ; preds = %xST.exit465 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1 ; <<4 x float>*>:986 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:987 [#uses=1] + store <4 x float> %982, <4 x float>* %987 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:988 [#uses=0] + br label %xST.exit467 + +; <label>:989 ; preds = %xST.exit465 + bitcast <4 x float> %982 to <4 x i32> ; <<4 x i32>>:990 [#uses=0] + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:991 [#uses=0] + store <4 x float> zeroinitializer, <4 x float>* %984 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 1 ; <<4 x float>*>:992 [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:993 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 2 ; <<4 x float>*>:994 [#uses=0] + bitcast <4 x i32> zeroinitializer to <4 x float> ; <<4 x float>>:995 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 1, i32 3 ; <<4 x float>*>:996 [#uses=0] + bitcast <4 x float> zeroinitializer to <4 x i32> ; <<4 x i32>>:997 [#uses=1] + bitcast <4 x float> %982 to <4 x i32> ; <<4 x i32>>:998 [#uses=1] + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:999 [#uses=1] + call <4 x i32> @llvm.ppc.altivec.vsel( <4 x i32> %997, <4 x i32> %998, <4 x i32> %999 ) ; <<4 x i32>>:1000 [#uses=1] + bitcast <4 x i32> %1000 to <4 x float> ; <<4 x float>>:1001 [#uses=0] + br label %xST.exit467 + +xST.exit467: ; preds = %989, %985 + load <4 x float>* %0 ; <<4 x float>>:1002 [#uses=5] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:1003 [#uses=2] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1003, <4 x i32> zeroinitializer ) ; <i32>:1004 [#uses=0] + br i1 false, label %1011, label %1005 + +; <label>:1005 ; preds = %xST.exit467 + load <4 x float>* null ; <<4 x float>>:1006 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:1007 [#uses=1] + load <4 x float>* %1007 ; <<4 x float>>:1008 [#uses=0] + load <4 x float>* null ; <<4 x float>>:1009 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:1010 [#uses=0] + br label %xST.exit469 + +; <label>:1011 ; preds = %xST.exit467 + shufflevector <4 x i32> %1003, <4 x i32> undef, <4 x i32> zeroinitializer ; <<4 x i32>>:1012 [#uses=0] + icmp eq i32 0, 0 ; <i1>:1013 [#uses=1] + br i1 %1013, label %1015, label %1014 + +; <label>:1014 ; preds = %1011 + br label %1015 + +; <label>:1015 ; preds = %1014, %1011 + %.07472 = phi <4 x float> [ %1002, %1014 ], [ %.27474, %1011 ] ; <<4 x float>> [#uses=0] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:1016 [#uses=1] + icmp eq i32 %1016, 0 ; <i1>:1017 [#uses=1] + br i1 %1017, label %1021, label %1018 + +; <label>:1018 ; preds = %1015 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 1 ; <<4 x float>*>:1019 [#uses=0] + shufflevector <4 x float> %1002, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:1020 [#uses=0] + br label %1021 + +; <label>:1021 ; preds = %1018, %1015 + %.07467 = phi <4 x float> [ %1002, %1018 ], [ %.27469, %1015 ] ; <<4 x float>> [#uses=2] + icmp eq i32 0, 0 ; <i1>:1022 [#uses=1] + br i1 %1022, label %1025, label %1023 + +; <label>:1023 ; preds = %1021 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:1024 [#uses=1] + store <4 x float> zeroinitializer, <4 x float>* %1024 + br label %1025 + +; <label>:1025 ; preds = %1023, %1021 + %.07462 = phi <4 x float> [ %1002, %1023 ], [ %.27464, %1021 ] ; <<4 x float>> [#uses=2] + icmp eq i32 0, 0 ; <i1>:1026 [#uses=1] + br i1 %1026, label %xST.exit469, label %1027 + +; <label>:1027 ; preds = %1025 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:1028 [#uses=0] + br label %xST.exit469 + +xST.exit469: ; preds = %1027, %1025, %1005 + %.17463 = phi <4 x float> [ %.27464, %1005 ], [ %.07462, %1027 ], [ %.07462, %1025 ] ; <<4 x float>> [#uses=1] + %.17468 = phi <4 x float> [ %.27469, %1005 ], [ %.07467, %1027 ], [ %.07467, %1025 ] ; <<4 x float>> [#uses=1] + %.07489 = phi <4 x float> [ %1002, %1005 ], [ %.17490, %1027 ], [ %.17490, %1025 ] ; <<4 x float>> [#uses=1] + load <4 x float>* null ; <<4 x float>>:1029 [#uses=0] + load <4 x float>* null ; <<4 x float>>:1030 [#uses=0] + sub <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1031 [#uses=1] + br i1 false, label %1037, label %1032 + +; <label>:1032 ; preds = %xST.exit469 + load <4 x float>* null ; <<4 x float>>:1033 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 2 ; <<4 x float>*>:1034 [#uses=1] + load <4 x float>* %1034 ; <<4 x float>>:1035 [#uses=0] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 3 ; <<4 x float>*>:1036 [#uses=0] + br label %xST.exit472 + +; <label>:1037 ; preds = %xST.exit469 + icmp eq i32 0, 0 ; <i1>:1038 [#uses=1] + br i1 %1038, label %1040, label %1039 + +; <label>:1039 ; preds = %1037 + br label %1040 + +; <label>:1040 ; preds = %1039, %1037 + %.07507 = phi <4 x float> [ zeroinitializer, %1039 ], [ zeroinitializer, %1037 ] ; <<4 x float>> [#uses=0] + icmp eq i32 0, 0 ; <i1>:1041 [#uses=1] + br i1 %1041, label %1045, label %1042 + +; <label>:1042 ; preds = %1040 + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 4, i32 1 ; <<4 x float>*>:1043 [#uses=1] + load <4 x float>* %1043 ; <<4 x float>>:1044 [#uses=0] + br label %1045 + +; <label>:1045 ; preds = %1042, %1040 + br i1 false, label %1048, label %1046 + +; <label>:1046 ; preds = %1045 + shufflevector <4 x float> %1031, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:1047 [#uses=0] + br label %1048 + +; <label>:1048 ; preds = %1046, %1045 + icmp eq i32 0, 0 ; <i1>:1049 [#uses=1] + br i1 %1049, label %xST.exit472, label %1050 + +; <label>:1050 ; preds = %1048 + br label %xST.exit472 + +xST.exit472: ; preds = %1050, %1048, %1032 + br i1 false, label %1052, label %1051 + +; <label>:1051 ; preds = %xST.exit472 + br label %xST.exit474 + +; <label>:1052 ; preds = %xST.exit472 + br i1 false, label %1054, label %1053 + +; <label>:1053 ; preds = %1052 + br label %1054 + +; <label>:1054 ; preds = %1053, %1052 + br i1 false, label %1056, label %1055 + +; <label>:1055 ; preds = %1054 + br label %1056 + +; <label>:1056 ; preds = %1055, %1054 + br i1 false, label %1058, label %1057 + +; <label>:1057 ; preds = %1056 + br label %1058 + +; <label>:1058 ; preds = %1057, %1056 + br i1 false, label %xST.exit474, label %1059 + +; <label>:1059 ; preds = %1058 + br label %xST.exit474 + +xST.exit474: ; preds = %1059, %1058, %1051 + load <4 x float>* null ; <<4 x float>>:1060 [#uses=1] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1061 [#uses=1] + mul <4 x float> %1060, zeroinitializer ; <<4 x float>>:1062 [#uses=2] + br i1 false, label %1065, label %1063 + +; <label>:1063 ; preds = %xST.exit474 + shufflevector <4 x float> %1062, <4 x float> zeroinitializer, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:1064 [#uses=1] + store <4 x float> %1064, <4 x float>* null + br label %xST.exit476 + +; <label>:1065 ; preds = %xST.exit474 + br i1 false, label %1067, label %1066 + +; <label>:1066 ; preds = %1065 + br label %1067 + +; <label>:1067 ; preds = %1066, %1065 + shufflevector <4 x i32> zeroinitializer, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:1068 [#uses=0] + br i1 false, label %1070, label %1069 + +; <label>:1069 ; preds = %1067 + br label %1070 + +; <label>:1070 ; preds = %1069, %1067 + br i1 false, label %1072, label %1071 + +; <label>:1071 ; preds = %1070 + br label %1072 + +; <label>:1072 ; preds = %1071, %1070 + br i1 false, label %xST.exit476, label %1073 + +; <label>:1073 ; preds = %1072 + br label %xST.exit476 + +xST.exit476: ; preds = %1073, %1072, %1063 + %.07551 = phi <4 x float> [ %1062, %1063 ], [ %.17552, %1073 ], [ %.17552, %1072 ] ; <<4 x float>> [#uses=1] + %.07555 = phi <4 x float> [ %1061, %1063 ], [ %.17556, %1073 ], [ %.17556, %1072 ] ; <<4 x float>> [#uses=1] + br i1 false, label %1075, label %1074 + +; <label>:1074 ; preds = %xST.exit476 + br label %xST.exit479 + +; <label>:1075 ; preds = %xST.exit476 + br i1 false, label %1077, label %1076 + +; <label>:1076 ; preds = %1075 + br label %1077 + +; <label>:1077 ; preds = %1076, %1075 + br i1 false, label %1079, label %1078 + +; <label>:1078 ; preds = %1077 + br label %1079 + +; <label>:1079 ; preds = %1078, %1077 + br i1 false, label %1081, label %1080 + +; <label>:1080 ; preds = %1079 + br label %1081 + +; <label>:1081 ; preds = %1080, %1079 + br i1 false, label %xST.exit479, label %1082 + +; <label>:1082 ; preds = %1081 + br label %xST.exit479 + +xST.exit479: ; preds = %1082, %1081, %1074 + br i1 false, label %1084, label %1083 + +; <label>:1083 ; preds = %xST.exit479 + br label %xST.exit482 + +; <label>:1084 ; preds = %xST.exit479 + br i1 false, label %1086, label %1085 + +; <label>:1085 ; preds = %1084 + br label %1086 + +; <label>:1086 ; preds = %1085, %1084 + br i1 false, label %1088, label %1087 + +; <label>:1087 ; preds = %1086 + br label %1088 + +; <label>:1088 ; preds = %1087, %1086 + br i1 false, label %1090, label %1089 + +; <label>:1089 ; preds = %1088 + br label %1090 + +; <label>:1090 ; preds = %1089, %1088 + br i1 false, label %xST.exit482, label %1091 + +; <label>:1091 ; preds = %1090 + br label %xST.exit482 + +xST.exit482: ; preds = %1091, %1090, %1083 + br i1 false, label %1093, label %1092 + +; <label>:1092 ; preds = %xST.exit482 + br label %xST.exit486 + +; <label>:1093 ; preds = %xST.exit482 + br i1 false, label %1095, label %1094 + +; <label>:1094 ; preds = %1093 + br label %1095 + +; <label>:1095 ; preds = %1094, %1093 + br i1 false, label %1097, label %1096 + +; <label>:1096 ; preds = %1095 + br label %1097 + +; <label>:1097 ; preds = %1096, %1095 + br i1 false, label %1099, label %1098 + +; <label>:1098 ; preds = %1097 + br label %1099 + +; <label>:1099 ; preds = %1098, %1097 + br i1 false, label %xST.exit486, label %1100 + +; <label>:1100 ; preds = %1099 + br label %xST.exit486 + +xST.exit486: ; preds = %1100, %1099, %1092 + br i1 false, label %1102, label %1101 + +; <label>:1101 ; preds = %xST.exit486 + br label %xST.exit489 + +; <label>:1102 ; preds = %xST.exit486 + br i1 false, label %1104, label %1103 + +; <label>:1103 ; preds = %1102 + br label %1104 + +; <label>:1104 ; preds = %1103, %1102 + br i1 false, label %1106, label %1105 + +; <label>:1105 ; preds = %1104 + br label %1106 + +; <label>:1106 ; preds = %1105, %1104 + br i1 false, label %1108, label %1107 + +; <label>:1107 ; preds = %1106 + br label %1108 + +; <label>:1108 ; preds = %1107, %1106 + br i1 false, label %xST.exit489, label %1109 + +; <label>:1109 ; preds = %1108 + br label %xST.exit489 + +xST.exit489: ; preds = %1109, %1108, %1101 + br i1 false, label %1111, label %1110 + +; <label>:1110 ; preds = %xST.exit489 + br label %xST.exit492 + +; <label>:1111 ; preds = %xST.exit489 + br i1 false, label %1113, label %1112 + +; <label>:1112 ; preds = %1111 + br label %1113 + +; <label>:1113 ; preds = %1112, %1111 + br i1 false, label %1115, label %1114 + +; <label>:1114 ; preds = %1113 + br label %1115 + +; <label>:1115 ; preds = %1114, %1113 + br i1 false, label %1117, label %1116 + +; <label>:1116 ; preds = %1115 + br label %1117 + +; <label>:1117 ; preds = %1116, %1115 + br i1 false, label %xST.exit492, label %1118 + +; <label>:1118 ; preds = %1117 + br label %xST.exit492 + +xST.exit492: ; preds = %1118, %1117, %1110 + load <4 x float>* null ; <<4 x float>>:1119 [#uses=1] + mul <4 x float> %1119, zeroinitializer ; <<4 x float>>:1120 [#uses=1] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1121 [#uses=1] + br i1 false, label %1123, label %1122 + +; <label>:1122 ; preds = %xST.exit492 + br label %xST.exit495 + +; <label>:1123 ; preds = %xST.exit492 + br i1 false, label %1125, label %1124 + +; <label>:1124 ; preds = %1123 + br label %1125 + +; <label>:1125 ; preds = %1124, %1123 + br i1 false, label %1127, label %1126 + +; <label>:1126 ; preds = %1125 + br label %1127 + +; <label>:1127 ; preds = %1126, %1125 + br i1 false, label %1129, label %1128 + +; <label>:1128 ; preds = %1127 + br label %1129 + +; <label>:1129 ; preds = %1128, %1127 + br i1 false, label %xST.exit495, label %1130 + +; <label>:1130 ; preds = %1129 + br label %xST.exit495 + +xST.exit495: ; preds = %1130, %1129, %1122 + %.07582 = phi <4 x float> [ %1121, %1122 ], [ %.17583, %1130 ], [ %.17583, %1129 ] ; <<4 x float>> [#uses=1] + %.07590 = phi <4 x float> [ %1120, %1122 ], [ %.17591, %1130 ], [ %.17591, %1129 ] ; <<4 x float>> [#uses=1] + load <4 x float>* null ; <<4 x float>>:1131 [#uses=1] + add <4 x float> %1131, zeroinitializer ; <<4 x float>>:1132 [#uses=1] + add <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1133 [#uses=1] + br i1 false, label %1135, label %1134 + +; <label>:1134 ; preds = %xST.exit495 + br label %xST.exit498 + +; <label>:1135 ; preds = %xST.exit495 + br i1 false, label %1137, label %1136 + +; <label>:1136 ; preds = %1135 + br label %1137 + +; <label>:1137 ; preds = %1136, %1135 + br i1 false, label %1139, label %1138 + +; <label>:1138 ; preds = %1137 + br label %1139 + +; <label>:1139 ; preds = %1138, %1137 + br i1 false, label %1141, label %1140 + +; <label>:1140 ; preds = %1139 + br label %1141 + +; <label>:1141 ; preds = %1140, %1139 + br i1 false, label %xST.exit498, label %1142 + +; <label>:1142 ; preds = %1141 + br label %xST.exit498 + +xST.exit498: ; preds = %1142, %1141, %1134 + %.07617 = phi <4 x float> [ %1133, %1134 ], [ %.17618, %1142 ], [ %.17618, %1141 ] ; <<4 x float>> [#uses=1] + %.07621 = phi <4 x float> [ %1132, %1134 ], [ %.17622, %1142 ], [ %.17622, %1141 ] ; <<4 x float>> [#uses=1] + load <4 x float>* null ; <<4 x float>>:1143 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:1144 [#uses=1] + load <4 x float>* %1144 ; <<4 x float>>:1145 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:1146 [#uses=1] + load <4 x float>* %1146 ; <<4 x float>>:1147 [#uses=1] + shufflevector <4 x float> %1143, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:1148 [#uses=1] + shufflevector <4 x float> %1145, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:1149 [#uses=1] + shufflevector <4 x float> %1147, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>>:1150 [#uses=1] + mul <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1151 [#uses=1] + mul <4 x float> zeroinitializer, %1148 ; <<4 x float>>:1152 [#uses=1] + mul <4 x float> zeroinitializer, %1149 ; <<4 x float>>:1153 [#uses=1] + mul <4 x float> zeroinitializer, %1150 ; <<4 x float>>:1154 [#uses=1] + br i1 false, label %1156, label %1155 + +; <label>:1155 ; preds = %xST.exit498 + br label %xST.exit501 + +; <label>:1156 ; preds = %xST.exit498 + br i1 false, label %1158, label %1157 + +; <label>:1157 ; preds = %1156 + br label %1158 + +; <label>:1158 ; preds = %1157, %1156 + br i1 false, label %1160, label %1159 + +; <label>:1159 ; preds = %1158 + br label %1160 + +; <label>:1160 ; preds = %1159, %1158 + br i1 false, label %1162, label %1161 + +; <label>:1161 ; preds = %1160 + br label %1162 + +; <label>:1162 ; preds = %1161, %1160 + br i1 false, label %xST.exit501, label %1163 + +; <label>:1163 ; preds = %1162 + br label %xST.exit501 + +xST.exit501: ; preds = %1163, %1162, %1155 + %.07652 = phi <4 x float> [ %1154, %1155 ], [ %.17653, %1163 ], [ %.17653, %1162 ] ; <<4 x float>> [#uses=1] + %.07656 = phi <4 x float> [ %1153, %1155 ], [ %.17657, %1163 ], [ %.17657, %1162 ] ; <<4 x float>> [#uses=1] + %.07660 = phi <4 x float> [ %1152, %1155 ], [ %.17661, %1163 ], [ %.17661, %1162 ] ; <<4 x float>> [#uses=1] + %.07664 = phi <4 x float> [ %1151, %1155 ], [ %.17665, %1163 ], [ %.17665, %1162 ] ; <<4 x float>> [#uses=1] + load <4 x float>* null ; <<4 x float>>:1164 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 2 ; <<4 x float>*>:1165 [#uses=1] + load <4 x float>* %1165 ; <<4 x float>>:1166 [#uses=1] + getelementptr [193 x [4 x <4 x float>]]* null, i32 0, i32 0, i32 3 ; <<4 x float>*>:1167 [#uses=1] + load <4 x float>* %1167 ; <<4 x float>>:1168 [#uses=1] + add <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1169 [#uses=1] + add <4 x float> zeroinitializer, %1164 ; <<4 x float>>:1170 [#uses=1] + add <4 x float> zeroinitializer, %1166 ; <<4 x float>>:1171 [#uses=1] + add <4 x float> zeroinitializer, %1168 ; <<4 x float>>:1172 [#uses=1] + br i1 false, label %1174, label %1173 + +; <label>:1173 ; preds = %xST.exit501 + br label %xST.exit504 + +; <label>:1174 ; preds = %xST.exit501 + br i1 false, label %1176, label %1175 + +; <label>:1175 ; preds = %1174 + br label %1176 + +; <label>:1176 ; preds = %1175, %1174 + br i1 false, label %1178, label %1177 + +; <label>:1177 ; preds = %1176 + br label %1178 + +; <label>:1178 ; preds = %1177, %1176 + br i1 false, label %1180, label %1179 + +; <label>:1179 ; preds = %1178 + br label %1180 + +; <label>:1180 ; preds = %1179, %1178 + br i1 false, label %xST.exit504, label %1181 + +; <label>:1181 ; preds = %1180 + br label %xST.exit504 + +xST.exit504: ; preds = %1181, %1180, %1173 + %.07722 = phi <4 x float> [ %1172, %1173 ], [ %.17723, %1181 ], [ %.17723, %1180 ] ; <<4 x float>> [#uses=1] + %.07726 = phi <4 x float> [ %1171, %1173 ], [ %.17727, %1181 ], [ %.17727, %1180 ] ; <<4 x float>> [#uses=1] + %.07730 = phi <4 x float> [ %1170, %1173 ], [ %.17731, %1181 ], [ %.17731, %1180 ] ; <<4 x float>> [#uses=1] + %.07734 = phi <4 x float> [ %1169, %1173 ], [ %.17735, %1181 ], [ %.17735, %1180 ] ; <<4 x float>> [#uses=1] + add <4 x float> zeroinitializer, zeroinitializer ; <<4 x float>>:1182 [#uses=1] + br i1 false, label %1184, label %1183 + +; <label>:1183 ; preds = %xST.exit504 + br label %xST.exit507 + +; <label>:1184 ; preds = %xST.exit504 + br i1 false, label %1186, label %1185 + +; <label>:1185 ; preds = %1184 + br label %1186 + +; <label>:1186 ; preds = %1185, %1184 + br i1 false, label %1188, label %1187 + +; <label>:1187 ; preds = %1186 + store <4 x float> zeroinitializer, <4 x float>* null + br label %1188 + +; <label>:1188 ; preds = %1187, %1186 + load <4 x i32>* %.sub7896 ; <<4 x i32>>:1189 [#uses=1] + shufflevector <4 x i32> %1189, <4 x i32> undef, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x i32>>:1190 [#uses=1] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1190, <4 x i32> zeroinitializer ) ; <i32>:1191 [#uses=1] + icmp eq i32 %1191, 0 ; <i1>:1192 [#uses=1] + br i1 %1192, label %1196, label %1193 + +; <label>:1193 ; preds = %1188 + load <4 x float>* null ; <<4 x float>>:1194 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> %1194, <4 x i32> < i32 0, i32 1, i32 2, i32 7 > ; <<4 x float>>:1195 [#uses=1] + store <4 x float> %1195, <4 x float>* null + br label %1196 + +; <label>:1196 ; preds = %1193, %1188 + %.07742 = phi <4 x float> [ zeroinitializer, %1193 ], [ zeroinitializer, %1188 ] ; <<4 x float>> [#uses=0] + load <4 x i32>* %.sub7896 ; <<4 x i32>>:1197 [#uses=1] + shufflevector <4 x i32> %1197, <4 x i32> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ; <<4 x i32>>:1198 [#uses=1] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1198, <4 x i32> zeroinitializer ) ; <i32>:1199 [#uses=1] + icmp eq i32 %1199, 0 ; <i1>:1200 [#uses=1] + br i1 %1200, label %xST.exit507, label %1201 + +; <label>:1201 ; preds = %1196 + store <4 x float> zeroinitializer, <4 x float>* null + br label %xST.exit507 + +xST.exit507: ; preds = %1201, %1196, %1183 + %.07769 = phi <4 x float> [ %1182, %1183 ], [ %.17770, %1201 ], [ %.17770, %1196 ] ; <<4 x float>> [#uses=1] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32>:1202 [#uses=1] + icmp eq i32 %1202, 0 ; <i1>:1203 [#uses=1] + br i1 %1203, label %1207, label %1204 + +; <label>:1204 ; preds = %xST.exit507 + load <4 x float>* null ; <<4 x float>>:1205 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> %1205, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:1206 [#uses=1] + store <4 x float> %1206, <4 x float>* null + br label %1207 + +; <label>:1207 ; preds = %1204, %xST.exit507 + load <4 x i32>* %.sub7896 ; <<4 x i32>>:1208 [#uses=1] + shufflevector <4 x i32> %1208, <4 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ; <<4 x i32>>:1209 [#uses=1] + call i32 @llvm.ppc.altivec.vcmpequw.p( i32 0, <4 x i32> %1209, <4 x i32> zeroinitializer ) ; <i32>:1210 [#uses=1] + icmp eq i32 %1210, 0 ; <i1>:1211 [#uses=1] + br i1 %1211, label %1215, label %1212 + +; <label>:1212 ; preds = %1207 + load <4 x float>* null ; <<4 x float>>:1213 [#uses=1] + shufflevector <4 x float> zeroinitializer, <4 x float> %1213, <4 x i32> < i32 0, i32 5, i32 6, i32 7 > ; <<4 x float>>:1214 [#uses=1] + store <4 x float> %1214, <4 x float>* null + br label %1215 + +; <label>:1215 ; preds = %1212, %1207 + store <4 x float> zeroinitializer, <4 x float>* null + br label %xLS.exit449 +} + +declare <4 x i32> @llvm.ppc.altivec.vsel(<4 x i32>, <4 x i32>, <4 x i32>) + +declare void @llvm.ppc.altivec.stvewx(<4 x i32>, i8*) + +declare <4 x float> @llvm.ppc.altivec.vrsqrtefp(<4 x float>) + +declare <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32>, i32) + +declare i32 @llvm.ppc.altivec.vcmpequw.p(i32, <4 x i32>, <4 x i32>) + +declare <4 x i32> @llvm.ppc.altivec.vcmpgtfp(<4 x float>, <4 x float>) diff --git a/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll b/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll new file mode 100644 index 000000000000..656b83192e00 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {foo r3, r4} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep {bari r3, 47} + +; PR1351 + +define i32 @test1(i32 %Y, i32 %X) nounwind { + %tmp1 = tail call i32 asm "foo${1:I} $0, $1", "=r,rI"( i32 %X ) + ret i32 %tmp1 +} + +define i32 @test2(i32 %Y, i32 %X) nounwind { + %tmp1 = tail call i32 asm "bar${1:I} $0, $1", "=r,rI"( i32 47 ) + ret i32 %tmp1 +} diff --git a/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll new file mode 100644 index 000000000000..ba0f8fe1b77d --- /dev/null +++ b/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll @@ -0,0 +1,30 @@ +; RUN: llvm-as < %s | llc | grep {subfc r3,r5,r4} +; RUN: llvm-as < %s | llc | grep {subfze r4,r2} +; RUN: llvm-as < %s | llc -regalloc=local | grep {subfc r5,r2,r4} +; RUN: llvm-as < %s | llc -regalloc=local | grep {subfze r2,r3} +; The first argument of subfc must not be the same as any other register. + +; PR1357 + +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "powerpc-apple-darwin8.8.0" + +;long long test(int A, int B, int C) { +; unsigned X, Y; +; __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" +; : "=r" (X), "=&r" (Y) +; : "r" (A), "rI" (B), "r" (C)); +; return ((long long)Y << 32) | X; +;} + +define i64 @test(i32 %A, i32 %B, i32 %C) nounwind { +entry: + %Y = alloca i32, align 4 ; <i32*> [#uses=2] + %tmp4 = call i32 asm "subf${3:I}c $1,$4,$3\0A\09subfze $0,$2", "=r,=*&r,r,rI,r"( i32* %Y, i32 %A, i32 %B, i32 %C ) ; <i32> [#uses=1] + %tmp5 = load i32* %Y ; <i32> [#uses=1] + %tmp56 = zext i32 %tmp5 to i64 ; <i64> [#uses=1] + %tmp7 = shl i64 %tmp56, 32 ; <i64> [#uses=1] + %tmp89 = zext i32 %tmp4 to i64 ; <i64> [#uses=1] + %tmp10 = or i64 %tmp7, %tmp89 ; <i64> [#uses=1] + ret i64 %tmp10 +} diff --git a/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll b/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll new file mode 100644 index 000000000000..989a7516aa4d --- /dev/null +++ b/test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc +; PR1382 + +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "powerpc-apple-darwin8.8.0" +@x = global [2 x i32] [ i32 1, i32 2 ] ; <[2 x i32]*> [#uses=1] + +define void @foo() { +entry: + tail call void asm sideeffect "$0 $1", "s,i"( i8* bitcast (i32* getelementptr ([2 x i32]* @x, i32 0, i32 1) to i8*), i8* bitcast (i32* getelementptr ([2 x i32]* @x, i32 0, i32 1) to i8*) ) + ret void +} diff --git a/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll b/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll new file mode 100644 index 000000000000..b64de683f837 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-05-14-InlineAsmSelectCrash.ll @@ -0,0 +1,25 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "powerpc-apple-darwin8.8.0" + %struct..0anon = type { i32 } + %struct.A = type { %struct.anon } + %struct.anon = type <{ }> + +define void @bork(%struct.A* %In0P) { +entry: + %tmp56 = bitcast %struct.A* %In0P to float* ; <float*> [#uses=1] + br label %bb + +bb: ; preds = %bb, %entry + %i.035.0 = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] + %tmp8 = getelementptr float* %tmp56, i32 %i.035.0 ; <float*> [#uses=2] + %tmp101112 = bitcast float* %tmp8 to i8* ; <i8*> [#uses=1] + %tmp1617 = bitcast float* %tmp8 to i32* ; <i32*> [#uses=1] + %tmp21 = tail call i32 asm "lwbrx $0, $2, $1", "=r,r,bO,*m"( i8* %tmp101112, i32 0, i32* %tmp1617 ) ; <i32> [#uses=0] + %indvar.next = add i32 %i.035.0, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %indvar.next, 4 ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb + ret void +} diff --git a/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll new file mode 100644 index 000000000000..5a86418f7cb7 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-05-22-tailmerge-3.ll @@ -0,0 +1,68 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*baz | count 2 +; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*quux | count 2 +; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge | grep bl.*baz | count 1 +; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge=1 | grep bl.*quux | count 1 +; Check that tail merging is not the default on ppc, and that -enable-tail-merge works. + +; ModuleID = 'tail.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "i686-apple-darwin8" + +define i32 @f(i32 %i, i32 %q) { +entry: + %i_addr = alloca i32 ; <i32*> [#uses=2] + %q_addr = alloca i32 ; <i32*> [#uses=2] + %retval = alloca i32, align 4 ; <i32*> [#uses=1] + "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i32 %i, i32* %i_addr + store i32 %q, i32* %q_addr + %tmp = load i32* %i_addr ; <i32> [#uses=1] + %tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1] + %tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1] + %toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1] + br i1 %toBool, label %cond_true, label %cond_false + +cond_true: ; preds = %entry + %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] + %tmp7 = load i32* %q_addr ; <i32> [#uses=1] + %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1] + %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1] + %toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1] + br i1 %toBool10, label %cond_true11, label %cond_false15 + +cond_false: ; preds = %entry + %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0] + %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] + %tmp27 = load i32* %q_addr ; <i32> [#uses=1] + %tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1] + %tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1] + %toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1] + br i1 %toBool210, label %cond_true11, label %cond_false15 + +cond_true11: ; preds = %cond_next + %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0] + %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] + br label %cond_next18 + +cond_false15: ; preds = %cond_next + %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0] + %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] + br label %cond_next18 + +cond_next18: ; preds = %cond_false15, %cond_true11 + %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0] + br label %return + +return: ; preds = %cond_next18 + %retval20 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval20 +} + +declare i32 @bar(...) + +declare i32 @baz(...) + +declare i32 @foo(...) + +declare i32 @quux(...) diff --git a/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll new file mode 100644 index 000000000000..ae853f67e200 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll @@ -0,0 +1,14 @@ +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "powerpc-apple-darwin8.8.0" + +; RUN: llvm-as < %s | llc -march=ppc32 | grep {rlwinm r3, r3, 23, 30, 30} +; PR1473 + +define i8 @foo(i16 zeroext %a) zeroext { + %tmp2 = lshr i16 %a, 10 ; <i16> [#uses=1] + %tmp23 = trunc i16 %tmp2 to i8 ; <i8> [#uses=1] + %tmp4 = shl i8 %tmp23, 1 ; <i8> [#uses=1] + %tmp5 = and i8 %tmp4, 2 ; <i8> [#uses=1] + ret i8 %tmp5 +} + diff --git a/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll b/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll new file mode 100644 index 000000000000..58260ec6b739 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-06-28-BCCISelBug.ll @@ -0,0 +1,85 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+altivec + + %struct.XATest = type { float, i16, i8, i8 } + %struct.XArrayRange = type { i8, i8, i8, i8 } + %struct.XBlendMode = type { i16, i16, i16, i16, %struct.GIC4, i16, i16, i8, i8, i8, i8 } + %struct.XClearC = type { double, %struct.GIC4, %struct.GIC4, float, i32 } + %struct.XClipPlane = type { i32, [6 x %struct.GIC4] } + %struct.XCBuffer = type { i16, i16, [8 x i16] } + %struct.XCMatrix = type { [16 x float]*, %struct.XICSS } + %struct.XConvolution = type { %struct.GIC4, %struct.XICSS, i16, i16, float*, i32, i32 } + %struct.XDepthTest = type { i16, i16, i8, i8, i8, i8, double, double } + %struct.XFixedFunctionProgram = type { %struct.PPSToken* } + %struct.XFogMode = type { %struct.GIC4, float, float, float, float, float, i16, i16, i16, i8, i8 } + %struct.XFramebufferAttachment = type { i32, i32, i32, i32 } + %struct.XHintMode = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 } + %struct.XHistogram = type { %struct.XFramebufferAttachment*, i32, i16, i8, i8 } + %struct.XICSS = type { %struct.GTCoord2, %struct.GTCoord2, %struct.GTCoord2, %struct.GTCoord2 } + %struct.XISubset = type { %struct.XConvolution, %struct.XConvolution, %struct.XConvolution, %struct.XCMatrix, %struct.XMinmax, %struct.XHistogram, %struct.XICSS, %struct.XICSS, %struct.XICSS, %struct.XICSS, i32 } + %struct.XLight = type { %struct.GIC4, %struct.GIC4, %struct.GIC4, %struct.GIC4, %struct.XPointLineLimits, float, float, float, float, float, %struct.XPointLineLimits, float, float, float, float, float } + %struct.XLightModel = type { %struct.GIC4, [8 x %struct.XLight], [2 x %struct.XMaterial], i32, i16, i16, i16, i8, i8, i8, i8, i8, i8 } + %struct.XLightProduct = type { %struct.GIC4, %struct.GIC4, %struct.GIC4 } + %struct.XLineMode = type { float, i32, i16, i16, i8, i8, i8, i8 } + %struct.XLogicOp = type { i16, i8, i8 } + %struct.XMaskMode = type { i32, [3 x i32], i8, i8, i8, i8, i8, i8, i8, i8 } + %struct.XMaterial = type { %struct.GIC4, %struct.GIC4, %struct.GIC4, %struct.GIC4, float, float, float, float, [8 x %struct.XLightProduct], %struct.GIC4, [6 x i32], [2 x i32] } + %struct.XMinmax = type { %struct.XMinmaxTable*, i16, i8, i8 } + %struct.XMinmaxTable = type { %struct.GIC4, %struct.GIC4 } + %struct.XMipmaplevel = type { [4 x i32], [4 x i32], [4 x float], [4 x i32], i32, i32, float*, i8*, i16, i16, i16, i16, [2 x float] } + %struct.XMultisample = type { float, i8, i8, i8, i8, i8, i8, i8, i8 } + %struct.XPipelineProgramState = type { i8, i8, i8, i8, %struct.GIC4* } + %struct.XPMap = type { i32*, float*, float*, float*, float*, float*, float*, float*, float*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } + %struct.XPMode = type { float, float, %struct.XPStore, %struct.XPTransfer, %struct.XPMap, %struct.XISubset, i32, i32 } + %struct.XPPack = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8 } + %struct.XPStore = type { %struct.XPPack, %struct.XPPack } + %struct.XPTransfer = type { float, float, float, float, float, float, float, float, float, float, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float } + %struct.XPointLineLimits = type { float, float, float } + %struct.XPointMode = type { float, float, float, float, %struct.XPointLineLimits, float, i8, i8, i8, i8, i16, i16, i32, i16, i16 } + %struct.XPGMode = type { [128 x i8], float, float, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8 } + %struct.XRegisterCCs = type { i8, i8, i8, i8, i32, [2 x %struct.GIC4], [8 x %struct.XRegisterCCsPerStageState], %struct.XRegisterCCsFinalStageState } + %struct.XRegisterCCsFinalStageState = type { i8, i8, i8, i8, [7 x %struct.XRegisterCCsPerVariableState] } + %struct.XRegisterCCsPerPortionState = type { [4 x %struct.XRegisterCCsPerVariableState], i8, i8, i8, i8, i16, i16, i16, i16, i16, i16 } + %struct.XRegisterCCsPerStageState = type { [2 x %struct.XRegisterCCsPerPortionState], [2 x %struct.GIC4] } + %struct.XRegisterCCsPerVariableState = type { i16, i16, i16, i16 } + %struct.XScissorTest = type { %struct.XFramebufferAttachment, i8, i8, i8, i8 } + %struct.XState = type { i16, i16, i16, i16, i32, i32, [256 x %struct.GIC4], [128 x %struct.GIC4], %struct.XViewport, %struct.XXF, %struct.XLightModel, %struct.XATest, %struct.XBlendMode, %struct.XClearC, %struct.XCBuffer, %struct.XDepthTest, %struct.XArrayRange, %struct.XFogMode, %struct.XHintMode, %struct.XLineMode, %struct.XLogicOp, %struct.XMaskMode, %struct.XPMode, %struct.XPointMode, %struct.XPGMode, %struct.XScissorTest, i32, %struct.XStencilTest, [16 x %struct.XTMode], %struct.XArrayRange, [8 x %struct.XTCoordGen], %struct.XClipPlane, %struct.XMultisample, %struct.XRegisterCCs, %struct.XArrayRange, %struct.XArrayRange, [3 x %struct.XPipelineProgramState], %struct.XXFFeedback, i32*, %struct.XFixedFunctionProgram, [3 x i32] } + %struct.XStencilTest = type { [3 x { i32, i32, i16, i16, i16, i16 }], i32, [4 x i8] } + %struct.XTCoordGen = type { { i16, i16, %struct.GIC4, %struct.GIC4 }, { i16, i16, %struct.GIC4, %struct.GIC4 }, { i16, i16, %struct.GIC4, %struct.GIC4 }, { i16, i16, %struct.GIC4, %struct.GIC4 }, i8, i8, i8, i8 } + %struct.XTGeomState = type { i16, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, [6 x i16], [6 x i16] } + %struct.XTLevel = type { i32, i32, i16, i16, i16, i8, i8, i16, i16, i16, i16, i8* } + %struct.XTMode = type { %struct.GIC4, i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, float, float, float, i16, i16, i16, i16, i16, i16, [4 x i16], i8, i8, i8, i8, [3 x float], [4 x float], float, float } + %struct.XTParamState = type { i16, i16, i16, i16, i16, i16, %struct.GIC4, float, float, float, float, i16, i16, i16, i16, float, i16, i8, i8, i32, i8* } + %struct.XTRec = type { %struct.XTState*, float, float, float, float, %struct.XMipmaplevel*, %struct.XMipmaplevel*, i32, i32, i32, i32, i32, i32, i32, [2 x %struct.PPSToken] } + %struct.XTState = type { i16, i8, i8, i16, i16, float, i32, %struct.GISWRSurface*, %struct.XTParamState, %struct.XTGeomState, %struct.XTLevel, [6 x [15 x %struct.XTLevel]] } + %struct.XXF = type { [24 x [16 x float]], [24 x [16 x float]], [16 x float], float, float, float, float, float, i8, i8, i8, i8, i32, i32, i32, i16, i16, i8, i8, i8, i8, i32 } + %struct.XXFFeedback = type { i8, i8, i8, i8, [16 x i32], [16 x i32] } + %struct.XViewport = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, double, double, i32, i32, i32, i32, float, float, float, float } + %struct.GIC4 = type { float, float, float, float } + %struct.GISWRSurface = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i8*, [4 x i8*], i32 } + %struct.GTCoord2 = type { float, float } + %struct.GVMFPContext = type { float, i32, i32, i32, float, [3 x float] } + %struct.GVMFPStack = type { [8 x i8*], i8*, i8*, i32, i32, { <4 x float> }, { <4 x float> }, <4 x i32> } + %struct.GVMFGAttrib = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, [8 x <4 x float>] } + %struct.GVMTs = type { [16 x %struct.XTRec*] } + %struct.PPSToken = type { { i16, i16, i32 } } + %struct._GVMConstants = type { <4 x i32>, <4 x i32>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, float, float, float, float, float, float, float, float, float, float, float, float, [256 x float], [528 x i8] } + +declare <4 x i32> @llvm.ppc.altivec.lvewx(i8*) + +declare i32 @llvm.ppc.altivec.vcmpequw.p(i32, <4 x i32>, <4 x i32>) + +define void @test(%struct.XState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._GVMConstants* %cnstn, %struct.PPSToken* %pstrm, %struct.GVMFPContext* %vmctx, %struct.GVMTs* %txtrs, %struct.GVMFPStack* %fpstk, %struct.GVMFGAttrib* %start, %struct.GVMFGAttrib* %deriv, i32 %fragx, i32 %fragy) { +bb58.i: + %tmp3405.i = getelementptr %struct.XTRec* null, i32 0, i32 1 ; <float*> [#uses=1] + %tmp34053406.i = bitcast float* %tmp3405.i to i8* ; <i8*> [#uses=1] + %tmp3407.i = call <4 x i32> @llvm.ppc.altivec.lvewx( i8* %tmp34053406.i ) ; <<4 x i32>> [#uses=0] + %tmp4146.i = call i32 @llvm.ppc.altivec.vcmpequw.p( i32 3, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <i32> [#uses=1] + %tmp4147.i = icmp eq i32 %tmp4146.i, 0 ; <i1> [#uses=1] + br i1 %tmp4147.i, label %bb8799.i, label %bb4150.i + +bb4150.i: ; preds = %bb58.i + br label %bb8799.i + +bb8799.i: ; preds = %bb4150.i, %bb58.i + ret void +} diff --git a/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll b/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll new file mode 100644 index 000000000000..34df7bb7d057 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-08-04-CoalescerAssert.ll @@ -0,0 +1,28 @@ +; RUN: llvm-as < %s | llc -march=ppc64 +; PR1596 + + %struct._obstack_chunk = type { i8* } + %struct.obstack = type { i8*, %struct._obstack_chunk* (i8*, i64)*, i8*, i8 } + +define i32 @_obstack_newchunk(%struct.obstack* %h, i32 %length) { +entry: + br i1 false, label %cond_false, label %cond_true + +cond_true: ; preds = %entry + br i1 false, label %cond_true28, label %cond_next30 + +cond_false: ; preds = %entry + %tmp22 = tail call %struct._obstack_chunk* null( i64 undef ) ; <%struct._obstack_chunk*> [#uses=2] + br i1 false, label %cond_true28, label %cond_next30 + +cond_true28: ; preds = %cond_false, %cond_true + %iftmp.0.043.0 = phi %struct._obstack_chunk* [ null, %cond_true ], [ %tmp22, %cond_false ] ; <%struct._obstack_chunk*> [#uses=1] + tail call void null( ) + br label %cond_next30 + +cond_next30: ; preds = %cond_true28, %cond_false, %cond_true + %iftmp.0.043.1 = phi %struct._obstack_chunk* [ %iftmp.0.043.0, %cond_true28 ], [ null, %cond_true ], [ %tmp22, %cond_false ] ; <%struct._obstack_chunk*> [#uses=1] + %tmp41 = getelementptr %struct._obstack_chunk* %iftmp.0.043.1, i32 0, i32 0 ; <i8**> [#uses=1] + store i8* null, i8** %tmp41, align 8 + ret i32 undef +} diff --git a/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll b/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll new file mode 100644 index 000000000000..9c8fa97be967 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-09-04-AltivecDST.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=ppc64 | grep dst | count 4 + +define hidden void @_Z4borkPc(i8* %image) { +entry: + tail call void @llvm.ppc.altivec.dst( i8* %image, i32 8, i32 0 ) + tail call void @llvm.ppc.altivec.dstt( i8* %image, i32 8, i32 0 ) + tail call void @llvm.ppc.altivec.dstst( i8* %image, i32 8, i32 0 ) + tail call void @llvm.ppc.altivec.dststt( i8* %image, i32 8, i32 0 ) + ret void +} + +declare void @llvm.ppc.altivec.dst(i8*, i32, i32) +declare void @llvm.ppc.altivec.dstt(i8*, i32, i32) +declare void @llvm.ppc.altivec.dstst(i8*, i32, i32) +declare void @llvm.ppc.altivec.dststt(i8*, i32, i32) diff --git a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll new file mode 100644 index 000000000000..c5e7a4d38a00 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc -march=ppc64 | grep lwzx + + %struct.__db_region = type { %struct.__mutex_t, [4 x i8], %struct.anon, i32, [1 x i32] } + %struct.__mutex_t = type { i32 } + %struct.anon = type { i64, i64 } + +define void @foo() { +entry: + %ttype = alloca i32, align 4 ; <i32*> [#uses=1] + %regs = alloca [1024 x %struct.__db_region], align 16 ; <[1024 x %struct.__db_region]*> [#uses=0] + %tmp = load i32* %ttype, align 4 ; <i32> [#uses=1] + %tmp1 = call i32 (...)* @bork( i32 %tmp ) ; <i32> [#uses=0] + ret void +} + +declare i32 @bork(...) diff --git a/test/CodeGen/PowerPC/2007-09-08-unaligned.ll b/test/CodeGen/PowerPC/2007-09-08-unaligned.ll new file mode 100644 index 000000000000..f6bd3337aef7 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-09-08-unaligned.ll @@ -0,0 +1,53 @@ +; RUN: llvm-as < %s | llc | grep stfd | count 3 +; RUN: llvm-as < %s | llc | grep stfs | count 1 +; RUN: llvm-as < %s | llc | grep lfd | count 2 +; RUN: llvm-as < %s | llc | grep lfs | count 2 +; ModuleID = 'foo.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin8" + %struct.anon = type <{ i8, float }> +@s = global %struct.anon <{ i8 3, float 0x4014666660000000 }> ; <%struct.anon*> [#uses=1] +@u = global <{ i8, double }> <{ i8 3, double 5.100000e+00 }> ; <<{ i8, double }>*> [#uses=1] +@t = weak global %struct.anon zeroinitializer ; <%struct.anon*> [#uses=2] +@v = weak global <{ i8, double }> zeroinitializer ; <<{ i8, double }>*> [#uses=2] +@.str = internal constant [8 x i8] c"%f %lf\0A\00" ; <[8 x i8]*> [#uses=1] + +define i32 @foo() { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + %tmp = getelementptr %struct.anon* @s, i32 0, i32 1 ; <float*> [#uses=1] + %tmp1 = load float* %tmp, align 1 ; <float> [#uses=1] + %tmp2 = getelementptr %struct.anon* @t, i32 0, i32 1 ; <float*> [#uses=1] + store float %tmp1, float* %tmp2, align 1 + %tmp3 = getelementptr <{ i8, double }>* @u, i32 0, i32 1 ; <double*> [#uses=1] + %tmp4 = load double* %tmp3, align 1 ; <double> [#uses=1] + %tmp5 = getelementptr <{ i8, double }>* @v, i32 0, i32 1 ; <double*> [#uses=1] + store double %tmp4, double* %tmp5, align 1 + br label %return + +return: ; preds = %entry + %retval6 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval6 +} + +define i32 @main() { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + %tmp = call i32 @foo( ) ; <i32> [#uses=0] + %tmp1 = getelementptr %struct.anon* @t, i32 0, i32 1 ; <float*> [#uses=1] + %tmp2 = load float* %tmp1, align 1 ; <float> [#uses=1] + %tmp23 = fpext float %tmp2 to double ; <double> [#uses=1] + %tmp4 = getelementptr <{ i8, double }>* @v, i32 0, i32 1 ; <double*> [#uses=1] + %tmp5 = load double* %tmp4, align 1 ; <double> [#uses=1] + %tmp6 = getelementptr [8 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1] + %tmp7 = call i32 (i8*, ...)* @printf( i8* %tmp6, double %tmp23, double %tmp5 ) ; <i32> [#uses=0] + br label %return + +return: ; preds = %entry + %retval8 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval8 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll b/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll new file mode 100644 index 000000000000..bb7aba45a963 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=ppc64 + + %struct.TCMalloc_SpinLock = type { i32 } + +define void @_ZN17TCMalloc_SpinLock4LockEv(%struct.TCMalloc_SpinLock* %this) { +entry: + %tmp3 = call i32 asm sideeffect "1: lwarx $0, 0, $1\0A\09stwcx. $2, 0, $1\0A\09bne- 1b\0A\09isync", "=&r,=*r,r,1,~{dirflag},~{fpsr},~{flags},~{memory}"( i32** null, i32 1, i32* null ) ; <i32> [#uses=0] + unreachable +} diff --git a/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll b/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll new file mode 100644 index 000000000000..f4b87cf4517b --- /dev/null +++ b/test/CodeGen/PowerPC/2007-09-12-LiveIntervalsAssert.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin + +declare void @cxa_atexit_check_1(i8*) + +define i32 @check_cxa_atexit(i32 (void (i8*)*, i8*, i8*)* %cxa_atexit, void (i8*)* %cxa_finalize) { +entry: + %tmp7 = call i32 null( void (i8*)* @cxa_atexit_check_1, i8* null, i8* null ) ; <i32> [#uses=0] + br i1 false, label %cond_true, label %cond_next + +cond_true: ; preds = %entry + ret i32 0 + +cond_next: ; preds = %entry + ret i32 0 +} diff --git a/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll b/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll new file mode 100644 index 000000000000..e71a8fb0f160 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-10-16-InlineAsmFrameOffset.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; rdar://5538377 + + %struct.disk_unsigned = type { i32 } + %struct._StorePageMax = type { %struct.disk_unsigned, %struct.disk_unsigned, [65536 x i8] } + +define i32 @test() { +entry: + %data = alloca i32 ; <i32*> [#uses=1] + %compressedPage = alloca %struct._StorePageMax ; <%struct._StorePageMax*> [#uses=0] + %tmp107 = call i32 asm "lwbrx $0, $2, $1", "=r,r,bO,*m"( i8* null, i32 0, i32* %data ) ; <i32> [#uses=0] + unreachable +} + diff --git a/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll b/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll new file mode 100644 index 000000000000..bd11b5d5b7b2 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-10-18-PtrArithmetic.ll @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=ppc64 -mattr=+altivec + %struct.inoutprops = type <{ i8, [3 x i8] }> + +define void @bork(float* %argA, float* %argB, float* %res, i8 %inoutspec.0) { +entry: + %.mask = and i8 %inoutspec.0, -16 ; <i8> [#uses=1] + %tmp6 = icmp eq i8 %.mask, 16 ; <i1> [#uses=1] + br i1 %tmp6, label %cond_true, label %UnifiedReturnBlock + +cond_true: ; preds = %entry + %tmp89 = bitcast float* %res to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %tmp1011 = bitcast float* %argA to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %tmp14 = load <4 x i32>* %tmp1011, align 16 ; <<4 x i32>> [#uses=1] + %tmp1516 = bitcast float* %argB to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %tmp18 = load <4 x i32>* %tmp1516, align 16 ; <<4 x i32>> [#uses=1] + %tmp19 = sdiv <4 x i32> %tmp14, %tmp18 ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp19, <4 x i32>* %tmp89, align 16 + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll new file mode 100644 index 000000000000..bca6e5a8fbdb --- /dev/null +++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll @@ -0,0 +1,27 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic + + %struct.NSError = type opaque + %struct.NSManagedObjectContext = type opaque + %struct.NSPersistentStoreCoordinator = type opaque + %struct.NSString = type opaque + %struct.NSURL = type opaque + %struct._message_ref_t = type { %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_selector* } + %struct.objc_object = type { } + %struct.objc_selector = type opaque +@"\01L_OBJC_MESSAGE_REF_2" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=1] +@"\01L_OBJC_MESSAGE_REF_6" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=1] +@NSXMLStoreType = external constant %struct.NSString* ; <%struct.NSString**> [#uses=1] +@"\01L_OBJC_MESSAGE_REF_5" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=2] +@"\01L_OBJC_MESSAGE_REF_4" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=1] + +define %struct.NSManagedObjectContext* @"+[ListGenerator(Private) managedObjectContextWithModelURL:storeURL:]"(%struct.objc_object* %self, %struct._message_ref_t* %_cmd, %struct.NSURL* %modelURL, %struct.NSURL* %storeURL) { +entry: + %storeCoordinator = alloca %struct.NSPersistentStoreCoordinator* ; <%struct.NSPersistentStoreCoordinator**> [#uses=0] + %tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" ) ; <%struct.objc_object*> [#uses=0] + %tmp34 = load %struct.NSString** @NSXMLStoreType, align 8 ; <%struct.NSString*> [#uses=1] + %tmp37 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1] + %tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 ) ; <%struct.objc_object*> [#uses=1] + %tmp45 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp37( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_5", %struct.objc_object* %tmp42, %struct.NSString* null ) ; <%struct.objc_object*> [#uses=1] + %tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* null( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* %tmp45, %struct.NSError** null ) ; <%struct.objc_object*> [#uses=0] + unreachable +} diff --git a/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll new file mode 100644 index 000000000000..80ef6f19f727 --- /dev/null +++ b/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll @@ -0,0 +1,25 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic + + %struct.NSError = type opaque + %struct.NSManagedObjectContext = type opaque + %struct.NSString = type opaque + %struct.NSURL = type opaque + %struct._message_ref_t = type { %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*, %struct.objc_selector* } + %struct.objc_object = type { } + %struct.objc_selector = type opaque +@"\01L_OBJC_MESSAGE_REF_2" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=2] +@"\01L_OBJC_MESSAGE_REF_6" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=2] +@NSXMLStoreType = external constant %struct.NSString* ; <%struct.NSString**> [#uses=1] +@"\01L_OBJC_MESSAGE_REF_4" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=2] + +define %struct.NSManagedObjectContext* @"+[ListGenerator(Private) managedObjectContextWithModelURL:storeURL:]"(%struct.objc_object* %self, %struct._message_ref_t* %_cmd, %struct.NSURL* %modelURL, %struct.NSURL* %storeURL) { +entry: + %tmp27 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1] + %tmp29 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp27( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_2" ) ; <%struct.objc_object*> [#uses=0] + %tmp33 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1] + %tmp34 = load %struct.NSString** @NSXMLStoreType, align 8 ; <%struct.NSString*> [#uses=1] + %tmp40 = load %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)** getelementptr (%struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 0, i32 0), align 8 ; <%struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)*> [#uses=1] + %tmp42 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp40( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_4", i32 1 ) ; <%struct.objc_object*> [#uses=0] + %tmp48 = call %struct.objc_object* (%struct.objc_object*, %struct._message_ref_t*, ...)* %tmp33( %struct.objc_object* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_6", %struct.NSString* %tmp34, i8* null, %struct.NSURL* null, %struct.objc_object* null, %struct.NSError** null ) ; <%struct.objc_object*> [#uses=0] + unreachable +} diff --git a/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll b/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll new file mode 100644 index 000000000000..e49d59acfe5f --- /dev/null +++ b/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll @@ -0,0 +1,148 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin + + %struct.HDescriptor = type <{ i32, i32 }> + +declare void @bcopy(i8*, i8*, i32) + +define i32 @main(i32 %argc, i8** %argv) { +entry: + br i1 false, label %bb31, label %bb + +bb: ; preds = %entry + ret i32 -6 + +bb31: ; preds = %entry + switch i32 0, label %bb189 [ + i32 73, label %cond_next209 + i32 74, label %bb74 + i32 77, label %bb57 + i32 78, label %cond_next209 + i32 85, label %cond_next209 + i32 97, label %cond_next209 + i32 100, label %cond_next209 + i32 107, label %cond_next209 + i32 109, label %bb57 + i32 112, label %bb43 + i32 115, label %cond_next209 + i32 117, label %bb51 + ] + +bb43: ; preds = %bb31 + br i1 false, label %cond_true48, label %cond_true200.critedge2117 + +cond_true48: ; preds = %bb43 + br i1 false, label %cond_next372, label %AllDone + +bb51: ; preds = %bb31 + ret i32 0 + +bb57: ; preds = %bb31, %bb31 + ret i32 0 + +bb74: ; preds = %bb31 + ret i32 0 + +bb189: ; preds = %bb31 + ret i32 0 + +cond_true200.critedge2117: ; preds = %bb43 + ret i32 0 + +cond_next209: ; preds = %bb31, %bb31, %bb31, %bb31, %bb31, %bb31, %bb31 + ret i32 0 + +cond_next372: ; preds = %cond_true48 + switch i32 0, label %bb1728 [ + i32 73, label %bb1723 + i32 74, label %cond_true1700 + i32 78, label %bb1718 + i32 85, label %bb1713 + i32 97, label %bb1620 + i32 107, label %AllDone + i32 112, label %cond_next423 + i32 117, label %cond_next1453 + ] + +cond_next423: ; preds = %cond_next372 + switch i16 0, label %cond_next691 [ + i16 18475, label %cond_next807 + i16 18520, label %cond_next807 + ] + +cond_next691: ; preds = %cond_next423 + ret i32 0 + +cond_next807: ; preds = %cond_next423, %cond_next423 + switch i16 0, label %cond_true1192 [ + i16 18475, label %cond_next21.i + i16 18520, label %cond_next21.i + ] + +cond_next21.i: ; preds = %cond_next807, %cond_next807 + br i1 false, label %cond_next934, label %free.i + +free.i: ; preds = %cond_next21.i + ret i32 0 + +cond_next934: ; preds = %bb1005, %cond_next21.i + %listsize.1 = phi i32 [ 0, %bb1005 ], [ 64, %cond_next21.i ] ; <i32> [#uses=1] + %catalogExtents.2 = phi %struct.HDescriptor* [ %catalogExtents.1.reg2mem.1, %bb1005 ], [ null, %cond_next21.i ] ; <%struct.HDescriptor*> [#uses=3] + br i1 false, label %cond_next942, label %Return1020 + +cond_next942: ; preds = %cond_next934 + br i1 false, label %bb1005, label %bb947 + +bb947: ; preds = %cond_next971, %cond_next942 + %indvar = phi i32 [ 0, %cond_next942 ], [ %indvar.next2140, %cond_next971 ] ; <i32> [#uses=2] + %catalogExtents.1.reg2mem.0 = phi %struct.HDescriptor* [ %catalogExtents.2, %cond_next942 ], [ %tmp977978, %cond_next971 ] ; <%struct.HDescriptor*> [#uses=1] + %extents.0.reg2mem.0 = phi %struct.HDescriptor* [ null, %cond_next942 ], [ %tmp977978, %cond_next971 ] ; <%struct.HDescriptor*> [#uses=1] + br i1 false, label %cond_next971, label %Return1020 + +cond_next971: ; preds = %bb947 + %tmp = shl i32 %indvar, 6 ; <i32> [#uses=1] + %listsize.0.reg2mem.0 = add i32 %tmp, %listsize.1 ; <i32> [#uses=1] + %tmp973 = add i32 %listsize.0.reg2mem.0, 64 ; <i32> [#uses=1] + %tmp974975 = bitcast %struct.HDescriptor* %extents.0.reg2mem.0 to i8* ; <i8*> [#uses=1] + %tmp977 = call i8* @realloc( i8* %tmp974975, i32 %tmp973 ) ; <i8*> [#uses=1] + %tmp977978 = bitcast i8* %tmp977 to %struct.HDescriptor* ; <%struct.HDescriptor*> [#uses=3] + call void @bcopy( i8* null, i8* null, i32 64 ) + %indvar.next2140 = add i32 %indvar, 1 ; <i32> [#uses=1] + br i1 false, label %bb1005, label %bb947 + +bb1005: ; preds = %cond_next971, %cond_next942 + %catalogExtents.1.reg2mem.1 = phi %struct.HDescriptor* [ %catalogExtents.2, %cond_next942 ], [ %tmp977978, %cond_next971 ] ; <%struct.HDescriptor*> [#uses=2] + br i1 false, label %Return1020, label %cond_next934 + +Return1020: ; preds = %bb1005, %bb947, %cond_next934 + %catalogExtents.3 = phi %struct.HDescriptor* [ %catalogExtents.1.reg2mem.0, %bb947 ], [ %catalogExtents.2, %cond_next934 ], [ %catalogExtents.1.reg2mem.1, %bb1005 ] ; <%struct.HDescriptor*> [#uses=0] + ret i32 0 + +cond_true1192: ; preds = %cond_next807 + ret i32 0 + +cond_next1453: ; preds = %cond_next372 + ret i32 0 + +bb1620: ; preds = %cond_next372 + ret i32 0 + +cond_true1700: ; preds = %cond_next372 + ret i32 0 + +bb1713: ; preds = %cond_next372 + ret i32 0 + +bb1718: ; preds = %cond_next372 + ret i32 0 + +bb1723: ; preds = %cond_next372 + ret i32 0 + +bb1728: ; preds = %cond_next372 + ret i32 -6 + +AllDone: ; preds = %cond_next372, %cond_true48 + ret i32 0 +} + +declare i8* @realloc(i8*, i32) diff --git a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll new file mode 100644 index 000000000000..a0649e08076e --- /dev/null +++ b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll @@ -0,0 +1,59 @@ +; RUN: llvm-as < %s | llc -enable-eh +;; Formerly crashed, see PR 1508 +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc64-apple-darwin8" + %struct.Range = type { i64, i64 } + +define void @Bork(i64 %range.0.0, i64 %range.0.1, i64 %size) { +entry: + %effectiveRange = alloca %struct.Range, align 8 ; <%struct.Range*> [#uses=2] + %tmp4 = call i8* @llvm.stacksave() ; <i8*> [#uses=1] + %size1 = trunc i64 %size to i32 ; <i32> [#uses=1] + %tmp17 = alloca i8*, i32 %size1 ; <i8**> [#uses=1] + invoke void @Foo(i8** %tmp17) + to label %bb30.preheader unwind label %unwind + +bb30.preheader: ; preds = %entry + %tmp26 = getelementptr %struct.Range* %effectiveRange, i64 0, i32 1 ; <i64*> [#uses=1] + br label %bb30 + +unwind: ; preds = %cond_true, %entry + %eh_ptr = call i8* @llvm.eh.exception() ; <i8*> [#uses=2] + %eh_select = call i64 (i8*, i8*, ...)* @llvm.eh.selector.i64(i8* %eh_ptr, i8* bitcast (void ()* @__gxx_personality_v0 to i8*), i8* null) ; <i64> [#uses=0] + call void @llvm.stackrestore(i8* %tmp4) + call void @_Unwind_Resume(i8* %eh_ptr) + unreachable + +invcont23: ; preds = %cond_true + %tmp27 = load i64* %tmp26, align 8 ; <i64> [#uses=1] + %tmp28 = sub i64 %range_addr.1.0, %tmp27 ; <i64> [#uses=1] + br label %bb30 + +bb30: ; preds = %invcont23, %bb30.preheader + %range_addr.1.0 = phi i64 [ %tmp28, %invcont23 ], [ %range.0.1, %bb30.preheader ] ; <i64> [#uses=2] + %tmp33 = icmp eq i64 %range_addr.1.0, 0 ; <i1> [#uses=1] + br i1 %tmp33, label %cleanup, label %cond_true + +cond_true: ; preds = %bb30 + invoke void @Bar(i64 %range.0.0, %struct.Range* %effectiveRange) + to label %invcont23 unwind label %unwind + +cleanup: ; preds = %bb30 + ret void +} + +declare i8* @llvm.stacksave() nounwind + +declare void @Foo(i8**) + +declare i8* @llvm.eh.exception() nounwind + +declare i64 @llvm.eh.selector.i64(i8*, i8*, ...) nounwind + +declare void @__gxx_personality_v0() + +declare void @_Unwind_Resume(i8*) + +declare void @Bar(i64, %struct.Range*) + +declare void @llvm.stackrestore(i8*) nounwind diff --git a/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll new file mode 100644 index 000000000000..5cccd315535b --- /dev/null +++ b/test/CodeGen/PowerPC/2007-11-19-VectorSplitting.ll @@ -0,0 +1,16 @@ +; RUN: llvm-as < %s | llc +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 +; PR1811 + +define void @execute_shader(<4 x float>* %OUT, <4 x float>* %IN, <4 x float>* +%CONST) { +entry: + %input2 = load <4 x float>* null, align 16 ; <<4 x float>> + %shuffle7 = shufflevector <4 x float> %input2, <4 x float> < float 0.000000e+00, float 1.000000e+00, float 0.000000e+00, float 1.000000e+00 >, <4 x i32> < i32 2, i32 2, i32 2, i32 2 > ; <<4 x float>> [#uses=1] + + %mul1 = mul <4 x float> %shuffle7, zeroinitializer ; <<4 x + %add2 = add <4 x float> %mul1, %input2 ; <<4 x float>> + store <4 x float> %add2, <4 x float>* null, align 16 + ret void +} diff --git a/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll b/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll new file mode 100644 index 000000000000..38ae87ce8c00 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep nop +target triple = "powerpc-apple-darwin8" + + +define void @bork() noreturn nounwind { +entry: + unreachable +} diff --git a/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll b/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll new file mode 100644 index 000000000000..5b9cd1d8408f --- /dev/null +++ b/test/CodeGen/PowerPC/2008-02-05-LiveIntervalsAssert.ll @@ -0,0 +1,67 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin + + %struct.Handle = type { %struct.oopDesc** } + %struct.JNI_ArgumentPusher = type { %struct.SignatureIterator, %struct.JavaCallArguments* } + %struct.JNI_ArgumentPusherArray = type { %struct.JNI_ArgumentPusher, %struct.JvmtiEventEnabled* } + %struct.JavaCallArguments = type { [9 x i32], [9 x i32], i32*, i32*, i32, i32, i32 } + %struct.JvmtiEventEnabled = type { i64 } + %struct.KlassHandle = type { %struct.Handle } + %struct.SignatureIterator = type { i32 (...)**, %struct.KlassHandle, i32, i32, i32 } + %struct.instanceOopDesc = type { %struct.oopDesc } + %struct.oopDesc = type { %struct.instanceOopDesc*, %struct.instanceOopDesc* } +@.str = external constant [44 x i8] ; <[44 x i8]*> [#uses=1] + +define void @_ZN23JNI_ArgumentPusherArray7iterateEy(%struct.JNI_ArgumentPusherArray* %this, i64 %fingerprint) nounwind { +entry: + br label %bb113 + +bb22.preheader: ; preds = %bb113 + ret void + +bb32.preheader: ; preds = %bb113 + ret void + +bb42.preheader: ; preds = %bb113 + ret void + +bb52: ; preds = %bb113 + br label %bb113 + +bb62.preheader: ; preds = %bb113 + ret void + +bb72.preheader: ; preds = %bb113 + ret void + +bb82: ; preds = %bb113 + br label %bb113 + +bb93: ; preds = %bb113 + br label %bb113 + +bb103.preheader: ; preds = %bb113 + ret void + +bb113: ; preds = %bb113, %bb93, %bb82, %bb52, %entry + %fingerprint_addr.0.reg2mem.9 = phi i64 [ 0, %entry ], [ 0, %bb52 ], [ 0, %bb82 ], [ 0, %bb93 ], [ %tmp118, %bb113 ] ; <i64> [#uses=1] + tail call void @_Z28report_should_not_reach_herePKci( i8* getelementptr ([44 x i8]* @.str, i32 0, i32 0), i32 817 ) nounwind + %tmp118 = lshr i64 %fingerprint_addr.0.reg2mem.9, 4 ; <i64> [#uses=2] + %tmp21158 = and i64 %tmp118, 15 ; <i64> [#uses=1] + switch i64 %tmp21158, label %bb113 [ + i64 1, label %bb22.preheader + i64 2, label %bb52 + i64 3, label %bb32.preheader + i64 4, label %bb42.preheader + i64 5, label %bb62.preheader + i64 6, label %bb82 + i64 7, label %bb93 + i64 8, label %bb103.preheader + i64 9, label %bb72.preheader + i64 10, label %UnifiedReturnBlock + ] + +UnifiedReturnBlock: ; preds = %bb113 + ret void +} + +declare void @_Z28report_should_not_reach_herePKci(i8*, i32) diff --git a/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll new file mode 100644 index 000000000000..5edf6b761fe8 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin -regalloc=local + +define i32 @bork(i64 %foo, i64 %bar) { +entry: + %tmp = load i64* null, align 8 ; <i64> [#uses=2] + %tmp2 = icmp ule i64 %tmp, 0 ; <i1> [#uses=1] + %min = select i1 %tmp2, i64 %tmp, i64 0 ; <i64> [#uses=1] + store i64 %min, i64* null, align 8 + ret i32 0 +} diff --git a/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll new file mode 100644 index 000000000000..8101a35a4fb4 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger + +declare i8* @bar(i32) + +define void @foo(i8* %pp) nounwind { +entry: + %tmp2 = tail call i8* @bar( i32 14 ) nounwind ; <i8*> [#uses=0] + %tmp28 = bitcast i8* %pp to void ()** ; <void ()**> [#uses=1] + %tmp38 = load void ()** %tmp28, align 4 ; <void ()*> [#uses=2] + br i1 false, label %bb34, label %bb25 +bb25: ; preds = %entry + %tmp30 = bitcast void ()* %tmp38 to void (i8*)* ; <void (i8*)*> [#uses=1] + tail call void %tmp30( i8* null ) nounwind + ret void +bb34: ; preds = %entry + tail call void %tmp38( ) nounwind + ret void +} diff --git a/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll b/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll new file mode 100644 index 000000000000..919de33234b8 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-03-06-KillInfo.ll @@ -0,0 +1,21 @@ +; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc64-regscavenger +@.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1] + +define fastcc void @ParseContent(i8* %buf, i32 %bufsize) { +entry: + %items = alloca [10000 x i8*], align 16 ; <[10000 x i8*]*> [#uses=0] + %tmp86 = add i32 0, -1 ; <i32> [#uses=1] + br i1 false, label %cond_true94, label %cond_next99 +cond_true94: ; preds = %entry + %tmp98 = call i32 (i8*, ...)* @printf( i8* getelementptr ([3 x i8]* @.str242, i32 0, i32 0), i8* null ) ; <i32> [#uses=0] + %tmp20971 = icmp sgt i32 %tmp86, 0 ; <i1> [#uses=1] + br i1 %tmp20971, label %bb101, label %bb212 +cond_next99: ; preds = %entry + ret void +bb101: ; preds = %cond_true94 + ret void +bb212: ; preds = %cond_true94 + ret void +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll new file mode 100644 index 000000000000..eaeccc5f27a4 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll @@ -0,0 +1,31 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -enable-ppc32-regscavenger + + %struct._cpp_strbuf = type { i8*, i32, i32 } + %struct.cpp_string = type { i32, i8* } + +declare fastcc void @emit_numeric_escape(i32, i32, %struct._cpp_strbuf*, i32) nounwind + +define i32 @cpp_interpret_string(i32 %pfile, %struct.cpp_string* %from, i32 %wide) nounwind { +entry: + %tmp61 = load i32* null, align 4 ; <i32> [#uses=1] + %toBool = icmp eq i32 %wide, 0 ; <i1> [#uses=2] + %iftmp.87.0 = select i1 %toBool, i32 %tmp61, i32 0 ; <i32> [#uses=2] + %tmp69 = icmp ult i32 %iftmp.87.0, 33 ; <i1> [#uses=1] + %min = select i1 %tmp69, i32 %iftmp.87.0, i32 32 ; <i32> [#uses=1] + %tmp71 = icmp ugt i32 %min, 31 ; <i1> [#uses=1] + br i1 %tmp71, label %bb79, label %bb75 +bb75: ; preds = %entry + ret i32 0 +bb79: ; preds = %entry + br i1 %toBool, label %bb103, label %bb94 +bb94: ; preds = %bb79 + br i1 false, label %bb729, label %bb130.preheader +bb103: ; preds = %bb79 + ret i32 0 +bb130.preheader: ; preds = %bb94 + %tmp134 = getelementptr %struct.cpp_string* %from, i32 0, i32 1 ; <i8**> [#uses=0] + ret i32 0 +bb729: ; preds = %bb94 + call fastcc void @emit_numeric_escape( i32 %pfile, i32 0, %struct._cpp_strbuf* null, i32 %wide ) nounwind + ret i32 1 +} diff --git a/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll new file mode 100644 index 000000000000..061c585c7476 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc64-regscavenger + +define i16 @test(i8* %d1, i16* %d2) { + %tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 ) + ret i16 %tmp237 +} diff --git a/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll b/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll new file mode 100644 index 000000000000..395c986a8412 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-03-24-AddressRegImm.ll @@ -0,0 +1,25 @@ +; RUN: llvm-as < %s | llc -march=ppc64 + +define fastcc i8* @page_rec_get_next(i8* %rec) nounwind { +entry: + %tmp2627 = ptrtoint i8* %rec to i64 ; <i64> [#uses=2] + %tmp28 = and i64 %tmp2627, -16384 ; <i64> [#uses=2] + %tmp2829 = inttoptr i64 %tmp28 to i8* ; <i8*> [#uses=1] + %tmp37 = getelementptr i8* %tmp2829, i64 42 ; <i8*> [#uses=1] + %tmp40 = load i8* %tmp37, align 1 ; <i8> [#uses=1] + %tmp4041 = zext i8 %tmp40 to i64 ; <i64> [#uses=1] + %tmp42 = shl i64 %tmp4041, 8 ; <i64> [#uses=1] + %tmp47 = add i64 %tmp42, 0 ; <i64> [#uses=1] + %tmp52 = and i64 %tmp47, 32768 ; <i64> [#uses=1] + %tmp72 = icmp eq i64 %tmp52, 0 ; <i1> [#uses=1] + br i1 %tmp72, label %bb91, label %bb +bb: ; preds = %entry + ret i8* null +bb91: ; preds = %entry + br i1 false, label %bb100, label %bb185 +bb100: ; preds = %bb91 + %tmp106 = sub i64 %tmp2627, %tmp28 ; <i64> [#uses=0] + ret i8* null +bb185: ; preds = %bb91 + ret i8* null +} diff --git a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll new file mode 100644 index 000000000000..67c167aca127 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll @@ -0,0 +1,30 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + + %struct..0objc_object = type { %struct.objc_class* } + %struct.NSArray = type { %struct..0objc_object } + %struct.NSMutableArray = type { %struct.NSArray } + %struct.PFTPersistentSymbols = type { %struct..0objc_object, %struct.VMUSymbolicator*, %struct.NSMutableArray*, %struct.__CFDictionary*, %struct.__CFDictionary*, %struct.__CFDictionary*, %struct.__CFDictionary*, %struct.NSMutableArray*, i8, %struct.pthread_mutex_t, %struct.NSMutableArray*, %struct.pthread_rwlock_t } + %struct.VMUMachTaskContainer = type { %struct..0objc_object, i32, i32 } + %struct.VMUSymbolicator = type { %struct..0objc_object, %struct.NSMutableArray*, %struct.NSArray*, %struct.NSArray*, %struct.VMUMachTaskContainer*, i8 } + %struct.__CFDictionary = type opaque + %struct.__builtin_CFString = type { i32*, i32, i8*, i32 } + %struct.objc_class = type opaque + %struct.objc_selector = type opaque + %struct.pthread_mutex_t = type { i32, [40 x i8] } + %struct.pthread_rwlock_t = type { i32, [124 x i8] } +external constant %struct.__builtin_CFString ; <%struct.__builtin_CFString*>:0 [#uses=1] + +define void @"-[PFTPersistentSymbols saveSymbolWithName:address:path:lineNumber:flags:owner:]"(%struct.PFTPersistentSymbols* %self, %struct.objc_selector* %_cmd, %struct.NSArray* %name, i64 %address, %struct.NSArray* %path, i32 %lineNumber, i64 %flags, %struct..0objc_object* %owner) nounwind { +entry: + br i1 false, label %bb12, label %bb21 +bb12: ; preds = %entry + %tmp17 = tail call i8 inttoptr (i64 4294901504 to i8 (%struct..0objc_object*, %struct.objc_selector*, %struct.NSArray*)*)( %struct..0objc_object* null, %struct.objc_selector* null, %struct.NSArray* bitcast (%struct.__builtin_CFString* @0 to %struct.NSArray*) ) signext nounwind ; <i8> [#uses=0] + br i1 false, label %bb25, label %bb21 +bb21: ; preds = %bb12, %entry + %tmp24 = or i64 %flags, 4 ; <i64> [#uses=1] + br label %bb25 +bb25: ; preds = %bb21, %bb12 + %flags_addr.0 = phi i64 [ %tmp24, %bb21 ], [ %flags, %bb12 ] ; <i64> [#uses=1] + %tmp3233 = trunc i64 %flags_addr.0 to i32 ; <i32> [#uses=0] + ret void +} diff --git a/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll new file mode 100644 index 000000000000..0b748d20b7ca --- /dev/null +++ b/test/CodeGen/PowerPC/2008-03-26-CoalescerBug.ll @@ -0,0 +1,28 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin + +define i32 @t(i64 %byteStart, i32 %activeIndex) nounwind { +entry: + %tmp50 = load i32* null, align 4 ; <i32> [#uses=1] + %tmp5051 = zext i32 %tmp50 to i64 ; <i64> [#uses=3] + %tmp53 = udiv i64 %byteStart, %tmp5051 ; <i64> [#uses=1] + %tmp5354 = trunc i64 %tmp53 to i32 ; <i32> [#uses=1] + %tmp62 = urem i64 %byteStart, %tmp5051 ; <i64> [#uses=1] + %tmp94 = add i32 0, 1 ; <i32> [#uses=1] + %tmp100 = urem i32 %tmp94, 0 ; <i32> [#uses=2] + %tmp108 = add i32 0, %activeIndex ; <i32> [#uses=1] + %tmp110 = sub i32 %tmp108, 0 ; <i32> [#uses=1] + %tmp112 = urem i32 %tmp110, 0 ; <i32> [#uses=2] + %tmp122 = icmp ult i32 %tmp112, %tmp100 ; <i1> [#uses=1] + %iftmp.175.0 = select i1 %tmp122, i32 %tmp112, i32 %tmp100 ; <i32> [#uses=1] + %tmp119 = add i32 %tmp5354, 0 ; <i32> [#uses=1] + %tmp131 = add i32 %tmp119, %iftmp.175.0 ; <i32> [#uses=1] + %tmp131132 = zext i32 %tmp131 to i64 ; <i64> [#uses=1] + %tmp147 = mul i64 %tmp131132, %tmp5051 ; <i64> [#uses=1] + br i1 false, label %bb164, label %bb190 +bb164: ; preds = %entry + %tmp171172 = and i64 %tmp62, 4294967295 ; <i64> [#uses=1] + %tmp173 = add i64 %tmp171172, %tmp147 ; <i64> [#uses=0] + ret i32 0 +bb190: ; preds = %entry + ret i32 0 +} diff --git a/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll b/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll new file mode 100644 index 000000000000..410736d5872d --- /dev/null +++ b/test/CodeGen/PowerPC/2008-04-10-LiveIntervalCrash.ll @@ -0,0 +1,100 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin + +define fastcc i64 @nonzero_bits1() nounwind { +entry: + switch i32 0, label %bb1385 [ + i32 28, label %bb235 + i32 35, label %bb153 + i32 37, label %bb951 + i32 40, label %bb289 + i32 44, label %bb1344 + i32 46, label %bb651 + i32 47, label %bb651 + i32 48, label %bb322 + i32 49, label %bb651 + i32 50, label %bb651 + i32 51, label %bb651 + i32 52, label %bb651 + i32 53, label %bb651 + i32 54, label %bb535 + i32 55, label %bb565 + i32 56, label %bb565 + i32 58, label %bb1100 + i32 59, label %bb1100 + i32 60, label %bb1100 + i32 61, label %bb1100 + i32 63, label %bb565 + i32 64, label %bb565 + i32 65, label %bb565 + i32 66, label %bb565 + i32 73, label %bb302 + i32 74, label %bb302 + i32 75, label %bb302 + i32 76, label %bb302 + i32 77, label %bb302 + i32 78, label %bb302 + i32 79, label %bb302 + i32 80, label %bb302 + i32 81, label %bb302 + i32 82, label %bb302 + i32 83, label %bb302 + i32 84, label %bb302 + i32 85, label %bb302 + i32 86, label %bb302 + i32 87, label %bb302 + i32 88, label %bb302 + i32 89, label %bb302 + i32 90, label %bb302 + i32 91, label %bb507 + i32 92, label %bb375 + i32 93, label %bb355 + i32 103, label %bb1277 + i32 104, label %bb1310 + i32 105, label %UnifiedReturnBlock + i32 106, label %bb1277 + i32 107, label %bb1343 + ] +bb153: ; preds = %entry + ret i64 0 +bb235: ; preds = %entry + br i1 false, label %bb245, label %UnifiedReturnBlock +bb245: ; preds = %bb235 + ret i64 0 +bb289: ; preds = %entry + ret i64 0 +bb302: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry, %entry + ret i64 0 +bb322: ; preds = %entry + ret i64 0 +bb355: ; preds = %entry + ret i64 0 +bb375: ; preds = %entry + ret i64 0 +bb507: ; preds = %entry + ret i64 0 +bb535: ; preds = %entry + ret i64 0 +bb565: ; preds = %entry, %entry, %entry, %entry, %entry, %entry + ret i64 0 +bb651: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry + ret i64 0 +bb951: ; preds = %entry + ret i64 0 +bb1100: ; preds = %entry, %entry, %entry, %entry + ret i64 0 +bb1277: ; preds = %entry, %entry + br i1 false, label %UnifiedReturnBlock, label %bb1284 +bb1284: ; preds = %bb1277 + ret i64 0 +bb1310: ; preds = %entry + ret i64 0 +bb1343: ; preds = %entry + ret i64 1 +bb1344: ; preds = %entry + ret i64 0 +bb1385: ; preds = %entry + ret i64 0 +UnifiedReturnBlock: ; preds = %bb1277, %bb235, %entry + %UnifiedRetVal = phi i64 [ 0, %bb235 ], [ undef, %bb1277 ], [ -1, %entry ] ; <i64> [#uses=1] + ret i64 %UnifiedRetVal +} diff --git a/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll new file mode 100644 index 000000000000..357ab100d2d4 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-04-16-CoalescerBug.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin +; Avoid reading memory that's already freed. + +@llvm.used = appending global [1 x i8*] [ i8* bitcast (i32 (i64)* @_Z13GetSectorSizey to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define i32 @_Z13GetSectorSizey(i64 %Base) nounwind { +entry: + br i1 false, label %bb, label %UnifiedReturnBlock +bb: ; preds = %entry + %tmp10 = and i64 0, %Base ; <i64> [#uses=0] + ret i32 0 +UnifiedReturnBlock: ; preds = %entry + ret i32 131072 +} diff --git a/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll b/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll new file mode 100644 index 000000000000..a390e522686d --- /dev/null +++ b/test/CodeGen/PowerPC/2008-04-23-CoalescerCrash.ll @@ -0,0 +1,89 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin + +@_ZL10DeviceCode = internal global i16 0 ; <i16*> [#uses=1] +@.str19 = internal constant [64 x i8] c"unlock_then_erase_sector: failed to erase block (status= 0x%x)\0A\00" ; <[64 x i8]*> [#uses=1] +@.str34 = internal constant [68 x i8] c"ProgramByWords - Erasing sector 0x%llx to 0x%llx (size 0x%x bytes)\0A\00" ; <[68 x i8]*> [#uses=1] +@.str35 = internal constant [37 x i8] c"ProgramByWords - Done erasing flash\0A\00" ; <[37 x i8]*> [#uses=1] +@.str36 = internal constant [48 x i8] c"ProgramByWords - Starting to write to FLASH...\0A\00" ; <[48 x i8]*> [#uses=1] + +declare void @IOLog(i8*, ...) + +declare void @IODelay(i32) + +define i32 @_Z14ProgramByWordsPvyy(i8* %buffer, i64 %Offset, i64 %bufferSize) nounwind { +entry: + volatile store i8 -1, i8* null, align 1 + %tmp28 = icmp eq i8 0, 0 ; <i1> [#uses=1] + br i1 %tmp28, label %bb107, label %bb + +bb: ; preds = %entry + %tmp9596430 = zext i32 0 to i64 ; <i64> [#uses=1] + %tmp98431 = add i64 %tmp9596430, %Offset ; <i64> [#uses=1] + %tmp100433 = icmp ugt i64 %tmp98431, %Offset ; <i1> [#uses=1] + br i1 %tmp100433, label %bb31, label %bb103 + +bb31: ; preds = %_Z24unlock_then_erase_sectory.exit, %bb + %Pos.0.reg2mem.0 = phi i64 [ %tmp93, %_Z24unlock_then_erase_sectory.exit ], [ %Offset, %bb ] ; <i64> [#uses=3] + %tmp35 = load i16* @_ZL10DeviceCode, align 2 ; <i16> [#uses=1] + %tmp3536 = zext i16 %tmp35 to i32 ; <i32> [#uses=2] + %tmp37 = and i32 %tmp3536, 65520 ; <i32> [#uses=1] + %tmp38 = icmp eq i32 %tmp37, 35008 ; <i1> [#uses=1] + %tmp34 = sub i64 %Pos.0.reg2mem.0, %Offset ; <i64> [#uses=2] + br i1 %tmp38, label %bb41, label %bb68 + +bb41: ; preds = %bb31 + %tmp43 = add i32 0, -1 ; <i32> [#uses=1] + %tmp4344 = zext i32 %tmp43 to i64 ; <i64> [#uses=1] + %tmp46 = and i64 %tmp4344, %tmp34 ; <i64> [#uses=0] + %tmp49 = and i32 %tmp3536, 1 ; <i32> [#uses=0] + ret i32 0 + +bb68: ; preds = %bb31 + tail call void (i8*, ...)* @IOLog( i8* getelementptr ([68 x i8]* @.str34, i32 0, i32 0), i64 %tmp34, i64 0, i32 131072 ) nounwind + %tmp2021.i = trunc i64 %Pos.0.reg2mem.0 to i32 ; <i32> [#uses=1] + %tmp202122.i = inttoptr i32 %tmp2021.i to i8* ; <i8*> [#uses=1] + tail call void @IODelay( i32 500 ) nounwind + %tmp53.i = volatile load i16* null, align 2 ; <i16> [#uses=2] + %tmp5455.i = zext i16 %tmp53.i to i32 ; <i32> [#uses=1] + br i1 false, label %bb.i, label %bb65.i + +bb.i: ; preds = %bb68 + ret i32 0 + +bb65.i: ; preds = %bb68 + %tmp67.i = icmp eq i16 %tmp53.i, 128 ; <i1> [#uses=1] + br i1 %tmp67.i, label %_Z24unlock_then_erase_sectory.exit, label %bb70.i + +bb70.i: ; preds = %bb65.i + tail call void (i8*, ...)* @IOLog( i8* getelementptr ([64 x i8]* @.str19, i32 0, i32 0), i32 %tmp5455.i ) nounwind + ret i32 0 + +_Z24unlock_then_erase_sectory.exit: ; preds = %bb65.i + volatile store i8 -1, i8* %tmp202122.i, align 1 + %tmp93 = add i64 0, %Pos.0.reg2mem.0 ; <i64> [#uses=2] + %tmp98 = add i64 0, %Offset ; <i64> [#uses=1] + %tmp100 = icmp ugt i64 %tmp98, %tmp93 ; <i1> [#uses=1] + br i1 %tmp100, label %bb31, label %bb103 + +bb103: ; preds = %_Z24unlock_then_erase_sectory.exit, %bb + tail call void (i8*, ...)* @IOLog( i8* getelementptr ([37 x i8]* @.str35, i32 0, i32 0) ) nounwind + ret i32 0 + +bb107: ; preds = %entry + tail call void (i8*, ...)* @IOLog( i8* getelementptr ([48 x i8]* @.str36, i32 0, i32 0) ) nounwind + %tmp114115 = bitcast i8* %buffer to i16* ; <i16*> [#uses=1] + %tmp256 = lshr i64 %bufferSize, 1 ; <i64> [#uses=1] + %tmp256257 = trunc i64 %tmp256 to i32 ; <i32> [#uses=1] + %tmp258 = getelementptr i16* %tmp114115, i32 %tmp256257 ; <i16*> [#uses=0] + ret i32 0 +} + +define i32 @_Z17program_64B_blockyPm(i64 %Base, i32* %pData) nounwind { +entry: + unreachable +} + +define i32 @_Z15ProgramByBlocksyy(i64 %Offset, i64 %bufferSize) nounwind { +entry: + ret i32 0 +} diff --git a/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll b/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll new file mode 100644 index 000000000000..5c40b9e0aed9 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-05-01-ppc_fp128.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +target triple = "powerpc-apple-darwin9.2.2" + +define i256 @func(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone { +entry: + br i1 false, label %bb36, label %bb484 + +bb36: ; preds = %entry + %tmp124 = fcmp ord ppc_fp128 %b, 0xM00000000000000000000000000000000 ; <i1> [#uses=1] + %tmp140 = and i1 %tmp124, fcmp une (ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 0xM00000000000000000000000000000000) ; <i1> [#uses=0] + unreachable + +bb484: ; preds = %entry + ret i256 0 +} diff --git a/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll b/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll new file mode 100644 index 000000000000..d337e3773098 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-06-19-LegalizerCrash.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + +define void @t() nounwind { + call void null( ppc_fp128 undef ) + unreachable +} diff --git a/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll b/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll new file mode 100644 index 000000000000..92b5ca26b2e6 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-06-21-F128LoadStore.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + +@g = external global ppc_fp128 +@h = external global ppc_fp128 + +define void @f() { + %tmp = load ppc_fp128* @g + store ppc_fp128 %tmp, ppc_fp128* @h + ret void +} diff --git a/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll b/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll new file mode 100644 index 000000000000..d3238d23c0ee --- /dev/null +++ b/test/CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll @@ -0,0 +1,25 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; <rdar://problem/6020042> + +define i32 @bork() nounwind { +entry: + br i1 true, label %bb1, label %bb3 + +bb1: + %tmp1 = load i8* null, align 1 + %tmp2 = icmp eq i8 %tmp1, 0 + br label %bb2 + +bb2: + %val1 = phi i32 [ 0, %bb1 ], [ %val2, %bb2 ] + %val2 = select i1 %tmp2, i32 -1, i32 %val1 + switch i32 %val2, label %bb2 [ + i32 -1, label %bb3 + i32 0, label %bb1 + i32 1, label %bb3 + i32 2, label %bb1 + ] + +bb3: + ret i32 -1 +} diff --git a/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll b/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll new file mode 100644 index 000000000000..b6b9c89730a3 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-07-10-SplatMiscompile.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vadduhm +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsubuhm + +define <4 x i32> @test() nounwind { + ret <4 x i32> < i32 4293066722, i32 4293066722, i32 4293066722, i32 4293066722> +} + +define <4 x i32> @test2() nounwind { + ret <4 x i32> < i32 1114129, i32 1114129, i32 1114129, i32 1114129> +} diff --git a/test/CodeGen/PowerPC/2008-07-15-Bswap.ll b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll new file mode 100644 index 000000000000..7060fe560e94 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll @@ -0,0 +1,386 @@ +; RUN: llvm-as < %s | llc +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin9" + %struct.BiPartSrcDescriptor = type <{ %"struct.BiPartSrcDescriptor::$_105" }> + %"struct.BiPartSrcDescriptor::$_105" = type { %struct.BiPartSrcDescriptor_NO_VECTOR_ALIGNMENT_size_is_16 } + %struct.BiPartSrcDescriptor_NO_VECTOR_ALIGNMENT_size_is_16 = type { [2 x %struct.MotionVectors], [2 x i8], %struct.Map4x4ToPartIdx, [2 x i8], i8, i8 } + %struct.Condv = type opaque + %struct.DHBFLayerId = type { i8 } + %struct.DecodeComplexityInfo = type { i32, i32, i32, i32, %"struct.DecodeComplexityInfo::IntraStats", %"struct.DecodeComplexityInfo::InterStats" } + %"struct.DecodeComplexityInfo::InterStats" = type { i32, i32, i32, i32, [5 x i32], [3 x i32], [4 x [4 x i32]], [4 x i32], i32, %struct.MotionVectors, %struct.MotionVectors } + %"struct.DecodeComplexityInfo::IntraStats" = type { i32, i32, i32, [5 x i32], [3 x i32], [4 x i32], [3 x i32] } + %struct.DecodeComplexityOptions = type { i8, i8, i32, double, i8, float, i8, float, i8, i8, i8, i8, i8 } + %struct.DescriptorAllocator = type { %struct.Mutex*, %struct.Mutex*, i8**, i32, i32, i8**, i32, i32, i8**, i32, i32 } + %struct.DetailsFromSliceType = type <{ i8 }> + %struct.FlatnessAnalysis = type { i16, i16, i32, i32*, i8*, [512 x i32], [256 x i32] } + %struct.Frame = type <{ i8, i8, i8, i8, i8, [3 x i8], i32, i32, %struct.Mutex*, %struct.Condv*, [8 x i8], %struct.FramePixels, %struct.FrameMotionVectorCache, %struct.FrameIndex, i32, i8*, i8*, i8*, i8*, i16*, %struct.FlatnessAnalysis, %struct.NoiseAnalysis, %struct.VisualActivity, %struct.FrameMotionInfo, %struct.FrameMotionAnalysis, %struct.FrameDataRateParameters, %struct.FrameEncoderTags, %struct.DecodeComplexityInfo, %struct.DecodeComplexityOptions, %struct.MotionInfoFor16x16_FasterSP*, [1 x i32] }> + %struct.FrameDataRateParameters = type { i32, float, i8, i8 } + %struct.FrameEncoderTags = type { i8, i8, i32, i8, i8, float } + %struct.FrameIndex = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i32, i32, %struct.Frame*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, %struct.DHBFLayerId } + %struct.FrameMotionAnalysis = type { i32, i32, i32, %struct.MoEstMotion16x16*, %struct.MbAnalysis*, i32, i32, i16, i16, i32, i32, i32, i32, i8, i8 } + %struct.FrameMotionInfo = type { i32, i32, %struct.MoEstMbMotionInfo*, i32, i32, i32, i32, i32 } + %struct.FrameMotionVectorCache = type <{ %struct.ThreadAllocator**, i32, i32, i32, %struct.BiPartSrcDescriptor, %struct.BiPartSrcDescriptor, %struct.BiPartSrcDescriptor, [3 x %struct.BiPartSrcDescriptor*], %struct.BiPartSrcDescriptor** }> + %struct.FramePixels = type <{ i8, i8, i8, i8, i8, i8, i8, i8, i8*, i8*, i32, [4 x i8*], [4 x i8*], [2 x [4 x i32]], [2 x [4 x i32]], %struct.PixelData, %struct.InterpolationCache*, %struct.InterpolationCache*, %struct.InterpolationCache*, [16 x i16], [16 x i16], [12 x i8], %"struct.PortableSInt32Array<4>", %"struct.PortableSInt32Array<8>", %struct.ICOffsetArraysY, %struct.UVSrcOffsetEtcX_Struct*, i32*, i32*, [3 x i32] }> + %struct.ICOffsetArraysY = type { [21 x i32], [21 x i32], [4 x [21 x i32]] } + %struct.InterpolationCache = type opaque + %struct.LoopFilterInfo = type { %struct.BiPartSrcDescriptor**, i32, i32, i32, i32, i32*, i32, %"struct.LoopFilterInfo::SliceInfoStruct"*, i32, %struct.Mutex*, i16*, %struct.FramePixels*, i8*, i8*, i8*, i8*, i8*, %struct.PerMacroblockBoundaryStrengths*, %struct.Mutex*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8*, i8*, i8, void (i8*, i8*, i32, i32, i32, i32, i32, i8*, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32, i8*, i32, i8*)*, i32 } + %"struct.LoopFilterInfo::SliceInfoStruct" = type { %"struct.LoopFilterInfo::SliceInfoStruct::LFDisableStats", i8, i8, i8, i8, [17 x %struct.Frame*], [17 x %struct.Frame*] } + %"struct.LoopFilterInfo::SliceInfoStruct::LFDisableStats" = type { i32, i32 } + %struct.LoopFilterParam = type { i32, %struct.LoopFilterInfo*, %struct.FramePixels*, %struct.FrameMotionVectorCache* } + %struct.Map4x4ToPartIdx = type { i16 } + %struct.MbAnalysis = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, %struct.RdCost, %struct.RdCost, i32 } + %struct.MoEstMbMotionInfo = type { i32, i32, i32, i32, [16 x %struct.MoEstPartMotionInfo] } + %struct.MoEstMotion16x16 = type { [2 x i8], [2 x %struct.MotionVectors], i8, [3 x %struct.MoEstPredCost] } + %struct.MoEstPartMotionInfo = type { i32, %struct.PartGeom, i32, i32, [2 x %struct.MotionVectors], [2 x i8], i16 } + %struct.MoEstPredCost = type { i32, i16, i16 } + %struct.MotionInfoFor16x16_FasterSP = type { [2 x %struct.MotionVectors], [2 x i8], i8, [2 x i32], i32, i32 } + %struct.MotionVectors = type { %"struct.MotionVectors::$_103" } + %"struct.MotionVectors::$_103" = type { i32 } + %struct.Mutex = type opaque + %struct.NoiseAnalysis = type { i16, i16, i32, i8*, i8*, i8*, [512 x i32] } + %struct.PartGeom = type { %struct.Map4x4ToPartIdx } + %struct.PerMacroblockBoundaryStrengths = type { [16 x i8], [16 x i8], [4 x i8], [4 x i8], [2 x i32] } + %struct.PixelData = type { i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8, i8 } + %"struct.PortableSInt32Array<4>" = type { [4 x i32] } + %"struct.PortableSInt32Array<8>" = type { [8 x i32] } + %struct.RdCost = type { i32, i32, i32, double } + %struct.ThreadAllocator = type { %struct.DescriptorAllocator*, %struct.BiPartSrcDescriptor*, [256 x %struct.BiPartSrcDescriptor*], i32, i32, i32 } + %struct.ThreadedBatch = type opaque + %struct.UVSrcOffsetEtcX_Struct = type <{ i16 }> + %struct.VisualActivity = type { i16, i16, i32, i32, i32*, i32*, i32, i32, i32*, i32, i32, i32, i32, i32, i8*, i32, [2 x i32], i32, i32, i32, i16*, i16, i16, i16, i16, float, i8*, i32*, i32, i32, i8 } +@_ZL33table_8_14_indexA_to_alpha_scalar = external constant [64 x i8] ; <[64 x i8]*> [#uses=0] +@_ZL32table_8_14_indexB_to_beta_scalar = external constant [64 x i8] ; <[64 x i8]*> [#uses=0] +@_ZL34table_8_15_indexA_bS_to_tc0_scalar = external constant [64 x [4 x i8]] ; <[64 x [4 x i8]]*> [#uses=0] +@gkDummy = external global i32 ; <i32*> [#uses=0] +@gkDetailsFromSliceTypeArray = external constant [10 x %struct.DetailsFromSliceType] ; <[10 x %struct.DetailsFromSliceType]*> [#uses=0] + +declare i32 @_Z20LoopFilter_ConstructP14LoopFilterInfojj(%struct.LoopFilterInfo*, i32, i32) + +declare i32 @_Z25LF_Threading2_assert_doneP14LoopFilterInfo(%struct.LoopFilterInfo*) nounwind + +declare i32 @_Z54S_CalcIfLargeMVDeltaForBMbBothPredictionsFromSameFramePK19BiPartSrcDescriptorS1_ijj(%struct.BiPartSrcDescriptor*, %struct.BiPartSrcDescriptor*, i32, i32, i32) nounwind + +declare void @_Z30LoopFilter_Internal_FilterLumaPhiiiiii(i8*, i32, i32, i32, i32, i32, i32) nounwind + +declare void @_Z33LoopFilter_Internal_FilterChromaVPhiiiiiiiiii(i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind + +declare void @_Z33LoopFilter_Internal_FilterChromaHPhiiiiii(i8*, i32, i32, i32, i32, i32, i32) nounwind + +declare void @_Z42LoopFilter_Internal_filter_macroblock_lumaPK14LoopFilterInfoPhS2_iiiPK30PerMacroblockBoundaryStrengthsjj(%struct.LoopFilterInfo*, i8*, i8*, i32, i32, i32, %struct.PerMacroblockBoundaryStrengths*, i32, i32) nounwind + +declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind + +declare i32 @_Z40LoopFilter_Internal_FilterLumaPlaneMBAFFPK14LoopFilterInfojjj(%struct.LoopFilterInfo*, i32, i32, i32) nounwind + +declare void @_Z18LoopFilter_DestroyP14LoopFilterInfo(%struct.LoopFilterInfo*) + +declare void @MutexDispose(%struct.Mutex*) + +declare void @_ZdaPv(i8*) nounwind + +declare void @jvtDisposePTRVectorAligned(i8*) + +declare void @jvtDisposePTR(i8*) + +declare void @jvtDisposePTRMemAligned(i8*) + +declare void @_Z31LoopFilter_Internal_ResetTablesP14LoopFilterInfo(%struct.LoopFilterInfo*) nounwind + +declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind + +define i32 @_Z60LoopFilter_Internal_CalculateBoundaryStrengths_MbaffFramePicPK14LoopFilterInfoP22FrameMotionVectorCachejj(%struct.LoopFilterInfo* %lfiPtr, %struct.FrameMotionVectorCache* %frameMotionVectorCachePtr, i32 %mbY_min, i32 %mbY_maxPlus1) nounwind { +entry: + icmp ult i32 %mbY_min, %mbY_maxPlus1 ; <i1>:0 [#uses=1] + br i1 %0, label %bb16, label %bb642 + +bb16: ; preds = %entry + bitcast %struct.PerMacroblockBoundaryStrengths* null to i32* ; <i32*>:1 [#uses=3] + getelementptr i32* %1, i32 1 ; <i32*>:2 [#uses=0] + getelementptr i32* %1, i32 2 ; <i32*>:3 [#uses=0] + getelementptr i32* %1, i32 3 ; <i32*>:4 [#uses=0] + bitcast [16 x i8]* null to i32* ; <i32*>:5 [#uses=3] + getelementptr i32* %5, i32 1 ; <i32*>:6 [#uses=0] + getelementptr i32* %5, i32 2 ; <i32*>:7 [#uses=0] + getelementptr i32* %5, i32 3 ; <i32*>:8 [#uses=0] + icmp eq i32 0, 0 ; <i1>:9 [#uses=0] + lshr i32 0, 30 ; <i32>:10 [#uses=0] + and i32 0, 268435455 ; <i32>:11 [#uses=0] + lshr i32 0, 28 ; <i32>:12 [#uses=1] + and i32 %12, 3 ; <i32>:13 [#uses=0] + and i32 0, 1 ; <i32>:14 [#uses=1] + icmp eq i32 %14, 0 ; <i1>:15 [#uses=0] + zext i8 0 to i32 ; <i32>:16 [#uses=1] + %.not656 = icmp ne i32 0, 0 ; <i1> [#uses=1] + icmp eq i8 0, 0 ; <i1>:17 [#uses=0] + trunc i32 0 to i8 ; <i8>:18 [#uses=2] + add i32 0, 1 ; <i32>:19 [#uses=1] + %.not658 = icmp ne i32 0, 0 ; <i1> [#uses=1] + and i32 0, 268369920 ; <i32>:20 [#uses=1] + icmp eq i32 %20, 268369920 ; <i1>:21 [#uses=2] + getelementptr %struct.PerMacroblockBoundaryStrengths* null, i32 0, i32 2 ; <[4 x i8]*>:22 [#uses=1] + getelementptr %struct.PerMacroblockBoundaryStrengths* null, i32 0, i32 2, i32 0 ; <i8*>:23 [#uses=0] + and i32 0, -2 ; <i32>:24 [#uses=1] + add i32 %24, -1 ; <i32>:25 [#uses=0] + bitcast [4 x i8]* %22 to i32* ; <i32*>:26 [#uses=3] + getelementptr i32* %26, i32 1 ; <i32*>:27 [#uses=0] + getelementptr i32* %26, i32 2 ; <i32*>:28 [#uses=0] + getelementptr i32* %26, i32 3 ; <i32*>:29 [#uses=0] + br label %bb144 + +bb144: ; preds = %bb395, %bb16 + %idxEachField11.0773 = phi i32 [ 0, %bb16 ], [ %162, %bb395 ] ; <i32> [#uses=3] + %mbYLeft.2776 = phi i32 [ 0, %bb16 ], [ %mbYLeft.2776, %bb395 ] ; <i32> [#uses=3] + %mbXYLeft.2775 = phi i32 [ 0, %bb16 ], [ %mbXYLeft.2775, %bb395 ] ; <i32> [#uses=1] + %mixedModeLeftEdgeOfMbFlag.2774 = phi i32 [ 0, %bb16 ], [ 0, %bb395 ] ; <i32> [#uses=0] + %mbIndexLeft.2772 = phi i32 [ 0, %bb16 ], [ %mbIndexLeft.2772, %bb395 ] ; <i32> [#uses=2] + %boundaryStrengthsV.1771 = phi i8* [ null, %bb16 ], [ %158, %bb395 ] ; <i8*> [#uses=2] + %numEdgesToTest.1770 = phi i32 [ 4, %bb16 ], [ %numEdgesToTest.2, %bb395 ] ; <i32> [#uses=1] + icmp eq i32 %idxEachField11.0773, 0 ; <i1>:30 [#uses=0] + getelementptr %struct.BiPartSrcDescriptor** null, i32 %mbIndexLeft.2772 ; <%struct.BiPartSrcDescriptor**>:31 [#uses=1] + load %struct.BiPartSrcDescriptor** %31, align 4 ; <%struct.BiPartSrcDescriptor*>:32 [#uses=0] + %fMacroblockHasNonZeroBS.4 = select i1 %21, i32 1, i32 0 ; <i32> [#uses=1] + %numEdgesToTest.2 = select i1 %21, i32 1, i32 %numEdgesToTest.1770 ; <i32> [#uses=2] + store i8 32, i8* %boundaryStrengthsV.1771, align 1 + br label %labelContinueEdgesLoopV + +bb200: ; preds = %labelContinueEdgesLoopV + lshr i32 %159, 28 ; <i32>:33 [#uses=2] + and i32 %160, %16 ; <i32>:34 [#uses=1] + icmp eq i32 %34, 0 ; <i1>:35 [#uses=0] + icmp eq i32 %160, 0 ; <i1>:36 [#uses=3] + zext i1 %36 to i32 ; <i32>:37 [#uses=1] + or i32 %37, -1 ; <i32>:38 [#uses=1] + or i32 %38, %33 ; <i32>:39 [#uses=1] + icmp eq i32 %39, 0 ; <i1>:40 [#uses=1] + br i1 %40, label %bb205, label %bb206 + +bb205: ; preds = %bb200 + store i8 32, i8* %158, align 1 + br label %labelContinueEdgesLoopV + +bb206: ; preds = %bb200 + icmp eq i32 %33, 15 ; <i1>:41 [#uses=1] + br i1 %41, label %labelContinueEdgesLoopV, label %bb210.preheader + +bb210.preheader: ; preds = %bb206 + add i32 %160, 0 ; <i32>:42 [#uses=2] + %bothcond657 = and i1 %36, %.not656 ; <i1> [#uses=0] + shl i32 %idxEachField11.0773, 1 ; <i32>:43 [#uses=1] + add i32 %43, 0 ; <i32>:44 [#uses=0] + shl i32 %mbYLeft.2776, 2 ; <i32>:45 [#uses=0] + add i32 %42, -1 ; <i32>:46 [#uses=1] + icmp eq i32 0, 0 ; <i1>:47 [#uses=1] + %brmerge689.not = and i1 %47, false ; <i1> [#uses=0] + %bothcond659 = and i1 %36, %.not658 ; <i1> [#uses=0] + shl i32 %mbYLeft.2776, 1 ; <i32>:48 [#uses=1] + or i32 %48, 0 ; <i32>:49 [#uses=1] + shl i32 %49, 1 ; <i32>:50 [#uses=0] + add i32 0, 0 ; <i32>:51 [#uses=2] + mul i32 %51, 0 ; <i32>:52 [#uses=1] + add i32 %52, %42 ; <i32>:53 [#uses=1] + mul i32 %51, 0 ; <i32>:54 [#uses=1] + add i32 %46, %54 ; <i32>:55 [#uses=1] + getelementptr %struct.BiPartSrcDescriptor** null, i32 %53 ; <%struct.BiPartSrcDescriptor**>:56 [#uses=1] + load %struct.BiPartSrcDescriptor** %56, align 4 ; <%struct.BiPartSrcDescriptor*>:57 [#uses=7] + getelementptr %struct.BiPartSrcDescriptor** null, i32 %55 ; <%struct.BiPartSrcDescriptor**>:58 [#uses=1] + load %struct.BiPartSrcDescriptor** %58, align 4 ; <%struct.BiPartSrcDescriptor*>:59 [#uses=5] + icmp slt i32 %159, 0 ; <i1>:60 [#uses=0] + icmp eq %struct.BiPartSrcDescriptor* %57, %59 ; <i1>:61 [#uses=0] + bitcast %struct.BiPartSrcDescriptor* %57 to i16* ; <i16*>:62 [#uses=5] + load i16* %62, align 2 ; <i16>:63 [#uses=2] + getelementptr i16* %62, i32 1 ; <i16*>:64 [#uses=1] + load i16* %64, align 2 ; <i16>:65 [#uses=2] + getelementptr i16* %62, i32 2 ; <i16*>:66 [#uses=1] + load i16* %66, align 2 ; <i16>:67 [#uses=2] + getelementptr i16* %62, i32 3 ; <i16*>:68 [#uses=1] + load i16* %68, align 2 ; <i16>:69 [#uses=2] + getelementptr i16* %62, i32 6 ; <i16*>:70 [#uses=1] + load i16* %70, align 2 ; <i16>:71 [#uses=2] + bitcast %struct.BiPartSrcDescriptor* %59 to i16* ; <i16*>:72 [#uses=5] + load i16* %72, align 2 ; <i16>:73 [#uses=2] + getelementptr i16* %72, i32 1 ; <i16*>:74 [#uses=1] + load i16* %74, align 2 ; <i16>:75 [#uses=2] + getelementptr i16* %72, i32 2 ; <i16*>:76 [#uses=1] + load i16* %76, align 2 ; <i16>:77 [#uses=2] + getelementptr i16* %72, i32 3 ; <i16*>:78 [#uses=1] + load i16* %78, align 2 ; <i16>:79 [#uses=2] + getelementptr i16* %72, i32 6 ; <i16*>:80 [#uses=1] + load i16* %80, align 2 ; <i16>:81 [#uses=2] + sub i16 %63, %73 ; <i16>:82 [#uses=3] + sub i16 %65, %75 ; <i16>:83 [#uses=3] + sub i16 %67, %77 ; <i16>:84 [#uses=3] + sub i16 %69, %79 ; <i16>:85 [#uses=3] + sub i16 %71, %81 ; <i16>:86 [#uses=3] + sub i16 0, %82 ; <i16>:87 [#uses=1] + icmp slt i16 %82, 0 ; <i1>:88 [#uses=1] + %. = select i1 %88, i16 %87, i16 %82 ; <i16> [#uses=1] + sub i16 0, %83 ; <i16>:89 [#uses=1] + icmp slt i16 %83, 0 ; <i1>:90 [#uses=1] + %.660 = select i1 %90, i16 %89, i16 %83 ; <i16> [#uses=1] + sub i16 0, %84 ; <i16>:91 [#uses=1] + icmp slt i16 %84, 0 ; <i1>:92 [#uses=1] + %.661 = select i1 %92, i16 %91, i16 %84 ; <i16> [#uses=1] + sub i16 0, %85 ; <i16>:93 [#uses=1] + icmp slt i16 %85, 0 ; <i1>:94 [#uses=1] + %.662 = select i1 %94, i16 %93, i16 %85 ; <i16> [#uses=1] + sub i16 0, %86 ; <i16>:95 [#uses=1] + icmp slt i16 %86, 0 ; <i1>:96 [#uses=1] + %.663 = select i1 %96, i16 %95, i16 %86 ; <i16> [#uses=1] + getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 1, i32 0 ; <i8*>:97 [#uses=1] + load i8* %97, align 1 ; <i8>:98 [#uses=1] + zext i8 %98 to i32 ; <i32>:99 [#uses=1] + getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 1, i32 1 ; <i8*>:100 [#uses=1] + load i8* %100, align 1 ; <i8>:101 [#uses=1] + zext i8 %101 to i32 ; <i32>:102 [#uses=1] + getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 3, i32 0 ; <i8*>:103 [#uses=1] + load i8* %103, align 1 ; <i8>:104 [#uses=2] + zext i8 %104 to i32 ; <i32>:105 [#uses=1] + getelementptr %struct.BiPartSrcDescriptor* %59, i32 0, i32 0, i32 0, i32 3, i32 0 ; <i8*>:106 [#uses=1] + load i8* %106, align 1 ; <i8>:107 [#uses=2] + zext i8 %107 to i32 ; <i32>:108 [#uses=1] + getelementptr %struct.BiPartSrcDescriptor* %57, i32 0, i32 0, i32 0, i32 3, i32 1 ; <i8*>:109 [#uses=1] + load i8* %109, align 1 ; <i8>:110 [#uses=1] + zext i8 %110 to i32 ; <i32>:111 [#uses=1] + getelementptr %struct.BiPartSrcDescriptor* %59, i32 0, i32 0, i32 0, i32 3, i32 1 ; <i8*>:112 [#uses=1] + load i8* %112, align 1 ; <i8>:113 [#uses=1] + zext i8 %113 to i32 ; <i32>:114 [#uses=1] + lshr i32 %99, 4 ; <i32>:115 [#uses=1] + and i32 %115, 2 ; <i32>:116 [#uses=1] + lshr i32 %102, 5 ; <i32>:117 [#uses=1] + or i32 %116, %117 ; <i32>:118 [#uses=3] + icmp eq i32 %118, 0 ; <i1>:119 [#uses=0] + icmp eq i32 %118, 1 ; <i1>:120 [#uses=1] + br i1 %120, label %bb297, label %bb298 + +bb297: ; preds = %bb210.preheader + br label %bb298 + +bb298: ; preds = %bb297, %bb210.preheader + %vu8Mask_0.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=1] + %vu8Mask_1.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=1] + %vu8Mask_2.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=0] + %vu8Mask_3.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=1] + %vu8Mask_4.1 = phi i8 [ 0, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=0] + %vu8Mask_5.1 = phi i8 [ 0, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=1] + %vu8Mask_6.1 = phi i8 [ 0, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=0] + %vu8Mask_7.1 = phi i8 [ 0, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=1] + %vu8Mask_12.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=0] + %vu8Mask_13.1 = phi i8 [ -1, %bb297 ], [ 0, %bb210.preheader ] ; <i8> [#uses=0] + icmp eq i32 %118, 2 ; <i1>:121 [#uses=0] + and i8 %vu8Mask_1.1, 3 ; <i8>:122 [#uses=0] + and i8 %vu8Mask_5.1, 3 ; <i8>:123 [#uses=0] + and i8 %vu8Mask_3.1, %18 ; <i8>:124 [#uses=0] + and i8 %vu8Mask_7.1, %18 ; <i8>:125 [#uses=0] + icmp eq i8 %104, %107 ; <i1>:126 [#uses=1] + br i1 %126, label %bb328, label %bb303 + +bb303: ; preds = %bb298 + call i16 @llvm.bswap.i16( i16 %81 ) ; <i16>:127 [#uses=1] + sub i16 %63, %77 ; <i16>:128 [#uses=3] + sub i16 %65, %79 ; <i16>:129 [#uses=3] + sub i16 %67, %73 ; <i16>:130 [#uses=3] + sub i16 %69, %75 ; <i16>:131 [#uses=3] + sub i16 %71, %127 ; <i16>:132 [#uses=3] + sub i16 0, %128 ; <i16>:133 [#uses=1] + icmp slt i16 %128, 0 ; <i1>:134 [#uses=1] + %.673 = select i1 %134, i16 %133, i16 %128 ; <i16> [#uses=1] + sub i16 0, %129 ; <i16>:135 [#uses=1] + icmp slt i16 %129, 0 ; <i1>:136 [#uses=1] + %.674 = select i1 %136, i16 %135, i16 %129 ; <i16> [#uses=1] + sub i16 0, %130 ; <i16>:137 [#uses=1] + icmp slt i16 %130, 0 ; <i1>:138 [#uses=1] + %.675 = select i1 %138, i16 %137, i16 %130 ; <i16> [#uses=1] + sub i16 0, %131 ; <i16>:139 [#uses=1] + icmp slt i16 %131, 0 ; <i1>:140 [#uses=1] + %.676 = select i1 %140, i16 %139, i16 %131 ; <i16> [#uses=1] + sub i16 0, %132 ; <i16>:141 [#uses=1] + icmp slt i16 %132, 0 ; <i1>:142 [#uses=1] + %.677 = select i1 %142, i16 %141, i16 %132 ; <i16> [#uses=1] + br label %bb328 + +bb328: ; preds = %bb303, %bb298 + %vu16Delta_0.0 = phi i16 [ %.673, %bb303 ], [ %., %bb298 ] ; <i16> [#uses=1] + %vu16Delta_1.0 = phi i16 [ %.674, %bb303 ], [ %.660, %bb298 ] ; <i16> [#uses=0] + %vu16Delta_2.0 = phi i16 [ %.675, %bb303 ], [ %.661, %bb298 ] ; <i16> [#uses=0] + %vu16Delta_3.0 = phi i16 [ %.676, %bb303 ], [ %.662, %bb298 ] ; <i16> [#uses=0] + %vu16Delta_6.0 = phi i16 [ %.677, %bb303 ], [ %.663, %bb298 ] ; <i16> [#uses=0] + lshr i16 %vu16Delta_0.0, 8 ; <i16>:143 [#uses=1] + trunc i16 %143 to i8 ; <i8>:144 [#uses=1] + and i8 %144, %vu8Mask_0.1 ; <i8>:145 [#uses=1] + icmp eq i8 %145, 0 ; <i1>:146 [#uses=0] + sub i32 %105, %114 ; <i32>:147 [#uses=1] + sub i32 %111, %108 ; <i32>:148 [#uses=1] + or i32 %147, %148 ; <i32>:149 [#uses=1] + icmp eq i32 %149, 0 ; <i1>:150 [#uses=0] + call i32 @_Z54S_CalcIfLargeMVDeltaForBMbBothPredictionsFromSameFramePK19BiPartSrcDescriptorS1_ijj( %struct.BiPartSrcDescriptor* %57, %struct.BiPartSrcDescriptor* %59, i32 %19, i32 0, i32 0 ) nounwind ; <i32>:151 [#uses=0] + unreachable + +labelContinueEdgesLoopV: ; preds = %bb206, %bb205, %bb144 + %fEdgeHasNonZeroBS.0 = phi i32 [ 0, %bb205 ], [ 0, %bb144 ], [ 1, %bb206 ] ; <i32> [#uses=2] + %fMacroblockHasNonZeroBS.6 = phi i32 [ %152, %bb205 ], [ %fMacroblockHasNonZeroBS.4, %bb144 ], [ %152, %bb206 ] ; <i32> [#uses=1] + %ixEdge.1 = phi i32 [ %160, %bb205 ], [ 0, %bb144 ], [ %160, %bb206 ] ; <i32> [#uses=1] + %bfNZ12.2 = phi i32 [ %159, %bb205 ], [ 0, %bb144 ], [ %159, %bb206 ] ; <i32> [#uses=1] + %boundaryStrengthsV.3 = phi i8* [ %158, %bb205 ], [ %boundaryStrengthsV.1771, %bb144 ], [ %158, %bb206 ] ; <i8*> [#uses=3] + or i32 %fMacroblockHasNonZeroBS.6, %fEdgeHasNonZeroBS.0 ; <i32>:152 [#uses=2] + load i8* %boundaryStrengthsV.3, align 1 ; <i8>:153 [#uses=1] + trunc i32 %fEdgeHasNonZeroBS.0 to i8 ; <i8>:154 [#uses=1] + shl i8 %154, 5 ; <i8>:155 [#uses=1] + xor i8 %155, 32 ; <i8>:156 [#uses=1] + or i8 %153, %156 ; <i8>:157 [#uses=1] + store i8 %157, i8* %boundaryStrengthsV.3, align 1 + getelementptr i8* %boundaryStrengthsV.3, i32 4 ; <i8*>:158 [#uses=4] + shl i32 %bfNZ12.2, 4 ; <i32>:159 [#uses=4] + add i32 %ixEdge.1, 1 ; <i32>:160 [#uses=6] + icmp ult i32 %160, %numEdgesToTest.2 ; <i1>:161 [#uses=1] + br i1 %161, label %bb200, label %bb395 + +bb395: ; preds = %labelContinueEdgesLoopV + add i32 %idxEachField11.0773, 1 ; <i32>:162 [#uses=2] + icmp ugt i32 %162, 0 ; <i1>:163 [#uses=1] + br i1 %163, label %bb398, label %bb144 + +bb398: ; preds = %bb395 + call void asm sideeffect "dcbt $0, $1", "b%,r,~{memory}"( i32 19, i32* null ) nounwind + unreachable + +bb642: ; preds = %entry + ret i32 0 +} + +declare i16 @llvm.bswap.i16(i16) nounwind readnone + +declare i8* @jvtNewPtrVectorAligned(i32) + +declare i8* @jvtNewPtr(i32) + +declare i8* @jvtNewPtrMemAligned(i32) + +declare %struct.Mutex* @MutexNew() + +declare i8* @_Znam(i32) + +declare i32 @_Z24LoopFilter_FilterMbGroupP14LoopFilterInfoP11FramePixelsP22FrameMotionVectorCacheP19ThreadedBatchStructjjij(%struct.LoopFilterInfo*, %struct.FramePixels*, %struct.FrameMotionVectorCache*, %struct.ThreadedBatch*, i32, i32, i32, i32) + +declare void @MutexLock(%struct.Mutex*) + +declare void @MutexUnlock(%struct.Mutex*) + +declare i32 @_Z35LoopFilter_Internal_FilterLumaPlanePK14LoopFilterInfojjjjj(%struct.LoopFilterInfo*, i32, i32, i32, i32, i32) + +declare i32 @_Z37LoopFilter_Internal_FilterChromaPlanePK14LoopFilterInfojjjjj(%struct.LoopFilterInfo*, i32, i32, i32, i32, i32) + +declare void @_Z44LoopFilter_Internal_filter_macroblock_chromaPK14LoopFilterInfoPhS2_iiiPK30PerMacroblockBoundaryStrengthsjj(%struct.LoopFilterInfo*, i8*, i8*, i32, i32, i32, %struct.PerMacroblockBoundaryStrengths*, i32, i32) nounwind + +declare i32 @_Z42LoopFilter_Internal_FilterChromaPlaneMBAFFPK14LoopFilterInfojjj(%struct.LoopFilterInfo*, i32, i32, i32) nounwind + +declare i32 @_Z26LF_Threading2_ProcessTasksP14LoopFilterInfoP11FramePixelsP22FrameMotionVectorCacheij(%struct.LoopFilterInfo*, %struct.FramePixels*, %struct.FrameMotionVectorCache*, i32, i32) + +declare i32 @_Z46LoopFilter_Internal_CalculateBoundaryStrengthsPK14LoopFilterInfoP22FrameMotionVectorCachejj(%struct.LoopFilterInfo*, %struct.FrameMotionVectorCache*, i32, i32) + +declare i32 @_Z44LoopFilter_Internal_FilterLumaChromaPlane_PPP14LoopFilterInfojjjjj(%struct.LoopFilterInfo*, i32, i32, i32, i32, i32) + +declare i32 @_Z22LoopFilter_FilterFrameP14LoopFilterInfoP11FramePixelsP22FrameMotionVectorCacheP19ThreadedBatchStructij(%struct.LoopFilterInfo*, %struct.FramePixels*, %struct.FrameMotionVectorCache*, %struct.ThreadedBatch*, i32, i32) + +declare void @_Z34LF_Threading2_ProcessTasks_WrapperPv(i8*) + +declare void @llvm.memset.i64(i8*, i8, i64, i32) nounwind diff --git a/test/CodeGen/PowerPC/2008-07-15-Fabs.ll b/test/CodeGen/PowerPC/2008-07-15-Fabs.ll new file mode 100644 index 000000000000..7d86434d24e2 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-07-15-Fabs.ll @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin9" + +define hidden i256 @__divtc3(ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind readnone { +entry: + call ppc_fp128 @fabsl( ppc_fp128 %d ) nounwind readnone ; <ppc_fp128>:0 [#uses=1] + fcmp olt ppc_fp128 0xM00000000000000000000000000000000, %0 ; <i1>:1 [#uses=1] + %.pn106 = select i1 %1, ppc_fp128 %a, ppc_fp128 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1] + %.pn = sub ppc_fp128 0xM00000000000000000000000000000000, %.pn106 ; <ppc_fp128> [#uses=1] + %y.0 = fdiv ppc_fp128 %.pn, 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1] + mul ppc_fp128 %y.0, 0xM3FF00000000000000000000000000000 ; <ppc_fp128>:2 [#uses=1] + add ppc_fp128 %2, mul (ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 0xM00000000000000000000000000000000) ; <ppc_fp128>:3 [#uses=1] + %tmpi = add ppc_fp128 %3, 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1] + store ppc_fp128 %tmpi, ppc_fp128* null, align 16 + ret i256 0 +} + +declare ppc_fp128 @fabsl(ppc_fp128) nounwind readnone diff --git a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll new file mode 100644 index 000000000000..32e36427c5e6 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin9" + +define i16 @t(i16* %dct) signext nounwind { +entry: + load i16* null, align 2 ; <i16>:0 [#uses=2] + lshr i16 %0, 11 ; <i16>:1 [#uses=0] + trunc i16 %0 to i8 ; <i8>:2 [#uses=1] + sext i8 %2 to i16 ; <i16>:3 [#uses=1] + add i16 0, %3 ; <i16>:4 [#uses=1] + sext i16 %4 to i32 ; <i32>:5 [#uses=1] + %dcval.0.in = shl i32 %5, 0 ; <i32> [#uses=1] + %dcval.0 = trunc i32 %dcval.0.in to i16 ; <i16> [#uses=1] + store i16 %dcval.0, i16* %dct, align 2 + ret i16 0 +} diff --git a/test/CodeGen/PowerPC/2008-07-17-Fneg.ll b/test/CodeGen/PowerPC/2008-07-17-Fneg.ll new file mode 100644 index 000000000000..54bb4b37f5e4 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-07-17-Fneg.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin9" + +define hidden i64 @__fixunstfdi(ppc_fp128 %a) nounwind { +entry: + br i1 false, label %bb3, label %bb4 + +bb3: ; preds = %entry + sub ppc_fp128 0xM80000000000000000000000000000000, 0xM00000000000000000000000000000000 ; <ppc_fp128>:0 [#uses=1] + fptoui ppc_fp128 %0 to i32 ; <i32>:1 [#uses=1] + zext i32 %1 to i64 ; <i64>:2 [#uses=1] + sub i64 0, %2 ; <i64>:3 [#uses=1] + ret i64 %3 + +bb4: ; preds = %entry + ret i64 0 +} diff --git a/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll b/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll new file mode 100644 index 000000000000..2ccca25e2a27 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-07-24-PPC64-CCBug.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin | grep lwz | grep 228 + +@"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] + +define void @llvm_static_func(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15) nounwind { +entry: + tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @"\01LC", i32 0, i64 0), i32 %a8 ) nounwind ; <i32>:0 [#uses=0] + ret void +} + +declare i32 @printf(i8*, ...) nounwind diff --git a/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll new file mode 100644 index 000000000000..c181b1c97021 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-09-12-CoalescerBug.ll @@ -0,0 +1,254 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin + + %struct.CGLDI = type { %struct.cgli*, i32, i32, i32, i32, i32, i8*, i32, void (%struct.CGLSI*, i32, %struct.CGLDI*)*, i8*, %struct.vv_t } + %struct.cgli = type { i32, %struct.cgli*, void (%struct.cgli*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32)*, i32, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i8*, i32*, %struct._cgro*, %struct._cgro*, float, float, float, float, i32, i8*, float, i8*, [16 x i32] } + %struct.CGLSI = type { %struct.cgli*, i32, i8*, i8*, i32, i32, i8*, void (%struct.cgli*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32)*, %struct.vv_t, %struct.vv_t, %struct.xx_t* } + %struct._cgro = type opaque + %struct.xx_t = type { [3 x %struct.vv_t], [2 x %struct.vv_t], [2 x [3 x i8*]] } + %struct.vv_t = type { <16 x i8> } +@llvm.used = appending global [1 x i8*] [ i8* bitcast (void (%struct.CGLSI*, i32, %struct.CGLDI*)* @lb to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define void @lb(%struct.CGLSI* %src, i32 %n, %struct.CGLDI* %dst) nounwind { +entry: + %0 = load i32* null, align 4 ; <i32> [#uses=1] + %1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1] + br i1 %1, label %bb.nph4945, label %return + +bb.nph4945: ; preds = %entry + %2 = bitcast [2 x %struct.vv_t]* null to i64* ; <i64*> [#uses=6] + %3 = getelementptr [2 x i64]* null, i32 0, i32 1 ; <i64*> [#uses=6] + %4 = bitcast %struct.vv_t* null to i64* ; <i64*> [#uses=5] + %5 = getelementptr [2 x i64]* null, i32 0, i32 1 ; <i64*> [#uses=3] + br label %bb2326 + +bb2217: ; preds = %bb2326 + %6 = or i64 0, 0 ; <i64> [#uses=2] + %7 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1] + %8 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1] + %9 = getelementptr float* null, i32 2 ; <float*> [#uses=1] + %10 = load float* %9, align 4 ; <float> [#uses=1] + %11 = getelementptr float* null, i32 3 ; <float*> [#uses=1] + %12 = load float* %11, align 4 ; <float> [#uses=1] + %13 = mul float %10, 6.553500e+04 ; <float> [#uses=1] + %14 = add float %13, 5.000000e-01 ; <float> [#uses=1] + %15 = mul float %12, 6.553500e+04 ; <float> [#uses=1] + %16 = add float %15, 5.000000e-01 ; <float> [#uses=3] + %17 = fcmp olt float %14, 0.000000e+00 ; <i1> [#uses=0] + %18 = fcmp olt float %16, 0.000000e+00 ; <i1> [#uses=1] + br i1 %18, label %bb2265, label %bb2262 + +bb2262: ; preds = %bb2217 + %19 = fcmp ogt float %16, 6.553500e+04 ; <i1> [#uses=1] + br i1 %19, label %bb2264, label %bb2265 + +bb2264: ; preds = %bb2262 + br label %bb2265 + +bb2265: ; preds = %bb2264, %bb2262, %bb2217 + %f3596.0 = phi float [ 6.553500e+04, %bb2264 ], [ 0.000000e+00, %bb2217 ], [ %16, %bb2262 ] ; <float> [#uses=1] + %20 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1] + %21 = fptosi float %f3596.0 to i32 ; <i32> [#uses=1] + %22 = zext i32 %7 to i64 ; <i64> [#uses=1] + %23 = shl i64 %22, 48 ; <i64> [#uses=1] + %24 = zext i32 %8 to i64 ; <i64> [#uses=1] + %25 = shl i64 %24, 32 ; <i64> [#uses=1] + %26 = sext i32 %20 to i64 ; <i64> [#uses=1] + %27 = shl i64 %26, 16 ; <i64> [#uses=1] + %28 = sext i32 %21 to i64 ; <i64> [#uses=1] + %29 = or i64 %25, %23 ; <i64> [#uses=1] + %30 = or i64 %29, %27 ; <i64> [#uses=1] + %31 = or i64 %30, %28 ; <i64> [#uses=2] + %32 = shl i64 %6, 48 ; <i64> [#uses=1] + %33 = shl i64 %31, 32 ; <i64> [#uses=1] + %34 = and i64 %33, 281470681743360 ; <i64> [#uses=1] + store i64 %6, i64* %2, align 16 + store i64 %31, i64* %3, align 8 + %35 = getelementptr i8* null, i32 0 ; <i8*> [#uses=1] + %36 = bitcast i8* %35 to float* ; <float*> [#uses=4] + %37 = load float* %36, align 4 ; <float> [#uses=1] + %38 = getelementptr float* %36, i32 1 ; <float*> [#uses=1] + %39 = load float* %38, align 4 ; <float> [#uses=1] + %40 = mul float %37, 6.553500e+04 ; <float> [#uses=1] + %41 = add float %40, 5.000000e-01 ; <float> [#uses=1] + %42 = mul float %39, 6.553500e+04 ; <float> [#uses=1] + %43 = add float %42, 5.000000e-01 ; <float> [#uses=3] + %44 = fcmp olt float %41, 0.000000e+00 ; <i1> [#uses=0] + %45 = fcmp olt float %43, 0.000000e+00 ; <i1> [#uses=1] + br i1 %45, label %bb2277, label %bb2274 + +bb2274: ; preds = %bb2265 + %46 = fcmp ogt float %43, 6.553500e+04 ; <i1> [#uses=0] + br label %bb2277 + +bb2277: ; preds = %bb2274, %bb2265 + %f1582.0 = phi float [ 0.000000e+00, %bb2265 ], [ %43, %bb2274 ] ; <float> [#uses=1] + %47 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1] + %48 = fptosi float %f1582.0 to i32 ; <i32> [#uses=1] + %49 = getelementptr float* %36, i32 2 ; <float*> [#uses=1] + %50 = load float* %49, align 4 ; <float> [#uses=1] + %51 = getelementptr float* %36, i32 3 ; <float*> [#uses=1] + %52 = load float* %51, align 4 ; <float> [#uses=1] + %53 = mul float %50, 6.553500e+04 ; <float> [#uses=1] + %54 = add float %53, 5.000000e-01 ; <float> [#uses=1] + %55 = mul float %52, 6.553500e+04 ; <float> [#uses=1] + %56 = add float %55, 5.000000e-01 ; <float> [#uses=1] + %57 = fcmp olt float %54, 0.000000e+00 ; <i1> [#uses=0] + %58 = fcmp olt float %56, 0.000000e+00 ; <i1> [#uses=0] + %59 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1] + %60 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1] + %61 = zext i32 %47 to i64 ; <i64> [#uses=1] + %62 = shl i64 %61, 48 ; <i64> [#uses=1] + %63 = zext i32 %48 to i64 ; <i64> [#uses=1] + %64 = shl i64 %63, 32 ; <i64> [#uses=1] + %65 = sext i32 %59 to i64 ; <i64> [#uses=1] + %66 = shl i64 %65, 16 ; <i64> [#uses=1] + %67 = sext i32 %60 to i64 ; <i64> [#uses=1] + %68 = or i64 %64, %62 ; <i64> [#uses=1] + %69 = or i64 %68, %66 ; <i64> [#uses=1] + %70 = or i64 %69, %67 ; <i64> [#uses=2] + %71 = getelementptr i8* null, i32 0 ; <i8*> [#uses=1] + %72 = bitcast i8* %71 to float* ; <float*> [#uses=4] + %73 = load float* %72, align 4 ; <float> [#uses=1] + %74 = getelementptr float* %72, i32 1 ; <float*> [#uses=1] + %75 = load float* %74, align 4 ; <float> [#uses=1] + %76 = mul float %73, 6.553500e+04 ; <float> [#uses=1] + %77 = add float %76, 5.000000e-01 ; <float> [#uses=3] + %78 = mul float %75, 6.553500e+04 ; <float> [#uses=1] + %79 = add float %78, 5.000000e-01 ; <float> [#uses=1] + %80 = fcmp olt float %77, 0.000000e+00 ; <i1> [#uses=1] + br i1 %80, label %bb2295, label %bb2292 + +bb2292: ; preds = %bb2277 + %81 = fcmp ogt float %77, 6.553500e+04 ; <i1> [#uses=1] + br i1 %81, label %bb2294, label %bb2295 + +bb2294: ; preds = %bb2292 + br label %bb2295 + +bb2295: ; preds = %bb2294, %bb2292, %bb2277 + %f0569.0 = phi float [ 6.553500e+04, %bb2294 ], [ 0.000000e+00, %bb2277 ], [ %77, %bb2292 ] ; <float> [#uses=1] + %82 = fcmp olt float %79, 0.000000e+00 ; <i1> [#uses=0] + %83 = fptosi float %f0569.0 to i32 ; <i32> [#uses=1] + %84 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1] + %85 = getelementptr float* %72, i32 2 ; <float*> [#uses=1] + %86 = load float* %85, align 4 ; <float> [#uses=1] + %87 = getelementptr float* %72, i32 3 ; <float*> [#uses=1] + %88 = load float* %87, align 4 ; <float> [#uses=1] + %89 = mul float %86, 6.553500e+04 ; <float> [#uses=1] + %90 = add float %89, 5.000000e-01 ; <float> [#uses=1] + %91 = mul float %88, 6.553500e+04 ; <float> [#uses=1] + %92 = add float %91, 5.000000e-01 ; <float> [#uses=1] + %93 = fcmp olt float %90, 0.000000e+00 ; <i1> [#uses=0] + %94 = fcmp olt float %92, 0.000000e+00 ; <i1> [#uses=0] + %95 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1] + %96 = fptosi float 0.000000e+00 to i32 ; <i32> [#uses=1] + %97 = zext i32 %83 to i64 ; <i64> [#uses=1] + %98 = shl i64 %97, 48 ; <i64> [#uses=1] + %99 = zext i32 %84 to i64 ; <i64> [#uses=1] + %100 = shl i64 %99, 32 ; <i64> [#uses=1] + %101 = sext i32 %95 to i64 ; <i64> [#uses=1] + %102 = shl i64 %101, 16 ; <i64> [#uses=1] + %103 = sext i32 %96 to i64 ; <i64> [#uses=1] + %104 = or i64 %100, %98 ; <i64> [#uses=1] + %105 = or i64 %104, %102 ; <i64> [#uses=1] + %106 = or i64 %105, %103 ; <i64> [#uses=2] + %107 = shl i64 %70, 16 ; <i64> [#uses=1] + %108 = and i64 %107, 4294901760 ; <i64> [#uses=1] + %109 = and i64 %106, 65535 ; <i64> [#uses=1] + %110 = or i64 %34, %32 ; <i64> [#uses=1] + %111 = or i64 %110, %108 ; <i64> [#uses=1] + %112 = or i64 %111, %109 ; <i64> [#uses=1] + store i64 %70, i64* %4, align 16 + store i64 %106, i64* %5, align 8 + %113 = icmp eq i64 %112, 0 ; <i1> [#uses=1] + br i1 %113, label %bb2325, label %bb2315 + +bb2315: ; preds = %bb2295 + %114 = icmp eq %struct.xx_t* %159, null ; <i1> [#uses=1] + br i1 %114, label %bb2318, label %bb2317 + +bb2317: ; preds = %bb2315 + %115 = load i64* %2, align 16 ; <i64> [#uses=1] + %116 = call i32 (...)* @_u16a_cm( i64 %115, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1] + %117 = sext i32 %116 to i64 ; <i64> [#uses=1] + store i64 %117, i64* %2, align 16 + %118 = load i64* %3, align 8 ; <i64> [#uses=1] + %119 = call i32 (...)* @_u16a_cm( i64 %118, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1] + %120 = sext i32 %119 to i64 ; <i64> [#uses=1] + store i64 %120, i64* %3, align 8 + %121 = load i64* %4, align 16 ; <i64> [#uses=1] + %122 = call i32 (...)* @_u16a_cm( i64 %121, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=1] + %123 = sext i32 %122 to i64 ; <i64> [#uses=1] + store i64 %123, i64* %4, align 16 + %124 = load i64* %5, align 8 ; <i64> [#uses=1] + %125 = call i32 (...)* @_u16a_cm( i64 %124, %struct.xx_t* %159, double 0.000000e+00, double 1.047551e+06 ) nounwind ; <i32> [#uses=0] + unreachable + +bb2318: ; preds = %bb2315 + %126 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 8 ; <%struct.vv_t*> [#uses=1] + %127 = bitcast %struct.vv_t* %126 to i64* ; <i64*> [#uses=1] + %128 = load i64* %127, align 8 ; <i64> [#uses=1] + %129 = trunc i64 %128 to i32 ; <i32> [#uses=4] + %130 = load i64* %2, align 16 ; <i64> [#uses=1] + %131 = call i32 (...)* @_u16_ff( i64 %130, i32 %129 ) nounwind ; <i32> [#uses=1] + %132 = sext i32 %131 to i64 ; <i64> [#uses=1] + store i64 %132, i64* %2, align 16 + %133 = load i64* %3, align 8 ; <i64> [#uses=1] + %134 = call i32 (...)* @_u16_ff( i64 %133, i32 %129 ) nounwind ; <i32> [#uses=1] + %135 = sext i32 %134 to i64 ; <i64> [#uses=1] + store i64 %135, i64* %3, align 8 + %136 = load i64* %4, align 16 ; <i64> [#uses=1] + %137 = call i32 (...)* @_u16_ff( i64 %136, i32 %129 ) nounwind ; <i32> [#uses=1] + %138 = sext i32 %137 to i64 ; <i64> [#uses=1] + store i64 %138, i64* %4, align 16 + %139 = load i64* %5, align 8 ; <i64> [#uses=1] + %140 = call i32 (...)* @_u16_ff( i64 %139, i32 %129 ) nounwind ; <i32> [#uses=0] + unreachable + +bb2319: ; preds = %bb2326 + %141 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 2 ; <i8**> [#uses=1] + %142 = load i8** %141, align 4 ; <i8*> [#uses=4] + %143 = getelementptr i8* %142, i32 0 ; <i8*> [#uses=1] + %144 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %143 ) nounwind ; <i32> [#uses=1] + %145 = sext i32 %144 to i64 ; <i64> [#uses=2] + %146 = getelementptr i8* %142, i32 0 ; <i8*> [#uses=1] + %147 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %146 ) nounwind ; <i32> [#uses=1] + %148 = sext i32 %147 to i64 ; <i64> [#uses=2] + %149 = shl i64 %145, 48 ; <i64> [#uses=0] + %150 = shl i64 %148, 32 ; <i64> [#uses=1] + %151 = and i64 %150, 281470681743360 ; <i64> [#uses=0] + store i64 %145, i64* %2, align 16 + store i64 %148, i64* %3, align 8 + %152 = getelementptr i8* %142, i32 0 ; <i8*> [#uses=1] + %153 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %152 ) nounwind ; <i32> [#uses=1] + %154 = sext i32 %153 to i64 ; <i64> [#uses=0] + %155 = getelementptr i8* %142, i32 0 ; <i8*> [#uses=1] + %156 = call i32 (...)* @_u16_sf32( double 0.000000e+00, double 6.553500e+04, double 5.000000e-01, i8* %155 ) nounwind ; <i32> [#uses=0] + unreachable + +bb2325: ; preds = %bb2326, %bb2295 + %indvar.next5145 = add i32 %indvar5021, 1 ; <i32> [#uses=1] + br label %bb2326 + +bb2326: ; preds = %bb2325, %bb.nph4945 + %indvar5021 = phi i32 [ 0, %bb.nph4945 ], [ %indvar.next5145, %bb2325 ] ; <i32> [#uses=6] + %157 = icmp slt i32 %indvar5021, %n ; <i1> [#uses=0] + %158 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 10 ; <%struct.xx_t**> [#uses=1] + %159 = load %struct.xx_t** %158, align 4 ; <%struct.xx_t*> [#uses=5] + %160 = getelementptr %struct.CGLSI* %src, i32 %indvar5021, i32 1 ; <i32*> [#uses=1] + %161 = load i32* %160, align 4 ; <i32> [#uses=1] + %162 = and i32 %161, 255 ; <i32> [#uses=1] + switch i32 %162, label %bb2325 [ + i32 59, label %bb2217 + i32 60, label %bb2319 + ] + +return: ; preds = %entry + ret void +} + +declare i32 @_u16_ff(...) + +declare i32 @_u16a_cm(...) + +declare i32 @_u16_sf32(...) diff --git a/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll b/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll new file mode 100644 index 000000000000..00ca81161027 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc +; XFAIL: * +; PR2356 +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin9" + +define i32 @test(i64 %x, i32* %p) nounwind { + %asmtmp = call i32 asm "", "=r,0"(i64 0) nounwind ; <i32> [#uses=0] + %y = add i32 %asmtmp, 1 + ret i32 %y +} diff --git a/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll b/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll new file mode 100644 index 000000000000..0283082e8c0f --- /dev/null +++ b/test/CodeGen/PowerPC/2008-10-28-UnprocessedNode.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=ppc64 + +define void @__divtc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind { +entry: + %imag59 = load ppc_fp128* null, align 8 ; <ppc_fp128> [#uses=1] + %0 = mul ppc_fp128 0xM00000000000000000000000000000000, %imag59 ; <ppc_fp128> [#uses=1] + %1 = mul ppc_fp128 0xM00000000000000000000000000000000, 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1] + %2 = add ppc_fp128 %0, %1 ; <ppc_fp128> [#uses=1] + store ppc_fp128 %2, ppc_fp128* null, align 16 + unreachable +} diff --git a/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll b/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll new file mode 100644 index 000000000000..4db577357da1 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll @@ -0,0 +1,33 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -o - | not grep fixunstfsi + +define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone { +entry: + %0 = fcmp olt ppc_fp128 %a, 0xM00000000000000000000000000000000 ; <i1> [#uses=1] + br i1 %0, label %bb5, label %bb1 + +bb1: ; preds = %entry + %1 = mul ppc_fp128 %a, 0xM3DF00000000000000000000000000000 ; <ppc_fp128> [#uses=1] + %2 = fptoui ppc_fp128 %1 to i32 ; <i32> [#uses=1] + %3 = zext i32 %2 to i64 ; <i64> [#uses=1] + %4 = shl i64 %3, 32 ; <i64> [#uses=3] + %5 = uitofp i64 %4 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %6 = sub ppc_fp128 %a, %5 ; <ppc_fp128> [#uses=3] + %7 = fcmp olt ppc_fp128 %6, 0xM00000000000000000000000000000000 ; <i1> [#uses=1] + br i1 %7, label %bb2, label %bb3 + +bb2: ; preds = %bb1 + %8 = sub ppc_fp128 0xM80000000000000000000000000000000, %6 ; <ppc_fp128> [#uses=1] + %9 = fptoui ppc_fp128 %8 to i32 ; <i32> [#uses=1] + %10 = zext i32 %9 to i64 ; <i64> [#uses=1] + %11 = sub i64 %4, %10 ; <i64> [#uses=1] + ret i64 %11 + +bb3: ; preds = %bb1 + %12 = fptoui ppc_fp128 %6 to i32 ; <i32> [#uses=1] + %13 = zext i32 %12 to i64 ; <i64> [#uses=1] + %14 = or i64 %13, %4 ; <i64> [#uses=1] + ret i64 %14 + +bb5: ; preds = %entry + ret i64 0 +} diff --git a/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll b/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll new file mode 100644 index 000000000000..af9a54ee9d13 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-10-30-IllegalShift.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; PR2986 +@argc = external global i32 ; <i32*> [#uses=1] +@buffer = external global [32 x i8], align 4 ; <[32 x i8]*> [#uses=1] + +define void @test1() nounwind noinline { +entry: + %0 = load i32* @argc, align 4 ; <i32> [#uses=1] + %1 = trunc i32 %0 to i8 ; <i8> [#uses=1] + tail call void @llvm.memset.i32(i8* getelementptr ([32 x i8]* @buffer, i32 0, i32 0), i8 %1, i32 17, i32 4) + unreachable +} + +declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind diff --git a/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll new file mode 100644 index 000000000000..0ad5b06c8032 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll @@ -0,0 +1,37 @@ +; RUN: llvm-as < %s | llc +; PR2988 +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin10.0" +@a = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; <ppc_fp128*> [#uses=2] +@b = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; <ppc_fp128*> [#uses=2] +@c = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; <ppc_fp128*> [#uses=3] +@d = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; <ppc_fp128*> [#uses=2] + +define void @foo() nounwind { +entry: + %0 = load ppc_fp128* @a, align 16 ; <ppc_fp128> [#uses=1] + %1 = call ppc_fp128 @llvm.sqrt.ppcf128(ppc_fp128 %0) ; <ppc_fp128> [#uses=1] + store ppc_fp128 %1, ppc_fp128* @a, align 16 + %2 = load ppc_fp128* @b, align 16 ; <ppc_fp128> [#uses=1] + %3 = call ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128 %2) nounwind readonly ; <ppc_fp128> [#uses=1] + store ppc_fp128 %3, ppc_fp128* @b, align 16 + %4 = load ppc_fp128* @c, align 16 ; <ppc_fp128> [#uses=1] + %5 = call ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128 %4) nounwind readonly ; <ppc_fp128> [#uses=1] + store ppc_fp128 %5, ppc_fp128* @c, align 16 + %6 = load ppc_fp128* @d, align 16 ; <ppc_fp128> [#uses=1] + %7 = load ppc_fp128* @c, align 16 ; <ppc_fp128> [#uses=1] + %8 = call ppc_fp128 @llvm.pow.ppcf128(ppc_fp128 %6, ppc_fp128 %7) ; <ppc_fp128> [#uses=1] + store ppc_fp128 %8, ppc_fp128* @d, align 16 + br label %return + +return: ; preds = %entry + ret void +} + +declare ppc_fp128 @llvm.sqrt.ppcf128(ppc_fp128) nounwind readonly + +declare ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128) nounwind readonly + +declare ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128) nounwind readonly + +declare ppc_fp128 @llvm.pow.ppcf128(ppc_fp128, ppc_fp128) nounwind readonly diff --git a/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll b/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll new file mode 100644 index 000000000000..f5b3e93d6170 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-12-02-LegalizeTypeAssert.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc64-apple-darwin9.5 + +define void @__multc3({ ppc_fp128, ppc_fp128 }* noalias sret %agg.result, ppc_fp128 %a, ppc_fp128 %b, ppc_fp128 %c, ppc_fp128 %d) nounwind { +entry: + %.pre139 = and i1 false, false ; <i1> [#uses=1] + br i1 false, label %bb6, label %bb21 + +bb6: ; preds = %entry + %0 = tail call ppc_fp128 @copysignl(ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128 %a) nounwind readnone ; <ppc_fp128> [#uses=0] + %iftmp.1.0 = select i1 %.pre139, ppc_fp128 0xM3FF00000000000000000000000000000, ppc_fp128 0xM00000000000000000000000000000000 ; <ppc_fp128> [#uses=1] + %1 = tail call ppc_fp128 @copysignl(ppc_fp128 %iftmp.1.0, ppc_fp128 %b) nounwind readnone ; <ppc_fp128> [#uses=0] + unreachable + +bb21: ; preds = %entry + unreachable +} + +declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) nounwind readnone diff --git a/test/CodeGen/PowerPC/2008-12-12-EH.ll b/test/CodeGen/PowerPC/2008-12-12-EH.ll new file mode 100644 index 000000000000..21218f55f039 --- /dev/null +++ b/test/CodeGen/PowerPC/2008-12-12-EH.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | grep ^.L_Z1fv.eh +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh + +define void @_Z1fv() { +entry: + br label %return + +return: + ret void +} diff --git a/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll b/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll new file mode 100644 index 000000000000..0cf55188278e --- /dev/null +++ b/test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin9.5 +; rdar://6499616 + + %llvm.dbg.anchor.type = type { i32, i32 } + %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8* } +@llvm.dbg.compile_units = linkonce constant %llvm.dbg.anchor.type { i32 458752, i32 17 } ; <%llvm.dbg.anchor.type*> [#uses=1] +@.str = internal constant [11 x i8] c"testcase.c\00" ; <[11 x i8]*> [#uses=1] +@.str1 = internal constant [30 x i8] c"/Volumes/SandBox/NightlyTest/\00" ; <[30 x i8]*> [#uses=1] +@.str2 = internal constant [57 x i8] c"4.2.1 (Based on Apple Inc. build 5628) (LLVM build 9999)\00" ; <[57 x i8]*> [#uses=1] +@llvm.dbg.compile_unit = internal constant %llvm.dbg.compile_unit.type { i32 458769, { }* bitcast (%llvm.dbg.anchor.type* @llvm.dbg.compile_units to { }*), i32 1, i8* getelementptr ([11 x i8]* @.str, i32 0, i32 0), i8* getelementptr ([30 x i8]* @.str1, i32 0, i32 0), i8* getelementptr ([57 x i8]* @.str2, i32 0, i32 0) } ; <%llvm.dbg.compile_unit.type*> [#uses=0] +@"\01LC" = internal constant [13 x i8] c"conftest.val\00" ; <[13 x i8]*> [#uses=1] + +define i32 @main() nounwind { +entry: + %0 = call i8* @fopen(i8* getelementptr ([13 x i8]* @"\01LC", i32 0, i32 0), i8* null) nounwind ; <i8*> [#uses=0] + unreachable +} + +declare i8* @fopen(i8*, i8*) diff --git a/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll b/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll new file mode 100644 index 000000000000..a898de0b4853 --- /dev/null +++ b/test/CodeGen/PowerPC/2009-03-17-LSRBug.ll @@ -0,0 +1,51 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin10 +; rdar://6692215 + +define fastcc void @_qsort(i8* %a, i32 %n, i32 %es, i32 (i8*, i8*)* %cmp, i32 %depth_limit) nounwind optsize ssp { +entry: + br i1 false, label %bb21, label %bb20.loopexit + +bb20.loopexit: ; preds = %entry + ret void + +bb21: ; preds = %entry + %0 = getelementptr i8* %a, i32 0 ; <i8*> [#uses=2] + br label %bb35 + +bb29: ; preds = %bb35 + br i1 false, label %bb7.i252, label %bb34 + +bb7.i252: ; preds = %bb7.i252, %bb29 + %pj.0.rec.i247 = phi i32 [ %indvar.next488, %bb7.i252 ], [ 0, %bb29 ] ; <i32> [#uses=2] + %pi.0.i248 = getelementptr i8* %pa.1, i32 %pj.0.rec.i247 ; <i8*> [#uses=0] + %indvar.next488 = add i32 %pj.0.rec.i247, 1 ; <i32> [#uses=1] + br i1 false, label %bb34, label %bb7.i252 + +bb34: ; preds = %bb7.i252, %bb29 + %indvar.next505 = add i32 %indvar504, 1 ; <i32> [#uses=1] + br label %bb35 + +bb35: ; preds = %bb34, %bb21 + %indvar504 = phi i32 [ %indvar.next505, %bb34 ], [ 0, %bb21 ] ; <i32> [#uses=2] + %pa.1 = phi i8* [ null, %bb34 ], [ %0, %bb21 ] ; <i8*> [#uses=2] + %pb.0.rec = mul i32 %indvar504, %es ; <i32> [#uses=1] + br i1 false, label %bb43, label %bb29 + +bb43: ; preds = %bb43, %bb35 + br i1 false, label %bb50, label %bb43 + +bb50: ; preds = %bb43 + %1 = ptrtoint i8* %pa.1 to i32 ; <i32> [#uses=1] + %2 = sub i32 %1, 0 ; <i32> [#uses=2] + %3 = icmp sle i32 0, %2 ; <i1> [#uses=1] + %min = select i1 %3, i32 0, i32 %2 ; <i32> [#uses=1] + br label %bb7.i161 + +bb7.i161: ; preds = %bb7.i161, %bb50 + %pj.0.rec.i156 = phi i32 [ %indvar.next394, %bb7.i161 ], [ 0, %bb50 ] ; <i32> [#uses=2] + %.sum279 = sub i32 %pj.0.rec.i156, %min ; <i32> [#uses=1] + %pb.0.sum542 = add i32 %pb.0.rec, %.sum279 ; <i32> [#uses=1] + %pj.0.i158 = getelementptr i8* %0, i32 %pb.0.sum542 ; <i8*> [#uses=0] + %indvar.next394 = add i32 %pj.0.rec.i156, 1 ; <i32> [#uses=1] + br label %bb7.i161 +} diff --git a/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll b/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll new file mode 100644 index 000000000000..4ea43ec505e3 --- /dev/null +++ b/test/CodeGen/PowerPC/2009-05-28-LegalizeBRCC.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin10 +; PR4280 + +define i32 @__fixunssfsi(float %a) nounwind readnone { +entry: + %0 = fcmp ult float %a, 0x41E0000000000000 ; <i1> [#uses=1] + br i1 %0, label %bb1, label %bb + +bb: ; preds = %entry + ret i32 1 + +bb1: ; preds = %entry + ret i32 0 +} + diff --git a/test/CodeGen/PowerPC/Atomics-32.ll b/test/CodeGen/PowerPC/Atomics-32.ll new file mode 100644 index 000000000000..f3246fda15cb --- /dev/null +++ b/test/CodeGen/PowerPC/Atomics-32.ll @@ -0,0 +1,749 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; ModuleID = 'Atomics.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin9" +@sc = common global i8 0 ; <i8*> [#uses=52] +@uc = common global i8 0 ; <i8*> [#uses=100] +@ss = common global i16 0 ; <i16*> [#uses=15] +@us = common global i16 0 ; <i16*> [#uses=15] +@si = common global i32 0 ; <i32*> [#uses=15] +@ui = common global i32 0 ; <i32*> [#uses=23] +@sl = common global i32 0 ; <i32*> [#uses=15] +@ul = common global i32 0 ; <i32*> [#uses=15] +@sll = common global i64 0, align 8 ; <i64*> [#uses=1] +@ull = common global i64 0, align 8 ; <i64*> [#uses=1] + +define void @test_op_ignore() nounwind { +entry: + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=0] + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=0] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:10 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %10, i32 1 ) ; <i32>:11 [#uses=0] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:12 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %12, i32 1 ) ; <i32>:13 [#uses=0] + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:14 [#uses=0] + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:15 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 1 ) ; <i16>:17 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 1 ) ; <i16>:19 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 1 ) ; <i32>:21 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:22 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 1 ) ; <i32>:23 [#uses=0] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:24 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 1 ) ; <i32>:25 [#uses=0] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:26 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 1 ) ; <i32>:27 [#uses=0] + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:28 [#uses=0] + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:29 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:30 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 1 ) ; <i16>:31 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:32 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 1 ) ; <i16>:33 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:34 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 1 ) ; <i32>:35 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:36 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 1 ) ; <i32>:37 [#uses=0] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:38 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %38, i32 1 ) ; <i32>:39 [#uses=0] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:40 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %40, i32 1 ) ; <i32>:41 [#uses=0] + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:42 [#uses=0] + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:43 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 1 ) ; <i16>:45 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:46 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 1 ) ; <i16>:47 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:48 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 1 ) ; <i32>:49 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:50 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 1 ) ; <i32>:51 [#uses=0] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:52 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %52, i32 1 ) ; <i32>:53 [#uses=0] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:54 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %54, i32 1 ) ; <i32>:55 [#uses=0] + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:56 [#uses=0] + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:57 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 1 ) ; <i16>:59 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 1 ) ; <i16>:61 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:62 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 1 ) ; <i32>:63 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:64 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 1 ) ; <i32>:65 [#uses=0] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:66 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %66, i32 1 ) ; <i32>:67 [#uses=0] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:68 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %68, i32 1 ) ; <i32>:69 [#uses=0] + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:70 [#uses=0] + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:71 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:72 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 1 ) ; <i16>:73 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:74 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 1 ) ; <i16>:75 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 1 ) ; <i32>:77 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:78 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 1 ) ; <i32>:79 [#uses=0] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:80 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %80, i32 1 ) ; <i32>:81 [#uses=0] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:82 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %82, i32 1 ) ; <i32>:83 [#uses=0] + br label %return + +return: ; preds = %entry + ret void +} + +declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind + +declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind + +declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind + +declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind + +declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind + +declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind + +define void @test_fetch_and_op() nounwind { +entry: + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:0 [#uses=1] + store i8 %0, i8* @sc, align 1 + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:1 [#uses=1] + store i8 %1, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 11 ) ; <i16>:3 [#uses=1] + store i16 %3, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 11 ) ; <i16>:5 [#uses=1] + store i16 %5, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 11 ) ; <i32>:7 [#uses=1] + store i32 %7, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 11 ) ; <i32>:9 [#uses=1] + store i32 %9, i32* @ui, align 4 + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:10 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %10, i32 11 ) ; <i32>:11 [#uses=1] + store i32 %11, i32* @sl, align 4 + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:12 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %12, i32 11 ) ; <i32>:13 [#uses=1] + store i32 %13, i32* @ul, align 4 + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:14 [#uses=1] + store i8 %14, i8* @sc, align 1 + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:15 [#uses=1] + store i8 %15, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 11 ) ; <i16>:17 [#uses=1] + store i16 %17, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 11 ) ; <i16>:19 [#uses=1] + store i16 %19, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 11 ) ; <i32>:21 [#uses=1] + store i32 %21, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:22 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 11 ) ; <i32>:23 [#uses=1] + store i32 %23, i32* @ui, align 4 + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:24 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %24, i32 11 ) ; <i32>:25 [#uses=1] + store i32 %25, i32* @sl, align 4 + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:26 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %26, i32 11 ) ; <i32>:27 [#uses=1] + store i32 %27, i32* @ul, align 4 + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:28 [#uses=1] + store i8 %28, i8* @sc, align 1 + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:29 [#uses=1] + store i8 %29, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:30 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 11 ) ; <i16>:31 [#uses=1] + store i16 %31, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:32 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 11 ) ; <i16>:33 [#uses=1] + store i16 %33, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:34 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 11 ) ; <i32>:35 [#uses=1] + store i32 %35, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:36 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 11 ) ; <i32>:37 [#uses=1] + store i32 %37, i32* @ui, align 4 + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:38 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %38, i32 11 ) ; <i32>:39 [#uses=1] + store i32 %39, i32* @sl, align 4 + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:40 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %40, i32 11 ) ; <i32>:41 [#uses=1] + store i32 %41, i32* @ul, align 4 + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:42 [#uses=1] + store i8 %42, i8* @sc, align 1 + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:43 [#uses=1] + store i8 %43, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 11 ) ; <i16>:45 [#uses=1] + store i16 %45, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:46 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 11 ) ; <i16>:47 [#uses=1] + store i16 %47, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:48 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 11 ) ; <i32>:49 [#uses=1] + store i32 %49, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:50 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 11 ) ; <i32>:51 [#uses=1] + store i32 %51, i32* @ui, align 4 + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:52 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %52, i32 11 ) ; <i32>:53 [#uses=1] + store i32 %53, i32* @sl, align 4 + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:54 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %54, i32 11 ) ; <i32>:55 [#uses=1] + store i32 %55, i32* @ul, align 4 + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:56 [#uses=1] + store i8 %56, i8* @sc, align 1 + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:57 [#uses=1] + store i8 %57, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 11 ) ; <i16>:59 [#uses=1] + store i16 %59, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 11 ) ; <i16>:61 [#uses=1] + store i16 %61, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:62 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 11 ) ; <i32>:63 [#uses=1] + store i32 %63, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:64 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 11 ) ; <i32>:65 [#uses=1] + store i32 %65, i32* @ui, align 4 + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:66 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %66, i32 11 ) ; <i32>:67 [#uses=1] + store i32 %67, i32* @sl, align 4 + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:68 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %68, i32 11 ) ; <i32>:69 [#uses=1] + store i32 %69, i32* @ul, align 4 + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:70 [#uses=1] + store i8 %70, i8* @sc, align 1 + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:71 [#uses=1] + store i8 %71, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:72 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 11 ) ; <i16>:73 [#uses=1] + store i16 %73, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:74 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 11 ) ; <i16>:75 [#uses=1] + store i16 %75, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 11 ) ; <i32>:77 [#uses=1] + store i32 %77, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:78 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 11 ) ; <i32>:79 [#uses=1] + store i32 %79, i32* @ui, align 4 + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:80 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %80, i32 11 ) ; <i32>:81 [#uses=1] + store i32 %81, i32* @sl, align 4 + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:82 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %82, i32 11 ) ; <i32>:83 [#uses=1] + store i32 %83, i32* @ul, align 4 + br label %return + +return: ; preds = %entry + ret void +} + +define void @test_op_and_fetch() nounwind { +entry: + load i8* @uc, align 1 ; <i8>:0 [#uses=2] + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 %0 ) ; <i8>:1 [#uses=1] + add i8 %1, %0 ; <i8>:2 [#uses=1] + store i8 %2, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:3 [#uses=2] + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 %3 ) ; <i8>:4 [#uses=1] + add i8 %4, %3 ; <i8>:5 [#uses=1] + store i8 %5, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:6 [#uses=1] + zext i8 %6 to i16 ; <i16>:7 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:8 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %8, i16 %7 ) ; <i16>:9 [#uses=1] + add i16 %9, %7 ; <i16>:10 [#uses=1] + store i16 %10, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:11 [#uses=1] + zext i8 %11 to i16 ; <i16>:12 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:13 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %13, i16 %12 ) ; <i16>:14 [#uses=1] + add i16 %14, %12 ; <i16>:15 [#uses=1] + store i16 %15, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:16 [#uses=1] + zext i8 %16 to i32 ; <i32>:17 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:18 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %18, i32 %17 ) ; <i32>:19 [#uses=1] + add i32 %19, %17 ; <i32>:20 [#uses=1] + store i32 %20, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:21 [#uses=1] + zext i8 %21 to i32 ; <i32>:22 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:23 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %23, i32 %22 ) ; <i32>:24 [#uses=1] + add i32 %24, %22 ; <i32>:25 [#uses=1] + store i32 %25, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:26 [#uses=1] + zext i8 %26 to i32 ; <i32>:27 [#uses=2] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:28 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %28, i32 %27 ) ; <i32>:29 [#uses=1] + add i32 %29, %27 ; <i32>:30 [#uses=1] + store i32 %30, i32* @sl, align 4 + load i8* @uc, align 1 ; <i8>:31 [#uses=1] + zext i8 %31 to i32 ; <i32>:32 [#uses=2] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:33 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %33, i32 %32 ) ; <i32>:34 [#uses=1] + add i32 %34, %32 ; <i32>:35 [#uses=1] + store i32 %35, i32* @ul, align 4 + load i8* @uc, align 1 ; <i8>:36 [#uses=2] + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 %36 ) ; <i8>:37 [#uses=1] + sub i8 %37, %36 ; <i8>:38 [#uses=1] + store i8 %38, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:39 [#uses=2] + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 %39 ) ; <i8>:40 [#uses=1] + sub i8 %40, %39 ; <i8>:41 [#uses=1] + store i8 %41, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:42 [#uses=1] + zext i8 %42 to i16 ; <i16>:43 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %44, i16 %43 ) ; <i16>:45 [#uses=1] + sub i16 %45, %43 ; <i16>:46 [#uses=1] + store i16 %46, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:47 [#uses=1] + zext i8 %47 to i16 ; <i16>:48 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:49 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %49, i16 %48 ) ; <i16>:50 [#uses=1] + sub i16 %50, %48 ; <i16>:51 [#uses=1] + store i16 %51, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:52 [#uses=1] + zext i8 %52 to i32 ; <i32>:53 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:54 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %54, i32 %53 ) ; <i32>:55 [#uses=1] + sub i32 %55, %53 ; <i32>:56 [#uses=1] + store i32 %56, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:57 [#uses=1] + zext i8 %57 to i32 ; <i32>:58 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:59 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %59, i32 %58 ) ; <i32>:60 [#uses=1] + sub i32 %60, %58 ; <i32>:61 [#uses=1] + store i32 %61, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:62 [#uses=1] + zext i8 %62 to i32 ; <i32>:63 [#uses=2] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:64 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %64, i32 %63 ) ; <i32>:65 [#uses=1] + sub i32 %65, %63 ; <i32>:66 [#uses=1] + store i32 %66, i32* @sl, align 4 + load i8* @uc, align 1 ; <i8>:67 [#uses=1] + zext i8 %67 to i32 ; <i32>:68 [#uses=2] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:69 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %69, i32 %68 ) ; <i32>:70 [#uses=1] + sub i32 %70, %68 ; <i32>:71 [#uses=1] + store i32 %71, i32* @ul, align 4 + load i8* @uc, align 1 ; <i8>:72 [#uses=2] + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 %72 ) ; <i8>:73 [#uses=1] + or i8 %73, %72 ; <i8>:74 [#uses=1] + store i8 %74, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:75 [#uses=2] + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 %75 ) ; <i8>:76 [#uses=1] + or i8 %76, %75 ; <i8>:77 [#uses=1] + store i8 %77, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:78 [#uses=1] + zext i8 %78 to i16 ; <i16>:79 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:80 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %80, i16 %79 ) ; <i16>:81 [#uses=1] + or i16 %81, %79 ; <i16>:82 [#uses=1] + store i16 %82, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:83 [#uses=1] + zext i8 %83 to i16 ; <i16>:84 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:85 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %85, i16 %84 ) ; <i16>:86 [#uses=1] + or i16 %86, %84 ; <i16>:87 [#uses=1] + store i16 %87, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:88 [#uses=1] + zext i8 %88 to i32 ; <i32>:89 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:90 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %90, i32 %89 ) ; <i32>:91 [#uses=1] + or i32 %91, %89 ; <i32>:92 [#uses=1] + store i32 %92, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:93 [#uses=1] + zext i8 %93 to i32 ; <i32>:94 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:95 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %95, i32 %94 ) ; <i32>:96 [#uses=1] + or i32 %96, %94 ; <i32>:97 [#uses=1] + store i32 %97, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:98 [#uses=1] + zext i8 %98 to i32 ; <i32>:99 [#uses=2] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:100 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %100, i32 %99 ) ; <i32>:101 [#uses=1] + or i32 %101, %99 ; <i32>:102 [#uses=1] + store i32 %102, i32* @sl, align 4 + load i8* @uc, align 1 ; <i8>:103 [#uses=1] + zext i8 %103 to i32 ; <i32>:104 [#uses=2] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:105 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %105, i32 %104 ) ; <i32>:106 [#uses=1] + or i32 %106, %104 ; <i32>:107 [#uses=1] + store i32 %107, i32* @ul, align 4 + load i8* @uc, align 1 ; <i8>:108 [#uses=2] + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 %108 ) ; <i8>:109 [#uses=1] + xor i8 %109, %108 ; <i8>:110 [#uses=1] + store i8 %110, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:111 [#uses=2] + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 %111 ) ; <i8>:112 [#uses=1] + xor i8 %112, %111 ; <i8>:113 [#uses=1] + store i8 %113, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:114 [#uses=1] + zext i8 %114 to i16 ; <i16>:115 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:116 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %116, i16 %115 ) ; <i16>:117 [#uses=1] + xor i16 %117, %115 ; <i16>:118 [#uses=1] + store i16 %118, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:119 [#uses=1] + zext i8 %119 to i16 ; <i16>:120 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:121 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %121, i16 %120 ) ; <i16>:122 [#uses=1] + xor i16 %122, %120 ; <i16>:123 [#uses=1] + store i16 %123, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:124 [#uses=1] + zext i8 %124 to i32 ; <i32>:125 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:126 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %126, i32 %125 ) ; <i32>:127 [#uses=1] + xor i32 %127, %125 ; <i32>:128 [#uses=1] + store i32 %128, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:129 [#uses=1] + zext i8 %129 to i32 ; <i32>:130 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:131 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %131, i32 %130 ) ; <i32>:132 [#uses=1] + xor i32 %132, %130 ; <i32>:133 [#uses=1] + store i32 %133, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:134 [#uses=1] + zext i8 %134 to i32 ; <i32>:135 [#uses=2] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:136 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %136, i32 %135 ) ; <i32>:137 [#uses=1] + xor i32 %137, %135 ; <i32>:138 [#uses=1] + store i32 %138, i32* @sl, align 4 + load i8* @uc, align 1 ; <i8>:139 [#uses=1] + zext i8 %139 to i32 ; <i32>:140 [#uses=2] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:141 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %141, i32 %140 ) ; <i32>:142 [#uses=1] + xor i32 %142, %140 ; <i32>:143 [#uses=1] + store i32 %143, i32* @ul, align 4 + load i8* @uc, align 1 ; <i8>:144 [#uses=2] + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 %144 ) ; <i8>:145 [#uses=1] + and i8 %145, %144 ; <i8>:146 [#uses=1] + store i8 %146, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:147 [#uses=2] + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 %147 ) ; <i8>:148 [#uses=1] + and i8 %148, %147 ; <i8>:149 [#uses=1] + store i8 %149, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:150 [#uses=1] + zext i8 %150 to i16 ; <i16>:151 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:152 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %152, i16 %151 ) ; <i16>:153 [#uses=1] + and i16 %153, %151 ; <i16>:154 [#uses=1] + store i16 %154, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:155 [#uses=1] + zext i8 %155 to i16 ; <i16>:156 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:157 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %157, i16 %156 ) ; <i16>:158 [#uses=1] + and i16 %158, %156 ; <i16>:159 [#uses=1] + store i16 %159, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:160 [#uses=1] + zext i8 %160 to i32 ; <i32>:161 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:162 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %162, i32 %161 ) ; <i32>:163 [#uses=1] + and i32 %163, %161 ; <i32>:164 [#uses=1] + store i32 %164, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:165 [#uses=1] + zext i8 %165 to i32 ; <i32>:166 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:167 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %167, i32 %166 ) ; <i32>:168 [#uses=1] + and i32 %168, %166 ; <i32>:169 [#uses=1] + store i32 %169, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:170 [#uses=1] + zext i8 %170 to i32 ; <i32>:171 [#uses=2] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:172 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %172, i32 %171 ) ; <i32>:173 [#uses=1] + and i32 %173, %171 ; <i32>:174 [#uses=1] + store i32 %174, i32* @sl, align 4 + load i8* @uc, align 1 ; <i8>:175 [#uses=1] + zext i8 %175 to i32 ; <i32>:176 [#uses=2] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:177 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %177, i32 %176 ) ; <i32>:178 [#uses=1] + and i32 %178, %176 ; <i32>:179 [#uses=1] + store i32 %179, i32* @ul, align 4 + load i8* @uc, align 1 ; <i8>:180 [#uses=2] + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 %180 ) ; <i8>:181 [#uses=1] + xor i8 %181, -1 ; <i8>:182 [#uses=1] + and i8 %182, %180 ; <i8>:183 [#uses=1] + store i8 %183, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:184 [#uses=2] + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 %184 ) ; <i8>:185 [#uses=1] + xor i8 %185, -1 ; <i8>:186 [#uses=1] + and i8 %186, %184 ; <i8>:187 [#uses=1] + store i8 %187, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:188 [#uses=1] + zext i8 %188 to i16 ; <i16>:189 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:190 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %190, i16 %189 ) ; <i16>:191 [#uses=1] + xor i16 %191, -1 ; <i16>:192 [#uses=1] + and i16 %192, %189 ; <i16>:193 [#uses=1] + store i16 %193, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:194 [#uses=1] + zext i8 %194 to i16 ; <i16>:195 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:196 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %196, i16 %195 ) ; <i16>:197 [#uses=1] + xor i16 %197, -1 ; <i16>:198 [#uses=1] + and i16 %198, %195 ; <i16>:199 [#uses=1] + store i16 %199, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:200 [#uses=1] + zext i8 %200 to i32 ; <i32>:201 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:202 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %202, i32 %201 ) ; <i32>:203 [#uses=1] + xor i32 %203, -1 ; <i32>:204 [#uses=1] + and i32 %204, %201 ; <i32>:205 [#uses=1] + store i32 %205, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:206 [#uses=1] + zext i8 %206 to i32 ; <i32>:207 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:208 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %208, i32 %207 ) ; <i32>:209 [#uses=1] + xor i32 %209, -1 ; <i32>:210 [#uses=1] + and i32 %210, %207 ; <i32>:211 [#uses=1] + store i32 %211, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:212 [#uses=1] + zext i8 %212 to i32 ; <i32>:213 [#uses=2] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:214 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %214, i32 %213 ) ; <i32>:215 [#uses=1] + xor i32 %215, -1 ; <i32>:216 [#uses=1] + and i32 %216, %213 ; <i32>:217 [#uses=1] + store i32 %217, i32* @sl, align 4 + load i8* @uc, align 1 ; <i8>:218 [#uses=1] + zext i8 %218 to i32 ; <i32>:219 [#uses=2] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:220 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %220, i32 %219 ) ; <i32>:221 [#uses=1] + xor i32 %221, -1 ; <i32>:222 [#uses=1] + and i32 %222, %219 ; <i32>:223 [#uses=1] + store i32 %223, i32* @ul, align 4 + br label %return + +return: ; preds = %entry + ret void +} + +define void @test_compare_and_swap() nounwind { +entry: + load i8* @uc, align 1 ; <i8>:0 [#uses=1] + load i8* @sc, align 1 ; <i8>:1 [#uses=1] + call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %0, i8 %1 ) ; <i8>:2 [#uses=1] + store i8 %2, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:3 [#uses=1] + load i8* @sc, align 1 ; <i8>:4 [#uses=1] + call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %3, i8 %4 ) ; <i8>:5 [#uses=1] + store i8 %5, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:6 [#uses=1] + zext i8 %6 to i16 ; <i16>:7 [#uses=1] + load i8* @sc, align 1 ; <i8>:8 [#uses=1] + sext i8 %8 to i16 ; <i16>:9 [#uses=1] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:10 [#uses=1] + call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %10, i16 %7, i16 %9 ) ; <i16>:11 [#uses=1] + store i16 %11, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:12 [#uses=1] + zext i8 %12 to i16 ; <i16>:13 [#uses=1] + load i8* @sc, align 1 ; <i8>:14 [#uses=1] + sext i8 %14 to i16 ; <i16>:15 [#uses=1] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:16 [#uses=1] + call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %16, i16 %13, i16 %15 ) ; <i16>:17 [#uses=1] + store i16 %17, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:18 [#uses=1] + zext i8 %18 to i32 ; <i32>:19 [#uses=1] + load i8* @sc, align 1 ; <i8>:20 [#uses=1] + sext i8 %20 to i32 ; <i32>:21 [#uses=1] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:22 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %22, i32 %19, i32 %21 ) ; <i32>:23 [#uses=1] + store i32 %23, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:24 [#uses=1] + zext i8 %24 to i32 ; <i32>:25 [#uses=1] + load i8* @sc, align 1 ; <i8>:26 [#uses=1] + sext i8 %26 to i32 ; <i32>:27 [#uses=1] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:28 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %28, i32 %25, i32 %27 ) ; <i32>:29 [#uses=1] + store i32 %29, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:30 [#uses=1] + zext i8 %30 to i32 ; <i32>:31 [#uses=1] + load i8* @sc, align 1 ; <i8>:32 [#uses=1] + sext i8 %32 to i32 ; <i32>:33 [#uses=1] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:34 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %34, i32 %31, i32 %33 ) ; <i32>:35 [#uses=1] + store i32 %35, i32* @sl, align 4 + load i8* @uc, align 1 ; <i8>:36 [#uses=1] + zext i8 %36 to i32 ; <i32>:37 [#uses=1] + load i8* @sc, align 1 ; <i8>:38 [#uses=1] + sext i8 %38 to i32 ; <i32>:39 [#uses=1] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:40 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %40, i32 %37, i32 %39 ) ; <i32>:41 [#uses=1] + store i32 %41, i32* @ul, align 4 + load i8* @uc, align 1 ; <i8>:42 [#uses=2] + load i8* @sc, align 1 ; <i8>:43 [#uses=1] + call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %42, i8 %43 ) ; <i8>:44 [#uses=1] + icmp eq i8 %44, %42 ; <i1>:45 [#uses=1] + zext i1 %45 to i32 ; <i32>:46 [#uses=1] + store i32 %46, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:47 [#uses=2] + load i8* @sc, align 1 ; <i8>:48 [#uses=1] + call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %47, i8 %48 ) ; <i8>:49 [#uses=1] + icmp eq i8 %49, %47 ; <i1>:50 [#uses=1] + zext i1 %50 to i32 ; <i32>:51 [#uses=1] + store i32 %51, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:52 [#uses=1] + zext i8 %52 to i16 ; <i16>:53 [#uses=2] + load i8* @sc, align 1 ; <i8>:54 [#uses=1] + sext i8 %54 to i16 ; <i16>:55 [#uses=1] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:56 [#uses=1] + call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %56, i16 %53, i16 %55 ) ; <i16>:57 [#uses=1] + icmp eq i16 %57, %53 ; <i1>:58 [#uses=1] + zext i1 %58 to i32 ; <i32>:59 [#uses=1] + store i32 %59, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:60 [#uses=1] + zext i8 %60 to i16 ; <i16>:61 [#uses=2] + load i8* @sc, align 1 ; <i8>:62 [#uses=1] + sext i8 %62 to i16 ; <i16>:63 [#uses=1] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:64 [#uses=1] + call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %64, i16 %61, i16 %63 ) ; <i16>:65 [#uses=1] + icmp eq i16 %65, %61 ; <i1>:66 [#uses=1] + zext i1 %66 to i32 ; <i32>:67 [#uses=1] + store i32 %67, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:68 [#uses=1] + zext i8 %68 to i32 ; <i32>:69 [#uses=2] + load i8* @sc, align 1 ; <i8>:70 [#uses=1] + sext i8 %70 to i32 ; <i32>:71 [#uses=1] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:72 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %72, i32 %69, i32 %71 ) ; <i32>:73 [#uses=1] + icmp eq i32 %73, %69 ; <i1>:74 [#uses=1] + zext i1 %74 to i32 ; <i32>:75 [#uses=1] + store i32 %75, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:76 [#uses=1] + zext i8 %76 to i32 ; <i32>:77 [#uses=2] + load i8* @sc, align 1 ; <i8>:78 [#uses=1] + sext i8 %78 to i32 ; <i32>:79 [#uses=1] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:80 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %80, i32 %77, i32 %79 ) ; <i32>:81 [#uses=1] + icmp eq i32 %81, %77 ; <i1>:82 [#uses=1] + zext i1 %82 to i32 ; <i32>:83 [#uses=1] + store i32 %83, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:84 [#uses=1] + zext i8 %84 to i32 ; <i32>:85 [#uses=2] + load i8* @sc, align 1 ; <i8>:86 [#uses=1] + sext i8 %86 to i32 ; <i32>:87 [#uses=1] + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:88 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %88, i32 %85, i32 %87 ) ; <i32>:89 [#uses=1] + icmp eq i32 %89, %85 ; <i1>:90 [#uses=1] + zext i1 %90 to i32 ; <i32>:91 [#uses=1] + store i32 %91, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:92 [#uses=1] + zext i8 %92 to i32 ; <i32>:93 [#uses=2] + load i8* @sc, align 1 ; <i8>:94 [#uses=1] + sext i8 %94 to i32 ; <i32>:95 [#uses=1] + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:96 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %96, i32 %93, i32 %95 ) ; <i32>:97 [#uses=1] + icmp eq i32 %97, %93 ; <i1>:98 [#uses=1] + zext i1 %98 to i32 ; <i32>:99 [#uses=1] + store i32 %99, i32* @ui, align 4 + br label %return + +return: ; preds = %entry + ret void +} + +declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind + +declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind + +declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind + +define void @test_lock() nounwind { +entry: + call i8 @llvm.atomic.swap.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=1] + store i8 %0, i8* @sc, align 1 + call i8 @llvm.atomic.swap.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=1] + store i8 %1, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1] + call i16 @llvm.atomic.swap.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=1] + store i16 %3, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1] + call i16 @llvm.atomic.swap.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=1] + store i16 %5, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1] + call i32 @llvm.atomic.swap.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=1] + store i32 %7, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1] + call i32 @llvm.atomic.swap.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=1] + store i32 %9, i32* @ui, align 4 + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:10 [#uses=1] + call i32 @llvm.atomic.swap.i32.p0i32( i32* %10, i32 1 ) ; <i32>:11 [#uses=1] + store i32 %11, i32* @sl, align 4 + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:12 [#uses=1] + call i32 @llvm.atomic.swap.i32.p0i32( i32* %12, i32 1 ) ; <i32>:13 [#uses=1] + store i32 %13, i32* @ul, align 4 + call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true, i1 false ) + volatile store i8 0, i8* @sc, align 1 + volatile store i8 0, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:14 [#uses=1] + volatile store i16 0, i16* %14, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:15 [#uses=1] + volatile store i16 0, i16* %15, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:16 [#uses=1] + volatile store i32 0, i32* %16, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:17 [#uses=1] + volatile store i32 0, i32* %17, align 4 + bitcast i8* bitcast (i32* @sl to i8*) to i32* ; <i32*>:18 [#uses=1] + volatile store i32 0, i32* %18, align 4 + bitcast i8* bitcast (i32* @ul to i8*) to i32* ; <i32*>:19 [#uses=1] + volatile store i32 0, i32* %19, align 4 + bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:20 [#uses=1] + volatile store i64 0, i64* %20, align 8 + bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:21 [#uses=1] + volatile store i64 0, i64* %21, align 8 + br label %return + +return: ; preds = %entry + ret void +} + +declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind + +declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind diff --git a/test/CodeGen/PowerPC/Atomics-64.ll b/test/CodeGen/PowerPC/Atomics-64.ll new file mode 100644 index 000000000000..c3de7102b038 --- /dev/null +++ b/test/CodeGen/PowerPC/Atomics-64.ll @@ -0,0 +1,773 @@ +; RUN: llvm-as < %s | llc -march=ppc64 +; ModuleID = 'Atomics.c' +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc64-apple-darwin9" +@sc = common global i8 0 ; <i8*> [#uses=52] +@uc = common global i8 0 ; <i8*> [#uses=100] +@ss = common global i16 0 ; <i16*> [#uses=15] +@us = common global i16 0 ; <i16*> [#uses=15] +@si = common global i32 0 ; <i32*> [#uses=15] +@ui = common global i32 0 ; <i32*> [#uses=23] +@sl = common global i64 0, align 8 ; <i64*> [#uses=15] +@ul = common global i64 0, align 8 ; <i64*> [#uses=15] +@sll = common global i64 0, align 8 ; <i64*> [#uses=1] +@ull = common global i64 0, align 8 ; <i64*> [#uses=1] + +define void @test_op_ignore() nounwind { +entry: + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=0] + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=0] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:10 [#uses=1] + call i64 @llvm.atomic.load.add.i64.p0i64( i64* %10, i64 1 ) ; <i64>:11 [#uses=0] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:12 [#uses=1] + call i64 @llvm.atomic.load.add.i64.p0i64( i64* %12, i64 1 ) ; <i64>:13 [#uses=0] + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:14 [#uses=0] + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:15 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 1 ) ; <i16>:17 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 1 ) ; <i16>:19 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 1 ) ; <i32>:21 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:22 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 1 ) ; <i32>:23 [#uses=0] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:24 [#uses=1] + call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %24, i64 1 ) ; <i64>:25 [#uses=0] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:26 [#uses=1] + call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %26, i64 1 ) ; <i64>:27 [#uses=0] + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:28 [#uses=0] + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:29 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:30 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 1 ) ; <i16>:31 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:32 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 1 ) ; <i16>:33 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:34 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 1 ) ; <i32>:35 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:36 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 1 ) ; <i32>:37 [#uses=0] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:38 [#uses=1] + call i64 @llvm.atomic.load.or.i64.p0i64( i64* %38, i64 1 ) ; <i64>:39 [#uses=0] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:40 [#uses=1] + call i64 @llvm.atomic.load.or.i64.p0i64( i64* %40, i64 1 ) ; <i64>:41 [#uses=0] + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:42 [#uses=0] + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:43 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 1 ) ; <i16>:45 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:46 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 1 ) ; <i16>:47 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:48 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 1 ) ; <i32>:49 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:50 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 1 ) ; <i32>:51 [#uses=0] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:52 [#uses=1] + call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %52, i64 1 ) ; <i64>:53 [#uses=0] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:54 [#uses=1] + call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %54, i64 1 ) ; <i64>:55 [#uses=0] + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:56 [#uses=0] + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:57 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 1 ) ; <i16>:59 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 1 ) ; <i16>:61 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:62 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 1 ) ; <i32>:63 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:64 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 1 ) ; <i32>:65 [#uses=0] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:66 [#uses=1] + call i64 @llvm.atomic.load.and.i64.p0i64( i64* %66, i64 1 ) ; <i64>:67 [#uses=0] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:68 [#uses=1] + call i64 @llvm.atomic.load.and.i64.p0i64( i64* %68, i64 1 ) ; <i64>:69 [#uses=0] + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:70 [#uses=0] + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:71 [#uses=0] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:72 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 1 ) ; <i16>:73 [#uses=0] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:74 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 1 ) ; <i16>:75 [#uses=0] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 1 ) ; <i32>:77 [#uses=0] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:78 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 1 ) ; <i32>:79 [#uses=0] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:80 [#uses=1] + call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %80, i64 1 ) ; <i64>:81 [#uses=0] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:82 [#uses=1] + call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %82, i64 1 ) ; <i64>:83 [#uses=0] + br label %return + +return: ; preds = %entry + ret void +} + +declare i8 @llvm.atomic.load.add.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.add.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind + +declare i64 @llvm.atomic.load.add.i64.p0i64(i64*, i64) nounwind + +declare i8 @llvm.atomic.load.sub.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.sub.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind + +declare i64 @llvm.atomic.load.sub.i64.p0i64(i64*, i64) nounwind + +declare i8 @llvm.atomic.load.or.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.or.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind + +declare i64 @llvm.atomic.load.or.i64.p0i64(i64*, i64) nounwind + +declare i8 @llvm.atomic.load.xor.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.xor.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind + +declare i64 @llvm.atomic.load.xor.i64.p0i64(i64*, i64) nounwind + +declare i8 @llvm.atomic.load.and.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.and.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind + +declare i64 @llvm.atomic.load.and.i64.p0i64(i64*, i64) nounwind + +declare i8 @llvm.atomic.load.nand.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.load.nand.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.load.nand.i32.p0i32(i32*, i32) nounwind + +declare i64 @llvm.atomic.load.nand.i64.p0i64(i64*, i64) nounwind + +define void @test_fetch_and_op() nounwind { +entry: + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:0 [#uses=1] + store i8 %0, i8* @sc, align 1 + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:1 [#uses=1] + store i8 %1, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %2, i16 11 ) ; <i16>:3 [#uses=1] + store i16 %3, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %4, i16 11 ) ; <i16>:5 [#uses=1] + store i16 %5, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %6, i32 11 ) ; <i32>:7 [#uses=1] + store i32 %7, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %8, i32 11 ) ; <i32>:9 [#uses=1] + store i32 %9, i32* @ui, align 4 + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:10 [#uses=1] + call i64 @llvm.atomic.load.add.i64.p0i64( i64* %10, i64 11 ) ; <i64>:11 [#uses=1] + store i64 %11, i64* @sl, align 8 + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:12 [#uses=1] + call i64 @llvm.atomic.load.add.i64.p0i64( i64* %12, i64 11 ) ; <i64>:13 [#uses=1] + store i64 %13, i64* @ul, align 8 + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:14 [#uses=1] + store i8 %14, i8* @sc, align 1 + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:15 [#uses=1] + store i8 %15, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:16 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %16, i16 11 ) ; <i16>:17 [#uses=1] + store i16 %17, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:18 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %18, i16 11 ) ; <i16>:19 [#uses=1] + store i16 %19, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:20 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %20, i32 11 ) ; <i32>:21 [#uses=1] + store i32 %21, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:22 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %22, i32 11 ) ; <i32>:23 [#uses=1] + store i32 %23, i32* @ui, align 4 + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:24 [#uses=1] + call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %24, i64 11 ) ; <i64>:25 [#uses=1] + store i64 %25, i64* @sl, align 8 + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:26 [#uses=1] + call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %26, i64 11 ) ; <i64>:27 [#uses=1] + store i64 %27, i64* @ul, align 8 + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:28 [#uses=1] + store i8 %28, i8* @sc, align 1 + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:29 [#uses=1] + store i8 %29, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:30 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %30, i16 11 ) ; <i16>:31 [#uses=1] + store i16 %31, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:32 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %32, i16 11 ) ; <i16>:33 [#uses=1] + store i16 %33, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:34 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %34, i32 11 ) ; <i32>:35 [#uses=1] + store i32 %35, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:36 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %36, i32 11 ) ; <i32>:37 [#uses=1] + store i32 %37, i32* @ui, align 4 + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:38 [#uses=1] + call i64 @llvm.atomic.load.or.i64.p0i64( i64* %38, i64 11 ) ; <i64>:39 [#uses=1] + store i64 %39, i64* @sl, align 8 + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:40 [#uses=1] + call i64 @llvm.atomic.load.or.i64.p0i64( i64* %40, i64 11 ) ; <i64>:41 [#uses=1] + store i64 %41, i64* @ul, align 8 + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:42 [#uses=1] + store i8 %42, i8* @sc, align 1 + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:43 [#uses=1] + store i8 %43, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %44, i16 11 ) ; <i16>:45 [#uses=1] + store i16 %45, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:46 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %46, i16 11 ) ; <i16>:47 [#uses=1] + store i16 %47, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:48 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %48, i32 11 ) ; <i32>:49 [#uses=1] + store i32 %49, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:50 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %50, i32 11 ) ; <i32>:51 [#uses=1] + store i32 %51, i32* @ui, align 4 + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:52 [#uses=1] + call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %52, i64 11 ) ; <i64>:53 [#uses=1] + store i64 %53, i64* @sl, align 8 + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:54 [#uses=1] + call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %54, i64 11 ) ; <i64>:55 [#uses=1] + store i64 %55, i64* @ul, align 8 + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:56 [#uses=1] + store i8 %56, i8* @sc, align 1 + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:57 [#uses=1] + store i8 %57, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %58, i16 11 ) ; <i16>:59 [#uses=1] + store i16 %59, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:60 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %60, i16 11 ) ; <i16>:61 [#uses=1] + store i16 %61, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:62 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %62, i32 11 ) ; <i32>:63 [#uses=1] + store i32 %63, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:64 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %64, i32 11 ) ; <i32>:65 [#uses=1] + store i32 %65, i32* @ui, align 4 + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:66 [#uses=1] + call i64 @llvm.atomic.load.and.i64.p0i64( i64* %66, i64 11 ) ; <i64>:67 [#uses=1] + store i64 %67, i64* @sl, align 8 + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:68 [#uses=1] + call i64 @llvm.atomic.load.and.i64.p0i64( i64* %68, i64 11 ) ; <i64>:69 [#uses=1] + store i64 %69, i64* @ul, align 8 + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 11 ) ; <i8>:70 [#uses=1] + store i8 %70, i8* @sc, align 1 + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 11 ) ; <i8>:71 [#uses=1] + store i8 %71, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:72 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %72, i16 11 ) ; <i16>:73 [#uses=1] + store i16 %73, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:74 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %74, i16 11 ) ; <i16>:75 [#uses=1] + store i16 %75, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %76, i32 11 ) ; <i32>:77 [#uses=1] + store i32 %77, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:78 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %78, i32 11 ) ; <i32>:79 [#uses=1] + store i32 %79, i32* @ui, align 4 + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:80 [#uses=1] + call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %80, i64 11 ) ; <i64>:81 [#uses=1] + store i64 %81, i64* @sl, align 8 + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:82 [#uses=1] + call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %82, i64 11 ) ; <i64>:83 [#uses=1] + store i64 %83, i64* @ul, align 8 + br label %return + +return: ; preds = %entry + ret void +} + +define void @test_op_and_fetch() nounwind { +entry: + load i8* @uc, align 1 ; <i8>:0 [#uses=2] + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @sc, i8 %0 ) ; <i8>:1 [#uses=1] + add i8 %1, %0 ; <i8>:2 [#uses=1] + store i8 %2, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:3 [#uses=2] + call i8 @llvm.atomic.load.add.i8.p0i8( i8* @uc, i8 %3 ) ; <i8>:4 [#uses=1] + add i8 %4, %3 ; <i8>:5 [#uses=1] + store i8 %5, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:6 [#uses=1] + zext i8 %6 to i16 ; <i16>:7 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:8 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %8, i16 %7 ) ; <i16>:9 [#uses=1] + add i16 %9, %7 ; <i16>:10 [#uses=1] + store i16 %10, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:11 [#uses=1] + zext i8 %11 to i16 ; <i16>:12 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:13 [#uses=1] + call i16 @llvm.atomic.load.add.i16.p0i16( i16* %13, i16 %12 ) ; <i16>:14 [#uses=1] + add i16 %14, %12 ; <i16>:15 [#uses=1] + store i16 %15, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:16 [#uses=1] + zext i8 %16 to i32 ; <i32>:17 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:18 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %18, i32 %17 ) ; <i32>:19 [#uses=1] + add i32 %19, %17 ; <i32>:20 [#uses=1] + store i32 %20, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:21 [#uses=1] + zext i8 %21 to i32 ; <i32>:22 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:23 [#uses=1] + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %23, i32 %22 ) ; <i32>:24 [#uses=1] + add i32 %24, %22 ; <i32>:25 [#uses=1] + store i32 %25, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:26 [#uses=1] + zext i8 %26 to i64 ; <i64>:27 [#uses=2] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:28 [#uses=1] + call i64 @llvm.atomic.load.add.i64.p0i64( i64* %28, i64 %27 ) ; <i64>:29 [#uses=1] + add i64 %29, %27 ; <i64>:30 [#uses=1] + store i64 %30, i64* @sl, align 8 + load i8* @uc, align 1 ; <i8>:31 [#uses=1] + zext i8 %31 to i64 ; <i64>:32 [#uses=2] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:33 [#uses=1] + call i64 @llvm.atomic.load.add.i64.p0i64( i64* %33, i64 %32 ) ; <i64>:34 [#uses=1] + add i64 %34, %32 ; <i64>:35 [#uses=1] + store i64 %35, i64* @ul, align 8 + load i8* @uc, align 1 ; <i8>:36 [#uses=2] + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @sc, i8 %36 ) ; <i8>:37 [#uses=1] + sub i8 %37, %36 ; <i8>:38 [#uses=1] + store i8 %38, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:39 [#uses=2] + call i8 @llvm.atomic.load.sub.i8.p0i8( i8* @uc, i8 %39 ) ; <i8>:40 [#uses=1] + sub i8 %40, %39 ; <i8>:41 [#uses=1] + store i8 %41, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:42 [#uses=1] + zext i8 %42 to i16 ; <i16>:43 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:44 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %44, i16 %43 ) ; <i16>:45 [#uses=1] + sub i16 %45, %43 ; <i16>:46 [#uses=1] + store i16 %46, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:47 [#uses=1] + zext i8 %47 to i16 ; <i16>:48 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:49 [#uses=1] + call i16 @llvm.atomic.load.sub.i16.p0i16( i16* %49, i16 %48 ) ; <i16>:50 [#uses=1] + sub i16 %50, %48 ; <i16>:51 [#uses=1] + store i16 %51, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:52 [#uses=1] + zext i8 %52 to i32 ; <i32>:53 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:54 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %54, i32 %53 ) ; <i32>:55 [#uses=1] + sub i32 %55, %53 ; <i32>:56 [#uses=1] + store i32 %56, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:57 [#uses=1] + zext i8 %57 to i32 ; <i32>:58 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:59 [#uses=1] + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %59, i32 %58 ) ; <i32>:60 [#uses=1] + sub i32 %60, %58 ; <i32>:61 [#uses=1] + store i32 %61, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:62 [#uses=1] + zext i8 %62 to i64 ; <i64>:63 [#uses=2] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:64 [#uses=1] + call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %64, i64 %63 ) ; <i64>:65 [#uses=1] + sub i64 %65, %63 ; <i64>:66 [#uses=1] + store i64 %66, i64* @sl, align 8 + load i8* @uc, align 1 ; <i8>:67 [#uses=1] + zext i8 %67 to i64 ; <i64>:68 [#uses=2] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:69 [#uses=1] + call i64 @llvm.atomic.load.sub.i64.p0i64( i64* %69, i64 %68 ) ; <i64>:70 [#uses=1] + sub i64 %70, %68 ; <i64>:71 [#uses=1] + store i64 %71, i64* @ul, align 8 + load i8* @uc, align 1 ; <i8>:72 [#uses=2] + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @sc, i8 %72 ) ; <i8>:73 [#uses=1] + or i8 %73, %72 ; <i8>:74 [#uses=1] + store i8 %74, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:75 [#uses=2] + call i8 @llvm.atomic.load.or.i8.p0i8( i8* @uc, i8 %75 ) ; <i8>:76 [#uses=1] + or i8 %76, %75 ; <i8>:77 [#uses=1] + store i8 %77, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:78 [#uses=1] + zext i8 %78 to i16 ; <i16>:79 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:80 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %80, i16 %79 ) ; <i16>:81 [#uses=1] + or i16 %81, %79 ; <i16>:82 [#uses=1] + store i16 %82, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:83 [#uses=1] + zext i8 %83 to i16 ; <i16>:84 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:85 [#uses=1] + call i16 @llvm.atomic.load.or.i16.p0i16( i16* %85, i16 %84 ) ; <i16>:86 [#uses=1] + or i16 %86, %84 ; <i16>:87 [#uses=1] + store i16 %87, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:88 [#uses=1] + zext i8 %88 to i32 ; <i32>:89 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:90 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %90, i32 %89 ) ; <i32>:91 [#uses=1] + or i32 %91, %89 ; <i32>:92 [#uses=1] + store i32 %92, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:93 [#uses=1] + zext i8 %93 to i32 ; <i32>:94 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:95 [#uses=1] + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %95, i32 %94 ) ; <i32>:96 [#uses=1] + or i32 %96, %94 ; <i32>:97 [#uses=1] + store i32 %97, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:98 [#uses=1] + zext i8 %98 to i64 ; <i64>:99 [#uses=2] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:100 [#uses=1] + call i64 @llvm.atomic.load.or.i64.p0i64( i64* %100, i64 %99 ) ; <i64>:101 [#uses=1] + or i64 %101, %99 ; <i64>:102 [#uses=1] + store i64 %102, i64* @sl, align 8 + load i8* @uc, align 1 ; <i8>:103 [#uses=1] + zext i8 %103 to i64 ; <i64>:104 [#uses=2] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:105 [#uses=1] + call i64 @llvm.atomic.load.or.i64.p0i64( i64* %105, i64 %104 ) ; <i64>:106 [#uses=1] + or i64 %106, %104 ; <i64>:107 [#uses=1] + store i64 %107, i64* @ul, align 8 + load i8* @uc, align 1 ; <i8>:108 [#uses=2] + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @sc, i8 %108 ) ; <i8>:109 [#uses=1] + xor i8 %109, %108 ; <i8>:110 [#uses=1] + store i8 %110, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:111 [#uses=2] + call i8 @llvm.atomic.load.xor.i8.p0i8( i8* @uc, i8 %111 ) ; <i8>:112 [#uses=1] + xor i8 %112, %111 ; <i8>:113 [#uses=1] + store i8 %113, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:114 [#uses=1] + zext i8 %114 to i16 ; <i16>:115 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:116 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %116, i16 %115 ) ; <i16>:117 [#uses=1] + xor i16 %117, %115 ; <i16>:118 [#uses=1] + store i16 %118, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:119 [#uses=1] + zext i8 %119 to i16 ; <i16>:120 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:121 [#uses=1] + call i16 @llvm.atomic.load.xor.i16.p0i16( i16* %121, i16 %120 ) ; <i16>:122 [#uses=1] + xor i16 %122, %120 ; <i16>:123 [#uses=1] + store i16 %123, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:124 [#uses=1] + zext i8 %124 to i32 ; <i32>:125 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:126 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %126, i32 %125 ) ; <i32>:127 [#uses=1] + xor i32 %127, %125 ; <i32>:128 [#uses=1] + store i32 %128, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:129 [#uses=1] + zext i8 %129 to i32 ; <i32>:130 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:131 [#uses=1] + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %131, i32 %130 ) ; <i32>:132 [#uses=1] + xor i32 %132, %130 ; <i32>:133 [#uses=1] + store i32 %133, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:134 [#uses=1] + zext i8 %134 to i64 ; <i64>:135 [#uses=2] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:136 [#uses=1] + call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %136, i64 %135 ) ; <i64>:137 [#uses=1] + xor i64 %137, %135 ; <i64>:138 [#uses=1] + store i64 %138, i64* @sl, align 8 + load i8* @uc, align 1 ; <i8>:139 [#uses=1] + zext i8 %139 to i64 ; <i64>:140 [#uses=2] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:141 [#uses=1] + call i64 @llvm.atomic.load.xor.i64.p0i64( i64* %141, i64 %140 ) ; <i64>:142 [#uses=1] + xor i64 %142, %140 ; <i64>:143 [#uses=1] + store i64 %143, i64* @ul, align 8 + load i8* @uc, align 1 ; <i8>:144 [#uses=2] + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @sc, i8 %144 ) ; <i8>:145 [#uses=1] + and i8 %145, %144 ; <i8>:146 [#uses=1] + store i8 %146, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:147 [#uses=2] + call i8 @llvm.atomic.load.and.i8.p0i8( i8* @uc, i8 %147 ) ; <i8>:148 [#uses=1] + and i8 %148, %147 ; <i8>:149 [#uses=1] + store i8 %149, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:150 [#uses=1] + zext i8 %150 to i16 ; <i16>:151 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:152 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %152, i16 %151 ) ; <i16>:153 [#uses=1] + and i16 %153, %151 ; <i16>:154 [#uses=1] + store i16 %154, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:155 [#uses=1] + zext i8 %155 to i16 ; <i16>:156 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:157 [#uses=1] + call i16 @llvm.atomic.load.and.i16.p0i16( i16* %157, i16 %156 ) ; <i16>:158 [#uses=1] + and i16 %158, %156 ; <i16>:159 [#uses=1] + store i16 %159, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:160 [#uses=1] + zext i8 %160 to i32 ; <i32>:161 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:162 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %162, i32 %161 ) ; <i32>:163 [#uses=1] + and i32 %163, %161 ; <i32>:164 [#uses=1] + store i32 %164, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:165 [#uses=1] + zext i8 %165 to i32 ; <i32>:166 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:167 [#uses=1] + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %167, i32 %166 ) ; <i32>:168 [#uses=1] + and i32 %168, %166 ; <i32>:169 [#uses=1] + store i32 %169, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:170 [#uses=1] + zext i8 %170 to i64 ; <i64>:171 [#uses=2] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:172 [#uses=1] + call i64 @llvm.atomic.load.and.i64.p0i64( i64* %172, i64 %171 ) ; <i64>:173 [#uses=1] + and i64 %173, %171 ; <i64>:174 [#uses=1] + store i64 %174, i64* @sl, align 8 + load i8* @uc, align 1 ; <i8>:175 [#uses=1] + zext i8 %175 to i64 ; <i64>:176 [#uses=2] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:177 [#uses=1] + call i64 @llvm.atomic.load.and.i64.p0i64( i64* %177, i64 %176 ) ; <i64>:178 [#uses=1] + and i64 %178, %176 ; <i64>:179 [#uses=1] + store i64 %179, i64* @ul, align 8 + load i8* @uc, align 1 ; <i8>:180 [#uses=2] + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @sc, i8 %180 ) ; <i8>:181 [#uses=1] + xor i8 %181, -1 ; <i8>:182 [#uses=1] + and i8 %182, %180 ; <i8>:183 [#uses=1] + store i8 %183, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:184 [#uses=2] + call i8 @llvm.atomic.load.nand.i8.p0i8( i8* @uc, i8 %184 ) ; <i8>:185 [#uses=1] + xor i8 %185, -1 ; <i8>:186 [#uses=1] + and i8 %186, %184 ; <i8>:187 [#uses=1] + store i8 %187, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:188 [#uses=1] + zext i8 %188 to i16 ; <i16>:189 [#uses=2] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:190 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %190, i16 %189 ) ; <i16>:191 [#uses=1] + xor i16 %191, -1 ; <i16>:192 [#uses=1] + and i16 %192, %189 ; <i16>:193 [#uses=1] + store i16 %193, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:194 [#uses=1] + zext i8 %194 to i16 ; <i16>:195 [#uses=2] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:196 [#uses=1] + call i16 @llvm.atomic.load.nand.i16.p0i16( i16* %196, i16 %195 ) ; <i16>:197 [#uses=1] + xor i16 %197, -1 ; <i16>:198 [#uses=1] + and i16 %198, %195 ; <i16>:199 [#uses=1] + store i16 %199, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:200 [#uses=1] + zext i8 %200 to i32 ; <i32>:201 [#uses=2] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:202 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %202, i32 %201 ) ; <i32>:203 [#uses=1] + xor i32 %203, -1 ; <i32>:204 [#uses=1] + and i32 %204, %201 ; <i32>:205 [#uses=1] + store i32 %205, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:206 [#uses=1] + zext i8 %206 to i32 ; <i32>:207 [#uses=2] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:208 [#uses=1] + call i32 @llvm.atomic.load.nand.i32.p0i32( i32* %208, i32 %207 ) ; <i32>:209 [#uses=1] + xor i32 %209, -1 ; <i32>:210 [#uses=1] + and i32 %210, %207 ; <i32>:211 [#uses=1] + store i32 %211, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:212 [#uses=1] + zext i8 %212 to i64 ; <i64>:213 [#uses=2] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:214 [#uses=1] + call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %214, i64 %213 ) ; <i64>:215 [#uses=1] + xor i64 %215, -1 ; <i64>:216 [#uses=1] + and i64 %216, %213 ; <i64>:217 [#uses=1] + store i64 %217, i64* @sl, align 8 + load i8* @uc, align 1 ; <i8>:218 [#uses=1] + zext i8 %218 to i64 ; <i64>:219 [#uses=2] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:220 [#uses=1] + call i64 @llvm.atomic.load.nand.i64.p0i64( i64* %220, i64 %219 ) ; <i64>:221 [#uses=1] + xor i64 %221, -1 ; <i64>:222 [#uses=1] + and i64 %222, %219 ; <i64>:223 [#uses=1] + store i64 %223, i64* @ul, align 8 + br label %return + +return: ; preds = %entry + ret void +} + +define void @test_compare_and_swap() nounwind { +entry: + load i8* @uc, align 1 ; <i8>:0 [#uses=1] + load i8* @sc, align 1 ; <i8>:1 [#uses=1] + call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %0, i8 %1 ) ; <i8>:2 [#uses=1] + store i8 %2, i8* @sc, align 1 + load i8* @uc, align 1 ; <i8>:3 [#uses=1] + load i8* @sc, align 1 ; <i8>:4 [#uses=1] + call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %3, i8 %4 ) ; <i8>:5 [#uses=1] + store i8 %5, i8* @uc, align 1 + load i8* @uc, align 1 ; <i8>:6 [#uses=1] + zext i8 %6 to i16 ; <i16>:7 [#uses=1] + load i8* @sc, align 1 ; <i8>:8 [#uses=1] + sext i8 %8 to i16 ; <i16>:9 [#uses=1] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:10 [#uses=1] + call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %10, i16 %7, i16 %9 ) ; <i16>:11 [#uses=1] + store i16 %11, i16* @ss, align 2 + load i8* @uc, align 1 ; <i8>:12 [#uses=1] + zext i8 %12 to i16 ; <i16>:13 [#uses=1] + load i8* @sc, align 1 ; <i8>:14 [#uses=1] + sext i8 %14 to i16 ; <i16>:15 [#uses=1] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:16 [#uses=1] + call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %16, i16 %13, i16 %15 ) ; <i16>:17 [#uses=1] + store i16 %17, i16* @us, align 2 + load i8* @uc, align 1 ; <i8>:18 [#uses=1] + zext i8 %18 to i32 ; <i32>:19 [#uses=1] + load i8* @sc, align 1 ; <i8>:20 [#uses=1] + sext i8 %20 to i32 ; <i32>:21 [#uses=1] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:22 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %22, i32 %19, i32 %21 ) ; <i32>:23 [#uses=1] + store i32 %23, i32* @si, align 4 + load i8* @uc, align 1 ; <i8>:24 [#uses=1] + zext i8 %24 to i32 ; <i32>:25 [#uses=1] + load i8* @sc, align 1 ; <i8>:26 [#uses=1] + sext i8 %26 to i32 ; <i32>:27 [#uses=1] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:28 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %28, i32 %25, i32 %27 ) ; <i32>:29 [#uses=1] + store i32 %29, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:30 [#uses=1] + zext i8 %30 to i64 ; <i64>:31 [#uses=1] + load i8* @sc, align 1 ; <i8>:32 [#uses=1] + sext i8 %32 to i64 ; <i64>:33 [#uses=1] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:34 [#uses=1] + call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %34, i64 %31, i64 %33 ) ; <i64>:35 [#uses=1] + store i64 %35, i64* @sl, align 8 + load i8* @uc, align 1 ; <i8>:36 [#uses=1] + zext i8 %36 to i64 ; <i64>:37 [#uses=1] + load i8* @sc, align 1 ; <i8>:38 [#uses=1] + sext i8 %38 to i64 ; <i64>:39 [#uses=1] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:40 [#uses=1] + call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %40, i64 %37, i64 %39 ) ; <i64>:41 [#uses=1] + store i64 %41, i64* @ul, align 8 + load i8* @uc, align 1 ; <i8>:42 [#uses=2] + load i8* @sc, align 1 ; <i8>:43 [#uses=1] + call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @sc, i8 %42, i8 %43 ) ; <i8>:44 [#uses=1] + icmp eq i8 %44, %42 ; <i1>:45 [#uses=1] + zext i1 %45 to i8 ; <i8>:46 [#uses=1] + zext i8 %46 to i32 ; <i32>:47 [#uses=1] + store i32 %47, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:48 [#uses=2] + load i8* @sc, align 1 ; <i8>:49 [#uses=1] + call i8 @llvm.atomic.cmp.swap.i8.p0i8( i8* @uc, i8 %48, i8 %49 ) ; <i8>:50 [#uses=1] + icmp eq i8 %50, %48 ; <i1>:51 [#uses=1] + zext i1 %51 to i8 ; <i8>:52 [#uses=1] + zext i8 %52 to i32 ; <i32>:53 [#uses=1] + store i32 %53, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:54 [#uses=1] + zext i8 %54 to i16 ; <i16>:55 [#uses=2] + load i8* @sc, align 1 ; <i8>:56 [#uses=1] + sext i8 %56 to i16 ; <i16>:57 [#uses=1] + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:58 [#uses=1] + call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %58, i16 %55, i16 %57 ) ; <i16>:59 [#uses=1] + icmp eq i16 %59, %55 ; <i1>:60 [#uses=1] + zext i1 %60 to i8 ; <i8>:61 [#uses=1] + zext i8 %61 to i32 ; <i32>:62 [#uses=1] + store i32 %62, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:63 [#uses=1] + zext i8 %63 to i16 ; <i16>:64 [#uses=2] + load i8* @sc, align 1 ; <i8>:65 [#uses=1] + sext i8 %65 to i16 ; <i16>:66 [#uses=1] + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:67 [#uses=1] + call i16 @llvm.atomic.cmp.swap.i16.p0i16( i16* %67, i16 %64, i16 %66 ) ; <i16>:68 [#uses=1] + icmp eq i16 %68, %64 ; <i1>:69 [#uses=1] + zext i1 %69 to i8 ; <i8>:70 [#uses=1] + zext i8 %70 to i32 ; <i32>:71 [#uses=1] + store i32 %71, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:72 [#uses=1] + zext i8 %72 to i32 ; <i32>:73 [#uses=2] + load i8* @sc, align 1 ; <i8>:74 [#uses=1] + sext i8 %74 to i32 ; <i32>:75 [#uses=1] + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:76 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %76, i32 %73, i32 %75 ) ; <i32>:77 [#uses=1] + icmp eq i32 %77, %73 ; <i1>:78 [#uses=1] + zext i1 %78 to i8 ; <i8>:79 [#uses=1] + zext i8 %79 to i32 ; <i32>:80 [#uses=1] + store i32 %80, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:81 [#uses=1] + zext i8 %81 to i32 ; <i32>:82 [#uses=2] + load i8* @sc, align 1 ; <i8>:83 [#uses=1] + sext i8 %83 to i32 ; <i32>:84 [#uses=1] + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:85 [#uses=1] + call i32 @llvm.atomic.cmp.swap.i32.p0i32( i32* %85, i32 %82, i32 %84 ) ; <i32>:86 [#uses=1] + icmp eq i32 %86, %82 ; <i1>:87 [#uses=1] + zext i1 %87 to i8 ; <i8>:88 [#uses=1] + zext i8 %88 to i32 ; <i32>:89 [#uses=1] + store i32 %89, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:90 [#uses=1] + zext i8 %90 to i64 ; <i64>:91 [#uses=2] + load i8* @sc, align 1 ; <i8>:92 [#uses=1] + sext i8 %92 to i64 ; <i64>:93 [#uses=1] + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:94 [#uses=1] + call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %94, i64 %91, i64 %93 ) ; <i64>:95 [#uses=1] + icmp eq i64 %95, %91 ; <i1>:96 [#uses=1] + zext i1 %96 to i8 ; <i8>:97 [#uses=1] + zext i8 %97 to i32 ; <i32>:98 [#uses=1] + store i32 %98, i32* @ui, align 4 + load i8* @uc, align 1 ; <i8>:99 [#uses=1] + zext i8 %99 to i64 ; <i64>:100 [#uses=2] + load i8* @sc, align 1 ; <i8>:101 [#uses=1] + sext i8 %101 to i64 ; <i64>:102 [#uses=1] + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:103 [#uses=1] + call i64 @llvm.atomic.cmp.swap.i64.p0i64( i64* %103, i64 %100, i64 %102 ) ; <i64>:104 [#uses=1] + icmp eq i64 %104, %100 ; <i1>:105 [#uses=1] + zext i1 %105 to i8 ; <i8>:106 [#uses=1] + zext i8 %106 to i32 ; <i32>:107 [#uses=1] + store i32 %107, i32* @ui, align 4 + br label %return + +return: ; preds = %entry + ret void +} + +declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8*, i8, i8) nounwind + +declare i16 @llvm.atomic.cmp.swap.i16.p0i16(i16*, i16, i16) nounwind + +declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind + +declare i64 @llvm.atomic.cmp.swap.i64.p0i64(i64*, i64, i64) nounwind + +define void @test_lock() nounwind { +entry: + call i8 @llvm.atomic.swap.i8.p0i8( i8* @sc, i8 1 ) ; <i8>:0 [#uses=1] + store i8 %0, i8* @sc, align 1 + call i8 @llvm.atomic.swap.i8.p0i8( i8* @uc, i8 1 ) ; <i8>:1 [#uses=1] + store i8 %1, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:2 [#uses=1] + call i16 @llvm.atomic.swap.i16.p0i16( i16* %2, i16 1 ) ; <i16>:3 [#uses=1] + store i16 %3, i16* @ss, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:4 [#uses=1] + call i16 @llvm.atomic.swap.i16.p0i16( i16* %4, i16 1 ) ; <i16>:5 [#uses=1] + store i16 %5, i16* @us, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:6 [#uses=1] + call i32 @llvm.atomic.swap.i32.p0i32( i32* %6, i32 1 ) ; <i32>:7 [#uses=1] + store i32 %7, i32* @si, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:8 [#uses=1] + call i32 @llvm.atomic.swap.i32.p0i32( i32* %8, i32 1 ) ; <i32>:9 [#uses=1] + store i32 %9, i32* @ui, align 4 + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:10 [#uses=1] + call i64 @llvm.atomic.swap.i64.p0i64( i64* %10, i64 1 ) ; <i64>:11 [#uses=1] + store i64 %11, i64* @sl, align 8 + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:12 [#uses=1] + call i64 @llvm.atomic.swap.i64.p0i64( i64* %12, i64 1 ) ; <i64>:13 [#uses=1] + store i64 %13, i64* @ul, align 8 + call void @llvm.memory.barrier( i1 true, i1 true, i1 true, i1 true, i1 false ) + volatile store i8 0, i8* @sc, align 1 + volatile store i8 0, i8* @uc, align 1 + bitcast i8* bitcast (i16* @ss to i8*) to i16* ; <i16*>:14 [#uses=1] + volatile store i16 0, i16* %14, align 2 + bitcast i8* bitcast (i16* @us to i8*) to i16* ; <i16*>:15 [#uses=1] + volatile store i16 0, i16* %15, align 2 + bitcast i8* bitcast (i32* @si to i8*) to i32* ; <i32*>:16 [#uses=1] + volatile store i32 0, i32* %16, align 4 + bitcast i8* bitcast (i32* @ui to i8*) to i32* ; <i32*>:17 [#uses=1] + volatile store i32 0, i32* %17, align 4 + bitcast i8* bitcast (i64* @sl to i8*) to i64* ; <i64*>:18 [#uses=1] + volatile store i64 0, i64* %18, align 8 + bitcast i8* bitcast (i64* @ul to i8*) to i64* ; <i64*>:19 [#uses=1] + volatile store i64 0, i64* %19, align 8 + bitcast i8* bitcast (i64* @sll to i8*) to i64* ; <i64*>:20 [#uses=1] + volatile store i64 0, i64* %20, align 8 + bitcast i8* bitcast (i64* @ull to i8*) to i64* ; <i64*>:21 [#uses=1] + volatile store i64 0, i64* %21, align 8 + br label %return + +return: ; preds = %entry + ret void +} + +declare i8 @llvm.atomic.swap.i8.p0i8(i8*, i8) nounwind + +declare i16 @llvm.atomic.swap.i16.p0i16(i16*, i16) nounwind + +declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind + +declare i64 @llvm.atomic.swap.i64.p0i64(i64*, i64) nounwind + +declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind diff --git a/test/CodeGen/PowerPC/Frames-alloca.ll b/test/CodeGen/PowerPC/Frames-alloca.ll new file mode 100644 index 000000000000..45c13a7bfe41 --- /dev/null +++ b/test/CodeGen/PowerPC/Frames-alloca.ll @@ -0,0 +1,37 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {stw r31, 20(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | \ +; RUN: grep {stwu r1, -80(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {lwz r1, 0(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {lwz r31, 20(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {stw r31, 20(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | \ +; RUN: grep {stwu r1, -80(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {lwz r1, 0(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {lwz r31, 20(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {std r31, 40(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {stdu r1, -112(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {ld r1, 0(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {ld r31, 40(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {std r31, 40(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {stdu r1, -112(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {ld r1, 0(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {ld r31, 40(r1)} + +define i32* @f1(i32 %n) { + %tmp = alloca i32, i32 %n ; <i32*> [#uses=1] + ret i32* %tmp +} diff --git a/test/CodeGen/PowerPC/Frames-large.ll b/test/CodeGen/PowerPC/Frames-large.ll new file mode 100644 index 000000000000..0a15d2233e79 --- /dev/null +++ b/test/CodeGen/PowerPC/Frames-large.ll @@ -0,0 +1,77 @@ +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: not grep {stw r31, 20(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | grep {lis r0, -1} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {ori r0, r0, 32704} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {stwux r1, r1, r0} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {lwz r1, 0(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: not grep {lwz r31, 20(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {stw r31, 20(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {lis r0, -1} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {ori r0, r0, 32704} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {stwux r1, r1, r0} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {lwz r1, 0(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {lwz r31, 20(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ +; RUN: not grep {std r31, 40(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {lis r0, -1} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {ori r0, r0, 32656} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {stdux r1, r1, r0} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {ld r1, 0(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 | \ +; RUN: not grep {ld r31, 40(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {std r31, 40(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {lis r0, -1} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {ori r0, r0, 32656} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {stdux r1, r1, r0} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {ld r1, 0(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | \ +; RUN: grep {ld r31, 40(r1)} + +define i32* @f1() { + %tmp = alloca i32, i32 8191 ; <i32*> [#uses=1] + ret i32* %tmp +} + diff --git a/test/CodeGen/PowerPC/Frames-leaf.ll b/test/CodeGen/PowerPC/Frames-leaf.ll new file mode 100644 index 000000000000..11b64703ebd8 --- /dev/null +++ b/test/CodeGen/PowerPC/Frames-leaf.ll @@ -0,0 +1,37 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: not grep {stw r31, 20(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: not grep {stwu r1, -.*(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: not grep {addi r1, r1, } +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: not grep {lwz r31, 20(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \ +; RUN: not grep {stw r31, 20(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \ +; RUN: not grep {stwu r1, -.*(r1)} +; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \ +; RUN: not grep {addi r1, r1, } +; RUN: llvm-as < %s | llc -march=ppc32 -disable-fp-elim | \ +; RUN: not grep {lwz r31, 20(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 | \ +; RUN: not grep {std r31, 40(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 | \ +; RUN: not grep {stdu r1, -.*(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 | \ +; RUN: not grep {addi r1, r1, } +; RUN: llvm-as < %s | llc -march=ppc64 | \ +; RUN: not grep {ld r31, 40(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \ +; RUN: not grep {stw r31, 40(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \ +; RUN: not grep {stdu r1, -.*(r1)} +; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \ +; RUN: not grep {addi r1, r1, } +; RUN: llvm-as < %s | llc -march=ppc64 -disable-fp-elim | \ +; RUN: not grep {ld r31, 40(r1)} + +define i32* @f1() { + %tmp = alloca i32, i32 2 ; <i32*> [#uses=1] + ret i32* %tmp +} diff --git a/test/CodeGen/PowerPC/Frames-small.ll b/test/CodeGen/PowerPC/Frames-small.ll new file mode 100644 index 000000000000..4ea3afba8831 --- /dev/null +++ b/test/CodeGen/PowerPC/Frames-small.ll @@ -0,0 +1,33 @@ +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1 -f +; RUN not grep {stw r31, 20(r1)} %t1 +; RUN: grep {stwu r1, -16448(r1)} %t1 +; RUN: grep {addi r1, r1, 16448} %t1 +; RUN: llvm-as < %s | \ +; RUN: not grep {lwz r31, 20(r1)} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ +; RUN: -o %t2 -f +; RUN: grep {stw r31, 20(r1)} %t2 +; RUN: grep {stwu r1, -16448(r1)} %t2 +; RUN: grep {addi r1, r1, 16448} %t2 +; RUN: grep {lwz r31, 20(r1)} %t2 +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3 -f +; RUN: not grep {std r31, 40(r1)} %t3 +; RUN: grep {stdu r1, -16496(r1)} %t3 +; RUN: grep {addi r1, r1, 16496} %t3 +; RUN: not grep {ld r31, 40(r1)} %t3 +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ +; RUN: -o %t4 -f +; RUN: grep {std r31, 40(r1)} %t4 +; RUN: grep {stdu r1, -16496(r1)} %t4 +; RUN: grep {addi r1, r1, 16496} %t4 +; RUN: grep {ld r31, 40(r1)} %t4 + +define i32* @f1() { + %tmp = alloca i32, i32 4095 ; <i32*> [#uses=1] + ret i32* %tmp +} + diff --git a/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll new file mode 100644 index 000000000000..17053796bc79 --- /dev/null +++ b/test/CodeGen/PowerPC/LargeAbsoluteAddr.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin | \ +; RUN: grep {stw r3, 32751} +; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin | \ +; RUN: grep {stw r3, 32751} +; RUN: llvm-as < %s | llc -march=ppc64 -mtriple=powerpc-apple-darwin | \ +; RUN: grep {std r2, 9024} + +define void @test() { + store i32 0, i32* inttoptr (i64 48725999 to i32*) + ret void +} + +define void @test2() { + store i64 0, i64* inttoptr (i64 74560 to i64*) + ret void +} + diff --git a/test/CodeGen/PowerPC/addc.ll b/test/CodeGen/PowerPC/addc.ll new file mode 100644 index 000000000000..406053bee27f --- /dev/null +++ b/test/CodeGen/PowerPC/addc.ll @@ -0,0 +1,26 @@ +; All of these should be codegen'd without loading immediates +; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: grep addc %t | count 1 +; RUN: grep adde %t | count 1 +; RUN: grep addze %t | count 1 +; RUN: grep addme %t | count 1 +; RUN: grep addic %t | count 2 + +define i64 @add_ll(i64 %a, i64 %b) { +entry: + %tmp.2 = add i64 %b, %a ; <i64> [#uses=1] + ret i64 %tmp.2 +} + +define i64 @add_l_5(i64 %a) { +entry: + %tmp.1 = add i64 %a, 5 ; <i64> [#uses=1] + ret i64 %tmp.1 +} + +define i64 @add_l_m5(i64 %a) { +entry: + %tmp.1 = add i64 %a, -5 ; <i64> [#uses=1] + ret i64 %tmp.1 +} + diff --git a/test/CodeGen/PowerPC/addi-reassoc.ll b/test/CodeGen/PowerPC/addi-reassoc.ll new file mode 100644 index 000000000000..bee8660a8a9e --- /dev/null +++ b/test/CodeGen/PowerPC/addi-reassoc.ll @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep addi + + %struct.X = type { [5 x i8] } + +define i32 @test1([4 x i32]* %P, i32 %i) { + %tmp.2 = add i32 %i, 2 ; <i32> [#uses=1] + %tmp.4 = getelementptr [4 x i32]* %P, i32 %tmp.2, i32 1 ; <i32*> [#uses=1] + %tmp.5 = load i32* %tmp.4 ; <i32> [#uses=1] + ret i32 %tmp.5 +} + +define i32 @test2(%struct.X* %P, i32 %i) { + %tmp.2 = add i32 %i, 2 ; <i32> [#uses=1] + %tmp.5 = getelementptr %struct.X* %P, i32 %tmp.2, i32 0, i32 1 ; <i8*> [#uses=1] + %tmp.6 = load i8* %tmp.5 ; <i8> [#uses=1] + %tmp.7 = sext i8 %tmp.6 to i32 ; <i32> [#uses=1] + ret i32 %tmp.7 +} + diff --git a/test/CodeGen/PowerPC/align.ll b/test/CodeGen/PowerPC/align.ll new file mode 100644 index 000000000000..7ffbe3676704 --- /dev/null +++ b/test/CodeGen/PowerPC/align.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep align.4 | count 1 +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep align.2 | count 1 +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep align.3 | count 1 + +@A = global <4 x i32> < i32 10, i32 20, i32 30, i32 40 > ; <<4 x i32>*> [#uses=0] +@B = global float 1.000000e+02 ; <float*> [#uses=0] +@C = global double 2.000000e+03 ; <double*> [#uses=0] + diff --git a/test/CodeGen/PowerPC/and-branch.ll b/test/CodeGen/PowerPC/and-branch.ll new file mode 100644 index 000000000000..f0bb5ea40157 --- /dev/null +++ b/test/CodeGen/PowerPC/and-branch.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep mfcr + +define void @foo(i32 %X, i32 %Y, i32 %Z) { +entry: + %tmp = icmp eq i32 %X, 0 ; <i1> [#uses=1] + %tmp3 = icmp slt i32 %Y, 5 ; <i1> [#uses=1] + %tmp4 = and i1 %tmp3, %tmp ; <i1> [#uses=1] + br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock +cond_true: ; preds = %entry + %tmp5 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + ret void +UnifiedReturnBlock: ; preds = %entry + ret void +} + +declare i32 @bar(...) + diff --git a/test/CodeGen/PowerPC/and-elim.ll b/test/CodeGen/PowerPC/and-elim.ll new file mode 100644 index 000000000000..eef8f51f7a19 --- /dev/null +++ b/test/CodeGen/PowerPC/and-elim.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwin + +define void @test(i8* %P) { + %W = load i8* %P + %X = shl i8 %W, 1 + %Y = add i8 %X, 2 + %Z = and i8 %Y, 254 ; dead and + store i8 %Z, i8* %P + ret void +} + +define i16 @test2(i16 zeroext %crc) zeroext { + ; No and's should be needed for the i16s here. + %tmp.1 = lshr i16 %crc, 1 + %tmp.7 = xor i16 %tmp.1, 40961 + ret i16 %tmp.7 +} + diff --git a/test/CodeGen/PowerPC/and-imm.ll b/test/CodeGen/PowerPC/and-imm.ll new file mode 100644 index 000000000000..9c806494be3b --- /dev/null +++ b/test/CodeGen/PowerPC/and-imm.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep {ori\\|lis} + +; andi. r3, r3, 32769 +define i32 @test(i32 %X) { + %Y = and i32 %X, 32769 ; <i32> [#uses=1] + ret i32 %Y +} + +; andis. r3, r3, 32769 +define i32 @test2(i32 %X) { + %Y = and i32 %X, -2147418112 ; <i32> [#uses=1] + ret i32 %Y +} + diff --git a/test/CodeGen/PowerPC/and_add.ll b/test/CodeGen/PowerPC/and_add.ll new file mode 100644 index 000000000000..f103e7c0df06 --- /dev/null +++ b/test/CodeGen/PowerPC/and_add.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: grep slwi %t +; RUN: not grep addi %t +; RUN: not grep rlwinm %t + +define i32 @test(i32 %A) { + ;; shift + %B = mul i32 %A, 8 ; <i32> [#uses=1] + ;; dead, no demanded bits. + %C = add i32 %B, 7 ; <i32> [#uses=1] + ;; dead once add is gone. + %D = and i32 %C, -8 ; <i32> [#uses=1] + ret i32 %D +} + diff --git a/test/CodeGen/PowerPC/and_sext.ll b/test/CodeGen/PowerPC/and_sext.ll new file mode 100644 index 000000000000..e0e498def057 --- /dev/null +++ b/test/CodeGen/PowerPC/and_sext.ll @@ -0,0 +1,28 @@ +; These tests should not contain a sign extend. +; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsh +; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsb + +define i32 @test1(i32 %mode.0.i.0) { + %tmp.79 = trunc i32 %mode.0.i.0 to i16 + %tmp.80 = sext i16 %tmp.79 to i32 + %tmp.81 = and i32 %tmp.80, 24 + ret i32 %tmp.81 +} + +define i16 @test2(i16 signext %X, i16 signext %x) signext { + %tmp = sext i16 %X to i32 + %tmp1 = sext i16 %x to i32 + %tmp2 = add i32 %tmp, %tmp1 + %tmp4 = ashr i32 %tmp2, 1 + %tmp5 = trunc i32 %tmp4 to i16 + %tmp45 = sext i16 %tmp5 to i32 + %retval = trunc i32 %tmp45 to i16 + ret i16 %retval +} + +define i16 @test3(i32 zeroext %X) signext { + %tmp1 = lshr i32 %X, 16 + %tmp2 = trunc i32 %tmp1 to i16 + ret i16 %tmp2 +} + diff --git a/test/CodeGen/PowerPC/and_sra.ll b/test/CodeGen/PowerPC/and_sra.ll new file mode 100644 index 000000000000..c780605c9753 --- /dev/null +++ b/test/CodeGen/PowerPC/and_sra.ll @@ -0,0 +1,27 @@ +; Neither of these functions should contain algebraic right shifts +; RUN: llvm-as < %s | llc -march=ppc32 | not grep srawi + +define i32 @test1(i32 %mode.0.i.0) { + %tmp.79 = bitcast i32 %mode.0.i.0 to i32 ; <i32> [#uses=1] + %tmp.80 = ashr i32 %tmp.79, 15 ; <i32> [#uses=1] + %tmp.81 = and i32 %tmp.80, 24 ; <i32> [#uses=1] + ret i32 %tmp.81 +} + +define i32 @test2(i32 %mode.0.i.0) { + %tmp.79 = bitcast i32 %mode.0.i.0 to i32 ; <i32> [#uses=1] + %tmp.80 = ashr i32 %tmp.79, 15 ; <i32> [#uses=1] + %tmp.81 = lshr i32 %mode.0.i.0, 16 ; <i32> [#uses=1] + %tmp.82 = bitcast i32 %tmp.81 to i32 ; <i32> [#uses=1] + %tmp.83 = and i32 %tmp.80, %tmp.82 ; <i32> [#uses=1] + ret i32 %tmp.83 +} + +define i32 @test3(i32 %specbits.6.1) { + %tmp.2540 = ashr i32 %specbits.6.1, 11 ; <i32> [#uses=1] + %tmp.2541 = bitcast i32 %tmp.2540 to i32 ; <i32> [#uses=1] + %tmp.2542 = shl i32 %tmp.2541, 13 ; <i32> [#uses=1] + %tmp.2543 = and i32 %tmp.2542, 8192 ; <i32> [#uses=1] + ret i32 %tmp.2543 +} + diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll new file mode 100644 index 000000000000..f6bb2983d565 --- /dev/null +++ b/test/CodeGen/PowerPC/atomic-1.ll @@ -0,0 +1,21 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep lwarx | count 3 +; RUN: llvm-as < %s | llc -march=ppc32 | grep stwcx. | count 4 + +define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind { + %tmp = call i32 @llvm.atomic.load.add.i32( i32* %mem, i32 %val ) + ret i32 %tmp +} + +define i32 @exchange_and_cmp(i32* %mem) nounwind { + %tmp = call i32 @llvm.atomic.cmp.swap.i32( i32* %mem, i32 0, i32 1 ) + ret i32 %tmp +} + +define i32 @exchange(i32* %mem, i32 %val) nounwind { + %tmp = call i32 @llvm.atomic.swap.i32( i32* %mem, i32 1 ) + ret i32 %tmp +} + +declare i32 @llvm.atomic.load.add.i32(i32*, i32) nounwind +declare i32 @llvm.atomic.cmp.swap.i32(i32*, i32, i32) nounwind +declare i32 @llvm.atomic.swap.i32(i32*, i32) nounwind diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll new file mode 100644 index 000000000000..77b7b08d8c22 --- /dev/null +++ b/test/CodeGen/PowerPC/atomic-2.ll @@ -0,0 +1,21 @@ +; RUN: llvm-as < %s | llc -march=ppc64 | grep ldarx | count 3 +; RUN: llvm-as < %s | llc -march=ppc64 | grep stdcx. | count 4 + +define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind { + %tmp = call i64 @llvm.atomic.load.add.i64( i64* %mem, i64 %val ) + ret i64 %tmp +} + +define i64 @exchange_and_cmp(i64* %mem) nounwind { + %tmp = call i64 @llvm.atomic.cmp.swap.i64( i64* %mem, i64 0, i64 1 ) + ret i64 %tmp +} + +define i64 @exchange(i64* %mem, i64 %val) nounwind { + %tmp = call i64 @llvm.atomic.swap.i64( i64* %mem, i64 1 ) + ret i64 %tmp +} + +declare i64 @llvm.atomic.load.add.i64(i64*, i64) nounwind +declare i64 @llvm.atomic.cmp.swap.i64(i64*, i64, i64) nounwind +declare i64 @llvm.atomic.swap.i64(i64*, i64) nounwind diff --git a/test/CodeGen/PowerPC/big-endian-actual-args.ll b/test/CodeGen/PowerPC/big-endian-actual-args.ll new file mode 100644 index 000000000000..d23935756dc2 --- /dev/null +++ b/test/CodeGen/PowerPC/big-endian-actual-args.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: grep {addc 4, 4, 6} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: grep {adde 3, 3, 5} + +define i64 @foo(i64 %x, i64 %y) { + %z = add i64 %x, %y + ret i64 %z +} diff --git a/test/CodeGen/PowerPC/big-endian-call-result.ll b/test/CodeGen/PowerPC/big-endian-call-result.ll new file mode 100644 index 000000000000..ab136f65d274 --- /dev/null +++ b/test/CodeGen/PowerPC/big-endian-call-result.ll @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: grep {addic 4, 4, 1} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: grep {addze 3, 3} + +declare i64 @foo() + +define i64 @bar() +{ + %t = call i64 @foo() + %s = add i64 %t, 1 + ret i64 %s +} diff --git a/test/CodeGen/PowerPC/big-endian-formal-args.ll b/test/CodeGen/PowerPC/big-endian-formal-args.ll new file mode 100644 index 000000000000..08589f499965 --- /dev/null +++ b/test/CodeGen/PowerPC/big-endian-formal-args.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: grep {li 6, 3} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: grep {li 4, 2} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: grep {li 3, 0} +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ +; RUN: grep {mr 5, 3} + +declare void @bar(i64 %x, i64 %y) + +define void @foo() { + call void @bar(i64 2, i64 3) + ret void +} diff --git a/test/CodeGen/PowerPC/branch-opt.ll b/test/CodeGen/PowerPC/branch-opt.ll new file mode 100644 index 000000000000..4aa55a39e5de --- /dev/null +++ b/test/CodeGen/PowerPC/branch-opt.ll @@ -0,0 +1,71 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep {b LBB.*} | count 4 + +target datalayout = "E-p:32:32" +target triple = "powerpc-apple-darwin8.7.0" + +define void @foo(i32 %W, i32 %X, i32 %Y, i32 %Z) { +entry: + %tmp1 = and i32 %W, 1 ; <i32> [#uses=1] + %tmp1.upgrd.1 = icmp eq i32 %tmp1, 0 ; <i1> [#uses=1] + br i1 %tmp1.upgrd.1, label %cond_false, label %bb5 +bb: ; preds = %bb5, %bb + %indvar77 = phi i32 [ %indvar.next78, %bb ], [ 0, %bb5 ] ; <i32> [#uses=1] + %tmp2 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %indvar.next78 = add i32 %indvar77, 1 ; <i32> [#uses=2] + %exitcond79 = icmp eq i32 %indvar.next78, %X ; <i1> [#uses=1] + br i1 %exitcond79, label %cond_next48, label %bb +bb5: ; preds = %entry + %tmp = icmp eq i32 %X, 0 ; <i1> [#uses=1] + br i1 %tmp, label %cond_next48, label %bb +cond_false: ; preds = %entry + %tmp10 = and i32 %W, 2 ; <i32> [#uses=1] + %tmp10.upgrd.2 = icmp eq i32 %tmp10, 0 ; <i1> [#uses=1] + br i1 %tmp10.upgrd.2, label %cond_false20, label %bb16 +bb12: ; preds = %bb16, %bb12 + %indvar72 = phi i32 [ %indvar.next73, %bb12 ], [ 0, %bb16 ] ; <i32> [#uses=1] + %tmp13 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %indvar.next73 = add i32 %indvar72, 1 ; <i32> [#uses=2] + %exitcond74 = icmp eq i32 %indvar.next73, %Y ; <i1> [#uses=1] + br i1 %exitcond74, label %cond_next48, label %bb12 +bb16: ; preds = %cond_false + %tmp18 = icmp eq i32 %Y, 0 ; <i1> [#uses=1] + br i1 %tmp18, label %cond_next48, label %bb12 +cond_false20: ; preds = %cond_false + %tmp23 = and i32 %W, 4 ; <i32> [#uses=1] + %tmp23.upgrd.3 = icmp eq i32 %tmp23, 0 ; <i1> [#uses=1] + br i1 %tmp23.upgrd.3, label %cond_false33, label %bb29 +bb25: ; preds = %bb29, %bb25 + %indvar67 = phi i32 [ %indvar.next68, %bb25 ], [ 0, %bb29 ] ; <i32> [#uses=1] + %tmp26 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %indvar.next68 = add i32 %indvar67, 1 ; <i32> [#uses=2] + %exitcond69 = icmp eq i32 %indvar.next68, %Z ; <i1> [#uses=1] + br i1 %exitcond69, label %cond_next48, label %bb25 +bb29: ; preds = %cond_false20 + %tmp31 = icmp eq i32 %Z, 0 ; <i1> [#uses=1] + br i1 %tmp31, label %cond_next48, label %bb25 +cond_false33: ; preds = %cond_false20 + %tmp36 = and i32 %W, 8 ; <i32> [#uses=1] + %tmp36.upgrd.4 = icmp eq i32 %tmp36, 0 ; <i1> [#uses=1] + br i1 %tmp36.upgrd.4, label %cond_next48, label %bb42 +bb38: ; preds = %bb42 + %tmp39 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1] + br label %bb42 +bb42: ; preds = %bb38, %cond_false33 + %indvar = phi i32 [ %indvar.next, %bb38 ], [ 0, %cond_false33 ] ; <i32> [#uses=4] + %W_addr.0 = sub i32 %W, %indvar ; <i32> [#uses=1] + %exitcond = icmp eq i32 %indvar, %W ; <i1> [#uses=1] + br i1 %exitcond, label %cond_next48, label %bb38 +cond_next48: ; preds = %bb42, %cond_false33, %bb29, %bb25, %bb16, %bb12, %bb5, %bb + %W_addr.1 = phi i32 [ %W, %bb5 ], [ %W, %bb16 ], [ %W, %bb29 ], [ %W, %cond_false33 ], [ %W_addr.0, %bb42 ], [ %W, %bb25 ], [ %W, %bb12 ], [ %W, %bb ] ; <i32> [#uses=1] + %tmp50 = icmp eq i32 %W_addr.1, 0 ; <i1> [#uses=1] + br i1 %tmp50, label %UnifiedReturnBlock, label %cond_true51 +cond_true51: ; preds = %cond_next48 + %tmp52 = tail call i32 (...)* @bar( ) ; <i32> [#uses=0] + ret void +UnifiedReturnBlock: ; preds = %cond_next48 + ret void +} + +declare i32 @bar(...) diff --git a/test/CodeGen/PowerPC/bswap-load-store.ll b/test/CodeGen/PowerPC/bswap-load-store.ll new file mode 100644 index 000000000000..e450eb8c2378 --- /dev/null +++ b/test/CodeGen/PowerPC/bswap-load-store.ll @@ -0,0 +1,45 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4 +; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwinm +; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwimi +; RUN: llvm-as < %s | llc -march=ppc64 | \ +; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4 +; RUN: llvm-as < %s | llc -march=ppc64 | not grep rlwinm +; RUN: llvm-as < %s | llc -march=ppc64 | not grep rlwimi + +define void @STWBRX(i32 %i, i8* %ptr, i32 %off) { + %tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1] + %tmp1.upgrd.1 = bitcast i8* %tmp1 to i32* ; <i32*> [#uses=1] + %tmp13 = tail call i32 @llvm.bswap.i32( i32 %i ) ; <i32> [#uses=1] + store i32 %tmp13, i32* %tmp1.upgrd.1 + ret void +} + +define i32 @LWBRX(i8* %ptr, i32 %off) { + %tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1] + %tmp1.upgrd.2 = bitcast i8* %tmp1 to i32* ; <i32*> [#uses=1] + %tmp = load i32* %tmp1.upgrd.2 ; <i32> [#uses=1] + %tmp14 = tail call i32 @llvm.bswap.i32( i32 %tmp ) ; <i32> [#uses=1] + ret i32 %tmp14 +} + +define void @STHBRX(i16 %s, i8* %ptr, i32 %off) { + %tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1] + %tmp1.upgrd.3 = bitcast i8* %tmp1 to i16* ; <i16*> [#uses=1] + %tmp5 = call i16 @llvm.bswap.i16( i16 %s ) ; <i16> [#uses=1] + store i16 %tmp5, i16* %tmp1.upgrd.3 + ret void +} + +define i16 @LHBRX(i8* %ptr, i32 %off) { + %tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1] + %tmp1.upgrd.4 = bitcast i8* %tmp1 to i16* ; <i16*> [#uses=1] + %tmp = load i16* %tmp1.upgrd.4 ; <i16> [#uses=1] + %tmp6 = call i16 @llvm.bswap.i16( i16 %tmp ) ; <i16> [#uses=1] + ret i16 %tmp6 +} + +declare i32 @llvm.bswap.i32(i32) + +declare i16 @llvm.bswap.i16(i16) + diff --git a/test/CodeGen/PowerPC/buildvec_canonicalize.ll b/test/CodeGen/PowerPC/buildvec_canonicalize.ll new file mode 100644 index 000000000000..66428c77e45a --- /dev/null +++ b/test/CodeGen/PowerPC/buildvec_canonicalize.ll @@ -0,0 +1,26 @@ +; There should be exactly one vxor here. +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \ +; RUN: grep vxor | count 1 + +; There should be exactly one vsplti here. +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mcpu=g5 --enable-unsafe-fp-math | \ +; RUN: grep vsplti | count 1 + +define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) { + %tmp = load <4 x float>* %P3 ; <<4 x float>> [#uses=1] + %tmp3 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %tmp4 = mul <4 x float> %tmp, %tmp3 ; <<4 x float>> [#uses=1] + store <4 x float> %tmp4, <4 x float>* %P3 + store <4 x float> zeroinitializer, <4 x float>* %P1 + store <4 x i32> zeroinitializer, <4 x i32>* %P2 + ret void +} + +define void @VSPLTI(<4 x i32>* %P2, <8 x i16>* %P3) { + store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), <4 x i32>* %P2 + store <8 x i16> < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >, <8 x i16>* %P3 + ret void +} + diff --git a/test/CodeGen/PowerPC/calls.ll b/test/CodeGen/PowerPC/calls.ll new file mode 100644 index 000000000000..034c14147a29 --- /dev/null +++ b/test/CodeGen/PowerPC/calls.ll @@ -0,0 +1,32 @@ +; Test various forms of calls. + +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep {bl } | count 2 +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep {bctrl} | count 1 +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep {bla } | count 1 + +declare void @foo() + +define void @test_direct() { + call void @foo( ) + ret void +} + +define void @test_extsym(i8* %P) { + free i8* %P + ret void +} + +define void @test_indirect(void ()* %fp) { + call void %fp( ) + ret void +} + +define void @test_abs() { + %fp = inttoptr i32 400 to void ()* ; <void ()*> [#uses=1] + call void %fp( ) + ret void +} + diff --git a/test/CodeGen/PowerPC/cmp-cmp.ll b/test/CodeGen/PowerPC/cmp-cmp.ll new file mode 100644 index 000000000000..07964d5aa315 --- /dev/null +++ b/test/CodeGen/PowerPC/cmp-cmp.ll @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep mfcr + +define void @test(i64 %X) { + %tmp1 = and i64 %X, 3 ; <i64> [#uses=1] + %tmp = icmp sgt i64 %tmp1, 2 ; <i1> [#uses=1] + br i1 %tmp, label %UnifiedReturnBlock, label %cond_true +cond_true: ; preds = %0 + tail call void @test( i64 0 ) + ret void +UnifiedReturnBlock: ; preds = %0 + ret void +} + diff --git a/test/CodeGen/PowerPC/compare-duplicate.ll b/test/CodeGen/PowerPC/compare-duplicate.ll new file mode 100644 index 000000000000..df2dfdc17b64 --- /dev/null +++ b/test/CodeGen/PowerPC/compare-duplicate.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin8 | not grep slwi + +define i32 @test(i32 %A, i32 %B) { + %C = sub i32 %B, %A + %D = icmp eq i32 %C, %A + br i1 %D, label %T, label %F +T: + ret i32 19123 +F: + ret i32 %C +} diff --git a/test/CodeGen/PowerPC/compare-simm.ll b/test/CodeGen/PowerPC/compare-simm.ll new file mode 100644 index 000000000000..b0ef2d3f9464 --- /dev/null +++ b/test/CodeGen/PowerPC/compare-simm.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {cmpwi cr0, r3, -1} + +define i32 @test(i32 %x) { + %c = icmp eq i32 %x, -1 + br i1 %c, label %T, label %F +T: + %A = call i32 @test(i32 123) + %B = add i32 %A, 43 + ret i32 %B +F: + %G = add i32 %x, 1234 + ret i32 %G +} diff --git a/test/CodeGen/PowerPC/constants.ll b/test/CodeGen/PowerPC/constants.ll new file mode 100644 index 000000000000..b58f59a7eb55 --- /dev/null +++ b/test/CodeGen/PowerPC/constants.ll @@ -0,0 +1,52 @@ +; All of these routines should be perform optimal load of constants. +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep lis | count 5 +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep ori | count 3 +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep {li } | count 4 + +define i32 @f1() { +entry: + ret i32 1 +} + +define i32 @f2() { +entry: + ret i32 -1 +} + +define i32 @f3() { +entry: + ret i32 0 +} + +define i32 @f4() { +entry: + ret i32 32767 +} + +define i32 @f5() { +entry: + ret i32 65535 +} + +define i32 @f6() { +entry: + ret i32 65536 +} + +define i32 @f7() { +entry: + ret i32 131071 +} + +define i32 @f8() { +entry: + ret i32 2147483647 +} + +define i32 @f9() { +entry: + ret i32 -2147483648 +} diff --git a/test/CodeGen/PowerPC/cr_spilling.ll b/test/CodeGen/PowerPC/cr_spilling.ll new file mode 100644 index 000000000000..4584c7118237 --- /dev/null +++ b/test/CodeGen/PowerPC/cr_spilling.ll @@ -0,0 +1,27 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o - +; PR1638 + +@.str242 = external constant [3 x i8] ; <[3 x i8]*> [#uses=1] + +define fastcc void @ParseContent(i8* %buf, i32 %bufsize) { +entry: + %items = alloca [10000 x i8*], align 16 ; <[10000 x i8*]*> [#uses=0] + %tmp86 = add i32 0, -1 ; <i32> [#uses=1] + br i1 false, label %cond_true94, label %cond_next99 + +cond_true94: ; preds = %entry + %tmp98 = call i32 (i8*, ...)* @printf(i8* getelementptr ([3 x i8]* @.str242, i32 0, i32 0), i8* null) ; <i32> [#uses=0] + %tmp20971 = icmp sgt i32 %tmp86, 0 ; <i1> [#uses=1] + br i1 %tmp20971, label %bb101, label %bb212 + +cond_next99: ; preds = %entry + ret void + +bb101: ; preds = %cond_true94 + ret void + +bb212: ; preds = %cond_true94 + ret void +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/PowerPC/cttz.ll b/test/CodeGen/PowerPC/cttz.ll new file mode 100644 index 000000000000..2c51e8afa558 --- /dev/null +++ b/test/CodeGen/PowerPC/cttz.ll @@ -0,0 +1,11 @@ +; Make sure this testcase does not use ctpop +; RUN: llvm-as < %s | llc -march=ppc32 | grep -i cntlzw + +declare i32 @llvm.cttz.i32(i32) + +define i32 @bar(i32 %x) { +entry: + %tmp.1 = call i32 @llvm.cttz.i32( i32 %x ) ; <i32> [#uses=1] + ret i32 %tmp.1 +} + diff --git a/test/CodeGen/PowerPC/darwin-labels.ll b/test/CodeGen/PowerPC/darwin-labels.ll new file mode 100644 index 000000000000..ceebc7099e4e --- /dev/null +++ b/test/CodeGen/PowerPC/darwin-labels.ll @@ -0,0 +1,6 @@ +; RUN: llvm-as < %s | llc | grep {foo bar":} + +target datalayout = "E-p:32:32" +target triple = "powerpc-apple-darwin8.2.0" +@"foo bar" = global i32 4 ; <i32*> [#uses=0] + diff --git a/test/CodeGen/PowerPC/delete-node.ll b/test/CodeGen/PowerPC/delete-node.ll new file mode 100644 index 000000000000..0b1d734f8a8c --- /dev/null +++ b/test/CodeGen/PowerPC/delete-node.ll @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + +; The DAGCombiner leaves behind a dead node in this testcase. Currently +; ISel is ignoring dead nodes, though it would be preferable for +; DAGCombiner to be able to eliminate the dead node. + +define void @GrayATo32ARGBTabB(i8* %baseAddr, i16** %cmp, i32 %rowBytes) nounwind { +entry: + br label %bb1 + +bb1: ; preds = %bb1, %entry + %0 = load i16* null, align 2 ; <i16> [#uses=1] + %1 = ashr i16 %0, 4 ; <i16> [#uses=1] + %2 = sext i16 %1 to i32 ; <i32> [#uses=1] + %3 = getelementptr i8* null, i32 %2 ; <i8*> [#uses=1] + %4 = load i8* %3, align 1 ; <i8> [#uses=1] + %5 = zext i8 %4 to i32 ; <i32> [#uses=1] + %6 = shl i32 %5, 24 ; <i32> [#uses=1] + %7 = or i32 0, %6 ; <i32> [#uses=1] + store i32 %7, i32* null, align 4 + br label %bb1 +} diff --git a/test/CodeGen/PowerPC/dg.exp b/test/CodeGen/PowerPC/dg.exp new file mode 100644 index 000000000000..9e50b558aa34 --- /dev/null +++ b/test/CodeGen/PowerPC/dg.exp @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target PowerPC] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] +} diff --git a/test/CodeGen/PowerPC/div-2.ll b/test/CodeGen/PowerPC/div-2.ll new file mode 100644 index 000000000000..26e622178408 --- /dev/null +++ b/test/CodeGen/PowerPC/div-2.ll @@ -0,0 +1,30 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep srawi +; RUN: llvm-as < %s | llc -march=ppc32 | grep blr + +define i32 @test1(i32 %X) { + %Y = and i32 %X, 15 ; <i32> [#uses=1] + %Z = sdiv i32 %Y, 4 ; <i32> [#uses=1] + ret i32 %Z +} + +define i32 @test2(i32 %W) { + %X = and i32 %W, 15 ; <i32> [#uses=1] + %Y = sub i32 16, %X ; <i32> [#uses=1] + %Z = sdiv i32 %Y, 4 ; <i32> [#uses=1] + ret i32 %Z +} + +define i32 @test3(i32 %W) { + %X = and i32 %W, 15 ; <i32> [#uses=1] + %Y = sub i32 15, %X ; <i32> [#uses=1] + %Z = sdiv i32 %Y, 4 ; <i32> [#uses=1] + ret i32 %Z +} + +define i32 @test4(i32 %W) { + %X = and i32 %W, 2 ; <i32> [#uses=1] + %Y = sub i32 5, %X ; <i32> [#uses=1] + %Z = sdiv i32 %Y, 2 ; <i32> [#uses=1] + ret i32 %Z +} + diff --git a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll new file mode 100644 index 000000000000..7be8a34be7ef --- /dev/null +++ b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll @@ -0,0 +1,93 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep eqv | count 3 +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \ +; RUN: grep andc | count 3 +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep orc | count 2 +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \ +; RUN: grep nor | count 3 +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep nand | count 1 + +define i32 @EQV1(i32 %X, i32 %Y) { + %A = xor i32 %X, %Y ; <i32> [#uses=1] + %B = xor i32 %A, -1 ; <i32> [#uses=1] + ret i32 %B +} + +define i32 @EQV2(i32 %X, i32 %Y) { + %A = xor i32 %X, -1 ; <i32> [#uses=1] + %B = xor i32 %A, %Y ; <i32> [#uses=1] + ret i32 %B +} + +define i32 @EQV3(i32 %X, i32 %Y) { + %A = xor i32 %X, -1 ; <i32> [#uses=1] + %B = xor i32 %Y, %A ; <i32> [#uses=1] + ret i32 %B +} + +define i32 @ANDC1(i32 %X, i32 %Y) { + %A = xor i32 %Y, -1 ; <i32> [#uses=1] + %B = and i32 %X, %A ; <i32> [#uses=1] + ret i32 %B +} + +define i32 @ANDC2(i32 %X, i32 %Y) { + %A = xor i32 %X, -1 ; <i32> [#uses=1] + %B = and i32 %A, %Y ; <i32> [#uses=1] + ret i32 %B +} + +define i32 @ORC1(i32 %X, i32 %Y) { + %A = xor i32 %Y, -1 ; <i32> [#uses=1] + %B = or i32 %X, %A ; <i32> [#uses=1] + ret i32 %B +} + +define i32 @ORC2(i32 %X, i32 %Y) { + %A = xor i32 %X, -1 ; <i32> [#uses=1] + %B = or i32 %A, %Y ; <i32> [#uses=1] + ret i32 %B +} + +define i32 @NOR1(i32 %X) { + %Y = xor i32 %X, -1 ; <i32> [#uses=1] + ret i32 %Y +} + +define i32 @NOR2(i32 %X, i32 %Y) { + %Z = or i32 %X, %Y ; <i32> [#uses=1] + %R = xor i32 %Z, -1 ; <i32> [#uses=1] + ret i32 %R +} + +define i32 @NAND1(i32 %X, i32 %Y) { + %Z = and i32 %X, %Y ; <i32> [#uses=1] + %W = xor i32 %Z, -1 ; <i32> [#uses=1] + ret i32 %W +} + +define void @VNOR(<4 x float>* %P, <4 x float>* %Q) { + %tmp = load <4 x float>* %P ; <<4 x float>> [#uses=1] + %tmp.upgrd.1 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp2 = load <4 x float>* %Q ; <<4 x float>> [#uses=1] + %tmp2.upgrd.2 = bitcast <4 x float> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp3 = or <4 x i32> %tmp.upgrd.1, %tmp2.upgrd.2 ; <<4 x i32>> [#uses=1] + %tmp4 = xor <4 x i32> %tmp3, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] + %tmp4.upgrd.3 = bitcast <4 x i32> %tmp4 to <4 x float> ; <<4 x float>> [#uses=1] + store <4 x float> %tmp4.upgrd.3, <4 x float>* %P + ret void +} + +define void @VANDC(<4 x float>* %P, <4 x float>* %Q) { + %tmp = load <4 x float>* %P ; <<4 x float>> [#uses=1] + %tmp.upgrd.4 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp2 = load <4 x float>* %Q ; <<4 x float>> [#uses=1] + %tmp2.upgrd.5 = bitcast <4 x float> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp4 = xor <4 x i32> %tmp2.upgrd.5, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] + %tmp3 = and <4 x i32> %tmp.upgrd.4, %tmp4 ; <<4 x i32>> [#uses=1] + %tmp4.upgrd.6 = bitcast <4 x i32> %tmp3 to <4 x float> ; <<4 x float>> [#uses=1] + store <4 x float> %tmp4.upgrd.6, <4 x float>* %P + ret void +} diff --git a/test/CodeGen/PowerPC/extsh.ll b/test/CodeGen/PowerPC/extsh.ll new file mode 100644 index 000000000000..5eca8cea3606 --- /dev/null +++ b/test/CodeGen/PowerPC/extsh.ll @@ -0,0 +1,8 @@ +; This should turn into a single extsh +; RUN: llvm-as < %s | llc -march=ppc32 | grep extsh | count 1 +define i32 @test(i32 %X) { + %tmp.81 = shl i32 %X, 16 ; <i32> [#uses=1] + %tmp.82 = ashr i32 %tmp.81, 16 ; <i32> [#uses=1] + ret i32 %tmp.82 +} + diff --git a/test/CodeGen/PowerPC/fabs.ll b/test/CodeGen/PowerPC/fabs.ll new file mode 100644 index 000000000000..54e49b009ace --- /dev/null +++ b/test/CodeGen/PowerPC/fabs.ll @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin | grep {fabs f1, f1} + +define double @fabs(double %f) { +entry: + %tmp2 = tail call double @fabs( double %f ) ; <double> [#uses=1] + ret double %tmp2 +} diff --git a/test/CodeGen/PowerPC/fma.ll b/test/CodeGen/PowerPC/fma.ll new file mode 100644 index 000000000000..fd9bd7400759 --- /dev/null +++ b/test/CodeGen/PowerPC/fma.ll @@ -0,0 +1,54 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: egrep {fn?madd|fn?msub} | count 8 + +define double @test_FMADD1(double %A, double %B, double %C) { + %D = mul double %A, %B ; <double> [#uses=1] + %E = add double %D, %C ; <double> [#uses=1] + ret double %E +} + +define double @test_FMADD2(double %A, double %B, double %C) { + %D = mul double %A, %B ; <double> [#uses=1] + %E = add double %D, %C ; <double> [#uses=1] + ret double %E +} + +define double @test_FMSUB(double %A, double %B, double %C) { + %D = mul double %A, %B ; <double> [#uses=1] + %E = sub double %D, %C ; <double> [#uses=1] + ret double %E +} + +define double @test_FNMADD1(double %A, double %B, double %C) { + %D = mul double %A, %B ; <double> [#uses=1] + %E = add double %D, %C ; <double> [#uses=1] + %F = sub double -0.000000e+00, %E ; <double> [#uses=1] + ret double %F +} + +define double @test_FNMADD2(double %A, double %B, double %C) { + %D = mul double %A, %B ; <double> [#uses=1] + %E = add double %C, %D ; <double> [#uses=1] + %F = sub double -0.000000e+00, %E ; <double> [#uses=1] + ret double %F +} + +define double @test_FNMSUB1(double %A, double %B, double %C) { + %D = mul double %A, %B ; <double> [#uses=1] + %E = sub double %C, %D ; <double> [#uses=1] + ret double %E +} + +define double @test_FNMSUB2(double %A, double %B, double %C) { + %D = mul double %A, %B ; <double> [#uses=1] + %E = sub double %D, %C ; <double> [#uses=1] + %F = sub double -0.000000e+00, %E ; <double> [#uses=1] + ret double %F +} + +define float @test_FNMSUBS(float %A, float %B, float %C) { + %D = mul float %A, %B ; <float> [#uses=1] + %E = sub float %D, %C ; <float> [#uses=1] + %F = sub float -0.000000e+00, %E ; <float> [#uses=1] + ret float %F +} diff --git a/test/CodeGen/PowerPC/fnabs.ll b/test/CodeGen/PowerPC/fnabs.ll new file mode 100644 index 000000000000..b9517de28f9d --- /dev/null +++ b/test/CodeGen/PowerPC/fnabs.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep fnabs + +declare double @fabs(double) + +define double @test(double %X) { + %Y = call double @fabs( double %X ) ; <double> [#uses=1] + %Z = sub double -0.000000e+00, %Y ; <double> [#uses=1] + ret double %Z +} + diff --git a/test/CodeGen/PowerPC/fneg.ll b/test/CodeGen/PowerPC/fneg.ll new file mode 100644 index 000000000000..a4f49f7625c7 --- /dev/null +++ b/test/CodeGen/PowerPC/fneg.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep fneg + +define double @test1(double %a, double %b, double %c, double %d) { +entry: + %tmp2 = sub double -0.000000e+00, %c ; <double> [#uses=1] + %tmp4 = mul double %tmp2, %d ; <double> [#uses=1] + %tmp7 = mul double %a, %b ; <double> [#uses=1] + %tmp9 = sub double %tmp7, %tmp4 ; <double> [#uses=1] + ret double %tmp9 +} + + diff --git a/test/CodeGen/PowerPC/fold-li.ll b/test/CodeGen/PowerPC/fold-li.ll new file mode 100644 index 000000000000..2ac79f149131 --- /dev/null +++ b/test/CodeGen/PowerPC/fold-li.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | \ +; RUN: grep -v align | not grep li + +;; Test that immediates are folded into these instructions correctly. + +define i32 @ADD(i32 %X) nounwind { + %Y = add i32 %X, 65537 ; <i32> [#uses=1] + ret i32 %Y +} + +define i32 @SUB(i32 %X) nounwind { + %Y = sub i32 %X, 65537 ; <i32> [#uses=1] + ret i32 %Y +} + diff --git a/test/CodeGen/PowerPC/fp-branch.ll b/test/CodeGen/PowerPC/fp-branch.ll new file mode 100644 index 000000000000..3db6ced572fe --- /dev/null +++ b/test/CodeGen/PowerPC/fp-branch.ll @@ -0,0 +1,21 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep fcmp | count 1 + +declare i1 @llvm.isunordered.f64(double, double) + +define i1 @intcoord_cond_next55(double %tmp48.reload) { +newFuncRoot: + br label %cond_next55 + +bb72.exitStub: ; preds = %cond_next55 + ret i1 true + +cond_next62.exitStub: ; preds = %cond_next55 + ret i1 false + +cond_next55: ; preds = %newFuncRoot + %tmp57 = fcmp oge double %tmp48.reload, 1.000000e+00 ; <i1> [#uses=1] + %tmp58 = fcmp uno double %tmp48.reload, 1.000000e+00 ; <i1> [#uses=1] + %tmp59 = or i1 %tmp57, %tmp58 ; <i1> [#uses=1] + br i1 %tmp59, label %bb72.exitStub, label %cond_next62.exitStub +} + diff --git a/test/CodeGen/PowerPC/fp-int-fp.ll b/test/CodeGen/PowerPC/fp-int-fp.ll new file mode 100644 index 000000000000..1b78b01e6c93 --- /dev/null +++ b/test/CodeGen/PowerPC/fp-int-fp.ll @@ -0,0 +1,27 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep r1 + +define double @test1(double %X) { + %Y = fptosi double %X to i64 ; <i64> [#uses=1] + %Z = sitofp i64 %Y to double ; <double> [#uses=1] + ret double %Z +} + +define float @test2(double %X) { + %Y = fptosi double %X to i64 ; <i64> [#uses=1] + %Z = sitofp i64 %Y to float ; <float> [#uses=1] + ret float %Z +} + +define double @test3(float %X) { + %Y = fptosi float %X to i64 ; <i64> [#uses=1] + %Z = sitofp i64 %Y to double ; <double> [#uses=1] + ret double %Z +} + +define float @test4(float %X) { + %Y = fptosi float %X to i64 ; <i64> [#uses=1] + %Z = sitofp i64 %Y to float ; <float> [#uses=1] + ret float %Z +} + + diff --git a/test/CodeGen/PowerPC/fp_to_uint.ll b/test/CodeGen/PowerPC/fp_to_uint.ll new file mode 100644 index 000000000000..43502bbb3ef0 --- /dev/null +++ b/test/CodeGen/PowerPC/fp_to_uint.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep fctiwz | count 1 + +define i16 @foo(float %a) { +entry: + %tmp.1 = fptoui float %a to i16 ; <i16> [#uses=1] + ret i16 %tmp.1 +} + diff --git a/test/CodeGen/PowerPC/fpcopy.ll b/test/CodeGen/PowerPC/fpcopy.ll new file mode 100644 index 000000000000..7d8059645ad2 --- /dev/null +++ b/test/CodeGen/PowerPC/fpcopy.ll @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep fmr + +define double @test(float %F) { + %F.upgrd.1 = fpext float %F to double ; <double> [#uses=1] + ret double %F.upgrd.1 +} + diff --git a/test/CodeGen/PowerPC/frounds.ll b/test/CodeGen/PowerPC/frounds.ll new file mode 100644 index 000000000000..0d8e621f354f --- /dev/null +++ b/test/CodeGen/PowerPC/frounds.ll @@ -0,0 +1,19 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + +define i32 @foo() { +entry: + %retval = alloca i32 ; <i32*> [#uses=2] + %tmp = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + %tmp1 = call i32 @llvm.flt.rounds( ) ; <i32> [#uses=1] + store i32 %tmp1, i32* %tmp, align 4 + %tmp2 = load i32* %tmp, align 4 ; <i32> [#uses=1] + store i32 %tmp2, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval3 = load i32* %retval ; <i32> [#uses=1] + ret i32 %retval3 +} + +declare i32 @llvm.flt.rounds() nounwind diff --git a/test/CodeGen/PowerPC/fsqrt.ll b/test/CodeGen/PowerPC/fsqrt.ll new file mode 100644 index 000000000000..1260c602f9d9 --- /dev/null +++ b/test/CodeGen/PowerPC/fsqrt.ll @@ -0,0 +1,23 @@ +; fsqrt should be generated when the fsqrt feature is enabled, but not +; otherwise. + +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \ +; RUN: grep {fsqrt f1, f1} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \ +; RUN: grep {fsqrt f1, f1} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \ +; RUN: not grep {fsqrt f1, f1} +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \ +; RUN: not grep {fsqrt f1, f1} + +declare double @llvm.sqrt.f64(double) + +define double @X(double %Y) { + %Z = call double @llvm.sqrt.f64( double %Y ) ; <double> [#uses=1] + ret double %Z +} + diff --git a/test/CodeGen/PowerPC/hello.ll b/test/CodeGen/PowerPC/hello.ll new file mode 100644 index 000000000000..1d7275f238bb --- /dev/null +++ b/test/CodeGen/PowerPC/hello.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llvm-as < %s | llc -march=ppc64 +; PR1399 + +@.str = internal constant [13 x i8] c"Hello World!\00" + +define i32 @main() { + %tmp2 = tail call i32 @puts( i8* getelementptr ([13 x i8]* @.str, i32 0, i64 0) ) + ret i32 0 +} + +declare i32 @puts(i8*) diff --git a/test/CodeGen/PowerPC/hidden-vis-2.ll b/test/CodeGen/PowerPC/hidden-vis-2.ll new file mode 100644 index 000000000000..4c9ae552f7c7 --- /dev/null +++ b/test/CodeGen/PowerPC/hidden-vis-2.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin9 | grep non_lazy_ptr | count 6 + +@x = external hidden global i32 ; <i32*> [#uses=1] +@y = extern_weak hidden global i32 ; <i32*> [#uses=1] + +define i32 @t() nounwind readonly { +entry: + %0 = load i32* @x, align 4 ; <i32> [#uses=1] + %1 = load i32* @y, align 4 ; <i32> [#uses=1] + %2 = add i32 %1, %0 ; <i32> [#uses=1] + ret i32 %2 +} diff --git a/test/CodeGen/PowerPC/hidden-vis.ll b/test/CodeGen/PowerPC/hidden-vis.ll new file mode 100644 index 000000000000..e04c89aebcc2 --- /dev/null +++ b/test/CodeGen/PowerPC/hidden-vis.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin9 | not grep non_lazy_ptr + +@x = weak hidden global i32 0 ; <i32*> [#uses=1] + +define i32 @t() nounwind readonly { +entry: + %0 = load i32* @x, align 4 ; <i32> [#uses=1] + ret i32 %0 +} diff --git a/test/CodeGen/PowerPC/i128-and-beyond.ll b/test/CodeGen/PowerPC/i128-and-beyond.ll new file mode 100644 index 000000000000..9e0d6c30b8c7 --- /dev/null +++ b/test/CodeGen/PowerPC/i128-and-beyond.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep 4294967295 | count 28 + +; These static initializers are too big to hand off to assemblers +; as monolithic blobs. + +@x = global i128 -1 +@y = global i256 -1 +@z = global i512 -1 diff --git a/test/CodeGen/PowerPC/i64_fp.ll b/test/CodeGen/PowerPC/i64_fp.ll new file mode 100644 index 000000000000..5ff2684d7b00 --- /dev/null +++ b/test/CodeGen/PowerPC/i64_fp.ll @@ -0,0 +1,26 @@ +; fcfid and fctid should be generated when the 64bit feature is enabled, but not +; otherwise. + +; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+64bit | \ +; RUN: grep fcfid +; RUN: llvm-as < %s | llc -march=ppc32 -mattr=+64bit | \ +; RUN: grep fctidz +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \ +; RUN: grep fcfid +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | \ +; RUN: grep fctidz +; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | \ +; RUN: not grep fcfid +; RUN: llvm-as < %s | llc -march=ppc32 -mattr=-64bit | \ +; RUN: not grep fctidz +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g4 | \ +; RUN: not grep fcfid +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g4 | \ +; RUN: not grep fctidz + +define double @X(double %Y) { + %A = fptosi double %Y to i64 ; <i64> [#uses=1] + %B = sitofp i64 %A to double ; <double> [#uses=1] + ret double %B +} + diff --git a/test/CodeGen/PowerPC/iabs.ll b/test/CodeGen/PowerPC/iabs.ll new file mode 100644 index 000000000000..677b41bb12e1 --- /dev/null +++ b/test/CodeGen/PowerPC/iabs.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -stats |& \ +; RUN: grep {4 .*Number of machine instrs printed} + +;; Integer absolute value, should produce something as good as: +;; srawi r2, r3, 31 +;; add r3, r3, r2 +;; xor r3, r3, r2 +;; blr +define i32 @test(i32 %a) { + %tmp1neg = sub i32 0, %a + %b = icmp sgt i32 %a, -1 + %abs = select i1 %b, i32 %a, i32 %tmp1neg + ret i32 %abs +} + diff --git a/test/CodeGen/PowerPC/illegal-element-type.ll b/test/CodeGen/PowerPC/illegal-element-type.ll new file mode 100644 index 000000000000..54a06656b1b9 --- /dev/null +++ b/test/CodeGen/PowerPC/illegal-element-type.ll @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 + +define void @foo() { +entry: + br label %bb + +bb: ; preds = %bb, %entry + br i1 false, label %bb26, label %bb + +bb19: ; preds = %bb26 + ret void + +bb26: ; preds = %bb + br i1 false, label %bb30, label %bb19 + +bb30: ; preds = %bb26 + br label %bb45 + +bb45: ; preds = %bb45, %bb30 + %V.0 = phi <8 x i16> [ %tmp42, %bb45 ], [ zeroinitializer, %bb30 ] ; <<8 x i16>> [#uses=1] + %tmp42 = mul <8 x i16> zeroinitializer, %V.0 ; <<8 x i16>> [#uses=1] + br label %bb45 +} diff --git a/test/CodeGen/PowerPC/inlineasm-copy.ll b/test/CodeGen/PowerPC/inlineasm-copy.ll new file mode 100644 index 000000000000..c0a397982adf --- /dev/null +++ b/test/CodeGen/PowerPC/inlineasm-copy.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep mr + +define i32 @test(i32 %Y, i32 %X) { +entry: + %tmp = tail call i32 asm "foo $0", "=r"( ) ; <i32> [#uses=1] + ret i32 %tmp +} + +define i32 @test2(i32 %Y, i32 %X) { +entry: + %tmp1 = tail call i32 asm "foo $0, $1", "=r,r"( i32 %X ) ; <i32> [#uses=1] + ret i32 %tmp1 +} + diff --git a/test/CodeGen/PowerPC/int-fp-conv-0.ll b/test/CodeGen/PowerPC/int-fp-conv-0.ll new file mode 100644 index 000000000000..3dfc4b10bc5c --- /dev/null +++ b/test/CodeGen/PowerPC/int-fp-conv-0.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=ppc64 -debug |& not grep {= store} +; RUN: llvm-as < %s | llc -march=ppc64 > %t +; RUN: grep __floattitf %t +; RUN: grep __fixunstfti %t + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc64-apple-darwin9.2.0" + +define ppc_fp128 @foo(i128 %a) nounwind { +entry: + %tmp2829 = uitofp i128 %a to ppc_fp128 ; <i64> [#uses=1] + ret ppc_fp128 %tmp2829 +} +define i128 @boo(ppc_fp128 %a) nounwind { +entry: + %tmp2829 = fptoui ppc_fp128 %a to i128 ; <i64> [#uses=1] + ret i128 %tmp2829 +} diff --git a/test/CodeGen/PowerPC/int-fp-conv-1.ll b/test/CodeGen/PowerPC/int-fp-conv-1.ll new file mode 100644 index 000000000000..3d6667539f24 --- /dev/null +++ b/test/CodeGen/PowerPC/int-fp-conv-1.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=ppc64 | grep __floatditf + +define i64 @__fixunstfdi(ppc_fp128 %a) nounwind { +entry: + %tmp1213 = uitofp i64 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %tmp15 = sub ppc_fp128 %a, %tmp1213 ; <ppc_fp128> [#uses=1] + %tmp2829 = fptoui ppc_fp128 %tmp15 to i32 ; <i32> [#uses=1] + %tmp282930 = zext i32 %tmp2829 to i64 ; <i64> [#uses=1] + %tmp32 = add i64 %tmp282930, 0 ; <i64> [#uses=1] + ret i64 %tmp32 +} diff --git a/test/CodeGen/PowerPC/invalid-memcpy.ll b/test/CodeGen/PowerPC/invalid-memcpy.ll new file mode 100644 index 000000000000..6df968dddae5 --- /dev/null +++ b/test/CodeGen/PowerPC/invalid-memcpy.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llvm-as < %s | llc -march=ppc64 + +; This testcase is invalid (the alignment specified for memcpy is +; greater than the alignment guaranteed for Qux or C.0.1173, but it +; should compile, not crash the code generator. + +@C.0.1173 = external constant [33 x i8] ; <[33 x i8]*> [#uses=1] + +define void @Bork() { +entry: + %Qux = alloca [33 x i8] ; <[33 x i8]*> [#uses=1] + %Qux1 = bitcast [33 x i8]* %Qux to i8* ; <i8*> [#uses=1] + call void @llvm.memcpy.i64( i8* %Qux1, i8* getelementptr ([33 x i8]* @C.0.1173, i32 0, i32 0), i64 33, i32 8 ) + ret void +} + +declare void @llvm.memcpy.i64(i8*, i8*, i64, i32) + + diff --git a/test/CodeGen/PowerPC/inverted-bool-compares.ll b/test/CodeGen/PowerPC/inverted-bool-compares.ll new file mode 100644 index 000000000000..f8c5f11180ca --- /dev/null +++ b/test/CodeGen/PowerPC/inverted-bool-compares.ll @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep xori + +define i32 @test(i1 %B, i32* %P) { + br i1 %B, label %T, label %F + +T: ; preds = %0 + store i32 123, i32* %P + ret i32 0 + +F: ; preds = %0 + ret i32 17 +} + diff --git a/test/CodeGen/PowerPC/ispositive.ll b/test/CodeGen/PowerPC/ispositive.ll new file mode 100644 index 000000000000..192d7384e953 --- /dev/null +++ b/test/CodeGen/PowerPC/ispositive.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {srwi r3, r3, 31} + +define i32 @test1(i32 %X) { +entry: + icmp slt i32 %X, 0 ; <i1>:0 [#uses=1] + zext i1 %0 to i32 ; <i32>:1 [#uses=1] + ret i32 %1 +} + diff --git a/test/CodeGen/PowerPC/itofp128.ll b/test/CodeGen/PowerPC/itofp128.ll new file mode 100644 index 000000000000..91119e9e8ef5 --- /dev/null +++ b/test/CodeGen/PowerPC/itofp128.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=ppc64 + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc64-apple-darwin9.2.0" + +define i128 @__fixunstfti(ppc_fp128 %a) nounwind { +entry: + %tmp1213 = uitofp i128 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %tmp15 = sub ppc_fp128 %a, %tmp1213 ; <ppc_fp128> [#uses=1] + %tmp2829 = fptoui ppc_fp128 %tmp15 to i64 ; <i64> [#uses=1] + %tmp282930 = zext i64 %tmp2829 to i128 ; <i128> [#uses=1] + %tmp32 = add i128 %tmp282930, 0 ; <i128> [#uses=1] + ret i128 %tmp32 +} diff --git a/test/CodeGen/PowerPC/lha.ll b/test/CodeGen/PowerPC/lha.ll new file mode 100644 index 000000000000..e8f73eea2e2e --- /dev/null +++ b/test/CodeGen/PowerPC/lha.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep lha + +define i32 @test(i16* %a) { + %tmp.1 = load i16* %a ; <i16> [#uses=1] + %tmp.2 = sext i16 %tmp.1 to i32 ; <i32> [#uses=1] + ret i32 %tmp.2 +} + diff --git a/test/CodeGen/PowerPC/load-constant-addr.ll b/test/CodeGen/PowerPC/load-constant-addr.ll new file mode 100644 index 000000000000..d2be04efd036 --- /dev/null +++ b/test/CodeGen/PowerPC/load-constant-addr.ll @@ -0,0 +1,9 @@ +; Should fold the ori into the lfs. +; RUN: llvm-as < %s | llc -march=ppc32 | grep lfs +; RUN: llvm-as < %s | llc -march=ppc32 | not grep ori + +define float @test() { + %tmp.i = load float* inttoptr (i32 186018016 to float*) ; <float> [#uses=1] + ret float %tmp.i +} + diff --git a/test/CodeGen/PowerPC/long-compare.ll b/test/CodeGen/PowerPC/long-compare.ll new file mode 100644 index 000000000000..7b907250e1fc --- /dev/null +++ b/test/CodeGen/PowerPC/long-compare.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep cntlzw +; RUN: llvm-as < %s | llc -march=ppc32 | not grep xori +; RUN: llvm-as < %s | llc -march=ppc32 | not grep {li } +; RUN: llvm-as < %s | llc -march=ppc32 | not grep {mr } + +define i1 @test(i64 %x) { + %tmp = icmp ult i64 %x, 4294967296 + ret i1 %tmp +} diff --git a/test/CodeGen/PowerPC/longdbl-truncate.ll b/test/CodeGen/PowerPC/longdbl-truncate.ll new file mode 100644 index 000000000000..a87382405a5d --- /dev/null +++ b/test/CodeGen/PowerPC/longdbl-truncate.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin8" + +define double @SolveCubic(ppc_fp128 %X) { +entry: + %Y = fptrunc ppc_fp128 %X to double + ret double %Y +} diff --git a/test/CodeGen/PowerPC/mask64.ll b/test/CodeGen/PowerPC/mask64.ll new file mode 100644 index 000000000000..69d2200212f9 --- /dev/null +++ b/test/CodeGen/PowerPC/mask64.ll @@ -0,0 +1,27 @@ +; RUN: llvm-as < %s | llc + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc64-apple-darwin9.2.0" + %struct.re_pattern_buffer = type <{ i8*, i64, i8, [7 x i8] }> + +define i32 @xre_search_2(%struct.re_pattern_buffer* %bufp, i32 %range) nounwind { +entry: + br i1 false, label %bb16, label %bb49 + +bb16: ; preds = %entry + %tmp19 = load i8** null, align 1 ; <i8*> [#uses=1] + %tmp21 = load i8* %tmp19, align 1 ; <i8> [#uses=1] + switch i8 %tmp21, label %bb49 [ + i8 0, label %bb45 + i8 1, label %bb34 + ] + +bb34: ; preds = %bb16 + ret i32 0 + +bb45: ; preds = %bb16 + ret i32 -1 + +bb49: ; preds = %bb16, %entry + ret i32 0 +} diff --git a/test/CodeGen/PowerPC/mem-rr-addr-mode.ll b/test/CodeGen/PowerPC/mem-rr-addr-mode.ll new file mode 100644 index 000000000000..d5484bd4b78d --- /dev/null +++ b/test/CodeGen/PowerPC/mem-rr-addr-mode.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep li.*16 +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep addi + +; Codegen lvx (R+16) as t = li 16, lvx t,R +; This shares the 16 between the two loads. + +define void @func(<4 x float>* %a, <4 x float>* %b) { + %tmp1 = getelementptr <4 x float>* %b, i32 1 ; <<4 x float>*> [#uses=1] + %tmp = load <4 x float>* %tmp1 ; <<4 x float>> [#uses=1] + %tmp3 = getelementptr <4 x float>* %a, i32 1 ; <<4 x float>*> [#uses=1] + %tmp4 = load <4 x float>* %tmp3 ; <<4 x float>> [#uses=1] + %tmp5 = mul <4 x float> %tmp, %tmp4 ; <<4 x float>> [#uses=1] + %tmp8 = load <4 x float>* %b ; <<4 x float>> [#uses=1] + %tmp9 = add <4 x float> %tmp5, %tmp8 ; <<4 x float>> [#uses=1] + store <4 x float> %tmp9, <4 x float>* %a + ret void +} + diff --git a/test/CodeGen/PowerPC/mem_update.ll b/test/CodeGen/PowerPC/mem_update.ll new file mode 100644 index 000000000000..a1527629980b --- /dev/null +++ b/test/CodeGen/PowerPC/mem_update.ll @@ -0,0 +1,68 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -enable-ppc-preinc | \ +; RUN: not grep addi +; RUN: llvm-as < %s | llc -march=ppc64 -enable-ppc-preinc | \ +; RUN: not grep addi + +@Glob = global i64 4 ; <i64*> [#uses=2] + +define i32* @test0(i32* %X, i32* %dest) { + %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2] + %A = load i32* %Y ; <i32> [#uses=1] + store i32 %A, i32* %dest + ret i32* %Y +} + +define i32* @test1(i32* %X, i32* %dest) { + %Y = getelementptr i32* %X, i32 4 ; <i32*> [#uses=2] + %A = load i32* %Y ; <i32> [#uses=1] + store i32 %A, i32* %dest + ret i32* %Y +} + +define i16* @test2(i16* %X, i32* %dest) { + %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2] + %A = load i16* %Y ; <i16> [#uses=1] + %B = sext i16 %A to i32 ; <i32> [#uses=1] + store i32 %B, i32* %dest + ret i16* %Y +} + +define i16* @test3(i16* %X, i32* %dest) { + %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2] + %A = load i16* %Y ; <i16> [#uses=1] + %B = zext i16 %A to i32 ; <i32> [#uses=1] + store i32 %B, i32* %dest + ret i16* %Y +} + +define i16* @test3a(i16* %X, i64* %dest) { + %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2] + %A = load i16* %Y ; <i16> [#uses=1] + %B = sext i16 %A to i64 ; <i64> [#uses=1] + store i64 %B, i64* %dest + ret i16* %Y +} + +define i64* @test4(i64* %X, i64* %dest) { + %Y = getelementptr i64* %X, i32 4 ; <i64*> [#uses=2] + %A = load i64* %Y ; <i64> [#uses=1] + store i64 %A, i64* %dest + ret i64* %Y +} + +define i16* @test5(i16* %X) { + %Y = getelementptr i16* %X, i32 4 ; <i16*> [#uses=2] + store i16 7, i16* %Y + ret i16* %Y +} + +define i64* @test6(i64* %X, i64 %A) { + %Y = getelementptr i64* %X, i32 4 ; <i64*> [#uses=2] + store i64 %A, i64* %Y + ret i64* %Y +} + +define i64* @test7(i64* %X, i64 %A) { + store i64 %A, i64* @Glob + ret i64* @Glob +} diff --git a/test/CodeGen/PowerPC/mul-neg-power-2.ll b/test/CodeGen/PowerPC/mul-neg-power-2.ll new file mode 100644 index 000000000000..90446d707db7 --- /dev/null +++ b/test/CodeGen/PowerPC/mul-neg-power-2.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep mul + +define i32 @test1(i32 %a) { + %tmp.1 = mul i32 %a, -2 ; <i32> [#uses=1] + %tmp.2 = add i32 %tmp.1, 63 ; <i32> [#uses=1] + ret i32 %tmp.2 +} + diff --git a/test/CodeGen/PowerPC/mulhs.ll b/test/CodeGen/PowerPC/mulhs.ll new file mode 100644 index 000000000000..3b0daad227e9 --- /dev/null +++ b/test/CodeGen/PowerPC/mulhs.ll @@ -0,0 +1,17 @@ +; All of these ands and shifts should be folded into rlwimi's +; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: not grep mulhwu %t +; RUN: not grep srawi %t +; RUN: not grep add %t +; RUN: grep mulhw %t | count 1 + +define i32 @mulhs(i32 %a, i32 %b) { +entry: + %tmp.1 = sext i32 %a to i64 ; <i64> [#uses=1] + %tmp.3 = sext i32 %b to i64 ; <i64> [#uses=1] + %tmp.4 = mul i64 %tmp.3, %tmp.1 ; <i64> [#uses=1] + %tmp.6 = lshr i64 %tmp.4, 32 ; <i64> [#uses=1] + %tmp.7 = trunc i64 %tmp.6 to i32 ; <i32> [#uses=1] + ret i32 %tmp.7 +} + diff --git a/test/CodeGen/PowerPC/multiple-return-values.ll b/test/CodeGen/PowerPC/multiple-return-values.ll new file mode 100644 index 000000000000..b72b148259dc --- /dev/null +++ b/test/CodeGen/PowerPC/multiple-return-values.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; RUN: llvm-as < %s | llc -march=ppc64 + +define {i64, float} @bar(i64 %a, float %b) { + %y = add i64 %a, 7 + %z = add float %b, 7.0 + ret i64 %y, float %z +} + +define i64 @foo() { + %M = call {i64, float} @bar(i64 21, float 21.0) + %N = getresult {i64, float} %M, 0 + %O = getresult {i64, float} %M, 1 + %P = fptosi float %O to i64 + %Q = add i64 %P, %N + ret i64 %Q +} diff --git a/test/CodeGen/PowerPC/neg.ll b/test/CodeGen/PowerPC/neg.ll new file mode 100644 index 000000000000..c13559903901 --- /dev/null +++ b/test/CodeGen/PowerPC/neg.ll @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep neg + +define i32 @test(i32 %X) { + %Y = sub i32 0, %X ; <i32> [#uses=1] + ret i32 %Y +} + diff --git a/test/CodeGen/PowerPC/no-dead-strip.ll b/test/CodeGen/PowerPC/no-dead-strip.ll new file mode 100644 index 000000000000..e7ceaaeab678 --- /dev/null +++ b/test/CodeGen/PowerPC/no-dead-strip.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc | grep {no_dead_strip.*_X} + +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "powerpc-apple-darwin8.8.0" +@X = weak global i32 0 ; <i32*> [#uses=1] +@.str = internal constant [4 x i8] c"t.c\00", section "llvm.metadata" ; <[4 x i8]*> [#uses=1] +@llvm.used = appending global [1 x i8*] [ i8* bitcast (i32* @X to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + diff --git a/test/CodeGen/PowerPC/or-addressing-mode.ll b/test/CodeGen/PowerPC/or-addressing-mode.ll new file mode 100644 index 000000000000..9b6e9551bf04 --- /dev/null +++ b/test/CodeGen/PowerPC/or-addressing-mode.ll @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin8 | not grep ori +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin8 | not grep rlwimi + +define i32 @test1(i8* %P) { + %tmp.2.i = ptrtoint i8* %P to i32 ; <i32> [#uses=2] + %tmp.4.i = and i32 %tmp.2.i, -65536 ; <i32> [#uses=1] + %tmp.10.i = lshr i32 %tmp.2.i, 5 ; <i32> [#uses=1] + %tmp.11.i = and i32 %tmp.10.i, 2040 ; <i32> [#uses=1] + %tmp.13.i = or i32 %tmp.11.i, %tmp.4.i ; <i32> [#uses=1] + %tmp.14.i = inttoptr i32 %tmp.13.i to i32* ; <i32*> [#uses=1] + %tmp.3 = load i32* %tmp.14.i ; <i32> [#uses=1] + ret i32 %tmp.3 +} + +define i32 @test2(i32 %P) { + %tmp.2 = shl i32 %P, 4 ; <i32> [#uses=1] + %tmp.3 = or i32 %tmp.2, 2 ; <i32> [#uses=1] + %tmp.4 = inttoptr i32 %tmp.3 to i32* ; <i32*> [#uses=1] + %tmp.5 = load i32* %tmp.4 ; <i32> [#uses=1] + ret i32 %tmp.5 +} + diff --git a/test/CodeGen/PowerPC/ppcf128-1-opt.ll b/test/CodeGen/PowerPC/ppcf128-1-opt.ll new file mode 100644 index 000000000000..5c059b4ea291 --- /dev/null +++ b/test/CodeGen/PowerPC/ppcf128-1-opt.ll @@ -0,0 +1,29 @@ +; RUN: llvm-as < %s | llc > %t +; ModuleID = '<stdin>' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin8" + +define ppc_fp128 @plus(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %tmp3 = add ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1] + ret ppc_fp128 %tmp3 +} + +define ppc_fp128 @minus(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %tmp3 = sub ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1] + ret ppc_fp128 %tmp3 +} + +define ppc_fp128 @times(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %tmp3 = mul ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1] + ret ppc_fp128 %tmp3 +} + +define ppc_fp128 @divide(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %tmp3 = fdiv ppc_fp128 %x, %y ; <ppc_fp128> [#uses=1] + ret ppc_fp128 %tmp3 +} + diff --git a/test/CodeGen/PowerPC/ppcf128-1.ll b/test/CodeGen/PowerPC/ppcf128-1.ll new file mode 100644 index 000000000000..ea8dd37c97d8 --- /dev/null +++ b/test/CodeGen/PowerPC/ppcf128-1.ll @@ -0,0 +1,92 @@ +; RUN: llvm-as < %s | opt -std-compile-opts | llc > %t +; ModuleID = 'ld3.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin8" + +define ppc_fp128 @plus(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2] + %y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2] + %retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2] + %tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store ppc_fp128 %x, ppc_fp128* %x_addr + store ppc_fp128 %y, ppc_fp128* %y_addr + %tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1] + %tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1] + %tmp3 = add ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1] + store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16 + %tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1] + store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16 + br label %return + +return: ; preds = %entry + %retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1] + ret ppc_fp128 %retval5 +} + +define ppc_fp128 @minus(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2] + %y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2] + %retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2] + %tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store ppc_fp128 %x, ppc_fp128* %x_addr + store ppc_fp128 %y, ppc_fp128* %y_addr + %tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1] + %tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1] + %tmp3 = sub ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1] + store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16 + %tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1] + store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16 + br label %return + +return: ; preds = %entry + %retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1] + ret ppc_fp128 %retval5 +} + +define ppc_fp128 @times(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2] + %y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2] + %retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2] + %tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store ppc_fp128 %x, ppc_fp128* %x_addr + store ppc_fp128 %y, ppc_fp128* %y_addr + %tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1] + %tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1] + %tmp3 = mul ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1] + store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16 + %tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1] + store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16 + br label %return + +return: ; preds = %entry + %retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1] + ret ppc_fp128 %retval5 +} + +define ppc_fp128 @divide(ppc_fp128 %x, ppc_fp128 %y) { +entry: + %x_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2] + %y_addr = alloca ppc_fp128 ; <ppc_fp128*> [#uses=2] + %retval = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2] + %tmp = alloca ppc_fp128, align 16 ; <ppc_fp128*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store ppc_fp128 %x, ppc_fp128* %x_addr + store ppc_fp128 %y, ppc_fp128* %y_addr + %tmp1 = load ppc_fp128* %x_addr, align 16 ; <ppc_fp128> [#uses=1] + %tmp2 = load ppc_fp128* %y_addr, align 16 ; <ppc_fp128> [#uses=1] + %tmp3 = fdiv ppc_fp128 %tmp1, %tmp2 ; <ppc_fp128> [#uses=1] + store ppc_fp128 %tmp3, ppc_fp128* %tmp, align 16 + %tmp4 = load ppc_fp128* %tmp, align 16 ; <ppc_fp128> [#uses=1] + store ppc_fp128 %tmp4, ppc_fp128* %retval, align 16 + br label %return + +return: ; preds = %entry + %retval5 = load ppc_fp128* %retval ; <ppc_fp128> [#uses=1] + ret ppc_fp128 %retval5 +} diff --git a/test/CodeGen/PowerPC/ppcf128-2.ll b/test/CodeGen/PowerPC/ppcf128-2.ll new file mode 100644 index 000000000000..b4f61f89fb64 --- /dev/null +++ b/test/CodeGen/PowerPC/ppcf128-2.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=ppc64 + +define i64 @__fixtfdi(ppc_fp128 %a) nounwind { +entry: + br i1 false, label %bb, label %bb8 +bb: ; preds = %entry + %tmp5 = sub ppc_fp128 0xM80000000000000000000000000000000, %a ; <ppc_fp128> [#uses=1] + %tmp6 = tail call i64 @__fixunstfdi( ppc_fp128 %tmp5 ) nounwind ; <i64> [#uses=0] + ret i64 0 +bb8: ; preds = %entry + ret i64 0 +} + +declare i64 @__fixunstfdi(ppc_fp128) diff --git a/test/CodeGen/PowerPC/ppcf128-3.ll b/test/CodeGen/PowerPC/ppcf128-3.ll new file mode 100644 index 000000000000..3a51f4d3dd60 --- /dev/null +++ b/test/CodeGen/PowerPC/ppcf128-3.ll @@ -0,0 +1,32 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + %struct.stp_sequence = type { double, double } + +define i32 @stp_sequence_set_short_data(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { +entry: + %tmp1112 = sitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +define i32 @stp_sequence_set_short_data2(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { +entry: + %tmp1112 = sitofp i8 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +define i32 @stp_sequence_set_short_data3(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { +entry: + %tmp1112 = uitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +define i32 @stp_sequence_set_short_data4(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { +entry: + %tmp1112 = uitofp i8 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +declare i32 @__inline_isfinite(...) diff --git a/test/CodeGen/PowerPC/ppcf128-4.ll b/test/CodeGen/PowerPC/ppcf128-4.ll new file mode 100644 index 000000000000..8921dfcd5a0d --- /dev/null +++ b/test/CodeGen/PowerPC/ppcf128-4.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + +define ppc_fp128 @__floatditf(i64 %u) nounwind { +entry: + %tmp6 = mul ppc_fp128 0xM00000000000000000000000000000000, 0xM41F00000000000000000000000000000 + %tmp78 = trunc i64 %u to i32 + %tmp789 = uitofp i32 %tmp78 to ppc_fp128 + %tmp11 = add ppc_fp128 %tmp789, %tmp6 + ret ppc_fp128 %tmp11 +} diff --git a/test/CodeGen/PowerPC/pr3711_widen_bit.ll b/test/CodeGen/PowerPC/pr3711_widen_bit.ll new file mode 100644 index 000000000000..e601e968341f --- /dev/null +++ b/test/CodeGen/PowerPC/pr3711_widen_bit.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 + +; Test that causes a abort in expanding a bit convert due to a missing support +; for widening. + +define i32 @main() nounwind { +entry: + br i1 icmp ne (i32 trunc (i64 bitcast (<2 x i32> <i32 2, i32 2> to i64) to i32), i32 2), label %bb, label %bb1 + +bb: ; preds = %entry + tail call void @abort() noreturn nounwind + unreachable + +bb1: ; preds = %entry + ret i32 0 +} + +declare void @abort() noreturn nounwind diff --git a/test/CodeGen/PowerPC/private.ll b/test/CodeGen/PowerPC/private.ll new file mode 100644 index 000000000000..0f0d13492a08 --- /dev/null +++ b/test/CodeGen/PowerPC/private.ll @@ -0,0 +1,26 @@ +; Test to make sure that the 'private' is used correctly. +; +; RUN: llvm-as < %s | llc -mtriple=powerpc-unknown-linux-gnu > %t +; RUN: grep .Lfoo: %t +; RUN: grep bl.*\.Lfoo %t +; RUN: grep .Lbaz: %t +; RUN: grep lis.*\.Lbaz %t +; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin > %t +; RUN: grep L_foo: %t +; RUN: grep bl.*\L_foo %t +; RUN: grep L_baz: %t +; RUN: grep lis.*\L_baz %t + +declare void @foo() + +define private void @foo() { + ret void +} + +@baz = private global i32 4; + +define i32 @bar() { + call void @foo() + %1 = load i32* @baz, align 4 + ret i32 %1 +} diff --git a/test/CodeGen/PowerPC/reg-coalesce-simple.ll b/test/CodeGen/PowerPC/reg-coalesce-simple.ll new file mode 100644 index 000000000000..b86ed1a6a76e --- /dev/null +++ b/test/CodeGen/PowerPC/reg-coalesce-simple.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep or + +%struct.foo = type { i32, i32, [0 x i8] } + +define i32 @test(%struct.foo* %X) nounwind { + %tmp1 = getelementptr %struct.foo* %X, i32 0, i32 2, i32 100 ; <i8*> [#uses=1] + %tmp = load i8* %tmp1 ; <i8> [#uses=1] + %tmp2 = zext i8 %tmp to i32 ; <i32> [#uses=1] + ret i32 %tmp2 +} + + diff --git a/test/CodeGen/PowerPC/retaddr.ll b/test/CodeGen/PowerPC/retaddr.ll new file mode 100644 index 000000000000..f4cad34addad --- /dev/null +++ b/test/CodeGen/PowerPC/retaddr.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep mflr +; RUN: llvm-as < %s | llc -march=ppc32 | grep lwz +; RUN: llvm-as < %s | llc -march=ppc64 | grep {ld r., 16(r1)} + +target triple = "powerpc-apple-darwin8" + +define void @foo(i8** %X) { +entry: + %tmp = tail call i8* @llvm.returnaddress( i32 0 ) ; <i8*> [#uses=1] + store i8* %tmp, i8** %X, align 4 + ret void +} + +declare i8* @llvm.returnaddress(i32) + diff --git a/test/CodeGen/PowerPC/return-val-i128.ll b/test/CodeGen/PowerPC/return-val-i128.ll new file mode 100644 index 000000000000..6e68ee3c5203 --- /dev/null +++ b/test/CodeGen/PowerPC/return-val-i128.ll @@ -0,0 +1,36 @@ +; RUN: llvm-as < %s | llc -march=ppc64 + +define i128 @__fixsfdi(float %a) { +entry: + %a_addr = alloca float ; <float*> [#uses=4] + %retval = alloca i128, align 16 ; <i128*> [#uses=2] + %tmp = alloca i128, align 16 ; <i128*> [#uses=3] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store float %a, float* %a_addr + %tmp1 = load float* %a_addr, align 4 ; <float> [#uses=1] + %tmp2 = fcmp olt float %tmp1, 0.000000e+00 ; <i1> [#uses=1] + %tmp23 = zext i1 %tmp2 to i8 ; <i8> [#uses=1] + %toBool = icmp ne i8 %tmp23, 0 ; <i1> [#uses=1] + br i1 %toBool, label %bb, label %bb8 +bb: ; preds = %entry + %tmp4 = load float* %a_addr, align 4 ; <float> [#uses=1] + %tmp5 = sub float -0.000000e+00, %tmp4 ; <float> [#uses=1] + %tmp6 = call i128 @__fixunssfDI( float %tmp5 ) nounwind ; <i128> [#uses=1] + %tmp7 = sub i128 0, %tmp6 ; <i128> [#uses=1] + store i128 %tmp7, i128* %tmp, align 16 + br label %bb11 +bb8: ; preds = %entry + %tmp9 = load float* %a_addr, align 4 ; <float> [#uses=1] + %tmp10 = call i128 @__fixunssfDI( float %tmp9 ) nounwind ; <i128> [#uses=1] + store i128 %tmp10, i128* %tmp, align 16 + br label %bb11 +bb11: ; preds = %bb8, %bb + %tmp12 = load i128* %tmp, align 16 ; <i128> [#uses=1] + store i128 %tmp12, i128* %retval, align 16 + br label %return +return: ; preds = %bb11 + %retval13 = load i128* %retval ; <i128> [#uses=1] + ret i128 %retval13 +} + +declare i128 @__fixunssfDI(float) diff --git a/test/CodeGen/PowerPC/rlwimi-commute.ll b/test/CodeGen/PowerPC/rlwimi-commute.ll new file mode 100644 index 000000000000..f8a42b514203 --- /dev/null +++ b/test/CodeGen/PowerPC/rlwimi-commute.ll @@ -0,0 +1,34 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwimi +; RUN: llvm-as < %s | llc -march=ppc32 | not grep {or } + +; Make sure there is no register-register copies here. + +define void @test1(i32* %A, i32* %B, i32* %D, i32* %E) { + %A.upgrd.1 = load i32* %A ; <i32> [#uses=2] + %B.upgrd.2 = load i32* %B ; <i32> [#uses=1] + %X = and i32 %A.upgrd.1, 15 ; <i32> [#uses=1] + %Y = and i32 %B.upgrd.2, -16 ; <i32> [#uses=1] + %Z = or i32 %X, %Y ; <i32> [#uses=1] + store i32 %Z, i32* %D + store i32 %A.upgrd.1, i32* %E + ret void +} + +define void @test2(i32* %A, i32* %B, i32* %D, i32* %E) { + %A.upgrd.3 = load i32* %A ; <i32> [#uses=1] + %B.upgrd.4 = load i32* %B ; <i32> [#uses=2] + %X = and i32 %A.upgrd.3, 15 ; <i32> [#uses=1] + %Y = and i32 %B.upgrd.4, -16 ; <i32> [#uses=1] + %Z = or i32 %X, %Y ; <i32> [#uses=1] + store i32 %Z, i32* %D + store i32 %B.upgrd.4, i32* %E + ret void +} + +define i32 @test3(i32 %a, i32 %b) { + %tmp.1 = and i32 %a, 15 ; <i32> [#uses=1] + %tmp.3 = and i32 %b, 240 ; <i32> [#uses=1] + %tmp.4 = or i32 %tmp.3, %tmp.1 ; <i32> [#uses=1] + ret i32 %tmp.4 +} + diff --git a/test/CodeGen/PowerPC/rlwimi.ll b/test/CodeGen/PowerPC/rlwimi.ll new file mode 100644 index 000000000000..5e310bb6a6ef --- /dev/null +++ b/test/CodeGen/PowerPC/rlwimi.ll @@ -0,0 +1,70 @@ +; All of these ands and shifts should be folded into rlwimi's +; RUN: llvm-as < %s | llc -march=ppc32 | not grep and +; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwimi | count 8 + +define i32 @test1(i32 %x, i32 %y) { +entry: + %tmp.3 = shl i32 %x, 16 ; <i32> [#uses=1] + %tmp.7 = and i32 %y, 65535 ; <i32> [#uses=1] + %tmp.9 = or i32 %tmp.7, %tmp.3 ; <i32> [#uses=1] + ret i32 %tmp.9 +} + +define i32 @test2(i32 %x, i32 %y) { +entry: + %tmp.7 = and i32 %x, 65535 ; <i32> [#uses=1] + %tmp.3 = shl i32 %y, 16 ; <i32> [#uses=1] + %tmp.9 = or i32 %tmp.7, %tmp.3 ; <i32> [#uses=1] + ret i32 %tmp.9 +} + +define i32 @test3(i32 %x, i32 %y) { +entry: + %tmp.3 = lshr i32 %x, 16 ; <i32> [#uses=1] + %tmp.6 = and i32 %y, -65536 ; <i32> [#uses=1] + %tmp.7 = or i32 %tmp.6, %tmp.3 ; <i32> [#uses=1] + ret i32 %tmp.7 +} + +define i32 @test4(i32 %x, i32 %y) { +entry: + %tmp.6 = and i32 %x, -65536 ; <i32> [#uses=1] + %tmp.3 = lshr i32 %y, 16 ; <i32> [#uses=1] + %tmp.7 = or i32 %tmp.6, %tmp.3 ; <i32> [#uses=1] + ret i32 %tmp.7 +} + +define i32 @test5(i32 %x, i32 %y) { +entry: + %tmp.3 = shl i32 %x, 1 ; <i32> [#uses=1] + %tmp.4 = and i32 %tmp.3, -65536 ; <i32> [#uses=1] + %tmp.7 = and i32 %y, 65535 ; <i32> [#uses=1] + %tmp.9 = or i32 %tmp.4, %tmp.7 ; <i32> [#uses=1] + ret i32 %tmp.9 +} + +define i32 @test6(i32 %x, i32 %y) { +entry: + %tmp.7 = and i32 %x, 65535 ; <i32> [#uses=1] + %tmp.3 = shl i32 %y, 1 ; <i32> [#uses=1] + %tmp.4 = and i32 %tmp.3, -65536 ; <i32> [#uses=1] + %tmp.9 = or i32 %tmp.4, %tmp.7 ; <i32> [#uses=1] + ret i32 %tmp.9 +} + +define i32 @test7(i32 %x, i32 %y) { +entry: + %tmp.2 = and i32 %x, -65536 ; <i32> [#uses=1] + %tmp.5 = and i32 %y, 65535 ; <i32> [#uses=1] + %tmp.7 = or i32 %tmp.5, %tmp.2 ; <i32> [#uses=1] + ret i32 %tmp.7 +} + +define i32 @test8(i32 %bar) { +entry: + %tmp.3 = shl i32 %bar, 1 ; <i32> [#uses=1] + %tmp.4 = and i32 %tmp.3, 2 ; <i32> [#uses=1] + %tmp.6 = and i32 %bar, -3 ; <i32> [#uses=1] + %tmp.7 = or i32 %tmp.4, %tmp.6 ; <i32> [#uses=1] + ret i32 %tmp.7 +} diff --git a/test/CodeGen/PowerPC/rlwimi2.ll b/test/CodeGen/PowerPC/rlwimi2.ll new file mode 100644 index 000000000000..33eaacf8b4fa --- /dev/null +++ b/test/CodeGen/PowerPC/rlwimi2.ll @@ -0,0 +1,29 @@ +; All of these ands and shifts should be folded into rlwimi's +; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: grep rlwimi %t | count 3 +; RUN: grep srwi %t | count 1 +; RUN: not grep slwi %t + +define i16 @test1(i32 %srcA, i32 %srcB, i32 %alpha) { +entry: + %tmp.1 = shl i32 %srcA, 15 ; <i32> [#uses=1] + %tmp.4 = and i32 %tmp.1, 32505856 ; <i32> [#uses=1] + %tmp.6 = and i32 %srcA, 31775 ; <i32> [#uses=1] + %tmp.7 = or i32 %tmp.4, %tmp.6 ; <i32> [#uses=1] + %tmp.9 = shl i32 %srcB, 15 ; <i32> [#uses=1] + %tmp.12 = and i32 %tmp.9, 32505856 ; <i32> [#uses=1] + %tmp.14 = and i32 %srcB, 31775 ; <i32> [#uses=1] + %tmp.15 = or i32 %tmp.12, %tmp.14 ; <i32> [#uses=1] + %tmp.18 = mul i32 %tmp.7, %alpha ; <i32> [#uses=1] + %tmp.20 = sub i32 32, %alpha ; <i32> [#uses=1] + %tmp.22 = mul i32 %tmp.15, %tmp.20 ; <i32> [#uses=1] + %tmp.23 = add i32 %tmp.22, %tmp.18 ; <i32> [#uses=2] + %tmp.27 = lshr i32 %tmp.23, 5 ; <i32> [#uses=1] + %tmp.28 = trunc i32 %tmp.27 to i16 ; <i16> [#uses=1] + %tmp.29 = and i16 %tmp.28, 31775 ; <i16> [#uses=1] + %tmp.33 = lshr i32 %tmp.23, 20 ; <i32> [#uses=1] + %tmp.34 = trunc i32 %tmp.33 to i16 ; <i16> [#uses=1] + %tmp.35 = and i16 %tmp.34, 992 ; <i16> [#uses=1] + %tmp.36 = or i16 %tmp.29, %tmp.35 ; <i16> [#uses=1] + ret i16 %tmp.36 +} diff --git a/test/CodeGen/PowerPC/rlwimi3.ll b/test/CodeGen/PowerPC/rlwimi3.ll new file mode 100644 index 000000000000..fedcfbfdb2c5 --- /dev/null +++ b/test/CodeGen/PowerPC/rlwimi3.ll @@ -0,0 +1,25 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -stats |& \ +; RUN: grep {Number of machine instrs printed} | grep 12 + +define i16 @Trans16Bit(i32 %srcA, i32 %srcB, i32 %alpha) { + %tmp1 = shl i32 %srcA, 15 ; <i32> [#uses=1] + %tmp2 = and i32 %tmp1, 32505856 ; <i32> [#uses=1] + %tmp4 = and i32 %srcA, 31775 ; <i32> [#uses=1] + %tmp5 = or i32 %tmp2, %tmp4 ; <i32> [#uses=1] + %tmp7 = shl i32 %srcB, 15 ; <i32> [#uses=1] + %tmp8 = and i32 %tmp7, 32505856 ; <i32> [#uses=1] + %tmp10 = and i32 %srcB, 31775 ; <i32> [#uses=1] + %tmp11 = or i32 %tmp8, %tmp10 ; <i32> [#uses=1] + %tmp14 = mul i32 %tmp5, %alpha ; <i32> [#uses=1] + %tmp16 = sub i32 32, %alpha ; <i32> [#uses=1] + %tmp18 = mul i32 %tmp11, %tmp16 ; <i32> [#uses=1] + %tmp19 = add i32 %tmp18, %tmp14 ; <i32> [#uses=2] + %tmp21 = lshr i32 %tmp19, 5 ; <i32> [#uses=1] + %tmp21.upgrd.1 = trunc i32 %tmp21 to i16 ; <i16> [#uses=1] + %tmp = and i16 %tmp21.upgrd.1, 31775 ; <i16> [#uses=1] + %tmp23 = lshr i32 %tmp19, 20 ; <i32> [#uses=1] + %tmp23.upgrd.2 = trunc i32 %tmp23 to i16 ; <i16> [#uses=1] + %tmp24 = and i16 %tmp23.upgrd.2, 992 ; <i16> [#uses=1] + %tmp25 = or i16 %tmp, %tmp24 ; <i16> [#uses=1] + ret i16 %tmp25 +} diff --git a/test/CodeGen/PowerPC/rlwinm.ll b/test/CodeGen/PowerPC/rlwinm.ll new file mode 100644 index 000000000000..9d34865be5a2 --- /dev/null +++ b/test/CodeGen/PowerPC/rlwinm.ll @@ -0,0 +1,61 @@ +; All of these ands and shifts should be folded into rlwimi's +; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: not grep and %t +; RUN: not grep srawi %t +; RUN: not grep srwi %t +; RUN: not grep slwi %t +; RUN: grep rlwinm %t | count 8 + +define i32 @test1(i32 %a) { +entry: + %tmp.1 = and i32 %a, 268431360 ; <i32> [#uses=1] + ret i32 %tmp.1 +} + +define i32 @test2(i32 %a) { +entry: + %tmp.1 = and i32 %a, -268435441 ; <i32> [#uses=1] + ret i32 %tmp.1 +} + +define i32 @test3(i32 %a) { +entry: + %tmp.2 = ashr i32 %a, 8 ; <i32> [#uses=1] + %tmp.3 = and i32 %tmp.2, 255 ; <i32> [#uses=1] + ret i32 %tmp.3 +} + +define i32 @test4(i32 %a) { +entry: + %tmp.3 = lshr i32 %a, 8 ; <i32> [#uses=1] + %tmp.4 = and i32 %tmp.3, 255 ; <i32> [#uses=1] + ret i32 %tmp.4 +} + +define i32 @test5(i32 %a) { +entry: + %tmp.2 = shl i32 %a, 8 ; <i32> [#uses=1] + %tmp.3 = and i32 %tmp.2, -8388608 ; <i32> [#uses=1] + ret i32 %tmp.3 +} + +define i32 @test6(i32 %a) { +entry: + %tmp.1 = and i32 %a, 65280 ; <i32> [#uses=1] + %tmp.2 = ashr i32 %tmp.1, 8 ; <i32> [#uses=1] + ret i32 %tmp.2 +} + +define i32 @test7(i32 %a) { +entry: + %tmp.1 = and i32 %a, 65280 ; <i32> [#uses=1] + %tmp.2 = lshr i32 %tmp.1, 8 ; <i32> [#uses=1] + ret i32 %tmp.2 +} + +define i32 @test8(i32 %a) { +entry: + %tmp.1 = and i32 %a, 16711680 ; <i32> [#uses=1] + %tmp.2 = shl i32 %tmp.1, 8 ; <i32> [#uses=1] + ret i32 %tmp.2 +} diff --git a/test/CodeGen/PowerPC/rlwinm2.ll b/test/CodeGen/PowerPC/rlwinm2.ll new file mode 100644 index 000000000000..06ceaa2a9cdc --- /dev/null +++ b/test/CodeGen/PowerPC/rlwinm2.ll @@ -0,0 +1,28 @@ +; All of these ands and shifts should be folded into rlw[i]nm instructions +; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: not grep and %t +; RUN: not grep srawi %t +; RUN: not grep srwi %t +; RUN: not grep slwi %t +; RUN: grep rlwnm %t | count 1 +; RUN: grep rlwinm %t | count 1 + +define i32 @test1(i32 %X, i32 %Y) { +entry: + %tmp = trunc i32 %Y to i8 ; <i8> [#uses=2] + %tmp1 = shl i32 %X, %Y ; <i32> [#uses=1] + %tmp2 = sub i32 32, %Y ; <i8> [#uses=1] + %tmp3 = lshr i32 %X, %tmp2 ; <i32> [#uses=1] + %tmp4 = or i32 %tmp1, %tmp3 ; <i32> [#uses=1] + %tmp6 = and i32 %tmp4, 127 ; <i32> [#uses=1] + ret i32 %tmp6 +} + +define i32 @test2(i32 %X) { +entry: + %tmp1 = lshr i32 %X, 27 ; <i32> [#uses=1] + %tmp2 = shl i32 %X, 5 ; <i32> [#uses=1] + %tmp2.masked = and i32 %tmp2, 96 ; <i32> [#uses=1] + %tmp5 = or i32 %tmp1, %tmp2.masked ; <i32> [#uses=1] + ret i32 %tmp5 +} diff --git a/test/CodeGen/PowerPC/rotl-2.ll b/test/CodeGen/PowerPC/rotl-2.ll new file mode 100644 index 000000000000..df104599fe3e --- /dev/null +++ b/test/CodeGen/PowerPC/rotl-2.ll @@ -0,0 +1,38 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwinm | count 4 +; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwnm | count 2 +; RUN: llvm-as < %s | llc -march=ppc32 | not grep or + +define i32 @rotl32(i32 %A, i8 %Amt) nounwind { + %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1] + %B = shl i32 %A, %shift.upgrd.1 ; <i32> [#uses=1] + %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] + %shift.upgrd.2 = zext i8 %Amt2 to i32 ; <i32> [#uses=1] + %C = lshr i32 %A, %shift.upgrd.2 ; <i32> [#uses=1] + %D = or i32 %B, %C ; <i32> [#uses=1] + ret i32 %D +} + +define i32 @rotr32(i32 %A, i8 %Amt) nounwind { + %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1] + %B = lshr i32 %A, %shift.upgrd.3 ; <i32> [#uses=1] + %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1] + %shift.upgrd.4 = zext i8 %Amt2 to i32 ; <i32> [#uses=1] + %C = shl i32 %A, %shift.upgrd.4 ; <i32> [#uses=1] + %D = or i32 %B, %C ; <i32> [#uses=1] + ret i32 %D +} + +define i32 @rotli32(i32 %A) nounwind { + %B = shl i32 %A, 5 ; <i32> [#uses=1] + %C = lshr i32 %A, 27 ; <i32> [#uses=1] + %D = or i32 %B, %C ; <i32> [#uses=1] + ret i32 %D +} + +define i32 @rotri32(i32 %A) nounwind { + %B = lshr i32 %A, 5 ; <i32> [#uses=1] + %C = shl i32 %A, 27 ; <i32> [#uses=1] + %D = or i32 %B, %C ; <i32> [#uses=1] + ret i32 %D +} + diff --git a/test/CodeGen/PowerPC/rotl-64.ll b/test/CodeGen/PowerPC/rotl-64.ll new file mode 100644 index 000000000000..3963d9a9d71a --- /dev/null +++ b/test/CodeGen/PowerPC/rotl-64.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=ppc64 | grep rldicl +; RUN: llvm-as < %s | llc -march=ppc64 | grep rldcl +; PR1613 + +define i64 @t1(i64 %A) { + %tmp1 = lshr i64 %A, 57 + %tmp2 = shl i64 %A, 7 + %tmp3 = or i64 %tmp1, %tmp2 + ret i64 %tmp3 +} + +define i64 @t2(i64 %A, i8 zeroext %Amt) { + %Amt1 = zext i8 %Amt to i64 + %tmp1 = lshr i64 %A, %Amt1 + %Amt2 = sub i8 64, %Amt + %Amt3 = zext i8 %Amt2 to i64 + %tmp2 = shl i64 %A, %Amt3 + %tmp3 = or i64 %tmp1, %tmp2 + ret i64 %tmp3 +} diff --git a/test/CodeGen/PowerPC/rotl.ll b/test/CodeGen/PowerPC/rotl.ll new file mode 100644 index 000000000000..aab5c8316a3d --- /dev/null +++ b/test/CodeGen/PowerPC/rotl.ll @@ -0,0 +1,37 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwnm | count 2 +; RUN: llvm-as < %s | llc -march=ppc32 | grep rlwinm | count 2 + +define i32 @rotlw(i32 %x, i32 %sh) { +entry: + %tmp.7 = sub i32 32, %sh ; <i32> [#uses=1] + %tmp.10 = lshr i32 %x, %tmp.7 ; <i32> [#uses=2] + %tmp.4 = shl i32 %x, %sh ; <i32> [#uses=1] + %tmp.12 = or i32 %tmp.10, %tmp.4 ; <i32> [#uses=1] + ret i32 %tmp.12 +} + +define i32 @rotrw(i32 %x, i32 %sh) { +entry: + %tmp.3 = trunc i32 %sh to i8 ; <i8> [#uses=1] + %tmp.4 = lshr i32 %x, %sh ; <i32> [#uses=2] + %tmp.7 = sub i32 32, %sh ; <i32> [#uses=1] + %tmp.10 = shl i32 %x, %tmp.7 ; <i32> [#uses=1] + %tmp.12 = or i32 %tmp.4, %tmp.10 ; <i32> [#uses=1] + ret i32 %tmp.12 +} + +define i32 @rotlwi(i32 %x) { +entry: + %tmp.7 = lshr i32 %x, 27 ; <i32> [#uses=2] + %tmp.3 = shl i32 %x, 5 ; <i32> [#uses=1] + %tmp.9 = or i32 %tmp.3, %tmp.7 ; <i32> [#uses=1] + ret i32 %tmp.9 +} + +define i32 @rotrwi(i32 %x) { +entry: + %tmp.3 = lshr i32 %x, 5 ; <i32> [#uses=2] + %tmp.7 = shl i32 %x, 27 ; <i32> [#uses=1] + %tmp.9 = or i32 %tmp.3, %tmp.7 ; <i32> [#uses=1] + ret i32 %tmp.9 +} diff --git a/test/CodeGen/PowerPC/select-cc.ll b/test/CodeGen/PowerPC/select-cc.ll new file mode 100644 index 000000000000..f9464c4b0516 --- /dev/null +++ b/test/CodeGen/PowerPC/select-cc.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=ppc32 +; PR3011 + +define <2 x double> @vector_select(<2 x double> %x, <2 x double> %y) nounwind { + %x.lo = extractelement <2 x double> %x, i32 0 ; <double> [#uses=1] + %x.lo.ge = fcmp oge double %x.lo, 0.000000e+00 ; <i1> [#uses=1] + %a.d = select i1 %x.lo.ge, <2 x double> %y, <2 x double> %x ; <<2 x double>> [#uses=1] + ret <2 x double> %a.d +} diff --git a/test/CodeGen/PowerPC/select_lt0.ll b/test/CodeGen/PowerPC/select_lt0.ll new file mode 100644 index 000000000000..86eb201c5796 --- /dev/null +++ b/test/CodeGen/PowerPC/select_lt0.ll @@ -0,0 +1,50 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep cmp + +define i32 @seli32_1(i32 %a) { +entry: + %tmp.1 = icmp slt i32 %a, 0 ; <i1> [#uses=1] + %retval = select i1 %tmp.1, i32 5, i32 0 ; <i32> [#uses=1] + ret i32 %retval +} + +define i32 @seli32_2(i32 %a, i32 %b) { +entry: + %tmp.1 = icmp slt i32 %a, 0 ; <i1> [#uses=1] + %retval = select i1 %tmp.1, i32 %b, i32 0 ; <i32> [#uses=1] + ret i32 %retval +} + +define i32 @seli32_3(i32 %a, i16 %b) { +entry: + %tmp.2 = sext i16 %b to i32 ; <i32> [#uses=1] + %tmp.1 = icmp slt i32 %a, 0 ; <i1> [#uses=1] + %retval = select i1 %tmp.1, i32 %tmp.2, i32 0 ; <i32> [#uses=1] + ret i32 %retval +} + +define i32 @seli32_4(i32 %a, i16 %b) { +entry: + %tmp.2 = zext i16 %b to i32 ; <i32> [#uses=1] + %tmp.1 = icmp slt i32 %a, 0 ; <i1> [#uses=1] + %retval = select i1 %tmp.1, i32 %tmp.2, i32 0 ; <i32> [#uses=1] + ret i32 %retval +} + +define i16 @seli16_1(i16 %a) { +entry: + %tmp.1 = icmp slt i16 %a, 0 ; <i1> [#uses=1] + %retval = select i1 %tmp.1, i16 7, i16 0 ; <i16> [#uses=1] + ret i16 %retval +} + +define i16 @seli16_2(i32 %a, i16 %b) { + %tmp.1 = icmp slt i32 %a, 0 ; <i1> [#uses=1] + %retval = select i1 %tmp.1, i16 %b, i16 0 ; <i16> [#uses=1] + ret i16 %retval +} + +define i32 @seli32_a_a(i32 %a) { + %tmp = icmp slt i32 %a, 1 ; <i1> [#uses=1] + %min = select i1 %tmp, i32 %a, i32 0 ; <i32> [#uses=1] + ret i32 %min +} diff --git a/test/CodeGen/PowerPC/setcc_no_zext.ll b/test/CodeGen/PowerPC/setcc_no_zext.ll new file mode 100644 index 000000000000..c31f35ce9af3 --- /dev/null +++ b/test/CodeGen/PowerPC/setcc_no_zext.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwinm + +define i32 @setcc_one_or_zero(i32* %a) { +entry: + %tmp.1 = icmp ne i32* %a, null ; <i1> [#uses=1] + %inc.1 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1] + ret i32 %inc.1 +} + diff --git a/test/CodeGen/PowerPC/seteq-0.ll b/test/CodeGen/PowerPC/seteq-0.ll new file mode 100644 index 000000000000..0f0afe9e665a --- /dev/null +++ b/test/CodeGen/PowerPC/seteq-0.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 | \ +; RUN: grep {srwi r., r., 5} + +define i32 @eq0(i32 %a) { + %tmp.1 = icmp eq i32 %a, 0 ; <i1> [#uses=1] + %tmp.2 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1] + ret i32 %tmp.2 +} + diff --git a/test/CodeGen/PowerPC/shift128.ll b/test/CodeGen/PowerPC/shift128.ll new file mode 100644 index 000000000000..cf5b3fc6ff0c --- /dev/null +++ b/test/CodeGen/PowerPC/shift128.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=ppc64 | grep sld | count 5 + +define i128 @foo_lshr(i128 %x, i128 %y) { + %r = lshr i128 %x, %y + ret i128 %r +} +define i128 @foo_ashr(i128 %x, i128 %y) { + %r = ashr i128 %x, %y + ret i128 %r +} +define i128 @foo_shl(i128 %x, i128 %y) { + %r = shl i128 %x, %y + ret i128 %r +} diff --git a/test/CodeGen/PowerPC/shl_elim.ll b/test/CodeGen/PowerPC/shl_elim.ll new file mode 100644 index 000000000000..3dc47729860b --- /dev/null +++ b/test/CodeGen/PowerPC/shl_elim.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep slwi + +define i32 @test1(i64 %a) { + %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1] + %tmp23 = trunc i64 %tmp29 to i32 ; <i32> [#uses=1] + %tmp410 = lshr i32 %tmp23, 9 ; <i32> [#uses=1] + %tmp45 = trunc i32 %tmp410 to i16 ; <i16> [#uses=1] + %tmp456 = sext i16 %tmp45 to i32 ; <i32> [#uses=1] + ret i32 %tmp456 +} + diff --git a/test/CodeGen/PowerPC/shl_sext.ll b/test/CodeGen/PowerPC/shl_sext.ll new file mode 100644 index 000000000000..61e5cdb11a42 --- /dev/null +++ b/test/CodeGen/PowerPC/shl_sext.ll @@ -0,0 +1,18 @@ +; This test should not contain a sign extend +; RUN: llvm-as < %s | llc -march=ppc32 | not grep extsb + +define i32 @test(i32 %mode.0.i.0) { + %tmp.79 = trunc i32 %mode.0.i.0 to i8 ; <i8> [#uses=1] + %tmp.80 = sext i8 %tmp.79 to i32 ; <i32> [#uses=1] + %tmp.81 = shl i32 %tmp.80, 24 ; <i32> [#uses=1] + ret i32 %tmp.81 +} + +define i32 @test2(i32 %mode.0.i.0) { + %tmp.79 = trunc i32 %mode.0.i.0 to i8 ; <i8> [#uses=1] + %tmp.80 = sext i8 %tmp.79 to i32 ; <i32> [#uses=1] + %tmp.81 = shl i32 %tmp.80, 16 ; <i32> [#uses=1] + %tmp.82 = and i32 %tmp.81, 16711680 ; <i32> [#uses=1] + ret i32 %tmp.82 +} + diff --git a/test/CodeGen/PowerPC/sign_ext_inreg1.ll b/test/CodeGen/PowerPC/sign_ext_inreg1.ll new file mode 100644 index 000000000000..0e67f7703882 --- /dev/null +++ b/test/CodeGen/PowerPC/sign_ext_inreg1.ll @@ -0,0 +1,12 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep srwi +; RUN: llvm-as < %s | llc -march=ppc32 | not grep rlwimi + +define i32 @baz(i64 %a) { + %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1] + %tmp23 = trunc i64 %tmp29 to i32 ; <i32> [#uses=1] + %tmp410 = lshr i32 %tmp23, 9 ; <i32> [#uses=1] + %tmp45 = trunc i32 %tmp410 to i16 ; <i16> [#uses=1] + %tmp456 = sext i16 %tmp45 to i32 ; <i32> [#uses=1] + ret i32 %tmp456 +} + diff --git a/test/CodeGen/PowerPC/small-arguments.ll b/test/CodeGen/PowerPC/small-arguments.ll new file mode 100644 index 000000000000..e211e86875a2 --- /dev/null +++ b/test/CodeGen/PowerPC/small-arguments.ll @@ -0,0 +1,52 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep {extsh\\|rlwinm} + +declare i16 @foo() signext + +define i32 @test1(i16 signext %X) { + %Y = sext i16 %X to i32 ;; dead + ret i32 %Y +} + +define i32 @test2(i16 zeroext %X) { + %Y = sext i16 %X to i32 + %Z = and i32 %Y, 65535 ;; dead + ret i32 %Z +} + +define void @test3() { + %tmp.0 = call i16 @foo() signext ;; no extsh! + %tmp.1 = icmp slt i16 %tmp.0, 1234 + br i1 %tmp.1, label %then, label %UnifiedReturnBlock + +then: + call i32 @test1(i16 0 signext) + ret void +UnifiedReturnBlock: + ret void +} + +define i32 @test4(i16* %P) { + %tmp.1 = load i16* %P + %tmp.2 = zext i16 %tmp.1 to i32 + %tmp.3 = and i32 %tmp.2, 255 + ret i32 %tmp.3 +} + +define i32 @test5(i16* %P) { + %tmp.1 = load i16* %P + %tmp.2 = bitcast i16 %tmp.1 to i16 + %tmp.3 = zext i16 %tmp.2 to i32 + %tmp.4 = and i32 %tmp.3, 255 + ret i32 %tmp.4 +} + +define i32 @test6(i32* %P) { + %tmp.1 = load i32* %P + %tmp.2 = and i32 %tmp.1, 255 + ret i32 %tmp.2 +} + +define i16 @test7(float %a) zeroext { + %tmp.1 = fptoui float %a to i16 + ret i16 %tmp.1 +} diff --git a/test/CodeGen/PowerPC/stfiwx-2.ll b/test/CodeGen/PowerPC/stfiwx-2.ll new file mode 100644 index 000000000000..5c4a834be445 --- /dev/null +++ b/test/CodeGen/PowerPC/stfiwx-2.ll @@ -0,0 +1,11 @@ +; This cannot be a stfiwx +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep stb +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep stfiwx + +define void @test(float %F, i8* %P) { + %I = fptosi float %F to i32 + %X = trunc i32 %I to i8 + store i8 %X, i8* %P + ret void +} + diff --git a/test/CodeGen/PowerPC/stfiwx.ll b/test/CodeGen/PowerPC/stfiwx.ll new file mode 100644 index 000000000000..c4afb63531b1 --- /dev/null +++ b/test/CodeGen/PowerPC/stfiwx.ll @@ -0,0 +1,26 @@ +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=stfiwx -o %t1 -f +; RUN: grep stfiwx %t1 +; RUN: not grep r1 %t1 +; RUN: llvm-as < %s | \ +; RUN: llc -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-stfiwx \ +; RUN: -o %t2 -f +; RUN: not grep stfiwx %t2 +; RUN: grep r1 %t2 + +define void @test(float %a, i32* %b) { + %tmp.2 = fptosi float %a to i32 ; <i32> [#uses=1] + store i32 %tmp.2, i32* %b + ret void +} + +define void @test2(float %a, i32* %b, i32 %i) { + %tmp.2 = getelementptr i32* %b, i32 1 ; <i32*> [#uses=1] + %tmp.5 = getelementptr i32* %b, i32 %i ; <i32*> [#uses=1] + %tmp.7 = fptosi float %a to i32 ; <i32> [#uses=3] + store i32 %tmp.7, i32* %tmp.5 + store i32 %tmp.7, i32* %tmp.2 + store i32 %tmp.7, i32* %b + ret void +} + diff --git a/test/CodeGen/PowerPC/store-load-fwd.ll b/test/CodeGen/PowerPC/store-load-fwd.ll new file mode 100644 index 000000000000..5cc478448ff7 --- /dev/null +++ b/test/CodeGen/PowerPC/store-load-fwd.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | not grep lwz + +define i32 @test(i32* %P) { + store i32 1, i32* %P + %V = load i32* %P ; <i32> [#uses=1] + ret i32 %V +} + diff --git a/test/CodeGen/PowerPC/subc.ll b/test/CodeGen/PowerPC/subc.ll new file mode 100644 index 000000000000..4ac95961f079 --- /dev/null +++ b/test/CodeGen/PowerPC/subc.ll @@ -0,0 +1,25 @@ +; All of these should be codegen'd without loading immediates +; RUN: llvm-as < %s | llc -march=ppc32 -o %t -f +; RUN: grep subfc %t | count 1 +; RUN: grep subfe %t | count 1 +; RUN: grep subfze %t | count 1 +; RUN: grep subfme %t | count 1 +; RUN: grep subfic %t | count 2 + +define i64 @sub_ll(i64 %a, i64 %b) { +entry: + %tmp.2 = sub i64 %a, %b ; <i64> [#uses=1] + ret i64 %tmp.2 +} + +define i64 @sub_l_5(i64 %a) { +entry: + %tmp.1 = sub i64 5, %a ; <i64> [#uses=1] + ret i64 %tmp.1 +} + +define i64 @sub_l_m5(i64 %a) { +entry: + %tmp.1 = sub i64 -5, %a ; <i64> [#uses=1] + ret i64 %tmp.1 +} diff --git a/test/CodeGen/PowerPC/tailcall1-64.ll b/test/CodeGen/PowerPC/tailcall1-64.ll new file mode 100644 index 000000000000..f39b40bdab81 --- /dev/null +++ b/test/CodeGen/PowerPC/tailcall1-64.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=ppc64 -tailcallopt | grep TC_RETURNd8 +define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { +entry: + ret i32 %a3 +} + +define fastcc i32 @tailcaller(i32 %in1, i32 %in2) { +entry: + %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 ) ; <i32> [#uses=1] + ret i32 %tmp11 +} diff --git a/test/CodeGen/PowerPC/tailcall1.ll b/test/CodeGen/PowerPC/tailcall1.ll new file mode 100644 index 000000000000..1fc4b94ddcf9 --- /dev/null +++ b/test/CodeGen/PowerPC/tailcall1.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -tailcallopt | grep TC_RETURN +define fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { +entry: + ret i32 %a3 +} + +define fastcc i32 @tailcaller(i32 %in1, i32 %in2) { +entry: + %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 ) ; <i32> [#uses=1] + ret i32 %tmp11 +} diff --git a/test/CodeGen/PowerPC/tailcallpic1.ll b/test/CodeGen/PowerPC/tailcallpic1.ll new file mode 100644 index 000000000000..678d366fb6a6 --- /dev/null +++ b/test/CodeGen/PowerPC/tailcallpic1.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -tailcallopt -mtriple=powerpc-apple-darwin -relocation-model=pic | grep TC_RETURN + + + +define protected fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { +entry: + ret i32 %a3 +} + +define fastcc i32 @tailcaller(i32 %in1, i32 %in2) { +entry: + %tmp11 = tail call fastcc i32 @tailcallee( i32 %in1, i32 %in2, i32 %in1, i32 %in2 ) ; <i32> [#uses=1] + ret i32 %tmp11 +} diff --git a/test/CodeGen/PowerPC/trampoline.ll b/test/CodeGen/PowerPC/trampoline.ll new file mode 100644 index 000000000000..530c7826ea83 --- /dev/null +++ b/test/CodeGen/PowerPC/trampoline.ll @@ -0,0 +1,166 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep {__trampoline_setup} + +module asm "\09.lazy_reference .objc_class_name_NSImageRep" +module asm "\09.objc_class_name_NSBitmapImageRep=0" +module asm "\09.globl .objc_class_name_NSBitmapImageRep" + %struct.CGImage = type opaque + %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]" = type { %struct.NSBitmapImageRep*, void (%struct.__block_1*, %struct.CGImage*)* } + %struct.NSBitmapImageRep = type { %struct.NSImageRep } + %struct.NSImageRep = type { } + %struct.NSZone = type opaque + %struct.__block_1 = type { %struct.__invoke_impl, %struct.NSZone*, %struct.NSBitmapImageRep** } + %struct.__builtin_trampoline = type { [40 x i8] } + %struct.__invoke_impl = type { i8*, i32, i32, i8* } + %struct._objc__method_prototype_list = type opaque + %struct._objc_class = type { %struct._objc_class*, %struct._objc_class*, i8*, i32, i32, i32, %struct._objc_ivar_list*, %struct._objc_method_list*, %struct.objc_cache*, %struct._objc_protocol**, i8*, %struct._objc_class_ext* } + %struct._objc_class_ext = type opaque + %struct._objc_ivar_list = type opaque + %struct._objc_method = type { %struct.objc_selector*, i8*, i8* } + %struct._objc_method_list = type opaque + %struct._objc_module = type { i32, i32, i8*, %struct._objc_symtab* } + %struct._objc_protocol = type { %struct._objc_protocol_extension*, i8*, %struct._objc_protocol**, %struct._objc__method_prototype_list*, %struct._objc__method_prototype_list* } + %struct._objc_protocol_extension = type opaque + %struct._objc_super = type { %struct.objc_object*, %struct._objc_class* } + %struct._objc_symtab = type { i32, %struct.objc_selector**, i16, i16, [1 x i8*] } + %struct.anon = type { %struct._objc__method_prototype_list*, i32, [1 x %struct._objc_method] } + %struct.objc_cache = type opaque + %struct.objc_object = type opaque + %struct.objc_selector = type opaque + %struct.objc_super = type opaque +@_NSConcreteStackBlock = external global i8* ; <i8**> [#uses=1] +@"\01L_OBJC_SELECTOR_REFERENCES_1" = internal global %struct.objc_selector* bitcast ([34 x i8]* @"\01L_OBJC_METH_VAR_NAME_1" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip" ; <%struct.objc_selector**> [#uses=2] +@"\01L_OBJC_CLASS_NSBitmapImageRep" = internal global %struct._objc_class { %struct._objc_class* @"\01L_OBJC_METACLASS_NSBitmapImageRep", %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), i8* getelementptr ([17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i32 0, i32 1, i32 0, %struct._objc_ivar_list* null, %struct._objc_method_list* bitcast ({ i8*, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" to %struct._objc_method_list*), %struct.objc_cache* null, %struct._objc_protocol** null, i8* null, %struct._objc_class_ext* null }, section "__OBJC,__class,regular,no_dead_strip" ; <%struct._objc_class*> [#uses=3] +@"\01L_OBJC_SELECTOR_REFERENCES_0" = internal global %struct.objc_selector* bitcast ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), section "__OBJC,__message_refs,literal_pointers,no_dead_strip" ; <%struct.objc_selector**> [#uses=2] +@"\01L_OBJC_SYMBOLS" = internal global { i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] } { i32 0, %struct.objc_selector** null, i16 1, i16 0, [1 x %struct._objc_class*] [ %struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep" ] }, section "__OBJC,__symbols,regular,no_dead_strip" ; <{ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }*> [#uses=2] +@"\01L_OBJC_METH_VAR_NAME_0" = internal global [14 x i8] c"copyWithZone:\00", section "__TEXT,__cstring,cstring_literals", align 4 ; <[14 x i8]*> [#uses=2] +@"\01L_OBJC_METH_VAR_TYPE_0" = internal global [20 x i8] c"@12@0:4^{_NSZone=}8\00", section "__TEXT,__cstring,cstring_literals", align 4 ; <[20 x i8]*> [#uses=1] +@"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" = internal global { i8*, i32, [1 x %struct._objc_method] } { i8* null, i32 1, [1 x %struct._objc_method] [ %struct._objc_method { %struct.objc_selector* bitcast ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), i8* getelementptr ([20 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), i8* bitcast (%struct.objc_object* (%struct.NSBitmapImageRep*, %struct.objc_selector*, %struct.NSZone*)* @"-[NSBitmapImageRep copyWithZone:]" to i8*) } ] }, section "__OBJC,__inst_meth,regular,no_dead_strip" ; <{ i8*, i32, [1 x %struct._objc_method] }*> [#uses=2] +@"\01L_OBJC_CLASS_NAME_0" = internal global [17 x i8] c"NSBitmapImageRep\00", section "__TEXT,__cstring,cstring_literals", align 4 ; <[17 x i8]*> [#uses=1] +@"\01L_OBJC_CLASS_NAME_1" = internal global [11 x i8] c"NSImageRep\00", section "__TEXT,__cstring,cstring_literals", align 4 ; <[11 x i8]*> [#uses=2] +@"\01L_OBJC_METACLASS_NSBitmapImageRep" = internal global %struct._objc_class { %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), %struct._objc_class* bitcast ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1" to %struct._objc_class*), i8* getelementptr ([17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i32 0, i32 2, i32 48, %struct._objc_ivar_list* null, %struct._objc_method_list* null, %struct.objc_cache* null, %struct._objc_protocol** null, i8* null, %struct._objc_class_ext* null }, section "__OBJC,__meta_class,regular,no_dead_strip" ; <%struct._objc_class*> [#uses=2] +@"\01L_OBJC_METH_VAR_NAME_1" = internal global [34 x i8] c"_performBlockUsingBackingCGImage:\00", section "__TEXT,__cstring,cstring_literals", align 4 ; <[34 x i8]*> [#uses=2] +@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] zeroinitializer, section "__OBJC, __image_info,regular" ; <[2 x i32]*> [#uses=1] +@"\01L_OBJC_CLASS_NAME_2" = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals", align 4 ; <[1 x i8]*> [#uses=1] +@"\01L_OBJC_MODULES" = internal global %struct._objc_module { i32 7, i32 16, i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), %struct._objc_symtab* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to %struct._objc_symtab*) }, section "__OBJC,__module_info,regular,no_dead_strip" ; <%struct._objc_module*> [#uses=1] +@llvm.used = appending global [14 x i8*] [ i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1" to i8*), i8* bitcast (%struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep" to i8*), i8* bitcast (%struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0" to i8*), i8* bitcast ({ i32, %struct.objc_selector**, i16, i16, [1 x %struct._objc_class*] }* @"\01L_OBJC_SYMBOLS" to i8*), i8* getelementptr ([14 x i8]* @"\01L_OBJC_METH_VAR_NAME_0", i32 0, i32 0), i8* getelementptr ([20 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), i8* bitcast ({ i8*, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_INSTANCE_METHODS_NSBitmapImageRep" to i8*), i8* getelementptr ([17 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i8* getelementptr ([11 x i8]* @"\01L_OBJC_CLASS_NAME_1", i32 0, i32 0), i8* bitcast (%struct._objc_class* @"\01L_OBJC_METACLASS_NSBitmapImageRep" to i8*), i8* getelementptr ([34 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*) ], section "llvm.metadata" ; <[14 x i8*]*> [#uses=0] + +define internal %struct.objc_object* @"-[NSBitmapImageRep copyWithZone:]"(%struct.NSBitmapImageRep* %self, %struct.objc_selector* %_cmd, %struct.NSZone* %zone) nounwind { +entry: + %self_addr = alloca %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep**> [#uses=2] + %_cmd_addr = alloca %struct.objc_selector* ; <%struct.objc_selector**> [#uses=1] + %zone_addr = alloca %struct.NSZone* ; <%struct.NSZone**> [#uses=2] + %retval = alloca %struct.objc_object* ; <%struct.objc_object**> [#uses=1] + %__block_holder_tmp_1.0 = alloca %struct.__block_1 ; <%struct.__block_1*> [#uses=7] + %new = alloca %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep**> [#uses=2] + %self.1 = alloca %struct.objc_object* ; <%struct.objc_object**> [#uses=2] + %0 = alloca i8* ; <i8**> [#uses=2] + %TRAMP.9 = alloca %struct.__builtin_trampoline, align 4 ; <%struct.__builtin_trampoline*> [#uses=1] + %1 = alloca void (%struct.__block_1*, %struct.CGImage*)* ; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=2] + %2 = alloca %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep**> [#uses=2] + %FRAME.7 = alloca %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]" ; <%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*> [#uses=5] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store %struct.NSBitmapImageRep* %self, %struct.NSBitmapImageRep** %self_addr + store %struct.objc_selector* %_cmd, %struct.objc_selector** %_cmd_addr + store %struct.NSZone* %zone, %struct.NSZone** %zone_addr + %3 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 0 ; <%struct.NSBitmapImageRep**> [#uses=1] + %4 = load %struct.NSBitmapImageRep** %self_addr, align 4 ; <%struct.NSBitmapImageRep*> [#uses=1] + store %struct.NSBitmapImageRep* %4, %struct.NSBitmapImageRep** %3, align 4 + %TRAMP.91 = bitcast %struct.__builtin_trampoline* %TRAMP.9 to i8* ; <i8*> [#uses=1] + %FRAME.72 = bitcast %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7 to i8* ; <i8*> [#uses=1] + %tramp = call i8* @llvm.init.trampoline(i8* %TRAMP.91, i8* bitcast (void (%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*, %struct.__block_1*, %struct.CGImage*)* @__helper_1.1632 to i8*), i8* %FRAME.72) ; <i8*> [#uses=1] + store i8* %tramp, i8** %0, align 4 + %5 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 1 ; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=1] + %6 = load i8** %0, align 4 ; <i8*> [#uses=1] + %7 = bitcast i8* %6 to void (%struct.__block_1*, %struct.CGImage*)* ; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1] + store void (%struct.__block_1*, %struct.CGImage*)* %7, void (%struct.__block_1*, %struct.CGImage*)** %5, align 4 + store %struct.NSBitmapImageRep* null, %struct.NSBitmapImageRep** %new, align 4 + %8 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0 ; <%struct.__invoke_impl*> [#uses=1] + %9 = getelementptr %struct.__invoke_impl* %8, i32 0, i32 0 ; <i8**> [#uses=1] + store i8* bitcast (i8** @_NSConcreteStackBlock to i8*), i8** %9, align 4 + %10 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0 ; <%struct.__invoke_impl*> [#uses=1] + %11 = getelementptr %struct.__invoke_impl* %10, i32 0, i32 1 ; <i32*> [#uses=1] + store i32 67108864, i32* %11, align 4 + %12 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0 ; <%struct.__invoke_impl*> [#uses=1] + %13 = getelementptr %struct.__invoke_impl* %12, i32 0, i32 2 ; <i32*> [#uses=1] + store i32 24, i32* %13, align 4 + %14 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 1 ; <void (%struct.__block_1*, %struct.CGImage*)**> [#uses=1] + %15 = load void (%struct.__block_1*, %struct.CGImage*)** %14, align 4 ; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1] + store void (%struct.__block_1*, %struct.CGImage*)* %15, void (%struct.__block_1*, %struct.CGImage*)** %1, align 4 + %16 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 0 ; <%struct.__invoke_impl*> [#uses=1] + %17 = getelementptr %struct.__invoke_impl* %16, i32 0, i32 3 ; <i8**> [#uses=1] + %18 = load void (%struct.__block_1*, %struct.CGImage*)** %1, align 4 ; <void (%struct.__block_1*, %struct.CGImage*)*> [#uses=1] + %19 = bitcast void (%struct.__block_1*, %struct.CGImage*)* %18 to i8* ; <i8*> [#uses=1] + store i8* %19, i8** %17, align 4 + %20 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 1 ; <%struct.NSZone**> [#uses=1] + %21 = load %struct.NSZone** %zone_addr, align 4 ; <%struct.NSZone*> [#uses=1] + store %struct.NSZone* %21, %struct.NSZone** %20, align 4 + %22 = getelementptr %struct.__block_1* %__block_holder_tmp_1.0, i32 0, i32 2 ; <%struct.NSBitmapImageRep***> [#uses=1] + store %struct.NSBitmapImageRep** %new, %struct.NSBitmapImageRep*** %22, align 4 + %23 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %FRAME.7, i32 0, i32 0 ; <%struct.NSBitmapImageRep**> [#uses=1] + %24 = load %struct.NSBitmapImageRep** %23, align 4 ; <%struct.NSBitmapImageRep*> [#uses=1] + store %struct.NSBitmapImageRep* %24, %struct.NSBitmapImageRep** %2, align 4 + %25 = load %struct.NSBitmapImageRep** %2, align 4 ; <%struct.NSBitmapImageRep*> [#uses=1] + %26 = bitcast %struct.NSBitmapImageRep* %25 to %struct.objc_object* ; <%struct.objc_object*> [#uses=1] + store %struct.objc_object* %26, %struct.objc_object** %self.1, align 4 + %27 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_1", align 4 ; <%struct.objc_selector*> [#uses=1] + %__block_holder_tmp_1.03 = bitcast %struct.__block_1* %__block_holder_tmp_1.0 to void (%struct.CGImage*)* ; <void (%struct.CGImage*)*> [#uses=1] + %28 = load %struct.objc_object** %self.1, align 4 ; <%struct.objc_object*> [#uses=1] + %29 = call %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)* inttoptr (i64 4294901504 to %struct.objc_object* (%struct.objc_object*, %struct.objc_selector*, ...)*)(%struct.objc_object* %28, %struct.objc_selector* %27, void (%struct.CGImage*)* %__block_holder_tmp_1.03) nounwind ; <%struct.objc_object*> [#uses=0] + br label %return + +return: ; preds = %entry + %retval5 = load %struct.objc_object** %retval ; <%struct.objc_object*> [#uses=1] + ret %struct.objc_object* %retval5 +} + +declare i8* @llvm.init.trampoline(i8*, i8*, i8*) nounwind + +define internal void @__helper_1.1632(%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* nest %CHAIN.8, %struct.__block_1* %_self, %struct.CGImage* %cgImage) nounwind { +entry: + %CHAIN.8_addr = alloca %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* ; <%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"**> [#uses=2] + %_self_addr = alloca %struct.__block_1* ; <%struct.__block_1**> [#uses=3] + %cgImage_addr = alloca %struct.CGImage* ; <%struct.CGImage**> [#uses=1] + %zone = alloca %struct.NSZone* ; <%struct.NSZone**> [#uses=2] + %objc_super = alloca %struct._objc_super ; <%struct._objc_super*> [#uses=3] + %new = alloca %struct.NSBitmapImageRep** ; <%struct.NSBitmapImageRep***> [#uses=2] + %objc_super.5 = alloca %struct.objc_super* ; <%struct.objc_super**> [#uses=2] + %0 = alloca %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep**> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %CHAIN.8, %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"** %CHAIN.8_addr + store %struct.__block_1* %_self, %struct.__block_1** %_self_addr + store %struct.CGImage* %cgImage, %struct.CGImage** %cgImage_addr + %1 = load %struct.__block_1** %_self_addr, align 4 ; <%struct.__block_1*> [#uses=1] + %2 = getelementptr %struct.__block_1* %1, i32 0, i32 2 ; <%struct.NSBitmapImageRep***> [#uses=1] + %3 = load %struct.NSBitmapImageRep*** %2, align 4 ; <%struct.NSBitmapImageRep**> [#uses=1] + store %struct.NSBitmapImageRep** %3, %struct.NSBitmapImageRep*** %new, align 4 + %4 = load %struct.__block_1** %_self_addr, align 4 ; <%struct.__block_1*> [#uses=1] + %5 = getelementptr %struct.__block_1* %4, i32 0, i32 1 ; <%struct.NSZone**> [#uses=1] + %6 = load %struct.NSZone** %5, align 4 ; <%struct.NSZone*> [#uses=1] + store %struct.NSZone* %6, %struct.NSZone** %zone, align 4 + %7 = load %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"** %CHAIN.8_addr, align 4 ; <%"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"*> [#uses=1] + %8 = getelementptr %"struct.FRAME.-[NSBitmapImageRep copyWithZone:]"* %7, i32 0, i32 0 ; <%struct.NSBitmapImageRep**> [#uses=1] + %9 = load %struct.NSBitmapImageRep** %8, align 4 ; <%struct.NSBitmapImageRep*> [#uses=1] + store %struct.NSBitmapImageRep* %9, %struct.NSBitmapImageRep** %0, align 4 + %10 = load %struct.NSBitmapImageRep** %0, align 4 ; <%struct.NSBitmapImageRep*> [#uses=1] + %11 = bitcast %struct.NSBitmapImageRep* %10 to %struct.objc_object* ; <%struct.objc_object*> [#uses=1] + %12 = getelementptr %struct._objc_super* %objc_super, i32 0, i32 0 ; <%struct.objc_object**> [#uses=1] + store %struct.objc_object* %11, %struct.objc_object** %12, align 4 + %13 = load %struct._objc_class** getelementptr (%struct._objc_class* @"\01L_OBJC_CLASS_NSBitmapImageRep", i32 0, i32 1), align 4 ; <%struct._objc_class*> [#uses=1] + %14 = getelementptr %struct._objc_super* %objc_super, i32 0, i32 1 ; <%struct._objc_class**> [#uses=1] + store %struct._objc_class* %13, %struct._objc_class** %14, align 4 + %objc_super1 = bitcast %struct._objc_super* %objc_super to %struct.objc_super* ; <%struct.objc_super*> [#uses=1] + store %struct.objc_super* %objc_super1, %struct.objc_super** %objc_super.5, align 4 + %15 = load %struct.objc_selector** @"\01L_OBJC_SELECTOR_REFERENCES_0", align 4 ; <%struct.objc_selector*> [#uses=1] + %16 = load %struct.objc_super** %objc_super.5, align 4 ; <%struct.objc_super*> [#uses=1] + %17 = load %struct.NSZone** %zone, align 4 ; <%struct.NSZone*> [#uses=1] + %18 = call %struct.objc_object* (%struct.objc_super*, %struct.objc_selector*, ...)* @objc_msgSendSuper(%struct.objc_super* %16, %struct.objc_selector* %15, %struct.NSZone* %17) nounwind ; <%struct.objc_object*> [#uses=1] + %19 = bitcast %struct.objc_object* %18 to %struct.NSBitmapImageRep* ; <%struct.NSBitmapImageRep*> [#uses=1] + %20 = load %struct.NSBitmapImageRep*** %new, align 4 ; <%struct.NSBitmapImageRep**> [#uses=1] + store %struct.NSBitmapImageRep* %19, %struct.NSBitmapImageRep** %20, align 4 + br label %return + +return: ; preds = %entry + ret void +} + +declare %struct.objc_object* @objc_msgSendSuper(%struct.objc_super*, %struct.objc_selector*, ...) diff --git a/test/CodeGen/PowerPC/unsafe-math.ll b/test/CodeGen/PowerPC/unsafe-math.ll new file mode 100644 index 000000000000..3d52d0c9e7ed --- /dev/null +++ b/test/CodeGen/PowerPC/unsafe-math.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=ppc32 | grep fmul | count 2 +; RUN: llvm-as < %s | llc -march=ppc32 -enable-unsafe-fp-math | \ +; RUN: grep fmul | count 1 + +define double @foo(double %X) { + %tmp1 = mul double %X, 1.23 + %tmp2 = mul double %tmp1, 4.124 + ret double %tmp2 +} + diff --git a/test/CodeGen/PowerPC/vcmp-fold.ll b/test/CodeGen/PowerPC/vcmp-fold.ll new file mode 100644 index 000000000000..815bb0aedff5 --- /dev/null +++ b/test/CodeGen/PowerPC/vcmp-fold.ll @@ -0,0 +1,22 @@ +; This should fold the "vcmpbfp." and "vcmpbfp" instructions into a single +; "vcmpbfp.". +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vcmpbfp | count 1 + + +define void @test(<4 x float>* %x, <4 x float>* %y, i32* %P) { +entry: + %tmp = load <4 x float>* %x ; <<4 x float>> [#uses=1] + %tmp2 = load <4 x float>* %y ; <<4 x float>> [#uses=1] + %tmp.upgrd.1 = call i32 @llvm.ppc.altivec.vcmpbfp.p( i32 1, <4 x float> %tmp, <4 x float> %tmp2 ) ; <i32> [#uses=1] + %tmp4 = load <4 x float>* %x ; <<4 x float>> [#uses=1] + %tmp6 = load <4 x float>* %y ; <<4 x float>> [#uses=1] + %tmp.upgrd.2 = call <4 x i32> @llvm.ppc.altivec.vcmpbfp( <4 x float> %tmp4, <4 x float> %tmp6 ) ; <<4 x i32>> [#uses=1] + %tmp7 = bitcast <4 x i32> %tmp.upgrd.2 to <4 x float> ; <<4 x float>> [#uses=1] + store <4 x float> %tmp7, <4 x float>* %x + store i32 %tmp.upgrd.1, i32* %P + ret void +} + +declare i32 @llvm.ppc.altivec.vcmpbfp.p(i32, <4 x float>, <4 x float>) + +declare <4 x i32> @llvm.ppc.altivec.vcmpbfp(<4 x float>, <4 x float>) diff --git a/test/CodeGen/PowerPC/vec_br_cmp.ll b/test/CodeGen/PowerPC/vec_br_cmp.ll new file mode 100644 index 000000000000..6d799676b77b --- /dev/null +++ b/test/CodeGen/PowerPC/vec_br_cmp.ll @@ -0,0 +1,22 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 -o %t -f +; RUN: grep vcmpeqfp. %t +; RUN: not grep mfcr %t + +; A predicate compare used immediately by a branch should not generate an mfcr. + +define void @test(<4 x float>* %A, <4 x float>* %B) { + %tmp = load <4 x float>* %A ; <<4 x float>> [#uses=1] + %tmp3 = load <4 x float>* %B ; <<4 x float>> [#uses=1] + %tmp.upgrd.1 = tail call i32 @llvm.ppc.altivec.vcmpeqfp.p( i32 1, <4 x float> %tmp, <4 x float> %tmp3 ) ; <i32> [#uses=1] + %tmp.upgrd.2 = icmp eq i32 %tmp.upgrd.1, 0 ; <i1> [#uses=1] + br i1 %tmp.upgrd.2, label %cond_true, label %UnifiedReturnBlock + +cond_true: ; preds = %0 + store <4 x float> zeroinitializer, <4 x float>* %B + ret void + +UnifiedReturnBlock: ; preds = %0 + ret void +} + +declare i32 @llvm.ppc.altivec.vcmpeqfp.p(i32, <4 x float>, <4 x float>) diff --git a/test/CodeGen/PowerPC/vec_call.ll b/test/CodeGen/PowerPC/vec_call.ll new file mode 100644 index 000000000000..8e7a08ebb7d7 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_call.ll @@ -0,0 +1,11 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 + +define <4 x i32> @test_arg(<4 x i32> %A, <4 x i32> %B) { + %C = add <4 x i32> %A, %B ; <<4 x i32>> [#uses=1] + ret <4 x i32> %C +} + +define <4 x i32> @foo() { + %X = call <4 x i32> @test_arg( <4 x i32> zeroinitializer, <4 x i32> zeroinitializer ) ; <<4 x i32>> [#uses=1] + ret <4 x i32> %X +} diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll new file mode 100644 index 000000000000..c4b42b9e9b8a --- /dev/null +++ b/test/CodeGen/PowerPC/vec_constants.ll @@ -0,0 +1,40 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep CPI + +define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) { + %tmp = load <4 x i32>* %P1 ; <<4 x i32>> [#uses=1] + %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp4, <4 x i32>* %P1 + %tmp7 = load <4 x i32>* %P2 ; <<4 x i32>> [#uses=1] + %tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp9, <4 x i32>* %P2 + %tmp.upgrd.1 = load <4 x float>* %P3 ; <<4 x float>> [#uses=1] + %tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] + %tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1] + store <4 x float> %tmp13, <4 x float>* %P3 + ret void +} + +define <4 x i32> @test_30() { + ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > +} + +define <4 x i32> @test_29() { + ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > +} + +define <8 x i16> @test_n30() { + ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > +} + +define <16 x i8> @test_n104() { + ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > +} + +define <4 x i32> @test_vsldoi() { + ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > +} + +define <4 x i32> @test_rol() { + ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > +} diff --git a/test/CodeGen/PowerPC/vec_fneg.ll b/test/CodeGen/PowerPC/vec_fneg.ll new file mode 100644 index 000000000000..2ef2099ddb97 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_fneg.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vsubfp + +define void @t(<4 x float>* %A) { + %tmp2 = load <4 x float>* %A + %tmp3 = sub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2 + store <4 x float> %tmp3, <4 x float>* %A + ret void +} diff --git a/test/CodeGen/PowerPC/vec_insert.ll b/test/CodeGen/PowerPC/vec_insert.ll new file mode 100644 index 000000000000..04bbe6574f62 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_insert.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep sth + +define <8 x i16> @insert(<8 x i16> %foo, i16 %a) nounwind { +entry: + %vecext = insertelement <8 x i16> %foo, i16 %a, i32 7 ; <i8> [#uses=1] + ret <8 x i16> %vecext +} + diff --git a/test/CodeGen/PowerPC/vec_misaligned.ll b/test/CodeGen/PowerPC/vec_misaligned.ll new file mode 100644 index 000000000000..15376caebefa --- /dev/null +++ b/test/CodeGen/PowerPC/vec_misaligned.ll @@ -0,0 +1,37 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 + +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" +target triple = "powerpc-apple-darwin8" + %struct.S2203 = type { %struct.u16qi } + %struct.u16qi = type { <16 x i8> } +@s = weak global %struct.S2203 zeroinitializer ; <%struct.S2203*> [#uses=1] + +define void @foo(i32 %x, ...) { +entry: + %x_addr = alloca i32 ; <i32*> [#uses=1] + %ap = alloca i8* ; <i8**> [#uses=3] + %ap.0 = alloca i8* ; <i8**> [#uses=3] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i32 %x, i32* %x_addr + %ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1] + call void @llvm.va_start( i8* %ap1 ) + %tmp = load i8** %ap, align 4 ; <i8*> [#uses=1] + store i8* %tmp, i8** %ap.0, align 4 + %tmp2 = load i8** %ap.0, align 4 ; <i8*> [#uses=1] + %tmp3 = getelementptr i8* %tmp2, i64 16 ; <i8*> [#uses=1] + store i8* %tmp3, i8** %ap, align 4 + %tmp4 = load i8** %ap.0, align 4 ; <i8*> [#uses=1] + %tmp45 = bitcast i8* %tmp4 to %struct.S2203* ; <%struct.S2203*> [#uses=1] + %tmp6 = getelementptr %struct.S2203* @s, i32 0, i32 0 ; <%struct.u16qi*> [#uses=1] + %tmp7 = getelementptr %struct.S2203* %tmp45, i32 0, i32 0 ; <%struct.u16qi*> [#uses=1] + %tmp8 = getelementptr %struct.u16qi* %tmp6, i32 0, i32 0 ; <<16 x i8>*> [#uses=1] + %tmp9 = getelementptr %struct.u16qi* %tmp7, i32 0, i32 0 ; <<16 x i8>*> [#uses=1] + %tmp10 = load <16 x i8>* %tmp9, align 4 ; <<16 x i8>> [#uses=1] + store <16 x i8> %tmp10, <16 x i8>* %tmp8, align 4 + br label %return + +return: ; preds = %entry + ret void +} + +declare void @llvm.va_start(i8*) nounwind diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll new file mode 100644 index 000000000000..b061fa9a54ee --- /dev/null +++ b/test/CodeGen/PowerPC/vec_mul.ll @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep mullw +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vmsumuhm + +define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) { + %tmp = load <4 x i32>* %X ; <<4 x i32>> [#uses=1] + %tmp2 = load <4 x i32>* %Y ; <<4 x i32>> [#uses=1] + %tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1] + ret <4 x i32> %tmp3 +} + +define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) { + %tmp = load <8 x i16>* %X ; <<8 x i16>> [#uses=1] + %tmp2 = load <8 x i16>* %Y ; <<8 x i16>> [#uses=1] + %tmp3 = mul <8 x i16> %tmp, %tmp2 ; <<8 x i16>> [#uses=1] + ret <8 x i16> %tmp3 +} + +define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) { + %tmp = load <16 x i8>* %X ; <<16 x i8>> [#uses=1] + %tmp2 = load <16 x i8>* %Y ; <<16 x i8>> [#uses=1] + %tmp3 = mul <16 x i8> %tmp, %tmp2 ; <<16 x i8>> [#uses=1] + ret <16 x i8> %tmp3 +} diff --git a/test/CodeGen/PowerPC/vec_perf_shuffle.ll b/test/CodeGen/PowerPC/vec_perf_shuffle.ll new file mode 100644 index 000000000000..5bb1b6083417 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_perf_shuffle.ll @@ -0,0 +1,36 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vperm + +define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) { + %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1] + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32 2 > ; <<4 x float>> [#uses=1] + ret <4 x float> %V3 +} + +define <4 x float> @test_30u5(<4 x float>* %P1, <4 x float>* %P2) { + %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1] + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 > ; <<4 x float>> [#uses=1] + ret <4 x float> %V3 +} + +define <4 x float> @test_3u73(<4 x float>* %P1, <4 x float>* %P2) { + %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1] + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 > ; <<4 x float>> [#uses=1] + ret <4 x float> %V3 +} + +define <4 x float> @test_3774(<4 x float>* %P1, <4 x float>* %P2) { + %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1] + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 > ; <<4 x float>> [#uses=1] + ret <4 x float> %V3 +} + +define <4 x float> @test_4450(<4 x float>* %P1, <4 x float>* %P2) { + %V1 = load <4 x float>* %P1 ; <<4 x float>> [#uses=1] + %V2 = load <4 x float>* %P2 ; <<4 x float>> [#uses=1] + %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 > ; <<4 x float>> [#uses=1] + ret <4 x float> %V3 +} diff --git a/test/CodeGen/PowerPC/vec_shuffle.ll b/test/CodeGen/PowerPC/vec_shuffle.ll new file mode 100644 index 000000000000..1289dca2d211 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_shuffle.ll @@ -0,0 +1,504 @@ +; RUN: llvm-as < %s | opt -instcombine | \ +; RUN: llc -march=ppc32 -mcpu=g5 | not grep vperm +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 > %t +; RUN: grep vsldoi %t | count 2 +; RUN: grep vmrgh %t | count 7 +; RUN: grep vmrgl %t | count 6 +; RUN: grep vpkuhum %t | count 1 +; RUN: grep vpkuwum %t | count 1 + +define void @VSLDOI_xy(<8 x i16>* %A, <8 x i16>* %B) { +entry: + %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=1] + %tmp2 = load <8 x i16>* %B ; <<8 x i16>> [#uses=1] + %tmp.upgrd.1 = bitcast <8 x i16> %tmp to <16 x i8> ; <<16 x i8>> [#uses=11] + %tmp2.upgrd.2 = bitcast <8 x i16> %tmp2 to <16 x i8> ; <<16 x i8>> [#uses=5] + %tmp.upgrd.3 = extractelement <16 x i8> %tmp.upgrd.1, i32 5 ; <i8> [#uses=1] + %tmp3 = extractelement <16 x i8> %tmp.upgrd.1, i32 6 ; <i8> [#uses=1] + %tmp4 = extractelement <16 x i8> %tmp.upgrd.1, i32 7 ; <i8> [#uses=1] + %tmp5 = extractelement <16 x i8> %tmp.upgrd.1, i32 8 ; <i8> [#uses=1] + %tmp6 = extractelement <16 x i8> %tmp.upgrd.1, i32 9 ; <i8> [#uses=1] + %tmp7 = extractelement <16 x i8> %tmp.upgrd.1, i32 10 ; <i8> [#uses=1] + %tmp8 = extractelement <16 x i8> %tmp.upgrd.1, i32 11 ; <i8> [#uses=1] + %tmp9 = extractelement <16 x i8> %tmp.upgrd.1, i32 12 ; <i8> [#uses=1] + %tmp10 = extractelement <16 x i8> %tmp.upgrd.1, i32 13 ; <i8> [#uses=1] + %tmp11 = extractelement <16 x i8> %tmp.upgrd.1, i32 14 ; <i8> [#uses=1] + %tmp12 = extractelement <16 x i8> %tmp.upgrd.1, i32 15 ; <i8> [#uses=1] + %tmp13 = extractelement <16 x i8> %tmp2.upgrd.2, i32 0 ; <i8> [#uses=1] + %tmp14 = extractelement <16 x i8> %tmp2.upgrd.2, i32 1 ; <i8> [#uses=1] + %tmp15 = extractelement <16 x i8> %tmp2.upgrd.2, i32 2 ; <i8> [#uses=1] + %tmp16 = extractelement <16 x i8> %tmp2.upgrd.2, i32 3 ; <i8> [#uses=1] + %tmp17 = extractelement <16 x i8> %tmp2.upgrd.2, i32 4 ; <i8> [#uses=1] + %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.3, i32 0 ; <<16 x i8>> [#uses=1] + %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1] + %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1] + %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1] + %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1] + %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1] + %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1] + %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1] + %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1] + %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1] + %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1] + %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1] + %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1] + %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1] + %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1] + %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1] + %tmp33.upgrd.4 = bitcast <16 x i8> %tmp33 to <8 x i16> ; <<8 x i16>> [#uses=1] + store <8 x i16> %tmp33.upgrd.4, <8 x i16>* %A + ret void +} + +define void @VSLDOI_xx(<8 x i16>* %A, <8 x i16>* %B) { + %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=1] + %tmp2 = load <8 x i16>* %A ; <<8 x i16>> [#uses=1] + %tmp.upgrd.5 = bitcast <8 x i16> %tmp to <16 x i8> ; <<16 x i8>> [#uses=11] + %tmp2.upgrd.6 = bitcast <8 x i16> %tmp2 to <16 x i8> ; <<16 x i8>> [#uses=5] + %tmp.upgrd.7 = extractelement <16 x i8> %tmp.upgrd.5, i32 5 ; <i8> [#uses=1] + %tmp3 = extractelement <16 x i8> %tmp.upgrd.5, i32 6 ; <i8> [#uses=1] + %tmp4 = extractelement <16 x i8> %tmp.upgrd.5, i32 7 ; <i8> [#uses=1] + %tmp5 = extractelement <16 x i8> %tmp.upgrd.5, i32 8 ; <i8> [#uses=1] + %tmp6 = extractelement <16 x i8> %tmp.upgrd.5, i32 9 ; <i8> [#uses=1] + %tmp7 = extractelement <16 x i8> %tmp.upgrd.5, i32 10 ; <i8> [#uses=1] + %tmp8 = extractelement <16 x i8> %tmp.upgrd.5, i32 11 ; <i8> [#uses=1] + %tmp9 = extractelement <16 x i8> %tmp.upgrd.5, i32 12 ; <i8> [#uses=1] + %tmp10 = extractelement <16 x i8> %tmp.upgrd.5, i32 13 ; <i8> [#uses=1] + %tmp11 = extractelement <16 x i8> %tmp.upgrd.5, i32 14 ; <i8> [#uses=1] + %tmp12 = extractelement <16 x i8> %tmp.upgrd.5, i32 15 ; <i8> [#uses=1] + %tmp13 = extractelement <16 x i8> %tmp2.upgrd.6, i32 0 ; <i8> [#uses=1] + %tmp14 = extractelement <16 x i8> %tmp2.upgrd.6, i32 1 ; <i8> [#uses=1] + %tmp15 = extractelement <16 x i8> %tmp2.upgrd.6, i32 2 ; <i8> [#uses=1] + %tmp16 = extractelement <16 x i8> %tmp2.upgrd.6, i32 3 ; <i8> [#uses=1] + %tmp17 = extractelement <16 x i8> %tmp2.upgrd.6, i32 4 ; <i8> [#uses=1] + %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.7, i32 0 ; <<16 x i8>> [#uses=1] + %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1] + %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1] + %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1] + %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1] + %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1] + %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1] + %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1] + %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1] + %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1] + %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1] + %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1] + %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1] + %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1] + %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1] + %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1] + %tmp33.upgrd.8 = bitcast <16 x i8> %tmp33 to <8 x i16> ; <<8 x i16>> [#uses=1] + store <8 x i16> %tmp33.upgrd.8, <8 x i16>* %A + ret void +} + +define void @VPERM_promote(<8 x i16>* %A, <8 x i16>* %B) { +entry: + %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=1] + %tmp.upgrd.9 = bitcast <8 x i16> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp2 = load <8 x i16>* %B ; <<8 x i16>> [#uses=1] + %tmp2.upgrd.10 = bitcast <8 x i16> %tmp2 to <4 x i32> ; <<4 x i32>> [#uses=1] + %tmp3 = call <4 x i32> @llvm.ppc.altivec.vperm( <4 x i32> %tmp.upgrd.9, <4 x i32> %tmp2.upgrd.10, <16 x i8> < i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14, i8 14 > ) ; <<4 x i32>> [#uses=1] + %tmp3.upgrd.11 = bitcast <4 x i32> %tmp3 to <8 x i16> ; <<8 x i16>> [#uses=1] + store <8 x i16> %tmp3.upgrd.11, <8 x i16>* %A + ret void +} + +declare <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32>, <4 x i32>, <16 x i8>) + +define void @tb_l(<16 x i8>* %A, <16 x i8>* %B) { +entry: + %tmp = load <16 x i8>* %A ; <<16 x i8>> [#uses=8] + %tmp2 = load <16 x i8>* %B ; <<16 x i8>> [#uses=8] + %tmp.upgrd.12 = extractelement <16 x i8> %tmp, i32 8 ; <i8> [#uses=1] + %tmp3 = extractelement <16 x i8> %tmp2, i32 8 ; <i8> [#uses=1] + %tmp4 = extractelement <16 x i8> %tmp, i32 9 ; <i8> [#uses=1] + %tmp5 = extractelement <16 x i8> %tmp2, i32 9 ; <i8> [#uses=1] + %tmp6 = extractelement <16 x i8> %tmp, i32 10 ; <i8> [#uses=1] + %tmp7 = extractelement <16 x i8> %tmp2, i32 10 ; <i8> [#uses=1] + %tmp8 = extractelement <16 x i8> %tmp, i32 11 ; <i8> [#uses=1] + %tmp9 = extractelement <16 x i8> %tmp2, i32 11 ; <i8> [#uses=1] + %tmp10 = extractelement <16 x i8> %tmp, i32 12 ; <i8> [#uses=1] + %tmp11 = extractelement <16 x i8> %tmp2, i32 12 ; <i8> [#uses=1] + %tmp12 = extractelement <16 x i8> %tmp, i32 13 ; <i8> [#uses=1] + %tmp13 = extractelement <16 x i8> %tmp2, i32 13 ; <i8> [#uses=1] + %tmp14 = extractelement <16 x i8> %tmp, i32 14 ; <i8> [#uses=1] + %tmp15 = extractelement <16 x i8> %tmp2, i32 14 ; <i8> [#uses=1] + %tmp16 = extractelement <16 x i8> %tmp, i32 15 ; <i8> [#uses=1] + %tmp17 = extractelement <16 x i8> %tmp2, i32 15 ; <i8> [#uses=1] + %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.12, i32 0 ; <<16 x i8>> [#uses=1] + %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1] + %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1] + %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1] + %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1] + %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1] + %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1] + %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1] + %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1] + %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1] + %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1] + %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1] + %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1] + %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1] + %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1] + %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1] + store <16 x i8> %tmp33, <16 x i8>* %A + ret void +} + +define void @th_l(<8 x i16>* %A, <8 x i16>* %B) { +entry: + %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=4] + %tmp2 = load <8 x i16>* %B ; <<8 x i16>> [#uses=4] + %tmp.upgrd.13 = extractelement <8 x i16> %tmp, i32 4 ; <i16> [#uses=1] + %tmp3 = extractelement <8 x i16> %tmp2, i32 4 ; <i16> [#uses=1] + %tmp4 = extractelement <8 x i16> %tmp, i32 5 ; <i16> [#uses=1] + %tmp5 = extractelement <8 x i16> %tmp2, i32 5 ; <i16> [#uses=1] + %tmp6 = extractelement <8 x i16> %tmp, i32 6 ; <i16> [#uses=1] + %tmp7 = extractelement <8 x i16> %tmp2, i32 6 ; <i16> [#uses=1] + %tmp8 = extractelement <8 x i16> %tmp, i32 7 ; <i16> [#uses=1] + %tmp9 = extractelement <8 x i16> %tmp2, i32 7 ; <i16> [#uses=1] + %tmp10 = insertelement <8 x i16> undef, i16 %tmp.upgrd.13, i32 0 ; <<8 x i16>> [#uses=1] + %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 1 ; <<8 x i16>> [#uses=1] + %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 2 ; <<8 x i16>> [#uses=1] + %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 3 ; <<8 x i16>> [#uses=1] + %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 4 ; <<8 x i16>> [#uses=1] + %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 5 ; <<8 x i16>> [#uses=1] + %tmp16 = insertelement <8 x i16> %tmp15, i16 %tmp8, i32 6 ; <<8 x i16>> [#uses=1] + %tmp17 = insertelement <8 x i16> %tmp16, i16 %tmp9, i32 7 ; <<8 x i16>> [#uses=1] + store <8 x i16> %tmp17, <8 x i16>* %A + ret void +} + +define void @tw_l(<4 x i32>* %A, <4 x i32>* %B) { +entry: + %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=2] + %tmp2 = load <4 x i32>* %B ; <<4 x i32>> [#uses=2] + %tmp.upgrd.14 = extractelement <4 x i32> %tmp, i32 2 ; <i32> [#uses=1] + %tmp3 = extractelement <4 x i32> %tmp2, i32 2 ; <i32> [#uses=1] + %tmp4 = extractelement <4 x i32> %tmp, i32 3 ; <i32> [#uses=1] + %tmp5 = extractelement <4 x i32> %tmp2, i32 3 ; <i32> [#uses=1] + %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.14, i32 0 ; <<4 x i32>> [#uses=1] + %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1] + %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 2 ; <<4 x i32>> [#uses=1] + %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp5, i32 3 ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp9, <4 x i32>* %A + ret void +} + +define void @tb_h(<16 x i8>* %A, <16 x i8>* %B) { +entry: + %tmp = load <16 x i8>* %A ; <<16 x i8>> [#uses=8] + %tmp2 = load <16 x i8>* %B ; <<16 x i8>> [#uses=8] + %tmp.upgrd.15 = extractelement <16 x i8> %tmp, i32 0 ; <i8> [#uses=1] + %tmp3 = extractelement <16 x i8> %tmp2, i32 0 ; <i8> [#uses=1] + %tmp4 = extractelement <16 x i8> %tmp, i32 1 ; <i8> [#uses=1] + %tmp5 = extractelement <16 x i8> %tmp2, i32 1 ; <i8> [#uses=1] + %tmp6 = extractelement <16 x i8> %tmp, i32 2 ; <i8> [#uses=1] + %tmp7 = extractelement <16 x i8> %tmp2, i32 2 ; <i8> [#uses=1] + %tmp8 = extractelement <16 x i8> %tmp, i32 3 ; <i8> [#uses=1] + %tmp9 = extractelement <16 x i8> %tmp2, i32 3 ; <i8> [#uses=1] + %tmp10 = extractelement <16 x i8> %tmp, i32 4 ; <i8> [#uses=1] + %tmp11 = extractelement <16 x i8> %tmp2, i32 4 ; <i8> [#uses=1] + %tmp12 = extractelement <16 x i8> %tmp, i32 5 ; <i8> [#uses=1] + %tmp13 = extractelement <16 x i8> %tmp2, i32 5 ; <i8> [#uses=1] + %tmp14 = extractelement <16 x i8> %tmp, i32 6 ; <i8> [#uses=1] + %tmp15 = extractelement <16 x i8> %tmp2, i32 6 ; <i8> [#uses=1] + %tmp16 = extractelement <16 x i8> %tmp, i32 7 ; <i8> [#uses=1] + %tmp17 = extractelement <16 x i8> %tmp2, i32 7 ; <i8> [#uses=1] + %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.15, i32 0 ; <<16 x i8>> [#uses=1] + %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1] + %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1] + %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1] + %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1] + %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1] + %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1] + %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1] + %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1] + %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1] + %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1] + %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1] + %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1] + %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1] + %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1] + %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1] + store <16 x i8> %tmp33, <16 x i8>* %A + ret void +} + +define void @th_h(<8 x i16>* %A, <8 x i16>* %B) { +entry: + %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=4] + %tmp2 = load <8 x i16>* %B ; <<8 x i16>> [#uses=4] + %tmp.upgrd.16 = extractelement <8 x i16> %tmp, i32 0 ; <i16> [#uses=1] + %tmp3 = extractelement <8 x i16> %tmp2, i32 0 ; <i16> [#uses=1] + %tmp4 = extractelement <8 x i16> %tmp, i32 1 ; <i16> [#uses=1] + %tmp5 = extractelement <8 x i16> %tmp2, i32 1 ; <i16> [#uses=1] + %tmp6 = extractelement <8 x i16> %tmp, i32 2 ; <i16> [#uses=1] + %tmp7 = extractelement <8 x i16> %tmp2, i32 2 ; <i16> [#uses=1] + %tmp8 = extractelement <8 x i16> %tmp, i32 3 ; <i16> [#uses=1] + %tmp9 = extractelement <8 x i16> %tmp2, i32 3 ; <i16> [#uses=1] + %tmp10 = insertelement <8 x i16> undef, i16 %tmp.upgrd.16, i32 0 ; <<8 x i16>> [#uses=1] + %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 1 ; <<8 x i16>> [#uses=1] + %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 2 ; <<8 x i16>> [#uses=1] + %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 3 ; <<8 x i16>> [#uses=1] + %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 4 ; <<8 x i16>> [#uses=1] + %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 5 ; <<8 x i16>> [#uses=1] + %tmp16 = insertelement <8 x i16> %tmp15, i16 %tmp8, i32 6 ; <<8 x i16>> [#uses=1] + %tmp17 = insertelement <8 x i16> %tmp16, i16 %tmp9, i32 7 ; <<8 x i16>> [#uses=1] + store <8 x i16> %tmp17, <8 x i16>* %A + ret void +} + +define void @tw_h(<4 x i32>* %A, <4 x i32>* %B) { +entry: + %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=2] + %tmp2 = load <4 x i32>* %B ; <<4 x i32>> [#uses=2] + %tmp.upgrd.17 = extractelement <4 x i32> %tmp2, i32 0 ; <i32> [#uses=1] + %tmp3 = extractelement <4 x i32> %tmp, i32 0 ; <i32> [#uses=1] + %tmp4 = extractelement <4 x i32> %tmp2, i32 1 ; <i32> [#uses=1] + %tmp5 = extractelement <4 x i32> %tmp, i32 1 ; <i32> [#uses=1] + %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.17, i32 0 ; <<4 x i32>> [#uses=1] + %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1] + %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 2 ; <<4 x i32>> [#uses=1] + %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp5, i32 3 ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp9, <4 x i32>* %A + ret void +} + +define void @tw_h_flop(<4 x i32>* %A, <4 x i32>* %B) { + %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=2] + %tmp2 = load <4 x i32>* %B ; <<4 x i32>> [#uses=2] + %tmp.upgrd.18 = extractelement <4 x i32> %tmp, i32 0 ; <i32> [#uses=1] + %tmp3 = extractelement <4 x i32> %tmp2, i32 0 ; <i32> [#uses=1] + %tmp4 = extractelement <4 x i32> %tmp, i32 1 ; <i32> [#uses=1] + %tmp5 = extractelement <4 x i32> %tmp2, i32 1 ; <i32> [#uses=1] + %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.18, i32 0 ; <<4 x i32>> [#uses=1] + %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1] + %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 2 ; <<4 x i32>> [#uses=1] + %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp5, i32 3 ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp9, <4 x i32>* %A + ret void +} + +define void @VMRG_UNARY_tb_l(<16 x i8>* %A, <16 x i8>* %B) { +entry: + %tmp = load <16 x i8>* %A ; <<16 x i8>> [#uses=16] + %tmp.upgrd.19 = extractelement <16 x i8> %tmp, i32 8 ; <i8> [#uses=1] + %tmp3 = extractelement <16 x i8> %tmp, i32 8 ; <i8> [#uses=1] + %tmp4 = extractelement <16 x i8> %tmp, i32 9 ; <i8> [#uses=1] + %tmp5 = extractelement <16 x i8> %tmp, i32 9 ; <i8> [#uses=1] + %tmp6 = extractelement <16 x i8> %tmp, i32 10 ; <i8> [#uses=1] + %tmp7 = extractelement <16 x i8> %tmp, i32 10 ; <i8> [#uses=1] + %tmp8 = extractelement <16 x i8> %tmp, i32 11 ; <i8> [#uses=1] + %tmp9 = extractelement <16 x i8> %tmp, i32 11 ; <i8> [#uses=1] + %tmp10 = extractelement <16 x i8> %tmp, i32 12 ; <i8> [#uses=1] + %tmp11 = extractelement <16 x i8> %tmp, i32 12 ; <i8> [#uses=1] + %tmp12 = extractelement <16 x i8> %tmp, i32 13 ; <i8> [#uses=1] + %tmp13 = extractelement <16 x i8> %tmp, i32 13 ; <i8> [#uses=1] + %tmp14 = extractelement <16 x i8> %tmp, i32 14 ; <i8> [#uses=1] + %tmp15 = extractelement <16 x i8> %tmp, i32 14 ; <i8> [#uses=1] + %tmp16 = extractelement <16 x i8> %tmp, i32 15 ; <i8> [#uses=1] + %tmp17 = extractelement <16 x i8> %tmp, i32 15 ; <i8> [#uses=1] + %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.19, i32 0 ; <<16 x i8>> [#uses=1] + %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1] + %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1] + %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1] + %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1] + %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1] + %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1] + %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1] + %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1] + %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1] + %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1] + %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1] + %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1] + %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1] + %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1] + %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1] + store <16 x i8> %tmp33, <16 x i8>* %A + ret void +} + +define void @VMRG_UNARY_th_l(<8 x i16>* %A, <8 x i16>* %B) { +entry: + %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=8] + %tmp.upgrd.20 = extractelement <8 x i16> %tmp, i32 4 ; <i16> [#uses=1] + %tmp3 = extractelement <8 x i16> %tmp, i32 4 ; <i16> [#uses=1] + %tmp4 = extractelement <8 x i16> %tmp, i32 5 ; <i16> [#uses=1] + %tmp5 = extractelement <8 x i16> %tmp, i32 5 ; <i16> [#uses=1] + %tmp6 = extractelement <8 x i16> %tmp, i32 6 ; <i16> [#uses=1] + %tmp7 = extractelement <8 x i16> %tmp, i32 6 ; <i16> [#uses=1] + %tmp8 = extractelement <8 x i16> %tmp, i32 7 ; <i16> [#uses=1] + %tmp9 = extractelement <8 x i16> %tmp, i32 7 ; <i16> [#uses=1] + %tmp10 = insertelement <8 x i16> undef, i16 %tmp.upgrd.20, i32 0 ; <<8 x i16>> [#uses=1] + %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 1 ; <<8 x i16>> [#uses=1] + %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 2 ; <<8 x i16>> [#uses=1] + %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 3 ; <<8 x i16>> [#uses=1] + %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 4 ; <<8 x i16>> [#uses=1] + %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 5 ; <<8 x i16>> [#uses=1] + %tmp16 = insertelement <8 x i16> %tmp15, i16 %tmp8, i32 6 ; <<8 x i16>> [#uses=1] + %tmp17 = insertelement <8 x i16> %tmp16, i16 %tmp9, i32 7 ; <<8 x i16>> [#uses=1] + store <8 x i16> %tmp17, <8 x i16>* %A + ret void +} + +define void @VMRG_UNARY_tw_l(<4 x i32>* %A, <4 x i32>* %B) { +entry: + %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=4] + %tmp.upgrd.21 = extractelement <4 x i32> %tmp, i32 2 ; <i32> [#uses=1] + %tmp3 = extractelement <4 x i32> %tmp, i32 2 ; <i32> [#uses=1] + %tmp4 = extractelement <4 x i32> %tmp, i32 3 ; <i32> [#uses=1] + %tmp5 = extractelement <4 x i32> %tmp, i32 3 ; <i32> [#uses=1] + %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.21, i32 0 ; <<4 x i32>> [#uses=1] + %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1] + %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 2 ; <<4 x i32>> [#uses=1] + %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp5, i32 3 ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp9, <4 x i32>* %A + ret void +} + +define void @VMRG_UNARY_tb_h(<16 x i8>* %A, <16 x i8>* %B) { +entry: + %tmp = load <16 x i8>* %A ; <<16 x i8>> [#uses=16] + %tmp.upgrd.22 = extractelement <16 x i8> %tmp, i32 0 ; <i8> [#uses=1] + %tmp3 = extractelement <16 x i8> %tmp, i32 0 ; <i8> [#uses=1] + %tmp4 = extractelement <16 x i8> %tmp, i32 1 ; <i8> [#uses=1] + %tmp5 = extractelement <16 x i8> %tmp, i32 1 ; <i8> [#uses=1] + %tmp6 = extractelement <16 x i8> %tmp, i32 2 ; <i8> [#uses=1] + %tmp7 = extractelement <16 x i8> %tmp, i32 2 ; <i8> [#uses=1] + %tmp8 = extractelement <16 x i8> %tmp, i32 3 ; <i8> [#uses=1] + %tmp9 = extractelement <16 x i8> %tmp, i32 3 ; <i8> [#uses=1] + %tmp10 = extractelement <16 x i8> %tmp, i32 4 ; <i8> [#uses=1] + %tmp11 = extractelement <16 x i8> %tmp, i32 4 ; <i8> [#uses=1] + %tmp12 = extractelement <16 x i8> %tmp, i32 5 ; <i8> [#uses=1] + %tmp13 = extractelement <16 x i8> %tmp, i32 5 ; <i8> [#uses=1] + %tmp14 = extractelement <16 x i8> %tmp, i32 6 ; <i8> [#uses=1] + %tmp15 = extractelement <16 x i8> %tmp, i32 6 ; <i8> [#uses=1] + %tmp16 = extractelement <16 x i8> %tmp, i32 7 ; <i8> [#uses=1] + %tmp17 = extractelement <16 x i8> %tmp, i32 7 ; <i8> [#uses=1] + %tmp18 = insertelement <16 x i8> undef, i8 %tmp.upgrd.22, i32 0 ; <<16 x i8>> [#uses=1] + %tmp19 = insertelement <16 x i8> %tmp18, i8 %tmp3, i32 1 ; <<16 x i8>> [#uses=1] + %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 2 ; <<16 x i8>> [#uses=1] + %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 3 ; <<16 x i8>> [#uses=1] + %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 4 ; <<16 x i8>> [#uses=1] + %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 5 ; <<16 x i8>> [#uses=1] + %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 6 ; <<16 x i8>> [#uses=1] + %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 7 ; <<16 x i8>> [#uses=1] + %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 8 ; <<16 x i8>> [#uses=1] + %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 9 ; <<16 x i8>> [#uses=1] + %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 10 ; <<16 x i8>> [#uses=1] + %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 11 ; <<16 x i8>> [#uses=1] + %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 12 ; <<16 x i8>> [#uses=1] + %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 13 ; <<16 x i8>> [#uses=1] + %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 14 ; <<16 x i8>> [#uses=1] + %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 15 ; <<16 x i8>> [#uses=1] + store <16 x i8> %tmp33, <16 x i8>* %A + ret void +} + +define void @VMRG_UNARY_th_h(<8 x i16>* %A, <8 x i16>* %B) { +entry: + %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=8] + %tmp.upgrd.23 = extractelement <8 x i16> %tmp, i32 0 ; <i16> [#uses=1] + %tmp3 = extractelement <8 x i16> %tmp, i32 0 ; <i16> [#uses=1] + %tmp4 = extractelement <8 x i16> %tmp, i32 1 ; <i16> [#uses=1] + %tmp5 = extractelement <8 x i16> %tmp, i32 1 ; <i16> [#uses=1] + %tmp6 = extractelement <8 x i16> %tmp, i32 2 ; <i16> [#uses=1] + %tmp7 = extractelement <8 x i16> %tmp, i32 2 ; <i16> [#uses=1] + %tmp8 = extractelement <8 x i16> %tmp, i32 3 ; <i16> [#uses=1] + %tmp9 = extractelement <8 x i16> %tmp, i32 3 ; <i16> [#uses=1] + %tmp10 = insertelement <8 x i16> undef, i16 %tmp.upgrd.23, i32 0 ; <<8 x i16>> [#uses=1] + %tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 1 ; <<8 x i16>> [#uses=1] + %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 2 ; <<8 x i16>> [#uses=1] + %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 3 ; <<8 x i16>> [#uses=1] + %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 4 ; <<8 x i16>> [#uses=1] + %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 5 ; <<8 x i16>> [#uses=1] + %tmp16 = insertelement <8 x i16> %tmp15, i16 %tmp8, i32 6 ; <<8 x i16>> [#uses=1] + %tmp17 = insertelement <8 x i16> %tmp16, i16 %tmp9, i32 7 ; <<8 x i16>> [#uses=1] + store <8 x i16> %tmp17, <8 x i16>* %A + ret void +} + +define void @VMRG_UNARY_tw_h(<4 x i32>* %A, <4 x i32>* %B) { +entry: + %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=4] + %tmp.upgrd.24 = extractelement <4 x i32> %tmp, i32 0 ; <i32> [#uses=1] + %tmp3 = extractelement <4 x i32> %tmp, i32 0 ; <i32> [#uses=1] + %tmp4 = extractelement <4 x i32> %tmp, i32 1 ; <i32> [#uses=1] + %tmp5 = extractelement <4 x i32> %tmp, i32 1 ; <i32> [#uses=1] + %tmp6 = insertelement <4 x i32> undef, i32 %tmp.upgrd.24, i32 0 ; <<4 x i32>> [#uses=1] + %tmp7 = insertelement <4 x i32> %tmp6, i32 %tmp3, i32 1 ; <<4 x i32>> [#uses=1] + %tmp8 = insertelement <4 x i32> %tmp7, i32 %tmp4, i32 2 ; <<4 x i32>> [#uses=1] + %tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp5, i32 3 ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp9, <4 x i32>* %A + ret void +} + +define void @VPCKUHUM_unary(<8 x i16>* %A, <8 x i16>* %B) { +entry: + %tmp = load <8 x i16>* %A ; <<8 x i16>> [#uses=2] + %tmp.upgrd.25 = bitcast <8 x i16> %tmp to <16 x i8> ; <<16 x i8>> [#uses=8] + %tmp3 = bitcast <8 x i16> %tmp to <16 x i8> ; <<16 x i8>> [#uses=8] + %tmp.upgrd.26 = extractelement <16 x i8> %tmp.upgrd.25, i32 1 ; <i8> [#uses=1] + %tmp4 = extractelement <16 x i8> %tmp.upgrd.25, i32 3 ; <i8> [#uses=1] + %tmp5 = extractelement <16 x i8> %tmp.upgrd.25, i32 5 ; <i8> [#uses=1] + %tmp6 = extractelement <16 x i8> %tmp.upgrd.25, i32 7 ; <i8> [#uses=1] + %tmp7 = extractelement <16 x i8> %tmp.upgrd.25, i32 9 ; <i8> [#uses=1] + %tmp8 = extractelement <16 x i8> %tmp.upgrd.25, i32 11 ; <i8> [#uses=1] + %tmp9 = extractelement <16 x i8> %tmp.upgrd.25, i32 13 ; <i8> [#uses=1] + %tmp10 = extractelement <16 x i8> %tmp.upgrd.25, i32 15 ; <i8> [#uses=1] + %tmp11 = extractelement <16 x i8> %tmp3, i32 1 ; <i8> [#uses=1] + %tmp12 = extractelement <16 x i8> %tmp3, i32 3 ; <i8> [#uses=1] + %tmp13 = extractelement <16 x i8> %tmp3, i32 5 ; <i8> [#uses=1] + %tmp14 = extractelement <16 x i8> %tmp3, i32 7 ; <i8> [#uses=1] + %tmp15 = extractelement <16 x i8> %tmp3, i32 9 ; <i8> [#uses=1] + %tmp16 = extractelement <16 x i8> %tmp3, i32 11 ; <i8> [#uses=1] + %tmp17 = extractelement <16 x i8> %tmp3, i32 13 ; <i8> [#uses=1] + %tmp18 = extractelement <16 x i8> %tmp3, i32 15 ; <i8> [#uses=1] + %tmp19 = insertelement <16 x i8> undef, i8 %tmp.upgrd.26, i32 0 ; <<16 x i8>> [#uses=1] + %tmp20 = insertelement <16 x i8> %tmp19, i8 %tmp4, i32 1 ; <<16 x i8>> [#uses=1] + %tmp21 = insertelement <16 x i8> %tmp20, i8 %tmp5, i32 2 ; <<16 x i8>> [#uses=1] + %tmp22 = insertelement <16 x i8> %tmp21, i8 %tmp6, i32 3 ; <<16 x i8>> [#uses=1] + %tmp23 = insertelement <16 x i8> %tmp22, i8 %tmp7, i32 4 ; <<16 x i8>> [#uses=1] + %tmp24 = insertelement <16 x i8> %tmp23, i8 %tmp8, i32 5 ; <<16 x i8>> [#uses=1] + %tmp25 = insertelement <16 x i8> %tmp24, i8 %tmp9, i32 6 ; <<16 x i8>> [#uses=1] + %tmp26 = insertelement <16 x i8> %tmp25, i8 %tmp10, i32 7 ; <<16 x i8>> [#uses=1] + %tmp27 = insertelement <16 x i8> %tmp26, i8 %tmp11, i32 8 ; <<16 x i8>> [#uses=1] + %tmp28 = insertelement <16 x i8> %tmp27, i8 %tmp12, i32 9 ; <<16 x i8>> [#uses=1] + %tmp29 = insertelement <16 x i8> %tmp28, i8 %tmp13, i32 10 ; <<16 x i8>> [#uses=1] + %tmp30 = insertelement <16 x i8> %tmp29, i8 %tmp14, i32 11 ; <<16 x i8>> [#uses=1] + %tmp31 = insertelement <16 x i8> %tmp30, i8 %tmp15, i32 12 ; <<16 x i8>> [#uses=1] + %tmp32 = insertelement <16 x i8> %tmp31, i8 %tmp16, i32 13 ; <<16 x i8>> [#uses=1] + %tmp33 = insertelement <16 x i8> %tmp32, i8 %tmp17, i32 14 ; <<16 x i8>> [#uses=1] + %tmp34 = insertelement <16 x i8> %tmp33, i8 %tmp18, i32 15 ; <<16 x i8>> [#uses=1] + %tmp34.upgrd.27 = bitcast <16 x i8> %tmp34 to <8 x i16> ; <<8 x i16>> [#uses=1] + store <8 x i16> %tmp34.upgrd.27, <8 x i16>* %A + ret void +} + +define void @VPCKUWUM_unary(<4 x i32>* %A, <4 x i32>* %B) { +entry: + %tmp = load <4 x i32>* %A ; <<4 x i32>> [#uses=2] + %tmp.upgrd.28 = bitcast <4 x i32> %tmp to <8 x i16> ; <<8 x i16>> [#uses=4] + %tmp3 = bitcast <4 x i32> %tmp to <8 x i16> ; <<8 x i16>> [#uses=4] + %tmp.upgrd.29 = extractelement <8 x i16> %tmp.upgrd.28, i32 1 ; <i16> [#uses=1] + %tmp4 = extractelement <8 x i16> %tmp.upgrd.28, i32 3 ; <i16> [#uses=1] + %tmp5 = extractelement <8 x i16> %tmp.upgrd.28, i32 5 ; <i16> [#uses=1] + %tmp6 = extractelement <8 x i16> %tmp.upgrd.28, i32 7 ; <i16> [#uses=1] + %tmp7 = extractelement <8 x i16> %tmp3, i32 1 ; <i16> [#uses=1] + %tmp8 = extractelement <8 x i16> %tmp3, i32 3 ; <i16> [#uses=1] + %tmp9 = extractelement <8 x i16> %tmp3, i32 5 ; <i16> [#uses=1] + %tmp10 = extractelement <8 x i16> %tmp3, i32 7 ; <i16> [#uses=1] + %tmp11 = insertelement <8 x i16> undef, i16 %tmp.upgrd.29, i32 0 ; <<8 x i16>> [#uses=1] + %tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp4, i32 1 ; <<8 x i16>> [#uses=1] + %tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 2 ; <<8 x i16>> [#uses=1] + %tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp6, i32 3 ; <<8 x i16>> [#uses=1] + %tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 4 ; <<8 x i16>> [#uses=1] + %tmp16 = insertelement <8 x i16> %tmp15, i16 %tmp8, i32 5 ; <<8 x i16>> [#uses=1] + %tmp17 = insertelement <8 x i16> %tmp16, i16 %tmp9, i32 6 ; <<8 x i16>> [#uses=1] + %tmp18 = insertelement <8 x i16> %tmp17, i16 %tmp10, i32 7 ; <<8 x i16>> [#uses=1] + %tmp18.upgrd.30 = bitcast <8 x i16> %tmp18 to <4 x i32> ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp18.upgrd.30, <4 x i32>* %A + ret void +} diff --git a/test/CodeGen/PowerPC/vec_splat.ll b/test/CodeGen/PowerPC/vec_splat.ll new file mode 100644 index 000000000000..a63113700038 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_splat.ll @@ -0,0 +1,71 @@ +; Test that vectors are scalarized/lowered correctly. +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 | \ +; RUN: grep stfs | count 4 +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 -o %t -f +; RUN: grep vspltw %t | count 2 +; RUN: grep vsplti %t | count 3 +; RUN: grep vsplth %t | count 1 + + %f4 = type <4 x float> + %i4 = type <4 x i32> + +define void @splat(%f4* %P, %f4* %Q, float %X) nounwind { + %tmp = insertelement %f4 undef, float %X, i32 0 ; <%f4> [#uses=1] + %tmp2 = insertelement %f4 %tmp, float %X, i32 1 ; <%f4> [#uses=1] + %tmp4 = insertelement %f4 %tmp2, float %X, i32 2 ; <%f4> [#uses=1] + %tmp6 = insertelement %f4 %tmp4, float %X, i32 3 ; <%f4> [#uses=1] + %q = load %f4* %Q ; <%f4> [#uses=1] + %R = add %f4 %q, %tmp6 ; <%f4> [#uses=1] + store %f4 %R, %f4* %P + ret void +} + +define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) nounwind { + %tmp = insertelement %i4 undef, i32 %X, i32 0 ; <%i4> [#uses=1] + %tmp2 = insertelement %i4 %tmp, i32 %X, i32 1 ; <%i4> [#uses=1] + %tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2 ; <%i4> [#uses=1] + %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3 ; <%i4> [#uses=1] + %q = load %i4* %Q ; <%i4> [#uses=1] + %R = add %i4 %q, %tmp6 ; <%i4> [#uses=1] + store %i4 %R, %i4* %P + ret void +} + +define void @splat_imm_i32(%i4* %P, %i4* %Q, i32 %X) nounwind { + %q = load %i4* %Q ; <%i4> [#uses=1] + %R = add %i4 %q, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <%i4> [#uses=1] + store %i4 %R, %i4* %P + ret void +} + +define void @splat_imm_i16(%i4* %P, %i4* %Q, i32 %X) nounwind { + %q = load %i4* %Q ; <%i4> [#uses=1] + %R = add %i4 %q, < i32 65537, i32 65537, i32 65537, i32 65537 > ; <%i4> [#uses=1] + store %i4 %R, %i4* %P + ret void +} + +define void @splat_h(i16 %tmp, <16 x i8>* %dst) nounwind { + %tmp.upgrd.1 = insertelement <8 x i16> undef, i16 %tmp, i32 0 + %tmp72 = insertelement <8 x i16> %tmp.upgrd.1, i16 %tmp, i32 1 + %tmp73 = insertelement <8 x i16> %tmp72, i16 %tmp, i32 2 + %tmp74 = insertelement <8 x i16> %tmp73, i16 %tmp, i32 3 + %tmp75 = insertelement <8 x i16> %tmp74, i16 %tmp, i32 4 + %tmp76 = insertelement <8 x i16> %tmp75, i16 %tmp, i32 5 + %tmp77 = insertelement <8 x i16> %tmp76, i16 %tmp, i32 6 + %tmp78 = insertelement <8 x i16> %tmp77, i16 %tmp, i32 7 + %tmp78.upgrd.2 = bitcast <8 x i16> %tmp78 to <16 x i8> + store <16 x i8> %tmp78.upgrd.2, <16 x i8>* %dst + ret void +} + +define void @spltish(<16 x i8>* %A, <16 x i8>* %B) nounwind { + %tmp = load <16 x i8>* %B ; <<16 x i8>> [#uses=1] + %tmp.s = bitcast <16 x i8> %tmp to <16 x i8> ; <<16 x i8>> [#uses=1] + %tmp4 = sub <16 x i8> %tmp.s, bitcast (<8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 + 15, i16 15, i16 15 > to <16 x i8>) ; <<16 x i8>> [#uses=1] + %tmp4.u = bitcast <16 x i8> %tmp4 to <16 x i8> ; <<16 x i8>> [#uses=1] + store <16 x i8> %tmp4.u, <16 x i8>* %A + ret void +} + diff --git a/test/CodeGen/PowerPC/vec_vrsave.ll b/test/CodeGen/PowerPC/vec_vrsave.ll new file mode 100644 index 000000000000..06769f6bf0f8 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_vrsave.ll @@ -0,0 +1,14 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 -o %t -f +; RUN: grep vrlw %t +; RUN: not grep spr %t +; RUN: not grep vrsave %t + +define <4 x i32> @test_rol() { + ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > +} + +define <4 x i32> @test_arg(<4 x i32> %A, <4 x i32> %B) { + %C = add <4 x i32> %A, %B ; <<4 x i32>> [#uses=1] + ret <4 x i32> %C +} + diff --git a/test/CodeGen/PowerPC/vec_zero.ll b/test/CodeGen/PowerPC/vec_zero.ll new file mode 100644 index 000000000000..8d06a7d94dac --- /dev/null +++ b/test/CodeGen/PowerPC/vec_zero.ll @@ -0,0 +1,9 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep vxor + +define void @foo(<4 x float>* %P) { + %T = load <4 x float>* %P ; <<4 x float>> [#uses=1] + %S = add <4 x float> zeroinitializer, %T ; <<4 x float>> [#uses=1] + store <4 x float> %S, <4 x float>* %P + ret void +} + diff --git a/test/CodeGen/PowerPC/vector-identity-shuffle.ll b/test/CodeGen/PowerPC/vector-identity-shuffle.ll new file mode 100644 index 000000000000..aefd2661a8bc --- /dev/null +++ b/test/CodeGen/PowerPC/vector-identity-shuffle.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep test: +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep vperm + +define void @test(<4 x float>* %tmp2.i) { + %tmp2.i.upgrd.1 = load <4 x float>* %tmp2.i ; <<4 x float>> [#uses=4] + %xFloat0.48 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 0 ; <float> [#uses=1] + %inFloat0.49 = insertelement <4 x float> undef, float %xFloat0.48, i32 0 ; <<4 x float>> [#uses=1] + %xFloat1.50 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 1 ; <float> [#uses=1] + %inFloat1.52 = insertelement <4 x float> %inFloat0.49, float %xFloat1.50, i32 1 ; <<4 x float>> [#uses=1] + %xFloat2.53 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 2 ; <float> [#uses=1] + %inFloat2.55 = insertelement <4 x float> %inFloat1.52, float %xFloat2.53, i32 2 ; <<4 x float>> [#uses=1] + %xFloat3.56 = extractelement <4 x float> %tmp2.i.upgrd.1, i32 3 ; <float> [#uses=1] + %inFloat3.58 = insertelement <4 x float> %inFloat2.55, float %xFloat3.56, i32 3 ; <<4 x float>> [#uses=1] + store <4 x float> %inFloat3.58, <4 x float>* %tmp2.i + ret void +} + diff --git a/test/CodeGen/PowerPC/vector.ll b/test/CodeGen/PowerPC/vector.ll new file mode 100644 index 000000000000..679e69effa3b --- /dev/null +++ b/test/CodeGen/PowerPC/vector.ll @@ -0,0 +1,158 @@ +; Test that vectors are scalarized/lowered correctly. +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 > %t +; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g3 > %t + +%d8 = type <8 x double> +%f1 = type <1 x float> +%f2 = type <2 x float> +%f4 = type <4 x float> +%f8 = type <8 x float> +%i4 = type <4 x i32> + +;;; TEST HANDLING OF VARIOUS VECTOR SIZES + +define void @test_f1(%f1* %P, %f1* %Q, %f1* %S) { + %p = load %f1* %P ; <%f1> [#uses=1] + %q = load %f1* %Q ; <%f1> [#uses=1] + %R = add %f1 %p, %q ; <%f1> [#uses=1] + store %f1 %R, %f1* %S + ret void +} + +define void @test_f2(%f2* %P, %f2* %Q, %f2* %S) { + %p = load %f2* %P ; <%f2> [#uses=1] + %q = load %f2* %Q ; <%f2> [#uses=1] + %R = add %f2 %p, %q ; <%f2> [#uses=1] + store %f2 %R, %f2* %S + ret void +} + +define void @test_f4(%f4* %P, %f4* %Q, %f4* %S) { + %p = load %f4* %P ; <%f4> [#uses=1] + %q = load %f4* %Q ; <%f4> [#uses=1] + %R = add %f4 %p, %q ; <%f4> [#uses=1] + store %f4 %R, %f4* %S + ret void +} + +define void @test_f8(%f8* %P, %f8* %Q, %f8* %S) { + %p = load %f8* %P ; <%f8> [#uses=1] + %q = load %f8* %Q ; <%f8> [#uses=1] + %R = add %f8 %p, %q ; <%f8> [#uses=1] + store %f8 %R, %f8* %S + ret void +} + +define void @test_fmul(%f8* %P, %f8* %Q, %f8* %S) { + %p = load %f8* %P ; <%f8> [#uses=1] + %q = load %f8* %Q ; <%f8> [#uses=1] + %R = mul %f8 %p, %q ; <%f8> [#uses=1] + store %f8 %R, %f8* %S + ret void +} + +define void @test_div(%f8* %P, %f8* %Q, %f8* %S) { + %p = load %f8* %P ; <%f8> [#uses=1] + %q = load %f8* %Q ; <%f8> [#uses=1] + %R = fdiv %f8 %p, %q ; <%f8> [#uses=1] + store %f8 %R, %f8* %S + ret void +} + +;;; TEST VECTOR CONSTRUCTS + +define void @test_cst(%f4* %P, %f4* %S) { + %p = load %f4* %P ; <%f4> [#uses=1] + %R = add %f4 %p, < float 0x3FB99999A0000000, float 1.000000e+00, float + 2.000000e+00, float 4.500000e+00 > ; <%f4> [#uses=1] + store %f4 %R, %f4* %S + ret void +} + +define void @test_zero(%f4* %P, %f4* %S) { + %p = load %f4* %P ; <%f4> [#uses=1] + %R = add %f4 %p, zeroinitializer ; <%f4> [#uses=1] + store %f4 %R, %f4* %S + ret void +} + +define void @test_undef(%f4* %P, %f4* %S) { + %p = load %f4* %P ; <%f4> [#uses=1] + %R = add %f4 %p, undef ; <%f4> [#uses=1] + store %f4 %R, %f4* %S + ret void +} + +define void @test_constant_insert(%f4* %S) { + %R = insertelement %f4 zeroinitializer, float 1.000000e+01, i32 0 + ; <%f4> [#uses=1] + store %f4 %R, %f4* %S + ret void +} + +define void @test_variable_buildvector(float %F, %f4* %S) { + %R = insertelement %f4 zeroinitializer, float %F, i32 0 + store %f4 %R, %f4* %S + ret void +} + +define void @test_scalar_to_vector(float %F, %f4* %S) { + %R = insertelement %f4 undef, float %F, i32 0 + store %f4 %R, %f4* %S + ret void +} + +define float @test_extract_elt(%f8* %P) { + %p = load %f8* %P ; <%f8> [#uses=1] + %R = extractelement %f8 %p, i32 3 ; <float> [#uses=1] + ret float %R +} + +define double @test_extract_elt2(%d8* %P) { + %p = load %d8* %P ; <%d8> [#uses=1] + %R = extractelement %d8 %p, i32 3 ; <double> [#uses=1] + ret double %R +} + +define void @test_cast_1(%f4* %b, %i4* %a) { + %tmp = load %f4* %b ; <%f4> [#uses=1] + %tmp2 = add %f4 %tmp, < float 1.000000e+00, float 2.000000e+00, float +3.000000e+00, float 4.000000e+00 > ; <%f4> [#uses=1] + %tmp3 = bitcast %f4 %tmp2 to %i4 ; <%i4> [#uses=1] + %tmp4 = add %i4 %tmp3, < i32 1, i32 2, i32 3, i32 4 > + store %i4 %tmp4, %i4* %a + ret void +} + +define void @test_cast_2(%f8* %a, <8 x i32>* %b) { + %T = load %f8* %a ; <%f8> [#uses=1] + %T2 = bitcast %f8 %T to <8 x i32> + store <8 x i32> %T2, <8 x i32>* %b + ret void +} + + +;;; TEST IMPORTANT IDIOMS + +define void @splat(%f4* %P, %f4* %Q, float %X) { + %tmp = insertelement %f4 undef, float %X, i32 0 + %tmp2 = insertelement %f4 %tmp, float %X, i32 1 + %tmp4 = insertelement %f4 %tmp2, float %X, i32 2 + %tmp6 = insertelement %f4 %tmp4, float %X, i32 3 + %q = load %f4* %Q ; <%f4> [#uses=1] + %R = add %f4 %q, %tmp6 ; <%f4> [#uses=1] + store %f4 %R, %f4* %P + ret void +} + +define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) { + %tmp = insertelement %i4 undef, i32 %X, i32 0 + %tmp2 = insertelement %i4 %tmp, i32 %X, i32 1 + %tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2 + %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3 + %q = load %i4* %Q ; <%i4> [#uses=1] + %R = add %i4 %q, %tmp6 ; <%i4> [#uses=1] + store %i4 %R, %i4* %P + ret void +} + |