diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2013-12-22 00:04:03 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2013-12-22 00:04:03 +0000 |
| commit | f8af5cf600354830d4ccf59732403f0f073eccb9 (patch) | |
| tree | 2ba0398b4c42ad4f55561327538044fd2c925a8b /test/CodeGen/R600 | |
| parent | 59d6cff90eecf31cb3dd860c4e786674cfdd42eb (diff) | |
Notes
Diffstat (limited to 'test/CodeGen/R600')
171 files changed, 9695 insertions, 1569 deletions
diff --git a/test/CodeGen/R600/128bit-kernel-args.ll b/test/CodeGen/R600/128bit-kernel-args.ll index 114f9e74474f..3c4fcf740c39 100644 --- a/test/CodeGen/R600/128bit-kernel-args.ll +++ b/test/CodeGen/R600/128bit-kernel-args.ll @@ -1,16 +1,26 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -; CHECK: @v4i32_kernel_arg -; CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 40 +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK +; R600-CHECK: @v4i32_kernel_arg +; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y +; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z +; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W +; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X +; SI-CHECK: @v4i32_kernel_arg +; SI-CHECK: BUFFER_STORE_DWORDX4 define void @v4i32_kernel_arg(<4 x i32> addrspace(1)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out ret void } -; CHECK: @v4f32_kernel_arg -; CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 40 +; R600-CHECK: @v4f32_kernel_arg +; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y +; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z +; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W +; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X +; SI-CHECK: @v4f32_kernel_arg +; SI-CHECK: BUFFER_STORE_DWORDX4 define void @v4f32_kernel_args(<4 x float> addrspace(1)* %out, <4 x float> %in) { entry: store <4 x float> %in, <4 x float> addrspace(1)* %out diff --git a/test/CodeGen/R600/32-bit-local-address-space.ll b/test/CodeGen/R600/32-bit-local-address-space.ll new file mode 100644 index 000000000000..7a126878bef4 --- /dev/null +++ b/test/CodeGen/R600/32-bit-local-address-space.ll @@ -0,0 +1,88 @@ +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and +; the global address space(1) uses 64-bit pointers. These tests check to make sure +; the correct pointer size is used for the local address space. + +; The e{{32|64}} suffix on the instructions refers to the encoding size and not +; the size of the operands. The operand size is denoted in the instruction name. +; Instructions with B32, U32, and I32 in their name take 32-bit operands, while +; instructions with B64, U64, and I64 take 64-bit operands. + +; CHECK-LABEL: @local_address_load +; CHECK: V_MOV_B32_e{{32|64}} [[PTR:v[0-9]]] +; CHECK: DS_READ_B32 [[PTR]] +define void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { +entry: + %0 = load i32 addrspace(3)* %in + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: @local_address_gep +; CHECK: S_ADD_I32 [[SPTR:s[0-9]]] +; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; CHECK: DS_READ_B32 [[VPTR]] +define void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) { +entry: + %0 = getelementptr i32 addrspace(3)* %in, i32 %offset + %1 = load i32 addrspace(3)* %0 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: @local_address_gep_const_offset +; CHECK: S_ADD_I32 [[SPTR:s[0-9]]] +; CHECK: V_MOV_B32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; CHECK: DS_READ_B32 [[VPTR]] +define void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { +entry: + %0 = getelementptr i32 addrspace(3)* %in, i32 1 + %1 = load i32 addrspace(3)* %0 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: @null_32bit_lds_ptr: +; CHECK: V_CMP_NE_I32 +; CHECK-NOT: V_CMP_NE_I32 +; CHECK: V_CNDMASK_B32 +define void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds) nounwind { + %cmp = icmp ne i32 addrspace(3)* %lds, null + %x = select i1 %cmp, i32 123, i32 456 + store i32 %x, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: @mul_32bit_ptr: +; CHECK: V_MUL_LO_I32 +; CHECK-NEXT: V_ADD_I32_e32 +; CHECK-NEXT: DS_READ_B32 +define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %lds, i32 %tid) { + %ptr = getelementptr [3 x float] addrspace(3)* %lds, i32 %tid, i32 0 + %val = load float addrspace(3)* %ptr + store float %val, float addrspace(1)* %out + ret void +} + +@g_lds = addrspace(3) global float zeroinitializer, align 4 + +; CHECK-LABEL: @infer_ptr_alignment_global_offset: +; CHECK: V_MOV_B32_e32 [[REG:v[0-9]+]], 0 +; CHECK: DS_READ_B32 v{{[0-9]+}}, 0, [[REG]] +define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) { + %val = load float addrspace(3)* @g_lds + store float %val, float addrspace(1)* %out + ret void +} + + +@ptr = addrspace(3) global i32 addrspace(3)* null +@dst = addrspace(3) global [16384 x i32] zeroinitializer + +; SI-LABEL: @global_ptr: +; SI-CHECK: DS_WRITE_B32 +define void @global_ptr() nounwind { + store i32 addrspace(3)* getelementptr ([16384 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr + ret void +} diff --git a/test/CodeGen/R600/64bit-kernel-args.ll b/test/CodeGen/R600/64bit-kernel-args.ll new file mode 100644 index 000000000000..0d6bfb144d3d --- /dev/null +++ b/test/CodeGen/R600/64bit-kernel-args.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; SI-CHECK: @f64_kernel_arg +; SI-CHECK-DAG: S_LOAD_DWORDX2 s[{{[0-9]:[0-9]}}], s[0:1], 9 +; SI-CHECK-DAG: S_LOAD_DWORDX2 s[{{[0-9]:[0-9]}}], s[0:1], 11 +; SI-CHECK: BUFFER_STORE_DWORDX2 +define void @f64_kernel_arg(double addrspace(1)* %out, double %in) { +entry: + store double %in, double addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll index 185998b26095..3d5506bfa5d2 100644 --- a/test/CodeGen/R600/add.ll +++ b/test/CodeGen/R600/add.ll @@ -1,14 +1,55 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK-LABEL: @test1: +;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +;SI-CHECK-LABEL: @test1: +;SI-CHECK: V_ADD_I32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} +;SI-CHECK-NOT: [[REG]] +;SI-CHECK: BUFFER_STORE_DWORD [[REG]], +define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1 + %a = load i32 addrspace(1)* %in + %b = load i32 addrspace(1)* %b_ptr + %result = add i32 %a, %b + store i32 %result, i32 addrspace(1)* %out + ret void +} + +;EG-CHECK-LABEL: @test2: +;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK-LABEL: @test2: +;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 + %a = load <2 x i32> addrspace(1)* %in + %b = load <2 x i32> addrspace(1)* %b_ptr + %result = add <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +;EG-CHECK-LABEL: @test4: +;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK-LABEL: @test4: +;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 - %a = load <4 x i32> addrspace(1) * %in - %b = load <4 x i32> addrspace(1) * %b_ptr + %a = load <4 x i32> addrspace(1)* %in + %b = load <4 x i32> addrspace(1)* %b_ptr %result = add <4 x i32> %a, %b store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void diff --git a/test/CodeGen/R600/add_i64.ll b/test/CodeGen/R600/add_i64.ll new file mode 100644 index 000000000000..303a1cb03914 --- /dev/null +++ b/test/CodeGen/R600/add_i64.ll @@ -0,0 +1,59 @@ +; XFAIL: * +; This will fail until i64 add is enabled + +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI %s + + +declare i32 @llvm.SI.tid() readnone + +; SI-LABEL: @test_i64_vreg: +define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) { + %tid = call i32 @llvm.SI.tid() readnone + %a_ptr = getelementptr i64 addrspace(1)* %inA, i32 %tid + %b_ptr = getelementptr i64 addrspace(1)* %inB, i32 %tid + %a = load i64 addrspace(1)* %a_ptr + %b = load i64 addrspace(1)* %b_ptr + %result = add i64 %a, %b + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; Check that the SGPR add operand is correctly moved to a VGPR. +; SI-LABEL: @sgpr_operand: +define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) { + %foo = load i64 addrspace(1)* %in, align 8 + %result = add i64 %foo, %a + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; Swap the arguments. Check that the SGPR -> VGPR copy works with the +; SGPR as other operand. +; +; SI-LABEL: @sgpr_operand_reversed: +define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) { + %foo = load i64 addrspace(1)* %in, align 8 + %result = add i64 %a, %foo + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +; SI-LABEL: @test_v2i64_sreg: +define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) { + %result = add <2 x i64> %a, %b + store <2 x i64> %result, <2 x i64> addrspace(1)* %out + ret void +} + +; SI-LABEL: @test_v2i64_vreg: +define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) { + %tid = call i32 @llvm.SI.tid() readnone + %a_ptr = getelementptr <2 x i64> addrspace(1)* %inA, i32 %tid + %b_ptr = getelementptr <2 x i64> addrspace(1)* %inB, i32 %tid + %a = load <2 x i64> addrspace(1)* %a_ptr + %b = load <2 x i64> addrspace(1)* %b_ptr + %result = add <2 x i64> %a, %b + store <2 x i64> %result, <2 x i64> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/address-space.ll b/test/CodeGen/R600/address-space.ll new file mode 100644 index 000000000000..1fc616a4ed42 --- /dev/null +++ b/test/CodeGen/R600/address-space.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s + +; Test that codegenprepare understands address space sizes + +%struct.foo = type { [3 x float], [3 x float] } + +; CHECK-LABEL: @do_as_ptr_calcs: +; CHECK: S_ADD_I32 {{s[0-9]+}}, +; CHECK: S_ADD_I32 [[SREG1:s[0-9]+]], +; CHECK: V_MOV_B32_e32 [[VREG1:v[0-9]+]], [[SREG1]] +; CHECK: DS_READ_B32 [[VREG1]], +define void @do_as_ptr_calcs(%struct.foo addrspace(3)* nocapture %ptr) nounwind { +entry: + %x = getelementptr inbounds %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0 + %y = getelementptr inbounds %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 2 + br label %bb32 + +bb32: + %a = load float addrspace(3)* %x, align 4 + %b = load float addrspace(3)* %y, align 4 + %cmp = fcmp one float %a, %b + br i1 %cmp, label %bb34, label %bb33 + +bb33: + unreachable + +bb34: + unreachable +} + + diff --git a/test/CodeGen/R600/alu-split.ll b/test/CodeGen/R600/alu-split.ll deleted file mode 100644 index 48496f6febf6..000000000000 --- a/test/CodeGen/R600/alu-split.ll +++ /dev/null @@ -1,851 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: ALU -;CHECK: ALU -;CHECK: ALU -;CHECK-NOT: ALU -;CHECK: CF_END - -define void @main() #0 { -main_body: - %0 = call float @llvm.R600.load.input(i32 4) - %1 = call float @llvm.R600.load.input(i32 5) - %2 = call float @llvm.R600.load.input(i32 6) - %3 = call float @llvm.R600.load.input(i32 7) - %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) - %5 = extractelement <4 x float> %4, i32 0 - %6 = fcmp une float 0x4016F2B020000000, %5 - %7 = select i1 %6, float 1.000000e+00, float 0.000000e+00 - %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) - %9 = extractelement <4 x float> %8, i32 1 - %10 = fcmp une float 0x401FDCC640000000, %9 - %11 = select i1 %10, float 1.000000e+00, float 0.000000e+00 - %12 = fsub float -0.000000e+00, %7 - %13 = fptosi float %12 to i32 - %14 = fsub float -0.000000e+00, %11 - %15 = fptosi float %14 to i32 - %16 = bitcast i32 %13 to float - %17 = bitcast i32 %15 to float - %18 = bitcast float %16 to i32 - %19 = bitcast float %17 to i32 - %20 = or i32 %18, %19 - %21 = bitcast i32 %20 to float - %22 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) - %23 = extractelement <4 x float> %22, i32 0 - %24 = fcmp une float 0xC00574BC60000000, %23 - %25 = select i1 %24, float 1.000000e+00, float 0.000000e+00 - %26 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17) - %27 = extractelement <4 x float> %26, i32 1 - %28 = fcmp une float 0x40210068E0000000, %27 - %29 = select i1 %28, float 1.000000e+00, float 0.000000e+00 - %30 = fsub float -0.000000e+00, %25 - %31 = fptosi float %30 to i32 - %32 = fsub float -0.000000e+00, %29 - %33 = fptosi float %32 to i32 - %34 = bitcast i32 %31 to float - %35 = bitcast i32 %33 to float - %36 = bitcast float %34 to i32 - %37 = bitcast float %35 to i32 - %38 = or i32 %36, %37 - %39 = bitcast i32 %38 to float - %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) - %41 = extractelement <4 x float> %40, i32 0 - %42 = fcmp une float 0xBFC9A6B500000000, %41 - %43 = select i1 %42, float 1.000000e+00, float 0.000000e+00 - %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18) - %45 = extractelement <4 x float> %44, i32 1 - %46 = fcmp une float 0xC0119BDA60000000, %45 - %47 = select i1 %46, float 1.000000e+00, float 0.000000e+00 - %48 = fsub float -0.000000e+00, %43 - %49 = fptosi float %48 to i32 - %50 = fsub float -0.000000e+00, %47 - %51 = fptosi float %50 to i32 - %52 = bitcast i32 %49 to float - %53 = bitcast i32 %51 to float - %54 = bitcast float %52 to i32 - %55 = bitcast float %53 to i32 - %56 = or i32 %54, %55 - %57 = bitcast i32 %56 to float - %58 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) - %59 = extractelement <4 x float> %58, i32 0 - %60 = fcmp une float 0xC02085D640000000, %59 - %61 = select i1 %60, float 1.000000e+00, float 0.000000e+00 - %62 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19) - %63 = extractelement <4 x float> %62, i32 1 - %64 = fcmp une float 0xBFD7C1BDA0000000, %63 - %65 = select i1 %64, float 1.000000e+00, float 0.000000e+00 - %66 = fsub float -0.000000e+00, %61 - %67 = fptosi float %66 to i32 - %68 = fsub float -0.000000e+00, %65 - %69 = fptosi float %68 to i32 - %70 = bitcast i32 %67 to float - %71 = bitcast i32 %69 to float - %72 = bitcast float %70 to i32 - %73 = bitcast float %71 to i32 - %74 = or i32 %72, %73 - %75 = bitcast i32 %74 to float - %76 = insertelement <4 x float> undef, float %21, i32 0 - %77 = insertelement <4 x float> %76, float %39, i32 1 - %78 = insertelement <4 x float> %77, float %57, i32 2 - %79 = insertelement <4 x float> %78, float %75, i32 3 - %80 = insertelement <4 x float> undef, float %21, i32 0 - %81 = insertelement <4 x float> %80, float %39, i32 1 - %82 = insertelement <4 x float> %81, float %57, i32 2 - %83 = insertelement <4 x float> %82, float %75, i32 3 - %84 = call float @llvm.AMDGPU.dp4(<4 x float> %79, <4 x float> %83) - %85 = bitcast float %84 to i32 - %86 = icmp ne i32 %85, 0 - %87 = sext i1 %86 to i32 - %88 = bitcast i32 %87 to float - %89 = bitcast float %88 to i32 - %90 = xor i32 %89, -1 - %91 = bitcast i32 %90 to float - %92 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) - %93 = extractelement <4 x float> %92, i32 0 - %94 = fcmp une float 0x401FDCC640000000, %93 - %95 = select i1 %94, float 1.000000e+00, float 0.000000e+00 - %96 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20) - %97 = extractelement <4 x float> %96, i32 1 - %98 = fcmp une float 0xC00574BC60000000, %97 - %99 = select i1 %98, float 1.000000e+00, float 0.000000e+00 - %100 = fsub float -0.000000e+00, %95 - %101 = fptosi float %100 to i32 - %102 = fsub float -0.000000e+00, %99 - %103 = fptosi float %102 to i32 - %104 = bitcast i32 %101 to float - %105 = bitcast i32 %103 to float - %106 = bitcast float %104 to i32 - %107 = bitcast float %105 to i32 - %108 = or i32 %106, %107 - %109 = bitcast i32 %108 to float - %110 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) - %111 = extractelement <4 x float> %110, i32 0 - %112 = fcmp une float 0x40210068E0000000, %111 - %113 = select i1 %112, float 1.000000e+00, float 0.000000e+00 - %114 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21) - %115 = extractelement <4 x float> %114, i32 1 - %116 = fcmp une float 0xBFC9A6B500000000, %115 - %117 = select i1 %116, float 1.000000e+00, float 0.000000e+00 - %118 = fsub float -0.000000e+00, %113 - %119 = fptosi float %118 to i32 - %120 = fsub float -0.000000e+00, %117 - %121 = fptosi float %120 to i32 - %122 = bitcast i32 %119 to float - %123 = bitcast i32 %121 to float - %124 = bitcast float %122 to i32 - %125 = bitcast float %123 to i32 - %126 = or i32 %124, %125 - %127 = bitcast i32 %126 to float - %128 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) - %129 = extractelement <4 x float> %128, i32 0 - %130 = fcmp une float 0xC0119BDA60000000, %129 - %131 = select i1 %130, float 1.000000e+00, float 0.000000e+00 - %132 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22) - %133 = extractelement <4 x float> %132, i32 1 - %134 = fcmp une float 0xC02085D640000000, %133 - %135 = select i1 %134, float 1.000000e+00, float 0.000000e+00 - %136 = fsub float -0.000000e+00, %131 - %137 = fptosi float %136 to i32 - %138 = fsub float -0.000000e+00, %135 - %139 = fptosi float %138 to i32 - %140 = bitcast i32 %137 to float - %141 = bitcast i32 %139 to float - %142 = bitcast float %140 to i32 - %143 = bitcast float %141 to i32 - %144 = or i32 %142, %143 - %145 = bitcast i32 %144 to float - %146 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) - %147 = extractelement <4 x float> %146, i32 0 - %148 = fcmp une float 0xBFD7C1BDA0000000, %147 - %149 = select i1 %148, float 1.000000e+00, float 0.000000e+00 - %150 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) - %151 = extractelement <4 x float> %150, i32 1 - %152 = fcmp une float 0x401E1D7DC0000000, %151 - %153 = select i1 %152, float 1.000000e+00, float 0.000000e+00 - %154 = fsub float -0.000000e+00, %149 - %155 = fptosi float %154 to i32 - %156 = fsub float -0.000000e+00, %153 - %157 = fptosi float %156 to i32 - %158 = bitcast i32 %155 to float - %159 = bitcast i32 %157 to float - %160 = bitcast float %158 to i32 - %161 = bitcast float %159 to i32 - %162 = or i32 %160, %161 - %163 = bitcast i32 %162 to float - %164 = insertelement <4 x float> undef, float %109, i32 0 - %165 = insertelement <4 x float> %164, float %127, i32 1 - %166 = insertelement <4 x float> %165, float %145, i32 2 - %167 = insertelement <4 x float> %166, float %163, i32 3 - %168 = insertelement <4 x float> undef, float %109, i32 0 - %169 = insertelement <4 x float> %168, float %127, i32 1 - %170 = insertelement <4 x float> %169, float %145, i32 2 - %171 = insertelement <4 x float> %170, float %163, i32 3 - %172 = call float @llvm.AMDGPU.dp4(<4 x float> %167, <4 x float> %171) - %173 = bitcast float %172 to i32 - %174 = icmp ne i32 %173, 0 - %175 = sext i1 %174 to i32 - %176 = bitcast i32 %175 to float - %177 = bitcast float %176 to i32 - %178 = xor i32 %177, -1 - %179 = bitcast i32 %178 to float - %180 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) - %181 = extractelement <4 x float> %180, i32 0 - %182 = fcmp une float 0x401FDCC640000000, %181 - %183 = select i1 %182, float 1.000000e+00, float 0.000000e+00 - %184 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) - %185 = extractelement <4 x float> %184, i32 1 - %186 = fcmp une float 0xC00574BC60000000, %185 - %187 = select i1 %186, float 1.000000e+00, float 0.000000e+00 - %188 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) - %189 = extractelement <4 x float> %188, i32 2 - %190 = fcmp une float 0x40210068E0000000, %189 - %191 = select i1 %190, float 1.000000e+00, float 0.000000e+00 - %192 = fsub float -0.000000e+00, %183 - %193 = fptosi float %192 to i32 - %194 = fsub float -0.000000e+00, %187 - %195 = fptosi float %194 to i32 - %196 = fsub float -0.000000e+00, %191 - %197 = fptosi float %196 to i32 - %198 = bitcast i32 %193 to float - %199 = bitcast i32 %195 to float - %200 = bitcast i32 %197 to float - %201 = bitcast float %199 to i32 - %202 = bitcast float %200 to i32 - %203 = or i32 %201, %202 - %204 = bitcast i32 %203 to float - %205 = bitcast float %198 to i32 - %206 = bitcast float %204 to i32 - %207 = or i32 %205, %206 - %208 = bitcast i32 %207 to float - %209 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) - %210 = extractelement <4 x float> %209, i32 0 - %211 = fcmp une float 0xBFC9A6B500000000, %210 - %212 = select i1 %211, float 1.000000e+00, float 0.000000e+00 - %213 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) - %214 = extractelement <4 x float> %213, i32 1 - %215 = fcmp une float 0xC0119BDA60000000, %214 - %216 = select i1 %215, float 1.000000e+00, float 0.000000e+00 - %217 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) - %218 = extractelement <4 x float> %217, i32 2 - %219 = fcmp une float 0xC02085D640000000, %218 - %220 = select i1 %219, float 1.000000e+00, float 0.000000e+00 - %221 = fsub float -0.000000e+00, %212 - %222 = fptosi float %221 to i32 - %223 = fsub float -0.000000e+00, %216 - %224 = fptosi float %223 to i32 - %225 = fsub float -0.000000e+00, %220 - %226 = fptosi float %225 to i32 - %227 = bitcast i32 %222 to float - %228 = bitcast i32 %224 to float - %229 = bitcast i32 %226 to float - %230 = bitcast float %228 to i32 - %231 = bitcast float %229 to i32 - %232 = or i32 %230, %231 - %233 = bitcast i32 %232 to float - %234 = bitcast float %227 to i32 - %235 = bitcast float %233 to i32 - %236 = or i32 %234, %235 - %237 = bitcast i32 %236 to float - %238 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) - %239 = extractelement <4 x float> %238, i32 0 - %240 = fcmp une float 0xBFD7C1BDA0000000, %239 - %241 = select i1 %240, float 1.000000e+00, float 0.000000e+00 - %242 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) - %243 = extractelement <4 x float> %242, i32 1 - %244 = fcmp une float 0x401E1D7DC0000000, %243 - %245 = select i1 %244, float 1.000000e+00, float 0.000000e+00 - %246 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) - %247 = extractelement <4 x float> %246, i32 2 - %248 = fcmp une float 0xC019893740000000, %247 - %249 = select i1 %248, float 1.000000e+00, float 0.000000e+00 - %250 = fsub float -0.000000e+00, %241 - %251 = fptosi float %250 to i32 - %252 = fsub float -0.000000e+00, %245 - %253 = fptosi float %252 to i32 - %254 = fsub float -0.000000e+00, %249 - %255 = fptosi float %254 to i32 - %256 = bitcast i32 %251 to float - %257 = bitcast i32 %253 to float - %258 = bitcast i32 %255 to float - %259 = bitcast float %257 to i32 - %260 = bitcast float %258 to i32 - %261 = or i32 %259, %260 - %262 = bitcast i32 %261 to float - %263 = bitcast float %256 to i32 - %264 = bitcast float %262 to i32 - %265 = or i32 %263, %264 - %266 = bitcast i32 %265 to float - %267 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) - %268 = extractelement <4 x float> %267, i32 0 - %269 = fcmp une float 0x40220F0D80000000, %268 - %270 = select i1 %269, float 1.000000e+00, float 0.000000e+00 - %271 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) - %272 = extractelement <4 x float> %271, i32 1 - %273 = fcmp une float 0xC018E2EB20000000, %272 - %274 = select i1 %273, float 1.000000e+00, float 0.000000e+00 - %275 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) - %276 = extractelement <4 x float> %275, i32 2 - %277 = fcmp une float 0xBFEA8DB8C0000000, %276 - %278 = select i1 %277, float 1.000000e+00, float 0.000000e+00 - %279 = fsub float -0.000000e+00, %270 - %280 = fptosi float %279 to i32 - %281 = fsub float -0.000000e+00, %274 - %282 = fptosi float %281 to i32 - %283 = fsub float -0.000000e+00, %278 - %284 = fptosi float %283 to i32 - %285 = bitcast i32 %280 to float - %286 = bitcast i32 %282 to float - %287 = bitcast i32 %284 to float - %288 = bitcast float %286 to i32 - %289 = bitcast float %287 to i32 - %290 = or i32 %288, %289 - %291 = bitcast i32 %290 to float - %292 = bitcast float %285 to i32 - %293 = bitcast float %291 to i32 - %294 = or i32 %292, %293 - %295 = bitcast i32 %294 to float - %296 = insertelement <4 x float> undef, float %208, i32 0 - %297 = insertelement <4 x float> %296, float %237, i32 1 - %298 = insertelement <4 x float> %297, float %266, i32 2 - %299 = insertelement <4 x float> %298, float %295, i32 3 - %300 = insertelement <4 x float> undef, float %208, i32 0 - %301 = insertelement <4 x float> %300, float %237, i32 1 - %302 = insertelement <4 x float> %301, float %266, i32 2 - %303 = insertelement <4 x float> %302, float %295, i32 3 - %304 = call float @llvm.AMDGPU.dp4(<4 x float> %299, <4 x float> %303) - %305 = bitcast float %304 to i32 - %306 = icmp ne i32 %305, 0 - %307 = sext i1 %306 to i32 - %308 = bitcast i32 %307 to float - %309 = bitcast float %308 to i32 - %310 = xor i32 %309, -1 - %311 = bitcast i32 %310 to float - %312 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) - %313 = extractelement <4 x float> %312, i32 0 - %314 = fcmp une float 0xC00574BC60000000, %313 - %315 = select i1 %314, float 1.000000e+00, float 0.000000e+00 - %316 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) - %317 = extractelement <4 x float> %316, i32 1 - %318 = fcmp une float 0x40210068E0000000, %317 - %319 = select i1 %318, float 1.000000e+00, float 0.000000e+00 - %320 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) - %321 = extractelement <4 x float> %320, i32 2 - %322 = fcmp une float 0xBFC9A6B500000000, %321 - %323 = select i1 %322, float 1.000000e+00, float 0.000000e+00 - %324 = fsub float -0.000000e+00, %315 - %325 = fptosi float %324 to i32 - %326 = fsub float -0.000000e+00, %319 - %327 = fptosi float %326 to i32 - %328 = fsub float -0.000000e+00, %323 - %329 = fptosi float %328 to i32 - %330 = bitcast i32 %325 to float - %331 = bitcast i32 %327 to float - %332 = bitcast i32 %329 to float - %333 = bitcast float %331 to i32 - %334 = bitcast float %332 to i32 - %335 = or i32 %333, %334 - %336 = bitcast i32 %335 to float - %337 = bitcast float %330 to i32 - %338 = bitcast float %336 to i32 - %339 = or i32 %337, %338 - %340 = bitcast i32 %339 to float - %341 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) - %342 = extractelement <4 x float> %341, i32 0 - %343 = fcmp une float 0xC0119BDA60000000, %342 - %344 = select i1 %343, float 1.000000e+00, float 0.000000e+00 - %345 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) - %346 = extractelement <4 x float> %345, i32 1 - %347 = fcmp une float 0xC02085D640000000, %346 - %348 = select i1 %347, float 1.000000e+00, float 0.000000e+00 - %349 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) - %350 = extractelement <4 x float> %349, i32 2 - %351 = fcmp une float 0xBFD7C1BDA0000000, %350 - %352 = select i1 %351, float 1.000000e+00, float 0.000000e+00 - %353 = fsub float -0.000000e+00, %344 - %354 = fptosi float %353 to i32 - %355 = fsub float -0.000000e+00, %348 - %356 = fptosi float %355 to i32 - %357 = fsub float -0.000000e+00, %352 - %358 = fptosi float %357 to i32 - %359 = bitcast i32 %354 to float - %360 = bitcast i32 %356 to float - %361 = bitcast i32 %358 to float - %362 = bitcast float %360 to i32 - %363 = bitcast float %361 to i32 - %364 = or i32 %362, %363 - %365 = bitcast i32 %364 to float - %366 = bitcast float %359 to i32 - %367 = bitcast float %365 to i32 - %368 = or i32 %366, %367 - %369 = bitcast i32 %368 to float - %370 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) - %371 = extractelement <4 x float> %370, i32 0 - %372 = fcmp une float 0x401E1D7DC0000000, %371 - %373 = select i1 %372, float 1.000000e+00, float 0.000000e+00 - %374 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) - %375 = extractelement <4 x float> %374, i32 1 - %376 = fcmp une float 0xC019893740000000, %375 - %377 = select i1 %376, float 1.000000e+00, float 0.000000e+00 - %378 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) - %379 = extractelement <4 x float> %378, i32 2 - %380 = fcmp une float 0x40220F0D80000000, %379 - %381 = select i1 %380, float 1.000000e+00, float 0.000000e+00 - %382 = fsub float -0.000000e+00, %373 - %383 = fptosi float %382 to i32 - %384 = fsub float -0.000000e+00, %377 - %385 = fptosi float %384 to i32 - %386 = fsub float -0.000000e+00, %381 - %387 = fptosi float %386 to i32 - %388 = bitcast i32 %383 to float - %389 = bitcast i32 %385 to float - %390 = bitcast i32 %387 to float - %391 = bitcast float %389 to i32 - %392 = bitcast float %390 to i32 - %393 = or i32 %391, %392 - %394 = bitcast i32 %393 to float - %395 = bitcast float %388 to i32 - %396 = bitcast float %394 to i32 - %397 = or i32 %395, %396 - %398 = bitcast i32 %397 to float - %399 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) - %400 = extractelement <4 x float> %399, i32 0 - %401 = fcmp une float 0xC018E2EB20000000, %400 - %402 = select i1 %401, float 1.000000e+00, float 0.000000e+00 - %403 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) - %404 = extractelement <4 x float> %403, i32 1 - %405 = fcmp une float 0xBFEA8DB8C0000000, %404 - %406 = select i1 %405, float 1.000000e+00, float 0.000000e+00 - %407 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) - %408 = extractelement <4 x float> %407, i32 2 - %409 = fcmp une float 0x4015236E20000000, %408 - %410 = select i1 %409, float 1.000000e+00, float 0.000000e+00 - %411 = fsub float -0.000000e+00, %402 - %412 = fptosi float %411 to i32 - %413 = fsub float -0.000000e+00, %406 - %414 = fptosi float %413 to i32 - %415 = fsub float -0.000000e+00, %410 - %416 = fptosi float %415 to i32 - %417 = bitcast i32 %412 to float - %418 = bitcast i32 %414 to float - %419 = bitcast i32 %416 to float - %420 = bitcast float %418 to i32 - %421 = bitcast float %419 to i32 - %422 = or i32 %420, %421 - %423 = bitcast i32 %422 to float - %424 = bitcast float %417 to i32 - %425 = bitcast float %423 to i32 - %426 = or i32 %424, %425 - %427 = bitcast i32 %426 to float - %428 = insertelement <4 x float> undef, float %340, i32 0 - %429 = insertelement <4 x float> %428, float %369, i32 1 - %430 = insertelement <4 x float> %429, float %398, i32 2 - %431 = insertelement <4 x float> %430, float %427, i32 3 - %432 = insertelement <4 x float> undef, float %340, i32 0 - %433 = insertelement <4 x float> %432, float %369, i32 1 - %434 = insertelement <4 x float> %433, float %398, i32 2 - %435 = insertelement <4 x float> %434, float %427, i32 3 - %436 = call float @llvm.AMDGPU.dp4(<4 x float> %431, <4 x float> %435) - %437 = bitcast float %436 to i32 - %438 = icmp ne i32 %437, 0 - %439 = sext i1 %438 to i32 - %440 = bitcast i32 %439 to float - %441 = bitcast float %440 to i32 - %442 = xor i32 %441, -1 - %443 = bitcast i32 %442 to float - %444 = load <4 x float> addrspace(8)* null - %445 = extractelement <4 x float> %444, i32 0 - %446 = fcmp une float 0xC00574BC60000000, %445 - %447 = select i1 %446, float 1.000000e+00, float 0.000000e+00 - %448 = load <4 x float> addrspace(8)* null - %449 = extractelement <4 x float> %448, i32 1 - %450 = fcmp une float 0x40210068E0000000, %449 - %451 = select i1 %450, float 1.000000e+00, float 0.000000e+00 - %452 = load <4 x float> addrspace(8)* null - %453 = extractelement <4 x float> %452, i32 2 - %454 = fcmp une float 0xBFC9A6B500000000, %453 - %455 = select i1 %454, float 1.000000e+00, float 0.000000e+00 - %456 = load <4 x float> addrspace(8)* null - %457 = extractelement <4 x float> %456, i32 3 - %458 = fcmp une float 0xC0119BDA60000000, %457 - %459 = select i1 %458, float 1.000000e+00, float 0.000000e+00 - %460 = fsub float -0.000000e+00, %447 - %461 = fptosi float %460 to i32 - %462 = fsub float -0.000000e+00, %451 - %463 = fptosi float %462 to i32 - %464 = fsub float -0.000000e+00, %455 - %465 = fptosi float %464 to i32 - %466 = fsub float -0.000000e+00, %459 - %467 = fptosi float %466 to i32 - %468 = bitcast i32 %461 to float - %469 = bitcast i32 %463 to float - %470 = bitcast i32 %465 to float - %471 = bitcast i32 %467 to float - %472 = bitcast float %468 to i32 - %473 = bitcast float %469 to i32 - %474 = or i32 %472, %473 - %475 = bitcast i32 %474 to float - %476 = bitcast float %470 to i32 - %477 = bitcast float %471 to i32 - %478 = or i32 %476, %477 - %479 = bitcast i32 %478 to float - %480 = bitcast float %475 to i32 - %481 = bitcast float %479 to i32 - %482 = or i32 %480, %481 - %483 = bitcast i32 %482 to float - %484 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %485 = extractelement <4 x float> %484, i32 0 - %486 = fcmp une float 0xC02085D640000000, %485 - %487 = select i1 %486, float 1.000000e+00, float 0.000000e+00 - %488 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %489 = extractelement <4 x float> %488, i32 1 - %490 = fcmp une float 0xBFD7C1BDA0000000, %489 - %491 = select i1 %490, float 1.000000e+00, float 0.000000e+00 - %492 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %493 = extractelement <4 x float> %492, i32 2 - %494 = fcmp une float 0x401E1D7DC0000000, %493 - %495 = select i1 %494, float 1.000000e+00, float 0.000000e+00 - %496 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %497 = extractelement <4 x float> %496, i32 3 - %498 = fcmp une float 0xC019893740000000, %497 - %499 = select i1 %498, float 1.000000e+00, float 0.000000e+00 - %500 = fsub float -0.000000e+00, %487 - %501 = fptosi float %500 to i32 - %502 = fsub float -0.000000e+00, %491 - %503 = fptosi float %502 to i32 - %504 = fsub float -0.000000e+00, %495 - %505 = fptosi float %504 to i32 - %506 = fsub float -0.000000e+00, %499 - %507 = fptosi float %506 to i32 - %508 = bitcast i32 %501 to float - %509 = bitcast i32 %503 to float - %510 = bitcast i32 %505 to float - %511 = bitcast i32 %507 to float - %512 = bitcast float %508 to i32 - %513 = bitcast float %509 to i32 - %514 = or i32 %512, %513 - %515 = bitcast i32 %514 to float - %516 = bitcast float %510 to i32 - %517 = bitcast float %511 to i32 - %518 = or i32 %516, %517 - %519 = bitcast i32 %518 to float - %520 = bitcast float %515 to i32 - %521 = bitcast float %519 to i32 - %522 = or i32 %520, %521 - %523 = bitcast i32 %522 to float - %524 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) - %525 = extractelement <4 x float> %524, i32 0 - %526 = fcmp une float 0x40220F0D80000000, %525 - %527 = select i1 %526, float 1.000000e+00, float 0.000000e+00 - %528 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) - %529 = extractelement <4 x float> %528, i32 1 - %530 = fcmp une float 0xC018E2EB20000000, %529 - %531 = select i1 %530, float 1.000000e+00, float 0.000000e+00 - %532 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) - %533 = extractelement <4 x float> %532, i32 2 - %534 = fcmp une float 0xBFEA8DB8C0000000, %533 - %535 = select i1 %534, float 1.000000e+00, float 0.000000e+00 - %536 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) - %537 = extractelement <4 x float> %536, i32 3 - %538 = fcmp une float 0x4015236E20000000, %537 - %539 = select i1 %538, float 1.000000e+00, float 0.000000e+00 - %540 = fsub float -0.000000e+00, %527 - %541 = fptosi float %540 to i32 - %542 = fsub float -0.000000e+00, %531 - %543 = fptosi float %542 to i32 - %544 = fsub float -0.000000e+00, %535 - %545 = fptosi float %544 to i32 - %546 = fsub float -0.000000e+00, %539 - %547 = fptosi float %546 to i32 - %548 = bitcast i32 %541 to float - %549 = bitcast i32 %543 to float - %550 = bitcast i32 %545 to float - %551 = bitcast i32 %547 to float - %552 = bitcast float %548 to i32 - %553 = bitcast float %549 to i32 - %554 = or i32 %552, %553 - %555 = bitcast i32 %554 to float - %556 = bitcast float %550 to i32 - %557 = bitcast float %551 to i32 - %558 = or i32 %556, %557 - %559 = bitcast i32 %558 to float - %560 = bitcast float %555 to i32 - %561 = bitcast float %559 to i32 - %562 = or i32 %560, %561 - %563 = bitcast i32 %562 to float - %564 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) - %565 = extractelement <4 x float> %564, i32 0 - %566 = fcmp une float 0x4016ED5D00000000, %565 - %567 = select i1 %566, float 1.000000e+00, float 0.000000e+00 - %568 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) - %569 = extractelement <4 x float> %568, i32 1 - %570 = fcmp une float 0x402332FEC0000000, %569 - %571 = select i1 %570, float 1.000000e+00, float 0.000000e+00 - %572 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) - %573 = extractelement <4 x float> %572, i32 2 - %574 = fcmp une float 0xC01484B5E0000000, %573 - %575 = select i1 %574, float 1.000000e+00, float 0.000000e+00 - %576 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) - %577 = extractelement <4 x float> %576, i32 3 - %578 = fcmp une float 0x400179A6C0000000, %577 - %579 = select i1 %578, float 1.000000e+00, float 0.000000e+00 - %580 = fsub float -0.000000e+00, %567 - %581 = fptosi float %580 to i32 - %582 = fsub float -0.000000e+00, %571 - %583 = fptosi float %582 to i32 - %584 = fsub float -0.000000e+00, %575 - %585 = fptosi float %584 to i32 - %586 = fsub float -0.000000e+00, %579 - %587 = fptosi float %586 to i32 - %588 = bitcast i32 %581 to float - %589 = bitcast i32 %583 to float - %590 = bitcast i32 %585 to float - %591 = bitcast i32 %587 to float - %592 = bitcast float %588 to i32 - %593 = bitcast float %589 to i32 - %594 = or i32 %592, %593 - %595 = bitcast i32 %594 to float - %596 = bitcast float %590 to i32 - %597 = bitcast float %591 to i32 - %598 = or i32 %596, %597 - %599 = bitcast i32 %598 to float - %600 = bitcast float %595 to i32 - %601 = bitcast float %599 to i32 - %602 = or i32 %600, %601 - %603 = bitcast i32 %602 to float - %604 = insertelement <4 x float> undef, float %483, i32 0 - %605 = insertelement <4 x float> %604, float %523, i32 1 - %606 = insertelement <4 x float> %605, float %563, i32 2 - %607 = insertelement <4 x float> %606, float %603, i32 3 - %608 = insertelement <4 x float> undef, float %483, i32 0 - %609 = insertelement <4 x float> %608, float %523, i32 1 - %610 = insertelement <4 x float> %609, float %563, i32 2 - %611 = insertelement <4 x float> %610, float %603, i32 3 - %612 = call float @llvm.AMDGPU.dp4(<4 x float> %607, <4 x float> %611) - %613 = bitcast float %612 to i32 - %614 = icmp ne i32 %613, 0 - %615 = sext i1 %614 to i32 - %616 = bitcast i32 %615 to float - %617 = bitcast float %616 to i32 - %618 = xor i32 %617, -1 - %619 = bitcast i32 %618 to float - %620 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) - %621 = extractelement <4 x float> %620, i32 0 - %622 = fcmp une float 0x40210068E0000000, %621 - %623 = select i1 %622, float 1.000000e+00, float 0.000000e+00 - %624 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) - %625 = extractelement <4 x float> %624, i32 1 - %626 = fcmp une float 0xBFC9A6B500000000, %625 - %627 = select i1 %626, float 1.000000e+00, float 0.000000e+00 - %628 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) - %629 = extractelement <4 x float> %628, i32 2 - %630 = fcmp une float 0xC0119BDA60000000, %629 - %631 = select i1 %630, float 1.000000e+00, float 0.000000e+00 - %632 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) - %633 = extractelement <4 x float> %632, i32 3 - %634 = fcmp une float 0xC02085D640000000, %633 - %635 = select i1 %634, float 1.000000e+00, float 0.000000e+00 - %636 = fsub float -0.000000e+00, %623 - %637 = fptosi float %636 to i32 - %638 = fsub float -0.000000e+00, %627 - %639 = fptosi float %638 to i32 - %640 = fsub float -0.000000e+00, %631 - %641 = fptosi float %640 to i32 - %642 = fsub float -0.000000e+00, %635 - %643 = fptosi float %642 to i32 - %644 = bitcast i32 %637 to float - %645 = bitcast i32 %639 to float - %646 = bitcast i32 %641 to float - %647 = bitcast i32 %643 to float - %648 = bitcast float %644 to i32 - %649 = bitcast float %645 to i32 - %650 = or i32 %648, %649 - %651 = bitcast i32 %650 to float - %652 = bitcast float %646 to i32 - %653 = bitcast float %647 to i32 - %654 = or i32 %652, %653 - %655 = bitcast i32 %654 to float - %656 = bitcast float %651 to i32 - %657 = bitcast float %655 to i32 - %658 = or i32 %656, %657 - %659 = bitcast i32 %658 to float - %660 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) - %661 = extractelement <4 x float> %660, i32 0 - %662 = fcmp une float 0xBFD7C1BDA0000000, %661 - %663 = select i1 %662, float 1.000000e+00, float 0.000000e+00 - %664 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) - %665 = extractelement <4 x float> %664, i32 1 - %666 = fcmp une float 0x401E1D7DC0000000, %665 - %667 = select i1 %666, float 1.000000e+00, float 0.000000e+00 - %668 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) - %669 = extractelement <4 x float> %668, i32 2 - %670 = fcmp une float 0xC019893740000000, %669 - %671 = select i1 %670, float 1.000000e+00, float 0.000000e+00 - %672 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) - %673 = extractelement <4 x float> %672, i32 3 - %674 = fcmp une float 0x40220F0D80000000, %673 - %675 = select i1 %674, float 1.000000e+00, float 0.000000e+00 - %676 = fsub float -0.000000e+00, %663 - %677 = fptosi float %676 to i32 - %678 = fsub float -0.000000e+00, %667 - %679 = fptosi float %678 to i32 - %680 = fsub float -0.000000e+00, %671 - %681 = fptosi float %680 to i32 - %682 = fsub float -0.000000e+00, %675 - %683 = fptosi float %682 to i32 - %684 = bitcast i32 %677 to float - %685 = bitcast i32 %679 to float - %686 = bitcast i32 %681 to float - %687 = bitcast i32 %683 to float - %688 = bitcast float %684 to i32 - %689 = bitcast float %685 to i32 - %690 = or i32 %688, %689 - %691 = bitcast i32 %690 to float - %692 = bitcast float %686 to i32 - %693 = bitcast float %687 to i32 - %694 = or i32 %692, %693 - %695 = bitcast i32 %694 to float - %696 = bitcast float %691 to i32 - %697 = bitcast float %695 to i32 - %698 = or i32 %696, %697 - %699 = bitcast i32 %698 to float - %700 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) - %701 = extractelement <4 x float> %700, i32 0 - %702 = fcmp une float 0xC018E2EB20000000, %701 - %703 = select i1 %702, float 1.000000e+00, float 0.000000e+00 - %704 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) - %705 = extractelement <4 x float> %704, i32 1 - %706 = fcmp une float 0xBFEA8DB8C0000000, %705 - %707 = select i1 %706, float 1.000000e+00, float 0.000000e+00 - %708 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) - %709 = extractelement <4 x float> %708, i32 2 - %710 = fcmp une float 0x4015236E20000000, %709 - %711 = select i1 %710, float 1.000000e+00, float 0.000000e+00 - %712 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) - %713 = extractelement <4 x float> %712, i32 3 - %714 = fcmp une float 0x4016ED5D00000000, %713 - %715 = select i1 %714, float 1.000000e+00, float 0.000000e+00 - %716 = fsub float -0.000000e+00, %703 - %717 = fptosi float %716 to i32 - %718 = fsub float -0.000000e+00, %707 - %719 = fptosi float %718 to i32 - %720 = fsub float -0.000000e+00, %711 - %721 = fptosi float %720 to i32 - %722 = fsub float -0.000000e+00, %715 - %723 = fptosi float %722 to i32 - %724 = bitcast i32 %717 to float - %725 = bitcast i32 %719 to float - %726 = bitcast i32 %721 to float - %727 = bitcast i32 %723 to float - %728 = bitcast float %724 to i32 - %729 = bitcast float %725 to i32 - %730 = or i32 %728, %729 - %731 = bitcast i32 %730 to float - %732 = bitcast float %726 to i32 - %733 = bitcast float %727 to i32 - %734 = or i32 %732, %733 - %735 = bitcast i32 %734 to float - %736 = bitcast float %731 to i32 - %737 = bitcast float %735 to i32 - %738 = or i32 %736, %737 - %739 = bitcast i32 %738 to float - %740 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) - %741 = extractelement <4 x float> %740, i32 0 - %742 = fcmp une float 0x402332FEC0000000, %741 - %743 = select i1 %742, float 1.000000e+00, float 0.000000e+00 - %744 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) - %745 = extractelement <4 x float> %744, i32 1 - %746 = fcmp une float 0xC01484B5E0000000, %745 - %747 = select i1 %746, float 1.000000e+00, float 0.000000e+00 - %748 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) - %749 = extractelement <4 x float> %748, i32 2 - %750 = fcmp une float 0x400179A6C0000000, %749 - %751 = select i1 %750, float 1.000000e+00, float 0.000000e+00 - %752 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) - %753 = extractelement <4 x float> %752, i32 3 - %754 = fcmp une float 0xBFEE752540000000, %753 - %755 = select i1 %754, float 1.000000e+00, float 0.000000e+00 - %756 = fsub float -0.000000e+00, %743 - %757 = fptosi float %756 to i32 - %758 = fsub float -0.000000e+00, %747 - %759 = fptosi float %758 to i32 - %760 = fsub float -0.000000e+00, %751 - %761 = fptosi float %760 to i32 - %762 = fsub float -0.000000e+00, %755 - %763 = fptosi float %762 to i32 - %764 = bitcast i32 %757 to float - %765 = bitcast i32 %759 to float - %766 = bitcast i32 %761 to float - %767 = bitcast i32 %763 to float - %768 = bitcast float %764 to i32 - %769 = bitcast float %765 to i32 - %770 = or i32 %768, %769 - %771 = bitcast i32 %770 to float - %772 = bitcast float %766 to i32 - %773 = bitcast float %767 to i32 - %774 = or i32 %772, %773 - %775 = bitcast i32 %774 to float - %776 = bitcast float %771 to i32 - %777 = bitcast float %775 to i32 - %778 = or i32 %776, %777 - %779 = bitcast i32 %778 to float - %780 = insertelement <4 x float> undef, float %659, i32 0 - %781 = insertelement <4 x float> %780, float %699, i32 1 - %782 = insertelement <4 x float> %781, float %739, i32 2 - %783 = insertelement <4 x float> %782, float %779, i32 3 - %784 = insertelement <4 x float> undef, float %659, i32 0 - %785 = insertelement <4 x float> %784, float %699, i32 1 - %786 = insertelement <4 x float> %785, float %739, i32 2 - %787 = insertelement <4 x float> %786, float %779, i32 3 - %788 = call float @llvm.AMDGPU.dp4(<4 x float> %783, <4 x float> %787) - %789 = bitcast float %788 to i32 - %790 = icmp ne i32 %789, 0 - %791 = sext i1 %790 to i32 - %792 = bitcast i32 %791 to float - %793 = bitcast float %792 to i32 - %794 = xor i32 %793, -1 - %795 = bitcast i32 %794 to float - %796 = bitcast float %91 to i32 - %797 = bitcast float %179 to i32 - %798 = and i32 %796, %797 - %799 = bitcast i32 %798 to float - %800 = bitcast float %311 to i32 - %801 = bitcast float %443 to i32 - %802 = and i32 %800, %801 - %803 = bitcast i32 %802 to float - %804 = bitcast float %799 to i32 - %805 = bitcast float %803 to i32 - %806 = and i32 %804, %805 - %807 = bitcast i32 %806 to float - %808 = bitcast float %619 to i32 - %809 = bitcast float %795 to i32 - %810 = and i32 %808, %809 - %811 = bitcast i32 %810 to float - %812 = bitcast float %807 to i32 - %813 = bitcast float %811 to i32 - %814 = and i32 %812, %813 - %815 = bitcast i32 %814 to float - %816 = bitcast float %815 to i32 - %817 = icmp ne i32 %816, 0 - %. = select i1 %817, float 1.000000e+00, float 0.000000e+00 - %.32 = select i1 %817, float 0.000000e+00, float 1.000000e+00 - %818 = insertelement <4 x float> undef, float %0, i32 0 - %819 = insertelement <4 x float> %818, float %1, i32 1 - %820 = insertelement <4 x float> %819, float %2, i32 2 - %821 = insertelement <4 x float> %820, float %3, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %821, i32 60, i32 1) - %822 = insertelement <4 x float> undef, float %.32, i32 0 - %823 = insertelement <4 x float> %822, float %., i32 1 - %824 = insertelement <4 x float> %823, float 0.000000e+00, i32 2 - %825 = insertelement <4 x float> %824, float 1.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %825, i32 0, i32 2) - ret void -} - -declare float @llvm.R600.load.input(i32) #1 - -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 - -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="1" } -attributes #1 = { readnone } diff --git a/test/CodeGen/R600/and.ll b/test/CodeGen/R600/and.ll index 166af2d8d128..ee9bc836eb86 100644 --- a/test/CodeGen/R600/and.ll +++ b/test/CodeGen/R600/and.ll @@ -1,11 +1,36 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: @test2 +;EG-CHECK: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +;SI-CHECK: @test2 +;SI-CHECK: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 + %a = load <2 x i32> addrspace(1) * %in + %b = load <2 x i32> addrspace(1) * %b_ptr + %result = and <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +;EG-CHECK: @test4 +;EG-CHECK: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK: @test4 +;SI-CHECK: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_AND_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 %a = load <4 x i32> addrspace(1) * %in %b = load <4 x i32> addrspace(1) * %b_ptr diff --git a/test/CodeGen/R600/array-ptr-calc-i64.ll b/test/CodeGen/R600/array-ptr-calc-i64.ll new file mode 100644 index 000000000000..652bbfe2a415 --- /dev/null +++ b/test/CodeGen/R600/array-ptr-calc-i64.ll @@ -0,0 +1,18 @@ +; XFAIL: * +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI %s + +declare i32 @llvm.SI.tid() readnone + + +; SI-LABEL: @test_array_ptr_calc( +define void @test_array_ptr_calc(i32 addrspace(1)* noalias %out, [16 x i32] addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) { + %tid = call i32 @llvm.SI.tid() readnone + %a_ptr = getelementptr [16 x i32] addrspace(1)* %inA, i32 1, i32 %tid + %b_ptr = getelementptr i32 addrspace(1)* %inB, i32 %tid + %a = load i32 addrspace(1)* %a_ptr + %b = load i32 addrspace(1)* %b_ptr + %result = add i32 %a, %b + store i32 %result, i32 addrspace(1)* %out + ret void +} + diff --git a/test/CodeGen/R600/atomic_load_add.ll b/test/CodeGen/R600/atomic_load_add.ll new file mode 100644 index 000000000000..0bc48a3590b2 --- /dev/null +++ b/test/CodeGen/R600/atomic_load_add.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; R600-CHECK-LABEL: @atomic_add_local +; R600-CHECK: LDS_ADD * +; SI-CHECK-LABEL: @atomic_add_local +; SI-CHECK: DS_ADD_U32_RTN 0 +define void @atomic_add_local(i32 addrspace(3)* %local) { +entry: + %0 = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst + ret void +} + +; R600-CHECK-LABEL: @atomic_add_ret_local +; R600-CHECK: LDS_ADD_RET * +; SI-CHECK-LABEL: @atomic_add_ret_local +; SI-CHECK: DS_ADD_U32_RTN 0 +define void @atomic_add_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) { +entry: + %0 = atomicrmw volatile add i32 addrspace(3)* %local, i32 5 seq_cst + store i32 %0, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/atomic_load_sub.ll b/test/CodeGen/R600/atomic_load_sub.ll new file mode 100644 index 000000000000..e4a682932c82 --- /dev/null +++ b/test/CodeGen/R600/atomic_load_sub.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; R600-CHECK-LABEL: @atomic_sub_local +; R600-CHECK: LDS_SUB * +; SI-CHECK-LABEL: @atomic_sub_local +; SI-CHECK: DS_SUB_U32_RTN 0 +define void @atomic_sub_local(i32 addrspace(3)* %local) { +entry: + %0 = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst + ret void +} + +; R600-CHECK-LABEL: @atomic_sub_ret_local +; R600-CHECK: LDS_SUB_RET * +; SI-CHECK-LABEL: @atomic_sub_ret_local +; SI-CHECK: DS_SUB_U32_RTN 0 +define void @atomic_sub_ret_local(i32 addrspace(1)* %out, i32 addrspace(3)* %local) { +entry: + %0 = atomicrmw volatile sub i32 addrspace(3)* %local, i32 5 seq_cst + store i32 %0, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/bfi_int.ll b/test/CodeGen/R600/bfi_int.ll index 4244dcf3c77b..bbfe856fc930 100644 --- a/test/CodeGen/R600/bfi_int.ll +++ b/test/CodeGen/R600/bfi_int.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ; BFI_INT Definition pattern from ISA docs ; (y & x) | (z & ~x) @@ -36,10 +36,10 @@ entry: ; SHA-256 Ma function ; ((x & z) | (y & (x | z))) ; R600-CHECK: @bfi_sha256_ma -; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV.x}}, {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; SI-CHECK: V_XOR_B32_e32 [[DST:VGPR[0-9]+]], {{VGPR[0-9]+, VGPR[0-9]+}} -; SI-CHECK: V_BFI_B32 {{VGPR[0-9]+}}, [[DST]], {{VGPR[0-9]+, VGPR[0-9]+}} +; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W +; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W +; SI-CHECK: V_XOR_B32_e64 [[DST:v[0-9]+]], {{[sv][0-9]+, v[0-9]+}} +; SI-CHECK: V_BFI_B32 {{v[0-9]+}}, [[DST]], {{[sv][0-9]+, [sv][0-9]+}} define void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) { entry: diff --git a/test/CodeGen/R600/big_alu.ll b/test/CodeGen/R600/big_alu.ll new file mode 100644 index 000000000000..6b683769fe06 --- /dev/null +++ b/test/CodeGen/R600/big_alu.ll @@ -0,0 +1,1174 @@ +;RUN: llc < %s -march=r600 -mcpu=cedar +;REQUIRES: asserts + +;This test ensures that R600 backend can handle ifcvt properly +;and do not generate ALU clauses with more than 128 instructions. + +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg %reg9) #0 { +main_body: + %0 = extractelement <4 x float> %reg0, i32 0 + %1 = extractelement <4 x float> %reg0, i32 1 + %2 = extractelement <4 x float> %reg0, i32 2 + %3 = extractelement <4 x float> %reg0, i32 3 + %4 = extractelement <4 x float> %reg1, i32 0 + %5 = extractelement <4 x float> %reg9, i32 0 + %6 = extractelement <4 x float> %reg8, i32 0 + %7 = fcmp ugt float %6, 0.000000e+00 + %8 = select i1 %7, float %4, float %5 + %9 = extractelement <4 x float> %reg1, i32 1 + %10 = extractelement <4 x float> %reg9, i32 1 + %11 = extractelement <4 x float> %reg8, i32 0 + %12 = fcmp ugt float %11, 0.000000e+00 + %13 = select i1 %12, float %9, float %10 + %14 = extractelement <4 x float> %reg1, i32 2 + %15 = extractelement <4 x float> %reg9, i32 2 + %16 = extractelement <4 x float> %reg8, i32 0 + %17 = fcmp ugt float %16, 0.000000e+00 + %18 = select i1 %17, float %14, float %15 + %19 = extractelement <4 x float> %reg1, i32 3 + %20 = extractelement <4 x float> %reg9, i32 3 + %21 = extractelement <4 x float> %reg8, i32 0 + %22 = extractelement <4 x float> %reg2, i32 0 + %23 = extractelement <4 x float> %reg2, i32 1 + %24 = extractelement <4 x float> %reg2, i32 2 + %25 = extractelement <4 x float> %reg2, i32 3 + %26 = extractelement <4 x float> %reg3, i32 0 + %27 = extractelement <4 x float> %reg3, i32 1 + %28 = extractelement <4 x float> %reg3, i32 2 + %29 = extractelement <4 x float> %reg3, i32 3 + %30 = extractelement <4 x float> %reg4, i32 0 + %31 = extractelement <4 x float> %reg4, i32 1 + %32 = extractelement <4 x float> %reg4, i32 2 + %33 = extractelement <4 x float> %reg4, i32 3 + %34 = extractelement <4 x float> %reg5, i32 0 + %35 = extractelement <4 x float> %reg5, i32 1 + %36 = extractelement <4 x float> %reg5, i32 2 + %37 = extractelement <4 x float> %reg5, i32 3 + %38 = extractelement <4 x float> %reg6, i32 0 + %39 = extractelement <4 x float> %reg6, i32 1 + %40 = extractelement <4 x float> %reg6, i32 2 + %41 = extractelement <4 x float> %reg6, i32 3 + %42 = extractelement <4 x float> %reg7, i32 0 + %43 = extractelement <4 x float> %reg7, i32 1 + %44 = extractelement <4 x float> %reg7, i32 2 + %45 = extractelement <4 x float> %reg7, i32 3 + %46 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) + %47 = extractelement <4 x float> %46, i32 0 + %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) + %49 = extractelement <4 x float> %48, i32 1 + %50 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) + %51 = extractelement <4 x float> %50, i32 2 + %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) + %53 = extractelement <4 x float> %52, i32 0 + %54 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) + %55 = extractelement <4 x float> %54, i32 0 + %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) + %57 = extractelement <4 x float> %56, i32 1 + %58 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) + %59 = extractelement <4 x float> %58, i32 2 + %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) + %61 = extractelement <4 x float> %60, i32 3 + %62 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) + %63 = extractelement <4 x float> %62, i32 0 + %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) + %65 = extractelement <4 x float> %64, i32 1 + %66 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) + %67 = extractelement <4 x float> %66, i32 2 + %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %69 = extractelement <4 x float> %68, i32 0 + %70 = fcmp oge float %69, 3.500000e+00 + %71 = sext i1 %70 to i32 + %72 = bitcast i32 %71 to float + %73 = bitcast float %72 to i32 + %74 = icmp ne i32 %73, 0 + %. = select i1 %74, float 0.000000e+00, float 0.000000e+00 + %75 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %76 = extractelement <4 x float> %75, i32 0 + %77 = fcmp oge float %76, 2.000000e+00 + %78 = sext i1 %77 to i32 + %79 = bitcast i32 %78 to float + %80 = bitcast float %79 to i32 + %81 = icmp ne i32 %80, 0 + br i1 %81, label %IF137, label %ENDIF136 + +IF137: ; preds = %main_body + %82 = insertelement <4 x float> undef, float %30, i32 0 + %83 = insertelement <4 x float> %82, float %31, i32 1 + %84 = insertelement <4 x float> %83, float %32, i32 2 + %85 = insertelement <4 x float> %84, float 0.000000e+00, i32 3 + %86 = insertelement <4 x float> undef, float %30, i32 0 + %87 = insertelement <4 x float> %86, float %31, i32 1 + %88 = insertelement <4 x float> %87, float %32, i32 2 + %89 = insertelement <4 x float> %88, float 0.000000e+00, i32 3 + %90 = call float @llvm.AMDGPU.dp4(<4 x float> %85, <4 x float> %89) + %91 = call float @llvm.AMDGPU.rsq(float %90) + %92 = fmul float %30, %91 + %93 = fmul float %31, %91 + %94 = fmul float %32, %91 + %95 = insertelement <4 x float> undef, float %92, i32 0 + %96 = insertelement <4 x float> %95, float %93, i32 1 + %97 = insertelement <4 x float> %96, float %94, i32 2 + %98 = insertelement <4 x float> %97, float 0.000000e+00, i32 3 + %99 = insertelement <4 x float> undef, float %37, i32 0 + %100 = insertelement <4 x float> %99, float %38, i32 1 + %101 = insertelement <4 x float> %100, float %39, i32 2 + %102 = insertelement <4 x float> %101, float 0.000000e+00, i32 3 + %103 = call float @llvm.AMDGPU.dp4(<4 x float> %98, <4 x float> %102) + %104 = insertelement <4 x float> undef, float %92, i32 0 + %105 = insertelement <4 x float> %104, float %93, i32 1 + %106 = insertelement <4 x float> %105, float %94, i32 2 + %107 = insertelement <4 x float> %106, float 0.000000e+00, i32 3 + %108 = insertelement <4 x float> undef, float %40, i32 0 + %109 = insertelement <4 x float> %108, float %41, i32 1 + %110 = insertelement <4 x float> %109, float %42, i32 2 + %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 3 + %112 = call float @llvm.AMDGPU.dp4(<4 x float> %107, <4 x float> %111) + %113 = fsub float -0.000000e+00, %92 + %114 = fsub float -0.000000e+00, %93 + %115 = fsub float -0.000000e+00, %94 + %116 = insertelement <4 x float> undef, float %34, i32 0 + %117 = insertelement <4 x float> %116, float %35, i32 1 + %118 = insertelement <4 x float> %117, float %36, i32 2 + %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3 + %120 = insertelement <4 x float> undef, float %113, i32 0 + %121 = insertelement <4 x float> %120, float %114, i32 1 + %122 = insertelement <4 x float> %121, float %115, i32 2 + %123 = insertelement <4 x float> %122, float 0.000000e+00, i32 3 + %124 = call float @llvm.AMDGPU.dp4(<4 x float> %119, <4 x float> %123) + %125 = fdiv float 1.000000e+00, %124 + %126 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %127 = extractelement <4 x float> %126, i32 0 + %128 = fmul float %127, %125 + %129 = fmul float %103, %128 + %130 = fmul float %112, %128 + %131 = bitcast float %. to i32 + %132 = sitofp i32 %131 to float + %133 = fdiv float 1.000000e+00, %132 + %134 = bitcast float %. to i32 + %135 = add i32 %134, -1 + %136 = bitcast i32 %135 to float + %137 = bitcast float %136 to i32 + br label %LOOP + +ENDIF136: ; preds = %main_body, %ENDIF154 + %temp68.1 = phi float [ %600, %ENDIF154 ], [ 0.000000e+00, %main_body ] + %temp69.0 = phi float [ %602, %ENDIF154 ], [ 0.000000e+00, %main_body ] + %temp70.0 = phi float [ %604, %ENDIF154 ], [ 1.000000e+00, %main_body ] + %138 = fmul float %26, 0x3F847AE140000000 + %139 = fmul float %27, 0x3F847AE140000000 + %140 = fmul float %28, 0x3F847AE140000000 + %141 = insertelement <4 x float> undef, float %138, i32 0 + %142 = insertelement <4 x float> %141, float %139, i32 1 + %143 = insertelement <4 x float> %142, float %140, i32 2 + %144 = insertelement <4 x float> %143, float 0.000000e+00, i32 3 + %145 = extractelement <4 x float> %144, i32 0 + %146 = extractelement <4 x float> %144, i32 1 + %147 = extractelement <4 x float> %144, i32 2 + %148 = extractelement <4 x float> %144, i32 3 + %149 = insertelement <4 x float> undef, float %145, i32 0 + %150 = insertelement <4 x float> %149, float %146, i32 1 + %151 = insertelement <4 x float> %150, float %147, i32 2 + %152 = insertelement <4 x float> %151, float %148, i32 3 + %153 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %152, i32 16, i32 0, i32 3) + %154 = extractelement <4 x float> %153, i32 0 + %155 = extractelement <4 x float> %153, i32 1 + %156 = extractelement <4 x float> %153, i32 2 + %157 = extractelement <4 x float> %153, i32 3 + %158 = fmul float %26, 0x3F45A07B40000000 + %159 = fmul float %27, 0x3F45A07B40000000 + %160 = fmul float %28, 0x3F45A07B40000000 + %161 = insertelement <4 x float> undef, float %158, i32 0 + %162 = insertelement <4 x float> %161, float %159, i32 1 + %163 = insertelement <4 x float> %162, float %160, i32 2 + %164 = insertelement <4 x float> %163, float 0.000000e+00, i32 3 + %165 = extractelement <4 x float> %164, i32 0 + %166 = extractelement <4 x float> %164, i32 1 + %167 = extractelement <4 x float> %164, i32 2 + %168 = extractelement <4 x float> %164, i32 3 + %169 = insertelement <4 x float> undef, float %165, i32 0 + %170 = insertelement <4 x float> %169, float %166, i32 1 + %171 = insertelement <4 x float> %170, float %167, i32 2 + %172 = insertelement <4 x float> %171, float %168, i32 3 + %173 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %172, i32 16, i32 0, i32 3) + %174 = extractelement <4 x float> %173, i32 0 + %175 = extractelement <4 x float> %173, i32 1 + %176 = extractelement <4 x float> %173, i32 2 + %177 = extractelement <4 x float> %173, i32 3 + %178 = fmul float %176, 3.000000e+03 + %179 = fadd float %178, %28 + %180 = fdiv float 1.000000e+00, %33 + %181 = fmul float %32, %180 + %182 = call float @fabs(float %181) + %183 = fmul float %174, 0x3FD99999A0000000 + %184 = fadd float %183, 0x3FAEB851E0000000 + %185 = fmul float %175, 0x3FE3333340000000 + %186 = fadd float %185, %184 + %187 = fmul float %176, 2.000000e+00 + %188 = fadd float %187, %186 + %189 = fmul float %177, 4.000000e+00 + %190 = fadd float %189, %188 + %191 = fmul float %154, 0x3FB99999A0000000 + %192 = fadd float %191, %190 + %193 = fmul float %155, 0x3FD99999A0000000 + %194 = fadd float %193, %192 + %195 = fmul float %156, 0x3FE99999A0000000 + %196 = fadd float %195, %194 + %197 = fmul float %157, 0x4000CCCCC0000000 + %198 = fadd float %197, %196 + %199 = fmul float 0xBE5EFB4CC0000000, %182 + %200 = fmul float %199, %182 + %201 = call float @llvm.AMDIL.exp.(float %200) + %202 = call float @llvm.AMDGPU.lrp(float %201, float %198, float 0x3FA99999A0000000) + %203 = fadd float %202, 0x3FF4CCCCC0000000 + %204 = fmul float %203, 0x3FE1C71C80000000 + %205 = call float @llvm.AMDIL.clamp.(float %204, float 0.000000e+00, float 1.000000e+00) + %206 = fadd float %202, 0x3FF4CCCCC0000000 + %207 = fmul float %206, 0x3FE1C71C80000000 + %208 = call float @llvm.AMDIL.clamp.(float %207, float 0.000000e+00, float 1.000000e+00) + %209 = fadd float %202, 2.000000e+00 + %210 = fmul float %209, 0x3FD611A7A0000000 + %211 = call float @llvm.AMDIL.clamp.(float %210, float 0.000000e+00, float 1.000000e+00) + %212 = fmul float 2.000000e+00, %205 + %213 = fsub float -0.000000e+00, %212 + %214 = fadd float 3.000000e+00, %213 + %215 = fmul float %205, %214 + %216 = fmul float %205, %215 + %217 = fmul float 2.000000e+00, %208 + %218 = fsub float -0.000000e+00, %217 + %219 = fadd float 3.000000e+00, %218 + %220 = fmul float %208, %219 + %221 = fmul float %208, %220 + %222 = fmul float 2.000000e+00, %211 + %223 = fsub float -0.000000e+00, %222 + %224 = fadd float 3.000000e+00, %223 + %225 = fmul float %211, %224 + %226 = fmul float %211, %225 + %227 = fmul float %26, 0x3F368B5CC0000000 + %228 = fmul float %27, 0x3F368B5CC0000000 + %229 = insertelement <4 x float> undef, float %227, i32 0 + %230 = insertelement <4 x float> %229, float %228, i32 1 + %231 = insertelement <4 x float> %230, float 0.000000e+00, i32 2 + %232 = insertelement <4 x float> %231, float 0.000000e+00, i32 3 + %233 = extractelement <4 x float> %232, i32 0 + %234 = extractelement <4 x float> %232, i32 1 + %235 = insertelement <4 x float> undef, float %233, i32 0 + %236 = insertelement <4 x float> %235, float %234, i32 1 + %237 = insertelement <4 x float> %236, float undef, i32 2 + %238 = insertelement <4 x float> %237, float undef, i32 3 + %239 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %238, i32 17, i32 1, i32 2) + %240 = extractelement <4 x float> %239, i32 0 + %241 = insertelement <4 x float> undef, float %240, i32 0 + %242 = insertelement <4 x float> %241, float %228, i32 1 + %243 = insertelement <4 x float> %242, float 0.000000e+00, i32 2 + %244 = insertelement <4 x float> %243, float 0.000000e+00, i32 3 + %245 = extractelement <4 x float> %244, i32 0 + %246 = insertelement <4 x float> undef, float %245, i32 0 + %247 = insertelement <4 x float> %246, float undef, i32 1 + %248 = insertelement <4 x float> %247, float undef, i32 2 + %249 = insertelement <4 x float> %248, float undef, i32 3 + %250 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %249, i32 18, i32 2, i32 1) + %251 = extractelement <4 x float> %250, i32 0 + %252 = extractelement <4 x float> %250, i32 1 + %253 = extractelement <4 x float> %250, i32 2 + %254 = extractelement <4 x float> %250, i32 3 + %255 = fmul float %251, %216 + %256 = fmul float %252, %221 + %257 = fmul float %253, %226 + %258 = fmul float %254, 0.000000e+00 + %259 = fadd float %202, 0x3FF4CCCCC0000000 + %260 = fmul float %259, 0x3FE1C71C80000000 + %261 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00) + %262 = fadd float %202, 0x3FF4CCCCC0000000 + %263 = fmul float %262, 0x3FE1C71C80000000 + %264 = call float @llvm.AMDIL.clamp.(float %263, float 0.000000e+00, float 1.000000e+00) + %265 = fadd float %202, 2.000000e+00 + %266 = fmul float %265, 0x3FD611A7A0000000 + %267 = call float @llvm.AMDIL.clamp.(float %266, float 0.000000e+00, float 1.000000e+00) + %268 = fmul float 2.000000e+00, %261 + %269 = fsub float -0.000000e+00, %268 + %270 = fadd float 3.000000e+00, %269 + %271 = fmul float %261, %270 + %272 = fmul float %261, %271 + %273 = fmul float 2.000000e+00, %264 + %274 = fsub float -0.000000e+00, %273 + %275 = fadd float 3.000000e+00, %274 + %276 = fmul float %264, %275 + %277 = fmul float %264, %276 + %278 = fmul float 2.000000e+00, %267 + %279 = fsub float -0.000000e+00, %278 + %280 = fadd float 3.000000e+00, %279 + %281 = fmul float %267, %280 + %282 = fmul float %267, %281 + %283 = fmul float %26, 0x3F22DFD6A0000000 + %284 = fmul float %27, 0x3F22DFD6A0000000 + %285 = insertelement <4 x float> undef, float %283, i32 0 + %286 = insertelement <4 x float> %285, float %284, i32 1 + %287 = insertelement <4 x float> %286, float 0.000000e+00, i32 2 + %288 = insertelement <4 x float> %287, float 0.000000e+00, i32 3 + %289 = extractelement <4 x float> %288, i32 0 + %290 = extractelement <4 x float> %288, i32 1 + %291 = insertelement <4 x float> undef, float %289, i32 0 + %292 = insertelement <4 x float> %291, float %290, i32 1 + %293 = insertelement <4 x float> %292, float undef, i32 2 + %294 = insertelement <4 x float> %293, float undef, i32 3 + %295 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %294, i32 19, i32 3, i32 2) + %296 = extractelement <4 x float> %295, i32 0 + %297 = extractelement <4 x float> %295, i32 1 + %298 = extractelement <4 x float> %295, i32 2 + %299 = extractelement <4 x float> %295, i32 3 + %300 = fmul float %296, %272 + %301 = fmul float %297, %277 + %302 = fmul float %298, %282 + %303 = fmul float %299, 0.000000e+00 + %304 = fmul float %temp68.1, %37 + %305 = fmul float %temp68.1, %38 + %306 = fmul float %temp68.1, %39 + %307 = fmul float %temp69.0, %40 + %308 = fadd float %307, %304 + %309 = fmul float %temp69.0, %41 + %310 = fadd float %309, %305 + %311 = fmul float %temp69.0, %42 + %312 = fadd float %311, %306 + %313 = fmul float %temp70.0, %34 + %314 = fadd float %313, %308 + %315 = fmul float %temp70.0, %35 + %316 = fadd float %315, %310 + %317 = fmul float %temp70.0, %36 + %318 = fadd float %317, %312 + %319 = insertelement <4 x float> undef, float %314, i32 0 + %320 = insertelement <4 x float> %319, float %316, i32 1 + %321 = insertelement <4 x float> %320, float %318, i32 2 + %322 = insertelement <4 x float> %321, float 0.000000e+00, i32 3 + %323 = insertelement <4 x float> undef, float %314, i32 0 + %324 = insertelement <4 x float> %323, float %316, i32 1 + %325 = insertelement <4 x float> %324, float %318, i32 2 + %326 = insertelement <4 x float> %325, float 0.000000e+00, i32 3 + %327 = call float @llvm.AMDGPU.dp4(<4 x float> %322, <4 x float> %326) + %328 = call float @llvm.AMDGPU.rsq(float %327) + %329 = fmul float %314, %328 + %330 = fmul float %316, %328 + %331 = fmul float %318, %328 + %332 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) + %333 = extractelement <4 x float> %332, i32 0 + %334 = fsub float -0.000000e+00, %333 + %335 = fadd float 1.000000e+00, %334 + %336 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %337 = extractelement <4 x float> %336, i32 0 + %338 = fsub float -0.000000e+00, %337 + %339 = fadd float 1.000000e+00, %338 + %340 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) + %341 = extractelement <4 x float> %340, i32 0 + %342 = fsub float -0.000000e+00, %341 + %343 = fadd float 1.000000e+00, %342 + %344 = fsub float -0.000000e+00, %335 + %345 = fadd float %202, %344 + %346 = fsub float -0.000000e+00, %339 + %347 = fadd float %202, %346 + %348 = fadd float %347, 0xBFE3333340000000 + %349 = fsub float -0.000000e+00, %202 + %350 = fsub float -0.000000e+00, %343 + %351 = fadd float %349, %350 + %352 = insertelement <4 x float> undef, float %43, i32 0 + %353 = insertelement <4 x float> %352, float %44, i32 1 + %354 = insertelement <4 x float> %353, float %45, i32 2 + %355 = insertelement <4 x float> %354, float 0.000000e+00, i32 3 + %356 = insertelement <4 x float> undef, float %43, i32 0 + %357 = insertelement <4 x float> %356, float %44, i32 1 + %358 = insertelement <4 x float> %357, float %45, i32 2 + %359 = insertelement <4 x float> %358, float 0.000000e+00, i32 3 + %360 = call float @llvm.AMDGPU.dp4(<4 x float> %355, <4 x float> %359) + %361 = call float @llvm.AMDGPU.rsq(float %360) + %362 = fmul float %45, %361 + %363 = call float @fabs(float %362) + %364 = fmul float %176, 0x3FECCCCCC0000000 + %365 = fadd float %364, %363 + %366 = fadd float %365, 0xBFEFAE1480000000 + %367 = fmul float %366, 0xC023FFFFC0000000 + %368 = call float @llvm.AMDIL.clamp.(float %367, float 0.000000e+00, float 1.000000e+00) + %369 = fsub float -0.000000e+00, %335 + %370 = fadd float %202, %369 + %371 = fadd float %370, 0x3FBEB851E0000000 + %372 = fsub float -0.000000e+00, %339 + %373 = fadd float %202, %372 + %374 = fadd float %373, 0xBFE0A3D700000000 + %375 = fsub float -0.000000e+00, %202 + %376 = fsub float -0.000000e+00, %343 + %377 = fadd float %375, %376 + %378 = insertelement <4 x float> undef, float %43, i32 0 + %379 = insertelement <4 x float> %378, float %44, i32 1 + %380 = insertelement <4 x float> %379, float %45, i32 2 + %381 = insertelement <4 x float> %380, float 0.000000e+00, i32 3 + %382 = insertelement <4 x float> undef, float %43, i32 0 + %383 = insertelement <4 x float> %382, float %44, i32 1 + %384 = insertelement <4 x float> %383, float %45, i32 2 + %385 = insertelement <4 x float> %384, float 0.000000e+00, i32 3 + %386 = call float @llvm.AMDGPU.dp4(<4 x float> %381, <4 x float> %385) + %387 = call float @llvm.AMDGPU.rsq(float %386) + %388 = fmul float %45, %387 + %389 = call float @fabs(float %388) + %390 = fmul float %176, 0x3FF51EB860000000 + %391 = fadd float %390, %389 + %392 = fadd float %391, 0xBFEFAE1480000000 + %393 = fmul float %392, 0xC0490001A0000000 + %394 = call float @llvm.AMDIL.clamp.(float %393, float 0.000000e+00, float 1.000000e+00) + %395 = fmul float 2.000000e+00, %368 + %396 = fsub float -0.000000e+00, %395 + %397 = fadd float 3.000000e+00, %396 + %398 = fmul float %368, %397 + %399 = fmul float %368, %398 + %400 = call float @llvm.AMDGPU.lrp(float %399, float %255, float %345) + %401 = call float @llvm.AMDGPU.lrp(float %399, float %256, float %348) + %402 = call float @llvm.AMDGPU.lrp(float %399, float %257, float %351) + %403 = call float @llvm.AMDGPU.lrp(float %399, float %258, float 0.000000e+00) + %404 = fmul float 2.000000e+00, %394 + %405 = fsub float -0.000000e+00, %404 + %406 = fadd float 3.000000e+00, %405 + %407 = fmul float %394, %406 + %408 = fmul float %394, %407 + %409 = call float @llvm.AMDGPU.lrp(float %408, float %255, float %371) + %410 = call float @llvm.AMDGPU.lrp(float %408, float %256, float %374) + %411 = call float @llvm.AMDGPU.lrp(float %408, float %257, float %377) + %412 = call float @llvm.AMDGPU.lrp(float %408, float %258, float 0x3FD3333340000000) + %413 = fcmp oge float 2.200000e+03, %179 + %414 = sext i1 %413 to i32 + %415 = bitcast i32 %414 to float + %416 = bitcast float %415 to i32 + %417 = icmp ne i32 %416, 0 + br i1 %417, label %IF161, label %ENDIF160 + +LOOP: ; preds = %ENDIF139, %IF137 + %temp88.0 = phi float [ 0.000000e+00, %IF137 ], [ %446, %ENDIF139 ] + %temp92.0 = phi float [ 1.000000e+00, %IF137 ], [ %.temp92.0, %ENDIF139 ] + %temp96.0 = phi float [ 0.000000e+00, %IF137 ], [ %477, %ENDIF139 ] + %418 = bitcast float %temp96.0 to i32 + %419 = icmp sge i32 %418, %137 + %420 = sext i1 %419 to i32 + %421 = bitcast i32 %420 to float + %422 = bitcast float %421 to i32 + %423 = icmp ne i32 %422, 0 + br i1 %423, label %IF140, label %ENDIF139 + +IF140: ; preds = %LOOP + %424 = fmul float %133, 5.000000e-01 + %425 = fmul float %129, %temp92.0 + %426 = fadd float %425, %22 + %427 = fmul float %130, %temp92.0 + %428 = fadd float %427, %23 + %429 = insertelement <4 x float> undef, float %426, i32 0 + %430 = insertelement <4 x float> %429, float %428, i32 1 + %431 = insertelement <4 x float> %430, float 0.000000e+00, i32 2 + %432 = insertelement <4 x float> %431, float 0.000000e+00, i32 3 + %433 = extractelement <4 x float> %432, i32 0 + %434 = extractelement <4 x float> %432, i32 1 + %435 = insertelement <4 x float> undef, float %433, i32 0 + %436 = insertelement <4 x float> %435, float %434, i32 1 + %437 = insertelement <4 x float> %436, float undef, i32 2 + %438 = insertelement <4 x float> %437, float undef, i32 3 + %439 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %438, i32 20, i32 4, i32 2) + %440 = extractelement <4 x float> %439, i32 3 + %441 = fcmp oge float %temp92.0, %440 + %442 = sext i1 %441 to i32 + %443 = bitcast i32 %442 to float + %444 = bitcast float %443 to i32 + %445 = icmp ne i32 %444, 0 + br i1 %445, label %IF146, label %ENDIF145 + +ENDIF139: ; preds = %LOOP + %446 = fadd float %temp88.0, %133 + %447 = fmul float %129, %446 + %448 = fadd float %447, %22 + %449 = fmul float %130, %446 + %450 = fadd float %449, %23 + %451 = insertelement <4 x float> undef, float %448, i32 0 + %452 = insertelement <4 x float> %451, float %450, i32 1 + %453 = insertelement <4 x float> %452, float 0.000000e+00, i32 2 + %454 = insertelement <4 x float> %453, float 0.000000e+00, i32 3 + %455 = extractelement <4 x float> %454, i32 0 + %456 = extractelement <4 x float> %454, i32 1 + %457 = insertelement <4 x float> undef, float %455, i32 0 + %458 = insertelement <4 x float> %457, float %456, i32 1 + %459 = insertelement <4 x float> %458, float undef, i32 2 + %460 = insertelement <4 x float> %459, float undef, i32 3 + %461 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %460, i32 20, i32 4, i32 2) + %462 = extractelement <4 x float> %461, i32 3 + %463 = fcmp olt float 0x3FEFDF3B60000000, %temp92.0 + %464 = sext i1 %463 to i32 + %465 = bitcast i32 %464 to float + %466 = fcmp oge float %446, %462 + %467 = sext i1 %466 to i32 + %468 = bitcast i32 %467 to float + %469 = bitcast float %465 to i32 + %470 = bitcast float %468 to i32 + %471 = and i32 %469, %470 + %472 = bitcast i32 %471 to float + %473 = bitcast float %472 to i32 + %474 = icmp ne i32 %473, 0 + %.temp92.0 = select i1 %474, float %446, float %temp92.0 + %475 = bitcast float %temp96.0 to i32 + %476 = add i32 %475, 1 + %477 = bitcast i32 %476 to float + br label %LOOP + +IF146: ; preds = %IF140 + %478 = fmul float 2.000000e+00, %424 + %479 = fsub float -0.000000e+00, %478 + %480 = fadd float %temp92.0, %479 + br label %ENDIF145 + +ENDIF145: ; preds = %IF140, %IF146 + %temp88.1 = phi float [ %480, %IF146 ], [ %temp92.0, %IF140 ] + %481 = fadd float %temp88.1, %424 + %482 = fmul float %424, 5.000000e-01 + %483 = fmul float %129, %481 + %484 = fadd float %483, %22 + %485 = fmul float %130, %481 + %486 = fadd float %485, %23 + %487 = insertelement <4 x float> undef, float %484, i32 0 + %488 = insertelement <4 x float> %487, float %486, i32 1 + %489 = insertelement <4 x float> %488, float 0.000000e+00, i32 2 + %490 = insertelement <4 x float> %489, float %440, i32 3 + %491 = extractelement <4 x float> %490, i32 0 + %492 = extractelement <4 x float> %490, i32 1 + %493 = insertelement <4 x float> undef, float %491, i32 0 + %494 = insertelement <4 x float> %493, float %492, i32 1 + %495 = insertelement <4 x float> %494, float undef, i32 2 + %496 = insertelement <4 x float> %495, float undef, i32 3 + %497 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %496, i32 20, i32 4, i32 2) + %498 = extractelement <4 x float> %497, i32 3 + %499 = fcmp oge float %481, %498 + %500 = sext i1 %499 to i32 + %501 = bitcast i32 %500 to float + %502 = bitcast float %501 to i32 + %503 = icmp ne i32 %502, 0 + br i1 %503, label %IF149, label %ENDIF148 + +IF149: ; preds = %ENDIF145 + %504 = fmul float 2.000000e+00, %482 + %505 = fsub float -0.000000e+00, %504 + %506 = fadd float %481, %505 + br label %ENDIF148 + +ENDIF148: ; preds = %ENDIF145, %IF149 + %temp88.2 = phi float [ %506, %IF149 ], [ %481, %ENDIF145 ] + %temp92.2 = phi float [ %481, %IF149 ], [ %temp92.0, %ENDIF145 ] + %507 = fadd float %temp88.2, %482 + %508 = fmul float %482, 5.000000e-01 + %509 = fmul float %129, %507 + %510 = fadd float %509, %22 + %511 = fmul float %130, %507 + %512 = fadd float %511, %23 + %513 = insertelement <4 x float> undef, float %510, i32 0 + %514 = insertelement <4 x float> %513, float %512, i32 1 + %515 = insertelement <4 x float> %514, float 0.000000e+00, i32 2 + %516 = insertelement <4 x float> %515, float %498, i32 3 + %517 = extractelement <4 x float> %516, i32 0 + %518 = extractelement <4 x float> %516, i32 1 + %519 = insertelement <4 x float> undef, float %517, i32 0 + %520 = insertelement <4 x float> %519, float %518, i32 1 + %521 = insertelement <4 x float> %520, float undef, i32 2 + %522 = insertelement <4 x float> %521, float undef, i32 3 + %523 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %522, i32 20, i32 4, i32 2) + %524 = extractelement <4 x float> %523, i32 3 + %525 = fcmp oge float %507, %524 + %526 = sext i1 %525 to i32 + %527 = bitcast i32 %526 to float + %528 = bitcast float %527 to i32 + %529 = icmp ne i32 %528, 0 + br i1 %529, label %IF152, label %ENDIF151 + +IF152: ; preds = %ENDIF148 + %530 = fmul float 2.000000e+00, %508 + %531 = fsub float -0.000000e+00, %530 + %532 = fadd float %507, %531 + br label %ENDIF151 + +ENDIF151: ; preds = %ENDIF148, %IF152 + %temp88.3 = phi float [ %532, %IF152 ], [ %507, %ENDIF148 ] + %temp92.3 = phi float [ %507, %IF152 ], [ %temp92.2, %ENDIF148 ] + %533 = fadd float %temp88.3, %508 + %534 = fmul float %508, 5.000000e-01 + %535 = fmul float %129, %533 + %536 = fadd float %535, %22 + %537 = fmul float %130, %533 + %538 = fadd float %537, %23 + %539 = insertelement <4 x float> undef, float %536, i32 0 + %540 = insertelement <4 x float> %539, float %538, i32 1 + %541 = insertelement <4 x float> %540, float 0.000000e+00, i32 2 + %542 = insertelement <4 x float> %541, float %524, i32 3 + %543 = extractelement <4 x float> %542, i32 0 + %544 = extractelement <4 x float> %542, i32 1 + %545 = insertelement <4 x float> undef, float %543, i32 0 + %546 = insertelement <4 x float> %545, float %544, i32 1 + %547 = insertelement <4 x float> %546, float undef, i32 2 + %548 = insertelement <4 x float> %547, float undef, i32 3 + %549 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %548, i32 20, i32 4, i32 2) + %550 = extractelement <4 x float> %549, i32 3 + %551 = fcmp oge float %533, %550 + %552 = sext i1 %551 to i32 + %553 = bitcast i32 %552 to float + %554 = bitcast float %553 to i32 + %555 = icmp ne i32 %554, 0 + br i1 %555, label %IF155, label %ENDIF154 + +IF155: ; preds = %ENDIF151 + %556 = fmul float 2.000000e+00, %534 + %557 = fsub float -0.000000e+00, %556 + %558 = fadd float %533, %557 + br label %ENDIF154 + +ENDIF154: ; preds = %ENDIF151, %IF155 + %temp88.4 = phi float [ %558, %IF155 ], [ %533, %ENDIF151 ] + %temp92.4 = phi float [ %533, %IF155 ], [ %temp92.3, %ENDIF151 ] + %559 = fadd float %temp88.4, %534 + %560 = fmul float %129, %559 + %561 = fadd float %560, %22 + %562 = fmul float %130, %559 + %563 = fadd float %562, %23 + %564 = insertelement <4 x float> undef, float %561, i32 0 + %565 = insertelement <4 x float> %564, float %563, i32 1 + %566 = insertelement <4 x float> %565, float 0.000000e+00, i32 2 + %567 = insertelement <4 x float> %566, float %550, i32 3 + %568 = extractelement <4 x float> %567, i32 0 + %569 = extractelement <4 x float> %567, i32 1 + %570 = insertelement <4 x float> undef, float %568, i32 0 + %571 = insertelement <4 x float> %570, float %569, i32 1 + %572 = insertelement <4 x float> %571, float undef, i32 2 + %573 = insertelement <4 x float> %572, float undef, i32 3 + %574 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %573, i32 20, i32 4, i32 2) + %575 = extractelement <4 x float> %574, i32 3 + %576 = fcmp oge float %559, %575 + %577 = sext i1 %576 to i32 + %578 = bitcast i32 %577 to float + %579 = bitcast float %578 to i32 + %580 = icmp ne i32 %579, 0 + %.temp92.4 = select i1 %580, float %559, float %temp92.4 + %581 = fmul float %129, %.temp92.4 + %582 = fadd float %581, %22 + %583 = fmul float %130, %.temp92.4 + %584 = fadd float %583, %23 + %585 = insertelement <4 x float> undef, float %582, i32 0 + %586 = insertelement <4 x float> %585, float %584, i32 1 + %587 = insertelement <4 x float> %586, float 0.000000e+00, i32 2 + %588 = insertelement <4 x float> %587, float %575, i32 3 + %589 = extractelement <4 x float> %588, i32 0 + %590 = extractelement <4 x float> %588, i32 1 + %591 = insertelement <4 x float> undef, float %589, i32 0 + %592 = insertelement <4 x float> %591, float %590, i32 1 + %593 = insertelement <4 x float> %592, float undef, i32 2 + %594 = insertelement <4 x float> %593, float undef, i32 3 + %595 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %594, i32 20, i32 4, i32 2) + %596 = extractelement <4 x float> %595, i32 0 + %597 = extractelement <4 x float> %595, i32 1 + %598 = extractelement <4 x float> %595, i32 2 + %599 = fmul float %596, 2.000000e+00 + %600 = fadd float %599, -1.000000e+00 + %601 = fmul float %597, 2.000000e+00 + %602 = fadd float %601, -1.000000e+00 + %603 = fmul float %598, 2.000000e+00 + %604 = fadd float %603, -1.000000e+00 + br label %ENDIF136 + +IF161: ; preds = %ENDIF136 + %605 = fmul float %202, 0x3FB99999A0000000 + %606 = fcmp uge float 0x3FE4CCCCC0000000, %605 + %607 = select i1 %606, float 0x3FE4CCCCC0000000, float %605 + %608 = fcmp uge float %607, 5.000000e-01 + %609 = select i1 %608, float 5.000000e-01, float %607 + %610 = call float @llvm.AMDGPU.lrp(float %609, float %400, float %300) + %611 = call float @llvm.AMDGPU.lrp(float %609, float %401, float %301) + %612 = call float @llvm.AMDGPU.lrp(float %609, float %402, float %302) + %613 = call float @llvm.AMDGPU.lrp(float %609, float %403, float %303) + %614 = insertelement <4 x float> undef, float %329, i32 0 + %615 = insertelement <4 x float> %614, float %330, i32 1 + %616 = insertelement <4 x float> %615, float %331, i32 2 + %617 = insertelement <4 x float> %616, float 0.000000e+00, i32 3 + %618 = insertelement <4 x float> undef, float %63, i32 0 + %619 = insertelement <4 x float> %618, float %65, i32 1 + %620 = insertelement <4 x float> %619, float %67, i32 2 + %621 = insertelement <4 x float> %620, float 0.000000e+00, i32 3 + %622 = call float @llvm.AMDGPU.dp4(<4 x float> %617, <4 x float> %621) + %623 = fcmp uge float 0x3FE6666660000000, %622 + %624 = select i1 %623, float 0x3FE6666660000000, float %622 + %625 = fmul float %8, %624 + %626 = fmul float %13, %624 + %627 = fmul float %18, %624 + %628 = insertelement <4 x float> undef, float %34, i32 0 + %629 = insertelement <4 x float> %628, float %35, i32 1 + %630 = insertelement <4 x float> %629, float %36, i32 2 + %631 = insertelement <4 x float> %630, float 0.000000e+00, i32 3 + %632 = insertelement <4 x float> undef, float %63, i32 0 + %633 = insertelement <4 x float> %632, float %65, i32 1 + %634 = insertelement <4 x float> %633, float %67, i32 2 + %635 = insertelement <4 x float> %634, float 0.000000e+00, i32 3 + %636 = call float @llvm.AMDGPU.dp4(<4 x float> %631, <4 x float> %635) + %637 = fcmp uge float 0x3FECCCCCC0000000, %636 + %638 = select i1 %637, float 0x3FECCCCCC0000000, float %636 + %639 = fmul float %625, %638 + %640 = fmul float %626, %638 + %641 = fmul float %627, %638 + br label %ENDIF160 + +ENDIF160: ; preds = %ENDIF136, %IF161 + %temp84.0 = phi float [ %610, %IF161 ], [ %255, %ENDIF136 ] + %temp85.0 = phi float [ %611, %IF161 ], [ %256, %ENDIF136 ] + %temp86.0 = phi float [ %612, %IF161 ], [ %257, %ENDIF136 ] + %temp87.0 = phi float [ %613, %IF161 ], [ %258, %ENDIF136 ] + %temp92.6 = phi float [ %639, %IF161 ], [ %415, %ENDIF136 ] + %temp93.0 = phi float [ %640, %IF161 ], [ 0.000000e+00, %ENDIF136 ] + %temp94.0 = phi float [ %641, %IF161 ], [ 0.000000e+00, %ENDIF136 ] + %642 = fcmp olt float 2.200000e+03, %179 + %643 = sext i1 %642 to i32 + %644 = bitcast i32 %643 to float + %645 = fcmp olt float %179, 2.300000e+03 + %646 = sext i1 %645 to i32 + %647 = bitcast i32 %646 to float + %648 = bitcast float %644 to i32 + %649 = bitcast float %647 to i32 + %650 = and i32 %648, %649 + %651 = bitcast i32 %650 to float + %652 = bitcast float %651 to i32 + %653 = icmp ne i32 %652, 0 + br i1 %653, label %IF164, label %ENDIF163 + +IF164: ; preds = %ENDIF160 + %654 = fmul float %202, 5.000000e-01 + %655 = fcmp uge float 0x3FE4CCCCC0000000, %654 + %656 = select i1 %655, float 0x3FE4CCCCC0000000, float %654 + %657 = fcmp uge float %656, 0x3FD6666660000000 + %658 = select i1 %657, float 0x3FD6666660000000, float %656 + %659 = call float @llvm.AMDGPU.lrp(float %658, float %400, float %300) + %660 = call float @llvm.AMDGPU.lrp(float %658, float %401, float %301) + %661 = call float @llvm.AMDGPU.lrp(float %658, float %402, float %302) + %662 = call float @llvm.AMDGPU.lrp(float %658, float %403, float %303) + %663 = insertelement <4 x float> undef, float %329, i32 0 + %664 = insertelement <4 x float> %663, float %330, i32 1 + %665 = insertelement <4 x float> %664, float %331, i32 2 + %666 = insertelement <4 x float> %665, float 0.000000e+00, i32 3 + %667 = insertelement <4 x float> undef, float %63, i32 0 + %668 = insertelement <4 x float> %667, float %65, i32 1 + %669 = insertelement <4 x float> %668, float %67, i32 2 + %670 = insertelement <4 x float> %669, float 0.000000e+00, i32 3 + %671 = call float @llvm.AMDGPU.dp4(<4 x float> %666, <4 x float> %670) + %672 = fcmp uge float 0x3FE6666660000000, %671 + %673 = select i1 %672, float 0x3FE6666660000000, float %671 + %674 = fmul float %8, %673 + %675 = fmul float %13, %673 + %676 = fmul float %18, %673 + %677 = insertelement <4 x float> undef, float %34, i32 0 + %678 = insertelement <4 x float> %677, float %35, i32 1 + %679 = insertelement <4 x float> %678, float %36, i32 2 + %680 = insertelement <4 x float> %679, float 0.000000e+00, i32 3 + %681 = insertelement <4 x float> undef, float %63, i32 0 + %682 = insertelement <4 x float> %681, float %65, i32 1 + %683 = insertelement <4 x float> %682, float %67, i32 2 + %684 = insertelement <4 x float> %683, float 0.000000e+00, i32 3 + %685 = call float @llvm.AMDGPU.dp4(<4 x float> %680, <4 x float> %684) + %686 = fcmp uge float 0x3FECCCCCC0000000, %685 + %687 = select i1 %686, float 0x3FECCCCCC0000000, float %685 + %688 = fmul float %674, %687 + %689 = fmul float %675, %687 + %690 = fmul float %676, %687 + br label %ENDIF163 + +ENDIF163: ; preds = %ENDIF160, %IF164 + %temp84.1 = phi float [ %659, %IF164 ], [ %temp84.0, %ENDIF160 ] + %temp85.1 = phi float [ %660, %IF164 ], [ %temp85.0, %ENDIF160 ] + %temp86.1 = phi float [ %661, %IF164 ], [ %temp86.0, %ENDIF160 ] + %temp87.1 = phi float [ %662, %IF164 ], [ %temp87.0, %ENDIF160 ] + %temp92.7 = phi float [ %688, %IF164 ], [ %temp92.6, %ENDIF160 ] + %temp93.1 = phi float [ %689, %IF164 ], [ %temp93.0, %ENDIF160 ] + %temp94.1 = phi float [ %690, %IF164 ], [ %temp94.0, %ENDIF160 ] + %691 = fcmp oge float %179, 2.300000e+03 + %692 = sext i1 %691 to i32 + %693 = bitcast i32 %692 to float + %694 = fcmp olt float %179, 2.480000e+03 + %695 = sext i1 %694 to i32 + %696 = bitcast i32 %695 to float + %697 = bitcast float %693 to i32 + %698 = bitcast float %696 to i32 + %699 = and i32 %697, %698 + %700 = bitcast i32 %699 to float + %701 = bitcast float %700 to i32 + %702 = icmp ne i32 %701, 0 + br i1 %702, label %IF167, label %ENDIF166 + +IF167: ; preds = %ENDIF163 + %703 = fmul float %202, 5.000000e-01 + %704 = fcmp uge float 0x3FE4CCCCC0000000, %703 + %705 = select i1 %704, float 0x3FE4CCCCC0000000, float %703 + %706 = fcmp uge float %705, 0x3FD3333340000000 + %707 = select i1 %706, float 0x3FD3333340000000, float %705 + %708 = call float @llvm.AMDGPU.lrp(float %707, float %409, float %300) + %709 = call float @llvm.AMDGPU.lrp(float %707, float %410, float %301) + %710 = call float @llvm.AMDGPU.lrp(float %707, float %411, float %302) + %711 = call float @llvm.AMDGPU.lrp(float %707, float %412, float %303) + %712 = insertelement <4 x float> undef, float %329, i32 0 + %713 = insertelement <4 x float> %712, float %330, i32 1 + %714 = insertelement <4 x float> %713, float %331, i32 2 + %715 = insertelement <4 x float> %714, float 0.000000e+00, i32 3 + %716 = insertelement <4 x float> undef, float %63, i32 0 + %717 = insertelement <4 x float> %716, float %65, i32 1 + %718 = insertelement <4 x float> %717, float %67, i32 2 + %719 = insertelement <4 x float> %718, float 0.000000e+00, i32 3 + %720 = call float @llvm.AMDGPU.dp4(<4 x float> %715, <4 x float> %719) + %721 = fcmp uge float 0x3FEB333340000000, %720 + %722 = select i1 %721, float 0x3FEB333340000000, float %720 + %723 = fmul float %8, %722 + %724 = fmul float %13, %722 + %725 = fmul float %18, %722 + %726 = insertelement <4 x float> undef, float %34, i32 0 + %727 = insertelement <4 x float> %726, float %35, i32 1 + %728 = insertelement <4 x float> %727, float %36, i32 2 + %729 = insertelement <4 x float> %728, float 0.000000e+00, i32 3 + %730 = insertelement <4 x float> undef, float %63, i32 0 + %731 = insertelement <4 x float> %730, float %65, i32 1 + %732 = insertelement <4 x float> %731, float %67, i32 2 + %733 = insertelement <4 x float> %732, float 0.000000e+00, i32 3 + %734 = call float @llvm.AMDGPU.dp4(<4 x float> %729, <4 x float> %733) + %735 = fcmp uge float 0x3FECCCCCC0000000, %734 + %736 = select i1 %735, float 0x3FECCCCCC0000000, float %734 + %737 = fmul float %723, %736 + %738 = fmul float %724, %736 + %739 = fmul float %725, %736 + br label %ENDIF166 + +ENDIF166: ; preds = %ENDIF163, %IF167 + %temp84.2 = phi float [ %708, %IF167 ], [ %temp84.1, %ENDIF163 ] + %temp85.2 = phi float [ %709, %IF167 ], [ %temp85.1, %ENDIF163 ] + %temp86.2 = phi float [ %710, %IF167 ], [ %temp86.1, %ENDIF163 ] + %temp87.2 = phi float [ %711, %IF167 ], [ %temp87.1, %ENDIF163 ] + %temp92.8 = phi float [ %737, %IF167 ], [ %temp92.7, %ENDIF163 ] + %temp93.2 = phi float [ %738, %IF167 ], [ %temp93.1, %ENDIF163 ] + %temp94.2 = phi float [ %739, %IF167 ], [ %temp94.1, %ENDIF163 ] + %740 = fcmp oge float %179, 2.480000e+03 + %741 = sext i1 %740 to i32 + %742 = bitcast i32 %741 to float + %743 = fcmp olt float %179, 2.530000e+03 + %744 = sext i1 %743 to i32 + %745 = bitcast i32 %744 to float + %746 = bitcast float %742 to i32 + %747 = bitcast float %745 to i32 + %748 = and i32 %746, %747 + %749 = bitcast i32 %748 to float + %750 = bitcast float %749 to i32 + %751 = icmp ne i32 %750, 0 + br i1 %751, label %IF170, label %ENDIF169 + +IF170: ; preds = %ENDIF166 + %752 = fmul float %202, 5.000000e-01 + %753 = fcmp uge float 0x3FE4CCCCC0000000, %752 + %754 = select i1 %753, float 0x3FE4CCCCC0000000, float %752 + %755 = fcmp uge float %754, 0x3FC99999A0000000 + %756 = select i1 %755, float 0x3FC99999A0000000, float %754 + %757 = call float @llvm.AMDGPU.lrp(float %756, float %409, float %300) + %758 = call float @llvm.AMDGPU.lrp(float %756, float %410, float %301) + %759 = call float @llvm.AMDGPU.lrp(float %756, float %411, float %302) + %760 = call float @llvm.AMDGPU.lrp(float %756, float %412, float %303) + %761 = insertelement <4 x float> undef, float %329, i32 0 + %762 = insertelement <4 x float> %761, float %330, i32 1 + %763 = insertelement <4 x float> %762, float %331, i32 2 + %764 = insertelement <4 x float> %763, float 0.000000e+00, i32 3 + %765 = insertelement <4 x float> undef, float %63, i32 0 + %766 = insertelement <4 x float> %765, float %65, i32 1 + %767 = insertelement <4 x float> %766, float %67, i32 2 + %768 = insertelement <4 x float> %767, float 0.000000e+00, i32 3 + %769 = call float @llvm.AMDGPU.dp4(<4 x float> %764, <4 x float> %768) + %770 = fcmp uge float 0x3FEB333340000000, %769 + %771 = select i1 %770, float 0x3FEB333340000000, float %769 + %772 = fmul float %8, %771 + %773 = fmul float %13, %771 + %774 = fmul float %18, %771 + %775 = insertelement <4 x float> undef, float %34, i32 0 + %776 = insertelement <4 x float> %775, float %35, i32 1 + %777 = insertelement <4 x float> %776, float %36, i32 2 + %778 = insertelement <4 x float> %777, float 0.000000e+00, i32 3 + %779 = insertelement <4 x float> undef, float %63, i32 0 + %780 = insertelement <4 x float> %779, float %65, i32 1 + %781 = insertelement <4 x float> %780, float %67, i32 2 + %782 = insertelement <4 x float> %781, float 0.000000e+00, i32 3 + %783 = call float @llvm.AMDGPU.dp4(<4 x float> %778, <4 x float> %782) + %784 = fcmp uge float 0x3FECCCCCC0000000, %783 + %785 = select i1 %784, float 0x3FECCCCCC0000000, float %783 + %786 = fmul float %772, %785 + %787 = fmul float %773, %785 + %788 = fmul float %774, %785 + br label %ENDIF169 + +ENDIF169: ; preds = %ENDIF166, %IF170 + %temp84.3 = phi float [ %757, %IF170 ], [ %temp84.2, %ENDIF166 ] + %temp85.3 = phi float [ %758, %IF170 ], [ %temp85.2, %ENDIF166 ] + %temp86.3 = phi float [ %759, %IF170 ], [ %temp86.2, %ENDIF166 ] + %temp87.3 = phi float [ %760, %IF170 ], [ %temp87.2, %ENDIF166 ] + %temp92.9 = phi float [ %786, %IF170 ], [ %temp92.8, %ENDIF166 ] + %temp93.3 = phi float [ %787, %IF170 ], [ %temp93.2, %ENDIF166 ] + %temp94.3 = phi float [ %788, %IF170 ], [ %temp94.2, %ENDIF166 ] + %789 = fcmp oge float %179, 2.530000e+03 + %790 = sext i1 %789 to i32 + %791 = bitcast i32 %790 to float + %792 = fcmp olt float %179, 2.670000e+03 + %793 = sext i1 %792 to i32 + %794 = bitcast i32 %793 to float + %795 = bitcast float %791 to i32 + %796 = bitcast float %794 to i32 + %797 = and i32 %795, %796 + %798 = bitcast i32 %797 to float + %799 = bitcast float %798 to i32 + %800 = icmp ne i32 %799, 0 + br i1 %800, label %IF173, label %ENDIF172 + +IF173: ; preds = %ENDIF169 + %801 = fmul float %202, 5.000000e-01 + %802 = fcmp uge float 0x3FE4CCCCC0000000, %801 + %803 = select i1 %802, float 0x3FE4CCCCC0000000, float %801 + %804 = fcmp uge float %803, 0x3FB99999A0000000 + %805 = select i1 %804, float 0x3FB99999A0000000, float %803 + %806 = call float @llvm.AMDGPU.lrp(float %805, float %400, float %300) + %807 = call float @llvm.AMDGPU.lrp(float %805, float %401, float %301) + %808 = call float @llvm.AMDGPU.lrp(float %805, float %402, float %302) + %809 = call float @llvm.AMDGPU.lrp(float %805, float %403, float %303) + %810 = insertelement <4 x float> undef, float %329, i32 0 + %811 = insertelement <4 x float> %810, float %330, i32 1 + %812 = insertelement <4 x float> %811, float %331, i32 2 + %813 = insertelement <4 x float> %812, float 0.000000e+00, i32 3 + %814 = insertelement <4 x float> undef, float %63, i32 0 + %815 = insertelement <4 x float> %814, float %65, i32 1 + %816 = insertelement <4 x float> %815, float %67, i32 2 + %817 = insertelement <4 x float> %816, float 0.000000e+00, i32 3 + %818 = call float @llvm.AMDGPU.dp4(<4 x float> %813, <4 x float> %817) + %819 = fcmp uge float 0x3FEB333340000000, %818 + %820 = select i1 %819, float 0x3FEB333340000000, float %818 + %821 = fmul float %8, %820 + %822 = fmul float %13, %820 + %823 = fmul float %18, %820 + %824 = insertelement <4 x float> undef, float %34, i32 0 + %825 = insertelement <4 x float> %824, float %35, i32 1 + %826 = insertelement <4 x float> %825, float %36, i32 2 + %827 = insertelement <4 x float> %826, float 0.000000e+00, i32 3 + %828 = insertelement <4 x float> undef, float %63, i32 0 + %829 = insertelement <4 x float> %828, float %65, i32 1 + %830 = insertelement <4 x float> %829, float %67, i32 2 + %831 = insertelement <4 x float> %830, float 0.000000e+00, i32 3 + %832 = call float @llvm.AMDGPU.dp4(<4 x float> %827, <4 x float> %831) + %833 = fcmp uge float 0x3FECCCCCC0000000, %832 + %834 = select i1 %833, float 0x3FECCCCCC0000000, float %832 + %835 = fmul float %821, %834 + %836 = fmul float %822, %834 + %837 = fmul float %823, %834 + br label %ENDIF172 + +ENDIF172: ; preds = %ENDIF169, %IF173 + %temp84.4 = phi float [ %806, %IF173 ], [ %temp84.3, %ENDIF169 ] + %temp85.4 = phi float [ %807, %IF173 ], [ %temp85.3, %ENDIF169 ] + %temp86.4 = phi float [ %808, %IF173 ], [ %temp86.3, %ENDIF169 ] + %temp87.4 = phi float [ %809, %IF173 ], [ %temp87.3, %ENDIF169 ] + %temp92.10 = phi float [ %835, %IF173 ], [ %temp92.9, %ENDIF169 ] + %temp93.4 = phi float [ %836, %IF173 ], [ %temp93.3, %ENDIF169 ] + %temp94.4 = phi float [ %837, %IF173 ], [ %temp94.3, %ENDIF169 ] + %838 = fcmp oge float %179, 2.670000e+03 + %839 = sext i1 %838 to i32 + %840 = bitcast i32 %839 to float + %841 = bitcast float %840 to i32 + %842 = icmp ne i32 %841, 0 + br i1 %842, label %IF176, label %ENDIF175 + +IF176: ; preds = %ENDIF172 + %843 = fmul float %202, 0x3FB99999A0000000 + %844 = fcmp uge float 0.000000e+00, %843 + %845 = select i1 %844, float 0.000000e+00, float %843 + %846 = fcmp uge float %845, 0x3FD99999A0000000 + %847 = select i1 %846, float 0x3FD99999A0000000, float %845 + %848 = call float @llvm.AMDGPU.lrp(float %847, float %400, float %300) + %849 = call float @llvm.AMDGPU.lrp(float %847, float %401, float %301) + %850 = call float @llvm.AMDGPU.lrp(float %847, float %402, float %302) + %851 = call float @llvm.AMDGPU.lrp(float %847, float %403, float %303) + %852 = insertelement <4 x float> undef, float %329, i32 0 + %853 = insertelement <4 x float> %852, float %330, i32 1 + %854 = insertelement <4 x float> %853, float %331, i32 2 + %855 = insertelement <4 x float> %854, float 0.000000e+00, i32 3 + %856 = insertelement <4 x float> undef, float %63, i32 0 + %857 = insertelement <4 x float> %856, float %65, i32 1 + %858 = insertelement <4 x float> %857, float %67, i32 2 + %859 = insertelement <4 x float> %858, float 0.000000e+00, i32 3 + %860 = call float @llvm.AMDGPU.dp4(<4 x float> %855, <4 x float> %859) + %861 = fcmp uge float 0x3FEB333340000000, %860 + %862 = select i1 %861, float 0x3FEB333340000000, float %860 + %863 = fmul float %8, %862 + %864 = fmul float %13, %862 + %865 = fmul float %18, %862 + %866 = insertelement <4 x float> undef, float %34, i32 0 + %867 = insertelement <4 x float> %866, float %35, i32 1 + %868 = insertelement <4 x float> %867, float %36, i32 2 + %869 = insertelement <4 x float> %868, float 0.000000e+00, i32 3 + %870 = insertelement <4 x float> undef, float %63, i32 0 + %871 = insertelement <4 x float> %870, float %65, i32 1 + %872 = insertelement <4 x float> %871, float %67, i32 2 + %873 = insertelement <4 x float> %872, float 0.000000e+00, i32 3 + %874 = call float @llvm.AMDGPU.dp4(<4 x float> %869, <4 x float> %873) + %875 = fcmp uge float 0x3FECCCCCC0000000, %874 + %876 = select i1 %875, float 0x3FECCCCCC0000000, float %874 + %877 = fmul float %863, %876 + %878 = fmul float %864, %876 + %879 = fmul float %865, %876 + br label %ENDIF175 + +ENDIF175: ; preds = %ENDIF172, %IF176 + %temp84.5 = phi float [ %848, %IF176 ], [ %temp84.4, %ENDIF172 ] + %temp85.5 = phi float [ %849, %IF176 ], [ %temp85.4, %ENDIF172 ] + %temp86.5 = phi float [ %850, %IF176 ], [ %temp86.4, %ENDIF172 ] + %temp87.5 = phi float [ %851, %IF176 ], [ %temp87.4, %ENDIF172 ] + %temp92.11 = phi float [ %877, %IF176 ], [ %temp92.10, %ENDIF172 ] + %temp93.5 = phi float [ %878, %IF176 ], [ %temp93.4, %ENDIF172 ] + %temp94.5 = phi float [ %879, %IF176 ], [ %temp94.4, %ENDIF172 ] + %880 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) + %881 = extractelement <4 x float> %880, i32 0 + %882 = fcmp olt float %881, %179 + %883 = sext i1 %882 to i32 + %884 = bitcast i32 %883 to float + %885 = bitcast float %884 to i32 + %886 = icmp ne i32 %885, 0 + br i1 %886, label %IF179, label %ENDIF178 + +IF179: ; preds = %ENDIF175 + %887 = fadd float %202, 1.000000e+00 + %888 = fadd float %202, 1.000000e+00 + %889 = fadd float %202, 1.000000e+00 + %890 = insertelement <4 x float> undef, float %43, i32 0 + %891 = insertelement <4 x float> %890, float %44, i32 1 + %892 = insertelement <4 x float> %891, float %45, i32 2 + %893 = insertelement <4 x float> %892, float 0.000000e+00, i32 3 + %894 = insertelement <4 x float> undef, float %43, i32 0 + %895 = insertelement <4 x float> %894, float %44, i32 1 + %896 = insertelement <4 x float> %895, float %45, i32 2 + %897 = insertelement <4 x float> %896, float 0.000000e+00, i32 3 + %898 = call float @llvm.AMDGPU.dp4(<4 x float> %893, <4 x float> %897) + %899 = call float @llvm.AMDGPU.rsq(float %898) + %900 = fmul float %45, %899 + %901 = call float @fabs(float %900) + %902 = fmul float %176, 0x3FECCCCCC0000000 + %903 = fadd float %902, %901 + %904 = fadd float %903, 0xBFEFAE1480000000 + %905 = fmul float %904, 0xC043FFFE20000000 + %906 = call float @llvm.AMDIL.clamp.(float %905, float 0.000000e+00, float 1.000000e+00) + %907 = fmul float 2.000000e+00, %906 + %908 = fsub float -0.000000e+00, %907 + %909 = fadd float 3.000000e+00, %908 + %910 = fmul float %906, %909 + %911 = fmul float %906, %910 + %912 = call float @llvm.AMDGPU.lrp(float %911, float %temp84.5, float %887) + %913 = call float @llvm.AMDGPU.lrp(float %911, float %temp85.5, float %888) + %914 = call float @llvm.AMDGPU.lrp(float %911, float %temp86.5, float %889) + %915 = call float @llvm.AMDGPU.lrp(float %911, float %temp87.5, float 0.000000e+00) + %916 = fmul float %202, 5.000000e-01 + %917 = fcmp uge float 0x3FE4CCCCC0000000, %916 + %918 = select i1 %917, float 0x3FE4CCCCC0000000, float %916 + %919 = fcmp uge float %918, 0x3FE3333340000000 + %920 = select i1 %919, float 0x3FE3333340000000, float %918 + %921 = call float @llvm.AMDGPU.lrp(float %920, float %912, float %temp84.5) + %922 = call float @llvm.AMDGPU.lrp(float %920, float %913, float %temp85.5) + %923 = call float @llvm.AMDGPU.lrp(float %920, float %914, float %temp86.5) + %924 = call float @llvm.AMDGPU.lrp(float %920, float %915, float %temp87.5) + %925 = insertelement <4 x float> undef, float %329, i32 0 + %926 = insertelement <4 x float> %925, float %330, i32 1 + %927 = insertelement <4 x float> %926, float %331, i32 2 + %928 = insertelement <4 x float> %927, float 0.000000e+00, i32 3 + %929 = insertelement <4 x float> undef, float %63, i32 0 + %930 = insertelement <4 x float> %929, float %65, i32 1 + %931 = insertelement <4 x float> %930, float %67, i32 2 + %932 = insertelement <4 x float> %931, float 0.000000e+00, i32 3 + %933 = call float @llvm.AMDGPU.dp4(<4 x float> %928, <4 x float> %932) + %934 = fcmp uge float 0x3FE99999A0000000, %933 + %935 = select i1 %934, float 0x3FE99999A0000000, float %933 + %936 = fmul float %8, %935 + %937 = fmul float %13, %935 + %938 = fmul float %18, %935 + %939 = insertelement <4 x float> undef, float %34, i32 0 + %940 = insertelement <4 x float> %939, float %35, i32 1 + %941 = insertelement <4 x float> %940, float %36, i32 2 + %942 = insertelement <4 x float> %941, float 0.000000e+00, i32 3 + %943 = insertelement <4 x float> undef, float %63, i32 0 + %944 = insertelement <4 x float> %943, float %65, i32 1 + %945 = insertelement <4 x float> %944, float %67, i32 2 + %946 = insertelement <4 x float> %945, float 0.000000e+00, i32 3 + %947 = call float @llvm.AMDGPU.dp4(<4 x float> %942, <4 x float> %946) + %948 = fcmp uge float 0x3FECCCCCC0000000, %947 + %949 = select i1 %948, float 0x3FECCCCCC0000000, float %947 + %950 = fmul float %936, %949 + %951 = fmul float %937, %949 + %952 = fmul float %938, %949 + br label %ENDIF178 + +ENDIF178: ; preds = %ENDIF175, %IF179 + %temp84.6 = phi float [ %921, %IF179 ], [ %temp84.5, %ENDIF175 ] + %temp85.6 = phi float [ %922, %IF179 ], [ %temp85.5, %ENDIF175 ] + %temp86.6 = phi float [ %923, %IF179 ], [ %temp86.5, %ENDIF175 ] + %temp87.6 = phi float [ %924, %IF179 ], [ %temp87.5, %ENDIF175 ] + %temp92.12 = phi float [ %950, %IF179 ], [ %temp92.11, %ENDIF175 ] + %temp93.6 = phi float [ %951, %IF179 ], [ %temp93.5, %ENDIF175 ] + %temp94.6 = phi float [ %952, %IF179 ], [ %temp94.5, %ENDIF175 ] + %953 = fmul float %55, %temp92.12 + %954 = fmul float %57, %temp93.6 + %955 = fmul float %59, %temp94.6 + %956 = fmul float %61, 0.000000e+00 + %957 = fmul float %temp84.6, %953 + %958 = fmul float %temp85.6, %954 + %959 = fmul float %temp86.6, %955 + %960 = fmul float %temp87.6, %956 + %961 = fmul float %2, -2.000000e+00 + %962 = fadd float %961, 1.000000e+00 + %963 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) + %964 = extractelement <4 x float> %963, i32 2 + %965 = fsub float -0.000000e+00, %964 + %966 = fadd float %962, %965 + %967 = fdiv float 1.000000e+00, %966 + %968 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) + %969 = extractelement <4 x float> %968, i32 2 + %970 = fmul float %969, %967 + %971 = fsub float -0.000000e+00, %53 + %972 = fmul float %971, %53 + %973 = fmul float %972, %970 + %974 = fmul float %973, %970 + %975 = fmul float %974, 0x3FF7154760000000 + %976 = call float @llvm.AMDIL.exp.(float %975) + %977 = fcmp oeq float %53, 1.000000e+00 + %978 = sext i1 %977 to i32 + %979 = bitcast i32 %978 to float + %980 = bitcast float %979 to i32 + %981 = icmp ne i32 %980, 0 + %.184 = select i1 %981, float 1.000000e+00, float %976 + %982 = call float @llvm.AMDGPU.lrp(float %.184, float %957, float %47) + %983 = call float @llvm.AMDGPU.lrp(float %.184, float %958, float %49) + %984 = call float @llvm.AMDGPU.lrp(float %.184, float %959, float %51) + %985 = insertelement <4 x float> undef, float %982, i32 0 + %986 = insertelement <4 x float> %985, float %983, i32 1 + %987 = insertelement <4 x float> %986, float %984, i32 2 + %988 = insertelement <4 x float> %987, float %960, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %988, i32 0, i32 0) + ret void +} + +; Function Attrs: readnone +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.rsq(float) #1 + +; Function Attrs: readnone +declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 + +; Function Attrs: readonly +declare float @fabs(float) #2 + +; Function Attrs: readnone +declare float @llvm.AMDIL.exp.(float) #1 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.lrp(float, float, float) #1 + +; Function Attrs: readnone +declare float @llvm.AMDIL.clamp.(float, float, float) #1 + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { readnone } +attributes #2 = { readonly } diff --git a/test/CodeGen/R600/bitcast.ll b/test/CodeGen/R600/bitcast.ll new file mode 100644 index 000000000000..bccc41638570 --- /dev/null +++ b/test/CodeGen/R600/bitcast.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s + +; This test just checks that the compiler doesn't crash. +; CHECK-LABEL: @v32i8_to_v8i32 +; CHECK: S_ENDPGM + +define void @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 { +entry: + %1 = load <32 x i8> addrspace(2)* %0 + %2 = bitcast <32 x i8> %1 to <8 x i32> + %3 = extractelement <8 x i32> %2, i32 1 + %4 = icmp ne i32 %3, 0 + %5 = select i1 %4, float 0.0, float 1.0 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %5, float %5, float %5) + ret void +} + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } + diff --git a/test/CodeGen/R600/build_vector.ll b/test/CodeGen/R600/build_vector.ll new file mode 100644 index 000000000000..8179de13e869 --- /dev/null +++ b/test/CodeGen/R600/build_vector.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; R600-CHECK: @build_vector2 +; R600-CHECK: MOV +; R600-CHECK: MOV +; R600-CHECK-NOT: MOV +; SI-CHECK: @build_vector2 +; SI-CHECK-DAG: V_MOV_B32_e32 v[[X:[0-9]]], 5 +; SI-CHECK-DAG: V_MOV_B32_e32 v[[Y:[0-9]]], 6 +; SI-CHECK: BUFFER_STORE_DWORDX2 v{{\[}}[[X]]:[[Y]]{{\]}} +define void @build_vector2 (<2 x i32> addrspace(1)* %out) { +entry: + store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK: @build_vector4 +; R600-CHECK: MOV +; R600-CHECK: MOV +; R600-CHECK: MOV +; R600-CHECK: MOV +; R600-CHECK-NOT: MOV +; SI-CHECK: @build_vector4 +; SI-CHECK-DAG: V_MOV_B32_e32 v[[X:[0-9]]], 5 +; SI-CHECK-DAG: V_MOV_B32_e32 v[[Y:[0-9]]], 6 +; SI-CHECK-DAG: V_MOV_B32_e32 v[[Z:[0-9]]], 7 +; SI-CHECK-DAG: V_MOV_B32_e32 v[[W:[0-9]]], 8 +; SI-CHECK: BUFFER_STORE_DWORDX4 v{{\[}}[[X]]:[[W]]{{\]}} +define void @build_vector4 (<4 x i32> addrspace(1)* %out) { +entry: + store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/call_fs.ll b/test/CodeGen/R600/call_fs.ll index e152bf6d559d..f7c4e5b22cb1 100644 --- a/test/CodeGen/R600/call_fs.ll +++ b/test/CodeGen/R600/call_fs.ll @@ -3,8 +3,10 @@ ; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600-CHECK %s ; EG-CHECK: @call_fs +; EG-CHECK: .long 257 ; EG-CHECK: CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x84] ; R600-CHECK: @call_fs +; R600-CHECK: .long 257 ; R600-CHECK:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89] diff --git a/test/CodeGen/R600/combine_vloads.ll b/test/CodeGen/R600/combine_vloads.ll new file mode 100644 index 000000000000..f8ec712c1ec8 --- /dev/null +++ b/test/CodeGen/R600/combine_vloads.ll @@ -0,0 +1,42 @@ +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s + +; +; kernel void combine_vloads(global char8* src, global char8* result) { +; for (int i = 0; i < 1024; ++i) +; result[i] = src[0] + src[1] + src[2] + src[3]; +; } +; + + +; 128-bit loads instead of many 8-bit +; EG-LABEL: @combine_vloads: +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @combine_vloads(<8 x i8> addrspace(1)* nocapture %src, <8 x i8> addrspace(1)* nocapture %result) nounwind { +entry: + br label %for.body + +for.exit: ; preds = %for.body + ret void + +for.body: ; preds = %for.body, %entry + %i.01 = phi i32 [ 0, %entry ], [ %tmp19, %for.body ] + %arrayidx_v4 = bitcast <8 x i8> addrspace(1)* %src to <32 x i8> addrspace(1)* + %0 = bitcast <32 x i8> addrspace(1)* %arrayidx_v4 to <8 x i32> addrspace(1)* + %vecload2 = load <8 x i32> addrspace(1)* %0, align 32 + %1 = bitcast <8 x i32> %vecload2 to <32 x i8> + %tmp5 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %tmp8 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %tmp9 = add nsw <8 x i8> %tmp5, %tmp8 + %tmp12 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23> + %tmp13 = add nsw <8 x i8> %tmp9, %tmp12 + %tmp16 = shufflevector <32 x i8> %1, <32 x i8> undef, <8 x i32> <i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> + %tmp17 = add nsw <8 x i8> %tmp13, %tmp16 + %scevgep = getelementptr <8 x i8> addrspace(1)* %result, i32 %i.01 + %2 = bitcast <8 x i8> %tmp17 to <2 x i32> + %3 = bitcast <8 x i8> addrspace(1)* %scevgep to <2 x i32> addrspace(1)* + store <2 x i32> %2, <2 x i32> addrspace(1)* %3, align 8 + %tmp19 = add nsw i32 %i.01, 1 + %exitcond = icmp eq i32 %tmp19, 1024 + br i1 %exitcond, label %for.exit, label %for.body +} diff --git a/test/CodeGen/R600/complex-folding.ll b/test/CodeGen/R600/complex-folding.ll new file mode 100644 index 000000000000..99f0d99b3529 --- /dev/null +++ b/test/CodeGen/R600/complex-folding.ll @@ -0,0 +1,19 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @main +; CHECK-NOT: MOV +define void @main(<4 x float> inreg %reg0) #0 { +entry: + %0 = extractelement <4 x float> %reg0, i32 0 + %1 = call float @fabs(float %0) + %2 = fptoui float %1 to i32 + %3 = bitcast i32 %2 to float + %4 = insertelement <4 x float> undef, float %3, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %4, i32 0, i32 0) + ret void +} + +declare float @fabs(float ) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="0" }
\ No newline at end of file diff --git a/test/CodeGen/R600/dot4-folding.ll b/test/CodeGen/R600/dot4-folding.ll new file mode 100644 index 000000000000..3e8330f9b3ed --- /dev/null +++ b/test/CodeGen/R600/dot4-folding.ll @@ -0,0 +1,27 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; Exactly one constant vector can be folded into dot4, which means exactly +; 4 MOV instructions +; CHECK: @main +; CHECK: MOV +; CHECK: MOV +; CHECK: MOV +; CHECK: MOV +; CHECK-NOT: MOV +; CHECK-NOT: MOV +; CHECK-NOT: MOV +; CHECK-NOT: MOV + +define void @main(float addrspace(1)* %out) { +main_body: + %0 = load <4 x float> addrspace(8)* null + %1 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %2 = call float @llvm.AMDGPU.dp4(<4 x float> %0,<4 x float> %1) + %3 = insertelement <4 x float> undef, float %2, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %3, i32 0, i32 0) + ret void +} + +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +attributes #1 = { readnone } diff --git a/test/CodeGen/R600/elf.ll b/test/CodeGen/R600/elf.ll index f460f13d53e0..93851504bd4e 100644 --- a/test/CodeGen/R600/elf.ll +++ b/test/CodeGen/R600/elf.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=r600 -mcpu=SI -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=CONFIG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs -o - | FileCheck --check-prefix=CONFIG-CHECK %s ; ELF-CHECK: Format: ELF32 ; ELF-CHECK: Name: .AMDGPU.config diff --git a/test/CodeGen/R600/extload.ll b/test/CodeGen/R600/extload.ll new file mode 100644 index 000000000000..aa660b38838d --- /dev/null +++ b/test/CodeGen/R600/extload.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s + +; EG-LABEL: @anyext_load_i8: +; EG: AND_INT +; EG-NEXT: 255 +define void @anyext_load_i8(i8 addrspace(1)* nocapture noalias %out, i8 addrspace(1)* nocapture noalias %src) nounwind { + %cast = bitcast i8 addrspace(1)* %src to i32 addrspace(1)* + %load = load i32 addrspace(1)* %cast, align 1 + %x = bitcast i32 %load to <4 x i8> + %castOut = bitcast i8 addrspace(1)* %out to <4 x i8> addrspace(1)* + store <4 x i8> %x, <4 x i8> addrspace(1)* %castOut, align 1 + ret void +} + +; EG-LABEL: @anyext_load_i16: +; EG: AND_INT +; EG: LSHL +; EG: 65535 +define void @anyext_load_i16(i16 addrspace(1)* nocapture noalias %out, i16 addrspace(1)* nocapture noalias %src) nounwind { + %cast = bitcast i16 addrspace(1)* %src to i32 addrspace(1)* + %load = load i32 addrspace(1)* %cast, align 1 + %x = bitcast i32 %load to <2 x i16> + %castOut = bitcast i16 addrspace(1)* %out to <2 x i16> addrspace(1)* + store <2 x i16> %x, <2 x i16> addrspace(1)* %castOut, align 1 + ret void +} + +; EG-LABEL: @anyext_load_lds_i8: +; EG: AND_INT +; EG-NEXT: 255 +define void @anyext_load_lds_i8(i8 addrspace(3)* nocapture noalias %out, i8 addrspace(3)* nocapture noalias %src) nounwind { + %cast = bitcast i8 addrspace(3)* %src to i32 addrspace(3)* + %load = load i32 addrspace(3)* %cast, align 1 + %x = bitcast i32 %load to <4 x i8> + %castOut = bitcast i8 addrspace(3)* %out to <4 x i8> addrspace(3)* + store <4 x i8> %x, <4 x i8> addrspace(3)* %castOut, align 1 + ret void +} + +; EG-LABEL: @anyext_load_lds_i16: +; EG: AND_INT +; EG: LSHL +; EG: 65535 +define void @anyext_load_lds_i16(i16 addrspace(3)* nocapture noalias %out, i16 addrspace(3)* nocapture noalias %src) nounwind { + %cast = bitcast i16 addrspace(3)* %src to i32 addrspace(3)* + %load = load i32 addrspace(3)* %cast, align 1 + %x = bitcast i32 %load to <2 x i16> + %castOut = bitcast i16 addrspace(3)* %out to <2 x i16> addrspace(3)* + store <2 x i16> %x, <2 x i16> addrspace(3)* %castOut, align 1 + ret void +} diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll index 85f2882289fa..a5f5df96b5d9 100644 --- a/test/CodeGen/R600/fabs.ll +++ b/test/CodeGen/R600/fabs.ll @@ -1,16 +1,54 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -;CHECK: MOV * T{{[0-9]+\.[XYZW], \|T[0-9]+\.[XYZW]\|}} +; DAGCombiner will transform: +; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF)) +; unless isFabsFree returns true -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @fabs( float %r0) - call void @llvm.AMDGPU.store.output(float %r1, i32 0) - ret void +; R600-CHECK-LABEL: @fabs_free +; R600-CHECK-NOT: AND +; R600-CHECK: |PV.{{[XYZW]}}| +; SI-CHECK-LABEL: @fabs_free +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 + +define void @fabs_free(float addrspace(1)* %out, i32 %in) { +entry: + %0 = bitcast i32 %in to float + %1 = call float @fabs(float %0) + store float %1, float addrspace(1)* %out + ret void } -declare float @llvm.R600.load.input(i32) readnone +; R600-CHECK-LABEL: @fabs_v2 +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; SI-CHECK-LABEL: @fabs_v2 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +define void @fabs_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) { +entry: + %0 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in) + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} -declare void @llvm.AMDGPU.store.output(float, i32) +; R600-CHECK-LABEL: @fabs_v4 +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; SI-CHECK-LABEL: @fabs_v4 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +define void @fabs_v4(<4 x float> addrspace(1)* %out, <4 x float> %in) { +entry: + %0 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in) + store <4 x float> %0, <4 x float> addrspace(1)* %out + ret void +} declare float @fabs(float ) readnone +declare <2 x float> @llvm.fabs.v2f32(<2 x float> ) readnone +declare <4 x float> @llvm.fabs.v4f32(<4 x float> ) readnone diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll index 9a672329e75c..f467bb785779 100644 --- a/test/CodeGen/R600/fadd.ll +++ b/test/CodeGen/R600/fadd.ll @@ -1,26 +1,40 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; CHECK: @fadd_f32 -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @fadd_f32() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.R600.load.input(i32 1) - %r2 = fadd float %r0, %r1 - call void @llvm.AMDGPU.store.output(float %r2, i32 0) +; R600-CHECK: @fadd_f32 +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W +; SI-CHECK: @fadd_f32 +; SI-CHECK: V_ADD_F32 +define void @fadd_f32(float addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fadd float %a, %b + store float %0, float addrspace(1)* %out ret void } -declare float @llvm.R600.load.input(i32) readnone - -declare void @llvm.AMDGPU.store.output(float, i32) - -; CHECK: @fadd_v4f32 -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: @fadd_v2f32 +; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z +; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y +; SI-CHECK: @fadd_v2f32 +; SI-CHECK: V_ADD_F32 +; SI-CHECK: V_ADD_F32 +define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { +entry: + %0 = fadd <2 x float> %a, %b + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} +; R600-CHECK: @fadd_v4f32 +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; SI-CHECK: @fadd_v4f32 +; SI-CHECK: V_ADD_F32 +; SI-CHECK: V_ADD_F32 +; SI-CHECK: V_ADD_F32 +; SI-CHECK: V_ADD_F32 define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float> addrspace(1) * %in diff --git a/test/CodeGen/R600/fadd64.ll b/test/CodeGen/R600/fadd64.ll new file mode 100644 index 000000000000..48cd3cfc8dfb --- /dev/null +++ b/test/CodeGen/R600/fadd64.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s + +; CHECK: @fadd_f64 +; CHECK: V_ADD_F64 {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}}, {{v[[0-9]+:[0-9]+]}} + +define void @fadd_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = fadd double %r0, %r1 + store double %r2, double addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fcmp-cnd.ll b/test/CodeGen/R600/fcmp-cnd.ll index 7373a214790e..1d4e323d3abf 100644 --- a/test/CodeGen/R600/fcmp-cnd.ll +++ b/test/CodeGen/R600/fcmp-cnd.ll @@ -2,7 +2,7 @@ ;Not checking arguments 2 and 3 to CNDE, because they may change between ;registers and literal.x depending on what the optimizer does. -;CHECK: CNDE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) { entry: diff --git a/test/CodeGen/R600/fcmp.ll b/test/CodeGen/R600/fcmp.ll index dc3a779dd609..c76a75876565 100644 --- a/test/CodeGen/R600/fcmp.ll +++ b/test/CodeGen/R600/fcmp.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; CHECK: @fcmp_sext -; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @fcmp_sext(i32 addrspace(1)* %out, float addrspace(1)* %in) { entry: diff --git a/test/CodeGen/R600/fcmp64.ll b/test/CodeGen/R600/fcmp64.ll new file mode 100644 index 000000000000..bcc7a8c8567a --- /dev/null +++ b/test/CodeGen/R600/fcmp64.ll @@ -0,0 +1,79 @@ +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s + +; CHECK: @flt_f64 +; CHECK: V_CMP_LT_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} + +define void @flt_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = fcmp ult double %r0, %r1 + %r3 = select i1 %r2, double %r0, double %r1 + store double %r3, double addrspace(1)* %out + ret void +} + +; CHECK: @fle_f64 +; CHECK: V_CMP_LE_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} + +define void @fle_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = fcmp ule double %r0, %r1 + %r3 = select i1 %r2, double %r0, double %r1 + store double %r3, double addrspace(1)* %out + ret void +} + +; CHECK: @fgt_f64 +; CHECK: V_CMP_GT_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} + +define void @fgt_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = fcmp ugt double %r0, %r1 + %r3 = select i1 %r2, double %r0, double %r1 + store double %r3, double addrspace(1)* %out + ret void +} + +; CHECK: @fge_f64 +; CHECK: V_CMP_GE_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} + +define void @fge_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = fcmp uge double %r0, %r1 + %r3 = select i1 %r2, double %r0, double %r1 + store double %r3, double addrspace(1)* %out + ret void +} + +; CHECK: @fne_f64 +; CHECK: V_CMP_NEQ_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} + +define void @fne_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = fcmp une double %r0, %r1 + %r3 = select i1 %r2, double %r0, double %r1 + store double %r3, double addrspace(1)* %out + ret void +} + +; CHECK: @feq_f64 +; CHECK: V_CMP_EQ_F64_e64 {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}} + +define void @feq_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = fcmp ueq double %r0, %r1 + %r3 = select i1 %r2, double %r0, double %r1 + store double %r3, double addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fconst64.ll b/test/CodeGen/R600/fconst64.ll new file mode 100644 index 000000000000..5c5ee7e9091b --- /dev/null +++ b/test/CodeGen/R600/fconst64.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s + +; CHECK: @fconst_f64 +; CHECK: V_MOV_B32_e32 {{v[0-9]+}}, 0.000000e+00 +; CHECK-NEXT: V_MOV_B32_e32 {{v[0-9]+}}, 2.312500e+00 + +define void @fconst_f64(double addrspace(1)* %out, double addrspace(1)* %in) { + %r1 = load double addrspace(1)* %in + %r2 = fadd double %r1, 5.000000e+00 + store double %r2, double addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fdiv.ll b/test/CodeGen/R600/fdiv.ll index 2e68e36be4d8..3d21524de0f4 100644 --- a/test/CodeGen/R600/fdiv.ll +++ b/test/CodeGen/R600/fdiv.ll @@ -1,15 +1,46 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; These tests check that fdiv is expanded correctly and also test that the +; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate +; instruction groups. -define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { +; R600-CHECK: @fdiv_v2f32 +; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z +; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y +; R600-CHECK-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS +; R600-CHECK-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS +; SI-CHECK: @fdiv_v2f32 +; SI-CHECK-DAG: V_RCP_F32 +; SI-CHECK-DAG: V_MUL_F32 +; SI-CHECK-DAG: V_RCP_F32 +; SI-CHECK-DAG: V_MUL_F32 +define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { +entry: + %0 = fdiv <2 x float> %a, %b + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; R600-CHECK: @fdiv_v4f32 +; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; R600-CHECK-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; R600-CHECK-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; R600-CHECK-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; SI-CHECK: @fdiv_v4f32 +; SI-CHECK-DAG: V_RCP_F32 +; SI-CHECK-DAG: V_MUL_F32 +; SI-CHECK-DAG: V_RCP_F32 +; SI-CHECK-DAG: V_MUL_F32 +; SI-CHECK-DAG: V_RCP_F32 +; SI-CHECK-DAG: V_MUL_F32 +; SI-CHECK-DAG: V_RCP_F32 +; SI-CHECK-DAG: V_MUL_F32 +define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float> addrspace(1) * %in %b = load <4 x float> addrspace(1) * %b_ptr diff --git a/test/CodeGen/R600/fdiv64.ll b/test/CodeGen/R600/fdiv64.ll new file mode 100644 index 000000000000..79b5c8bb96ee --- /dev/null +++ b/test/CodeGen/R600/fdiv64.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s + +; CHECK: @fdiv_f64 +; CHECK: V_RCP_F64_e32 {{v\[[0-9]+:[0-9]+\]}} +; CHECK: V_MUL_F64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} + +define void @fdiv_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = fdiv double %r0, %r1 + store double %r2, double addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fetch-limits.r600.ll b/test/CodeGen/R600/fetch-limits.r600.ll new file mode 100644 index 000000000000..f78d1d968e5d --- /dev/null +++ b/test/CodeGen/R600/fetch-limits.r600.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -march=r600 -mcpu=r600 | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=rs880 | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=rv670 | FileCheck %s + +; R600 supports 8 fetches in a clause +; CHECK: @fetch_limits_r600 +; CHECK: Fetch clause +; CHECK: Fetch clause + +define void @fetch_limits_r600() #0 { +entry: + %0 = load <4 x float> addrspace(8)* null + %1 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %3 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %5 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %6 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) + %7 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) + %res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1) + %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1) + %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1) + %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1) + %res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1) + %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1) + %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1) + %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1) + %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1) + %a = fadd <4 x float> %res0, %res1 + %b = fadd <4 x float> %res2, %res3 + %c = fadd <4 x float> %res4, %res5 + %d = fadd <4 x float> %res6, %res7 + %e = fadd <4 x float> %res8, %a + + %bc = fadd <4 x float> %b, %c + %de = fadd <4 x float> %d, %e + + %bcde = fadd <4 x float> %bc, %de + + call void @llvm.R600.store.swizzle(<4 x float> %bcde, i32 0, i32 1) + ret void +} + +attributes #0 = { "ShaderType"="0" } ; Pixel Shader + +declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/R600/fetch-limits.r700+.ll b/test/CodeGen/R600/fetch-limits.r700+.ll new file mode 100644 index 000000000000..1a8a43fccc72 --- /dev/null +++ b/test/CodeGen/R600/fetch-limits.r700+.ll @@ -0,0 +1,81 @@ +; RUN: llc < %s -march=r600 -mcpu=rv710 | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=rv730 | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=rv770 | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=sumo | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=juniper | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=cypress | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=barts | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=turks | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=caicos | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s + +; r700+ supports 16 fetches in a clause +; CHECK: @fetch_limits_r700 +; CHECK: Fetch clause +; CHECK: Fetch clause + +define void @fetch_limits_r700() #0 { +entry: + %0 = load <4 x float> addrspace(8)* null + %1 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %3 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %5 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %6 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) + %7 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) + %9 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) + %11 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) + %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) + %13 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13) + %14 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) + %15 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) + %16 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) + %res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1) + %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1) + %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1) + %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1) + %res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1) + %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1) + %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1) + %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1) + %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1) + %res9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %9, i32 0, i32 0, i32 1) + %res10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %10, i32 0, i32 0, i32 1) + %res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %11, i32 0, i32 0, i32 1) + %res12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %12, i32 0, i32 0, i32 1) + %res13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 0, i32 0, i32 1) + %res14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %14, i32 0, i32 0, i32 1) + %res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %15, i32 0, i32 0, i32 1) + %res16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %16, i32 0, i32 0, i32 1) + %a = fadd <4 x float> %res0, %res1 + %b = fadd <4 x float> %res2, %res3 + %c = fadd <4 x float> %res4, %res5 + %d = fadd <4 x float> %res6, %res7 + %e = fadd <4 x float> %res8, %res9 + %f = fadd <4 x float> %res10, %res11 + %g = fadd <4 x float> %res12, %res13 + %h = fadd <4 x float> %res14, %res15 + %i = fadd <4 x float> %res16, %a + + %bc = fadd <4 x float> %b, %c + %de = fadd <4 x float> %d, %e + %fg = fadd <4 x float> %f, %g + %hi = fadd <4 x float> %h, %i + + %bcde = fadd <4 x float> %bc, %de + %fghi = fadd <4 x float> %fg, %hi + + %bcdefghi = fadd <4 x float> %bcde, %fghi + call void @llvm.R600.store.swizzle(<4 x float> %bcdefghi, i32 0, i32 1) + ret void +} + +attributes #0 = { "ShaderType"="0" } ; Pixel Shader + +declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/R600/floor.ll b/test/CodeGen/R600/floor.ll index 877d69a65b43..67e86c41fdcf 100644 --- a/test/CodeGen/R600/floor.ll +++ b/test/CodeGen/R600/floor.ll @@ -2,15 +2,15 @@ ;CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = call float @floor(float %r0) - call void @llvm.AMDGPU.store.output(float %r1, i32 0) + %vec = insertelement <4 x float> undef, float %r1, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare float @llvm.R600.load.input(i32) readnone - -declare void @llvm.AMDGPU.store.output(float, i32) - declare float @floor(float) readonly +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="0" }
\ No newline at end of file diff --git a/test/CodeGen/R600/fma.ll b/test/CodeGen/R600/fma.ll new file mode 100644 index 000000000000..51e9d29a5ca2 --- /dev/null +++ b/test/CodeGen/R600/fma.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s + +; CHECK: @fma_f32 +; CHECK: V_FMA_F32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}} + +define void @fma_f32(float addrspace(1)* %out, float addrspace(1)* %in1, + float addrspace(1)* %in2, float addrspace(1)* %in3) { + %r0 = load float addrspace(1)* %in1 + %r1 = load float addrspace(1)* %in2 + %r2 = load float addrspace(1)* %in3 + %r3 = tail call float @llvm.fma.f32(float %r0, float %r1, float %r2) + store float %r3, float addrspace(1)* %out + ret void +} + +declare float @llvm.fma.f32(float, float, float) + +; CHECK: @fma_f64 +; CHECK: V_FMA_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} + +define void @fma_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2, double addrspace(1)* %in3) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = load double addrspace(1)* %in3 + %r3 = tail call double @llvm.fma.f64(double %r0, double %r1, double %r2) + store double %r3, double addrspace(1)* %out + ret void +} + +declare double @llvm.fma.f64(double, double, double) diff --git a/test/CodeGen/R600/fmad.ll b/test/CodeGen/R600/fmad.ll index 62001edc3aa5..935e35123f45 100644 --- a/test/CodeGen/R600/fmad.ll +++ b/test/CodeGen/R600/fmad.ll @@ -1,19 +1,19 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: MULADD_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.R600.load.input(i32 1) - %r2 = call float @llvm.R600.load.input(i32 2) +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 + %r1 = extractelement <4 x float> %reg0, i32 1 + %r2 = extractelement <4 x float> %reg0, i32 2 %r3 = fmul float %r0, %r1 - %r4 = fadd float %r3, %r2 - call void @llvm.AMDGPU.store.output(float %r4, i32 0) + %r4 = fadd float %r3, %r2 + %vec = insertelement <4 x float> undef, float %r4, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare float @llvm.R600.load.input(i32) readnone - -declare void @llvm.AMDGPU.store.output(float, i32) - declare float @fabs(float ) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="0" }
\ No newline at end of file diff --git a/test/CodeGen/R600/fmax.ll b/test/CodeGen/R600/fmax.ll index 8b704e56484b..d7127f485c74 100644 --- a/test/CodeGen/R600/fmax.ll +++ b/test/CodeGen/R600/fmax.ll @@ -2,15 +2,16 @@ ;CHECK: MAX * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.R600.load.input(i32 1) - %r2 = fcmp uge float %r0, %r1 +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 + %r1 = extractelement <4 x float> %reg0, i32 1 + %r2 = fcmp oge float %r0, %r1 %r3 = select i1 %r2, float %r0, float %r1 - call void @llvm.AMDGPU.store.output(float %r3, i32 0) + %vec = insertelement <4 x float> undef, float %r3, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare float @llvm.R600.load.input(i32) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -declare void @llvm.AMDGPU.store.output(float, i32) +attributes #0 = { "ShaderType"="0" }
\ No newline at end of file diff --git a/test/CodeGen/R600/fmin.ll b/test/CodeGen/R600/fmin.ll index 5e34b7c8902e..defa8c09638a 100644 --- a/test/CodeGen/R600/fmin.ll +++ b/test/CodeGen/R600/fmin.ll @@ -2,15 +2,16 @@ ;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.R600.load.input(i32 1) +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 + %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = fcmp uge float %r0, %r1 %r3 = select i1 %r2, float %r1, float %r0 - call void @llvm.AMDGPU.store.output(float %r3, i32 0) + %vec = insertelement <4 x float> undef, float %r3, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare float @llvm.R600.load.input(i32) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -declare void @llvm.AMDGPU.store.output(float, i32) +attributes #0 = { "ShaderType"="0" }
\ No newline at end of file diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll index c29294632dc0..2a7825f9ecf7 100644 --- a/test/CodeGen/R600/fmul.ll +++ b/test/CodeGen/R600/fmul.ll @@ -1,26 +1,44 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; CHECK: @fmul_f32 -; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @fmul_f32() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.R600.load.input(i32 1) - %r2 = fmul float %r0, %r1 - call void @llvm.AMDGPU.store.output(float %r2, i32 0) - ret void +; R600-CHECK: @fmul_f32 +; R600-CHECK: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W +; SI-CHECK: @fmul_f32 +; SI-CHECK: V_MUL_F32 +define void @fmul_f32(float addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fmul float %a, %b + store float %0, float addrspace(1)* %out + ret void } declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) -; CHECK: @fmul_v4f32 -; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: @fmul_v2f32 +; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} +; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} +; SI-CHECK: @fmul_v2f32 +; SI-CHECK: V_MUL_F32 +; SI-CHECK: V_MUL_F32 +define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { +entry: + %0 = fmul <2 x float> %a, %b + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} +; R600-CHECK: @fmul_v4f32 +; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; SI-CHECK: @fmul_v4f32 +; SI-CHECK: V_MUL_F32 +; SI-CHECK: V_MUL_F32 +; SI-CHECK: V_MUL_F32 +; SI-CHECK: V_MUL_F32 define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float> addrspace(1) * %in diff --git a/test/CodeGen/R600/fmul.v4f32.ll b/test/CodeGen/R600/fmul.v4f32.ll deleted file mode 100644 index 74a58f74026a..000000000000 --- a/test/CodeGen/R600/fmul.v4f32.ll +++ /dev/null @@ -1,15 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 - %a = load <4 x float> addrspace(1) * %in - %b = load <4 x float> addrspace(1) * %b_ptr - %result = fmul <4 x float> %a, %b - store <4 x float> %result, <4 x float> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/fmul64.ll b/test/CodeGen/R600/fmul64.ll new file mode 100644 index 000000000000..7c7bf041496b --- /dev/null +++ b/test/CodeGen/R600/fmul64.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s + +; CHECK: @fmul_f64 +; CHECK: V_MUL_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} + +define void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = fmul double %r0, %r1 + store double %r2, double addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fmuladd.ll b/test/CodeGen/R600/fmuladd.ll new file mode 100644 index 000000000000..48944f629482 --- /dev/null +++ b/test/CodeGen/R600/fmuladd.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s + +; CHECK: @fmuladd_f32 +; CHECK: V_MAD_F32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}} + +define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1, + float addrspace(1)* %in2, float addrspace(1)* %in3) { + %r0 = load float addrspace(1)* %in1 + %r1 = load float addrspace(1)* %in2 + %r2 = load float addrspace(1)* %in3 + %r3 = tail call float @llvm.fmuladd.f32(float %r0, float %r1, float %r2) + store float %r3, float addrspace(1)* %out + ret void +} + +declare float @llvm.fmuladd.f32(float, float, float) + +; CHECK: @fmuladd_f64 +; CHECK: V_FMA_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} + +define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2, double addrspace(1)* %in3) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = load double addrspace(1)* %in3 + %r3 = tail call double @llvm.fmuladd.f64(double %r0, double %r1, double %r2) + store double %r3, double addrspace(1)* %out + ret void +} + +declare double @llvm.fmuladd.f64(double, double, double) diff --git a/test/CodeGen/R600/fneg.ll b/test/CodeGen/R600/fneg.ll new file mode 100644 index 000000000000..9446aa8ea9c3 --- /dev/null +++ b/test/CodeGen/R600/fneg.ll @@ -0,0 +1,61 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; R600-CHECK-LABEL: @fneg +; R600-CHECK: -PV +; SI-CHECK-LABEL: @fneg +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1 +define void @fneg(float addrspace(1)* %out, float %in) { +entry: + %0 = fsub float -0.000000e+00, %in + store float %0, float addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @fneg_v2 +; R600-CHECK: -PV +; R600-CHECK: -PV +; SI-CHECK-LABEL: @fneg_v2 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1 +define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) { +entry: + %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @fneg_v4 +; R600-CHECK: -PV +; R600-CHECK: -T +; R600-CHECK: -PV +; R600-CHECK: -PV +; SI-CHECK-LABEL: @fneg_v4 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 0, 0, 0, 1 +define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) { +entry: + %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in + store <4 x float> %0, <4 x float> addrspace(1)* %out + ret void +} + +; DAGCombiner will transform: +; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000)) +; unless the target returns true for isNegFree() + +; R600-CHECK-LABEL: @fneg_free +; R600-CHECK-NOT: XOR +; R600-CHECK: -KC0[2].Z +; SI-CHECK-LABEL: @fneg_free +; XXX: We could use V_ADD_F32_e64 with the negate bit here instead. +; SI-CHECK: V_SUB_F32_e64 v{{[0-9]}}, 0.000000e+00, s{{[0-9]}}, 0, 0, 0, 0 +define void @fneg_free(float addrspace(1)* %out, i32 %in) { +entry: + %0 = bitcast i32 %in to float + %1 = fsub float 0.0, %0 + store float %1, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fp64_to_sint.ll b/test/CodeGen/R600/fp64_to_sint.ll new file mode 100644 index 000000000000..185e21c9caa3 --- /dev/null +++ b/test/CodeGen/R600/fp64_to_sint.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK + +; CHECK: @fp64_to_sint +; CHECK: V_CVT_I32_F64_e32 +define void @fp64_to_sint(i32 addrspace(1)* %out, double %in) { + %result = fptosi double %in to i32 + store i32 %result, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fp_to_sint.ll b/test/CodeGen/R600/fp_to_sint.ll index f5716e1d47e6..8302b4f8233e 100644 --- a/test/CodeGen/R600/fp_to_sint.ll +++ b/test/CodeGen/R600/fp_to_sint.ll @@ -1,11 +1,28 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; CHECK: @fp_to_sint_v4i32 -; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: @fp_to_sint_v2i32 +; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +; SI-CHECK: @fp_to_sint_v2i32 +; SI-CHECK: V_CVT_I32_F32_e32 +; SI-CHECK: V_CVT_I32_F32_e32 +define void @fp_to_sint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) { + %result = fptosi <2 x float> %in to <2 x i32> + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} +; R600-CHECK: @fp_to_sint_v4i32 +; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW]}} +; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +; R600-CHECK: FLT_TO_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +; SI-CHECK: @fp_to_sint_v4i32 +; SI-CHECK: V_CVT_I32_F32_e32 +; SI-CHECK: V_CVT_I32_F32_e32 +; SI-CHECK: V_CVT_I32_F32_e32 +; SI-CHECK: V_CVT_I32_F32_e32 define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %value = load <4 x float> addrspace(1) * %in %result = fptosi <4 x float> %value to <4 x i32> diff --git a/test/CodeGen/R600/fp_to_uint.ll b/test/CodeGen/R600/fp_to_uint.ll index 1c3c0c62cf50..77db43b39c5f 100644 --- a/test/CodeGen/R600/fp_to_uint.ll +++ b/test/CodeGen/R600/fp_to_uint.ll @@ -1,10 +1,29 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; CHECK: @fp_to_uint_v4i32 -; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: @fp_to_uint_v2i32 +; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; SI-CHECK: @fp_to_uint_v2i32 +; SI-CHECK: V_CVT_U32_F32_e32 +; SI-CHECK: V_CVT_U32_F32_e32 + +define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) { + %result = fptoui <2 x float> %in to <2 x i32> + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK: @fp_to_uint_v4i32 +; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +; R600-CHECK: FLT_TO_UINT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}} +; SI-CHECK: @fp_to_uint_v4i32 +; SI-CHECK: V_CVT_U32_F32_e32 +; SI-CHECK: V_CVT_U32_F32_e32 +; SI-CHECK: V_CVT_U32_F32_e32 +; SI-CHECK: V_CVT_U32_F32_e32 define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %value = load <4 x float> addrspace(1) * %in diff --git a/test/CodeGen/R600/fpext.ll b/test/CodeGen/R600/fpext.ll new file mode 100644 index 000000000000..143ee79fa151 --- /dev/null +++ b/test/CodeGen/R600/fpext.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK + +; CHECK: @fpext +; CHECK: V_CVT_F64_F32_e32 +define void @fpext(double addrspace(1)* %out, float %in) { + %result = fpext float %in to double + store double %result, double addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fptrunc.ll b/test/CodeGen/R600/fptrunc.ll new file mode 100644 index 000000000000..20a8c00ba498 --- /dev/null +++ b/test/CodeGen/R600/fptrunc.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK + +; CHECK: @fptrunc +; CHECK: V_CVT_F32_F64_e32 +define void @fptrunc(float addrspace(1)* %out, double %in) { + %result = fptrunc double %in to float + store float %result, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fsqrt.ll b/test/CodeGen/R600/fsqrt.ll new file mode 100644 index 000000000000..ae50b17d38fc --- /dev/null +++ b/test/CodeGen/R600/fsqrt.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s + +; CHECK: @fsqrt_f32 +; CHECK: V_SQRT_F32_e32 {{v[0-9]+, v[0-9]+}} + +define void @fsqrt_f32(float addrspace(1)* %out, float addrspace(1)* %in) { + %r0 = load float addrspace(1)* %in + %r1 = call float @llvm.sqrt.f32(float %r0) + store float %r1, float addrspace(1)* %out + ret void +} + +; CHECK: @fsqrt_f64 +; CHECK: V_SQRT_F64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} + +define void @fsqrt_f64(double addrspace(1)* %out, double addrspace(1)* %in) { + %r0 = load double addrspace(1)* %in + %r1 = call double @llvm.sqrt.f64(double %r0) + store double %r1, double addrspace(1)* %out + ret void +} + +declare float @llvm.sqrt.f32(float %Val) +declare double @llvm.sqrt.f64(double %Val) diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll index f784cde46cd2..4f74efba4d8b 100644 --- a/test/CodeGen/R600/fsub.ll +++ b/test/CodeGen/R600/fsub.ll @@ -1,26 +1,44 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; CHECK: @fsub_f32 -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} - -define void @fsub_f32() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.R600.load.input(i32 1) - %r2 = fsub float %r0, %r1 - call void @llvm.AMDGPU.store.output(float %r2, i32 0) - ret void +; R600-CHECK: @fsub_f32 +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W +; SI-CHECK: @fsub_f32 +; SI-CHECK: V_SUB_F32 +define void @fsub_f32(float addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fsub float %a, %b + store float %0, float addrspace(1)* %out + ret void } declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) -; CHECK: @fsub_v4f32 -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: @fsub_v2f32 +; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z +; R600-CHECK-DAG: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y +; SI-CHECK: @fsub_v2f32 +; SI-CHECK: V_SUB_F32 +; SI-CHECK: V_SUB_F32 +define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { +entry: + %0 = fsub <2 x float> %a, %b + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} +; R600-CHECK: @fsub_v4f32 +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; SI-CHECK: @fsub_v4f32 +; SI-CHECK: V_SUB_F32 +; SI-CHECK: V_SUB_F32 +; SI-CHECK: V_SUB_F32 +; SI-CHECK: V_SUB_F32 define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float> addrspace(1) * %in diff --git a/test/CodeGen/R600/fsub64.ll b/test/CodeGen/R600/fsub64.ll new file mode 100644 index 000000000000..1445a20839ad --- /dev/null +++ b/test/CodeGen/R600/fsub64.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s + +; CHECK: @fsub_f64 +; CHECK: V_ADD_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}, 0, 0, 0, 0, 2 + +define void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %in1, + double addrspace(1)* %in2) { + %r0 = load double addrspace(1)* %in1 + %r1 = load double addrspace(1)* %in2 + %r2 = fsub double %r0, %r1 + store double %r2, double addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/gep-address-space.ll b/test/CodeGen/R600/gep-address-space.ll new file mode 100644 index 000000000000..4ea21dde8a05 --- /dev/null +++ b/test/CodeGen/R600/gep-address-space.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s + +define void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind { +; CHECK-LABEL @use_gep_address_space: +; CHECK: S_ADD_I32 + %p = getelementptr [1024 x i32] addrspace(3)* %array, i16 0, i16 16 + store i32 99, i32 addrspace(3)* %p + ret void +} + +define void @gep_as_vector_v4(<4 x [1024 x i32] addrspace(3)*> %array) nounwind { +; CHECK-LABEL: @gep_as_vector_v4: +; CHECK: S_ADD_I32 +; CHECK: S_ADD_I32 +; CHECK: S_ADD_I32 +; CHECK: S_ADD_I32 + %p = getelementptr <4 x [1024 x i32] addrspace(3)*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16> + %p0 = extractelement <4 x i32 addrspace(3)*> %p, i32 0 + %p1 = extractelement <4 x i32 addrspace(3)*> %p, i32 1 + %p2 = extractelement <4 x i32 addrspace(3)*> %p, i32 2 + %p3 = extractelement <4 x i32 addrspace(3)*> %p, i32 3 + store i32 99, i32 addrspace(3)* %p0 + store i32 99, i32 addrspace(3)* %p1 + store i32 99, i32 addrspace(3)* %p2 + store i32 99, i32 addrspace(3)* %p3 + ret void +} + +define void @gep_as_vector_v2(<2 x [1024 x i32] addrspace(3)*> %array) nounwind { +; CHECK-LABEL: @gep_as_vector_v2: +; CHECK: S_ADD_I32 +; CHECK: S_ADD_I32 + %p = getelementptr <2 x [1024 x i32] addrspace(3)*> %array, <2 x i16> zeroinitializer, <2 x i16> <i16 16, i16 16> + %p0 = extractelement <2 x i32 addrspace(3)*> %p, i32 0 + %p1 = extractelement <2 x i32 addrspace(3)*> %p, i32 1 + store i32 99, i32 addrspace(3)* %p0 + store i32 99, i32 addrspace(3)* %p1 + ret void +} + diff --git a/test/CodeGen/R600/icmp-select-sete-reverse-args.ll b/test/CodeGen/R600/icmp-select-sete-reverse-args.ll index e3005fe82da1..71705a64f50e 100644 --- a/test/CodeGen/R600/icmp-select-sete-reverse-args.ll +++ b/test/CodeGen/R600/icmp-select-sete-reverse-args.ll @@ -3,7 +3,7 @@ ;Test that a select with reversed True/False values is correctly lowered ;to a SETNE_INT. There should only be one SETNE_INT instruction. -;CHECK: SETNE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: SETNE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;CHECK-NOT: SETNE_INT define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll index 979efb00e7bd..b047315be71a 100644 --- a/test/CodeGen/R600/imm.ll +++ b/test/CodeGen/R600/imm.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ; Use a 64-bit value with lo bits that can be represented as an inline constant ; CHECK: @i64_imm_inline_lo -; CHECK: S_MOV_B32 [[LO:SGPR[0-9]+]], 5 -; CHECK: V_MOV_B32_e32 [[LO_VGPR:VGPR[0-9]+]], [[LO]] -; CHECK: BUFFER_STORE_DWORDX2 [[LO_VGPR]]_ +; CHECK: S_MOV_B32 [[LO:s[0-9]+]], 5 +; CHECK: V_MOV_B32_e32 v[[LO_VGPR:[0-9]+]], [[LO]] +; CHECK: BUFFER_STORE_DWORDX2 v{{\[}}[[LO_VGPR]]: define void @i64_imm_inline_lo(i64 addrspace(1) *%out) { entry: store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005 @@ -13,9 +13,9 @@ entry: ; Use a 64-bit value with hi bits that can be represented as an inline constant ; CHECK: @i64_imm_inline_hi -; CHECK: S_MOV_B32 [[HI:SGPR[0-9]+]], 5 -; CHECK: V_MOV_B32_e32 [[HI_VGPR:VGPR[0-9]+]], [[HI]] -; CHECK: BUFFER_STORE_DWORDX2 {{VGPR[0-9]+}}_[[HI_VGPR]] +; CHECK: S_MOV_B32 [[HI:s[0-9]+]], 5 +; CHECK: V_MOV_B32_e32 v[[HI_VGPR:[0-9]+]], [[HI]] +; CHECK: BUFFER_STORE_DWORDX2 v{{\[[0-9]+:}}[[HI_VGPR]] define void @i64_imm_inline_hi(i64 addrspace(1) *%out) { entry: store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678 diff --git a/test/CodeGen/R600/indirect-addressing-si.ll b/test/CodeGen/R600/indirect-addressing-si.ll new file mode 100644 index 000000000000..169d69b7c25c --- /dev/null +++ b/test/CodeGen/R600/indirect-addressing-si.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s + +; Tests for indirect addressing on SI, which is implemented using dynamic +; indexing of vectors. + +; CHECK: extract_w_offset +; CHECK: S_MOV_B32 m0 +; CHECK-NEXT: V_MOVRELS_B32_e32 +define void @extract_w_offset(float addrspace(1)* %out, i32 %in) { +entry: + %0 = add i32 %in, 1 + %1 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %0 + store float %1, float addrspace(1)* %out + ret void +} + +; CHECK: extract_wo_offset +; CHECK: S_MOV_B32 m0 +; CHECK-NEXT: V_MOVRELS_B32_e32 +define void @extract_wo_offset(float addrspace(1)* %out, i32 %in) { +entry: + %0 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %in + store float %0, float addrspace(1)* %out + ret void +} + +; CHECK: insert_w_offset +; CHECK: S_MOV_B32 m0 +; CHECK-NEXT: V_MOVRELD_B32_e32 +define void @insert_w_offset(float addrspace(1)* %out, i32 %in) { +entry: + %0 = add i32 %in, 1 + %1 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %0 + %2 = extractelement <4 x float> %1, i32 2 + store float %2, float addrspace(1)* %out + ret void +} + +; CHECK: insert_wo_offset +; CHECK: S_MOV_B32 m0 +; CHECK-NEXT: V_MOVRELD_B32_e32 +define void @insert_wo_offset(float addrspace(1)* %out, i32 %in) { +entry: + %0 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %in + %1 = extractelement <4 x float> %0, i32 2 + store float %1, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/insert_vector_elt.ll b/test/CodeGen/R600/insert_vector_elt.ll new file mode 100644 index 000000000000..05aeccebac00 --- /dev/null +++ b/test/CodeGen/R600/insert_vector_elt.ll @@ -0,0 +1,16 @@ +; XFAIL: * +; RUN: llc < %s -march=r600 -mcpu=redwood -o %t + +define void @var_insert(<4 x i32> addrspace(1)* %out, <4 x i32> %x, i32 %val, i32 %idx) nounwind { +entry: + %tmp3 = insertelement <4 x i32> %x, i32 %val, i32 %idx ; <<4 x i32>> [#uses=1] + store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out + ret void +} + +define void @var_extract(i32 addrspace(1)* %out, <4 x i32> %x, i32 %idx) nounwind { +entry: + %tmp3 = extractelement <4 x i32> %x, i32 %idx ; <<i32>> [#uses=1] + store i32 %tmp3, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/kcache-fold.ll b/test/CodeGen/R600/kcache-fold.ll index 3d70e4bd54aa..0baa3cd3e1a3 100644 --- a/test/CodeGen/R600/kcache-fold.ll +++ b/test/CodeGen/R600/kcache-fold.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; CHECK: @main1 -; CHECK: MOV T{{[0-9]+\.[XYZW], KC0}} +; CHECK: MOV * T{{[0-9]+\.[XYZW], KC0}} define void @main1() { main_body: %0 = load <4 x float> addrspace(8)* null @@ -10,7 +10,7 @@ main_body: %3 = extractelement <4 x float> %2, i32 0 %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %5 = extractelement <4 x float> %4, i32 0 - %6 = fcmp ult float %1, 0.000000e+00 + %6 = fcmp ogt float %1, 0.000000e+00 %7 = select i1 %6, float %3, float %5 %8 = load <4 x float> addrspace(8)* null %9 = extractelement <4 x float> %8, i32 1 @@ -18,7 +18,7 @@ main_body: %11 = extractelement <4 x float> %10, i32 1 %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %13 = extractelement <4 x float> %12, i32 1 - %14 = fcmp ult float %9, 0.000000e+00 + %14 = fcmp ogt float %9, 0.000000e+00 %15 = select i1 %14, float %11, float %13 %16 = load <4 x float> addrspace(8)* null %17 = extractelement <4 x float> %16, i32 2 @@ -26,7 +26,7 @@ main_body: %19 = extractelement <4 x float> %18, i32 2 %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %21 = extractelement <4 x float> %20, i32 2 - %22 = fcmp ult float %17, 0.000000e+00 + %22 = fcmp ogt float %17, 0.000000e+00 %23 = select i1 %22, float %19, float %21 %24 = load <4 x float> addrspace(8)* null %25 = extractelement <4 x float> %24, i32 3 @@ -34,7 +34,7 @@ main_body: %27 = extractelement <4 x float> %26, i32 3 %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %29 = extractelement <4 x float> %28, i32 3 - %30 = fcmp ult float %25, 0.000000e+00 + %30 = fcmp ogt float %25, 0.000000e+00 %31 = select i1 %30, float %27, float %29 %32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00) %33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) @@ -58,7 +58,7 @@ main_body: %3 = extractelement <4 x float> %2, i32 0 %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %5 = extractelement <4 x float> %4, i32 1 - %6 = fcmp ult float %1, 0.000000e+00 + %6 = fcmp ogt float %1, 0.000000e+00 %7 = select i1 %6, float %3, float %5 %8 = load <4 x float> addrspace(8)* null %9 = extractelement <4 x float> %8, i32 1 @@ -66,7 +66,7 @@ main_body: %11 = extractelement <4 x float> %10, i32 0 %12 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %13 = extractelement <4 x float> %12, i32 1 - %14 = fcmp ult float %9, 0.000000e+00 + %14 = fcmp ogt float %9, 0.000000e+00 %15 = select i1 %14, float %11, float %13 %16 = load <4 x float> addrspace(8)* null %17 = extractelement <4 x float> %16, i32 2 @@ -74,7 +74,7 @@ main_body: %19 = extractelement <4 x float> %18, i32 3 %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %21 = extractelement <4 x float> %20, i32 2 - %22 = fcmp ult float %17, 0.000000e+00 + %22 = fcmp ogt float %17, 0.000000e+00 %23 = select i1 %22, float %19, float %21 %24 = load <4 x float> addrspace(8)* null %25 = extractelement <4 x float> %24, i32 3 @@ -82,7 +82,7 @@ main_body: %27 = extractelement <4 x float> %26, i32 3 %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) %29 = extractelement <4 x float> %28, i32 2 - %30 = fcmp ult float %25, 0.000000e+00 + %30 = fcmp ogt float %25, 0.000000e+00 %31 = select i1 %30, float %27, float %29 %32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00) %33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) diff --git a/test/CodeGen/R600/kernel-args.ll b/test/CodeGen/R600/kernel-args.ll new file mode 100644 index 000000000000..247e3163823f --- /dev/null +++ b/test/CodeGen/R600/kernel-args.ll @@ -0,0 +1,455 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; EG-CHECK-LABEL: @i8_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK-LABEL: @i8_arg +; SI-CHECK: BUFFER_LOAD_UBYTE + +define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind { +entry: + %0 = zext i8 %in to i32 + store i32 %0, i32 addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @i8_zext_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK-LABEL: @i8_zext_arg +; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11 + +define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind { +entry: + %0 = zext i8 %in to i32 + store i32 %0, i32 addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @i8_sext_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK-LABEL: @i8_sext_arg +; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11 + +define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind { +entry: + %0 = sext i8 %in to i32 + store i32 %0, i32 addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @i16_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK-LABEL: @i16_arg +; SI-CHECK: BUFFER_LOAD_USHORT + +define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind { +entry: + %0 = zext i16 %in to i32 + store i32 %0, i32 addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @i16_zext_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK-LABEL: @i16_zext_arg +; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11 + +define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind { +entry: + %0 = zext i16 %in to i32 + store i32 %0, i32 addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @i16_sext_arg +; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK-LABEL: @i16_sext_arg +; SI-CHECK: S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11 + +define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind { +entry: + %0 = sext i16 %in to i32 + store i32 %0, i32 addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @i32_arg +; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z +; SI-CHECK-LABEL: @i32_arg +; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11 +define void @i32_arg(i32 addrspace(1)* nocapture %out, i32 %in) nounwind { +entry: + store i32 %in, i32 addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @f32_arg +; EG-CHECK: T{{[0-9]\.[XYZW]}}, KC0[2].Z +; SI-CHECK-LABEL: @f32_arg +; S_LOAD_DWORD s{{[0-9]}}, s[0:1], 11 +define void @f32_arg(float addrspace(1)* nocapture %out, float %in) nounwind { +entry: + store float %in, float addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v2i8_arg +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; SI-CHECK-LABEL: @v2i8_arg +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +define void @v2i8_arg(<2 x i8> addrspace(1)* %out, <2 x i8> %in) { +entry: + store <2 x i8> %in, <2 x i8> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @v2i16_arg +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; SI-CHECK-LABEL: @v2i16_arg +; SI-CHECK-DAG: BUFFER_LOAD_USHORT +; SI-CHECK-DAG: BUFFER_LOAD_USHORT +define void @v2i16_arg(<2 x i16> addrspace(1)* %out, <2 x i16> %in) { +entry: + store <2 x i16> %in, <2 x i16> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @v2i32_arg +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W +; SI-CHECK-LABEL: @v2i32_arg +; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 11 +define void @v2i32_arg(<2 x i32> addrspace(1)* nocapture %out, <2 x i32> %in) nounwind { +entry: + store <2 x i32> %in, <2 x i32> addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v2f32_arg +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].X +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[2].W +; SI-CHECK-LABEL: @v2f32_arg +; SI-CHECK: S_LOAD_DWORDX2 s{{\[[0-9]:[0-9]\]}}, s[0:1], 11 +define void @v2f32_arg(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) nounwind { +entry: + store <2 x float> %in, <2 x float> addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v3i8_arg +; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 40 +; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 41 +; VTX_READ_8 T{{[0-9]}}.X, T{{[0-9]}}.X, 42 +; SI-CHECK-LABEL: @v3i8_arg +define void @v3i8_arg(<3 x i8> addrspace(1)* nocapture %out, <3 x i8> %in) nounwind { +entry: + store <3 x i8> %in, <3 x i8> addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v3i16_arg +; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 44 +; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 46 +; VTX_READ_16 T{{[0-9]}}.X, T{{[0-9]}}.X, 48 +; SI-CHECK-LABEL: @v3i16_arg +define void @v3i16_arg(<3 x i16> addrspace(1)* nocapture %out, <3 x i16> %in) nounwind { +entry: + store <3 x i16> %in, <3 x i16> addrspace(1)* %out, align 4 + ret void +} +; EG-CHECK-LABEL: @v3i32_arg +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; SI-CHECK-LABEL: @v3i32_arg +; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 13 +define void @v3i32_arg(<3 x i32> addrspace(1)* nocapture %out, <3 x i32> %in) nounwind { +entry: + store <3 x i32> %in, <3 x i32> addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v3f32_arg +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; SI-CHECK-LABEL: @v3f32_arg +; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 13 +define void @v3f32_arg(<3 x float> addrspace(1)* nocapture %out, <3 x float> %in) nounwind { +entry: + store <3 x float> %in, <3 x float> addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v4i8_arg +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; SI-CHECK-LABEL: @v4i8_arg +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +define void @v4i8_arg(<4 x i8> addrspace(1)* %out, <4 x i8> %in) { +entry: + store <4 x i8> %in, <4 x i8> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @v4i16_arg +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; SI-CHECK-LABEL: @v4i16_arg +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +define void @v4i16_arg(<4 x i16> addrspace(1)* %out, <4 x i16> %in) { +entry: + store <4 x i16> %in, <4 x i16> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @v4i32_arg +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X +; SI-CHECK-LABEL: @v4i32_arg +; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 13 +define void @v4i32_arg(<4 x i32> addrspace(1)* nocapture %out, <4 x i32> %in) nounwind { +entry: + store <4 x i32> %in, <4 x i32> addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v4f32_arg +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[3].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].X +; SI-CHECK-LABEL: @v4f32_arg +; SI-CHECK: S_LOAD_DWORDX4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 13 +define void @v4f32_arg(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) nounwind { +entry: + store <4 x float> %in, <4 x float> addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v8i8_arg +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; SI-CHECK-LABEL: @v8i8_arg +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +define void @v8i8_arg(<8 x i8> addrspace(1)* %out, <8 x i8> %in) { +entry: + store <8 x i8> %in, <8 x i8> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @v8i16_arg +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; SI-CHECK-LABEL: @v8i16_arg +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +define void @v8i16_arg(<8 x i16> addrspace(1)* %out, <8 x i16> %in) { +entry: + store <8 x i16> %in, <8 x i16> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @v8i32_arg +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X +; SI-CHECK-LABEL: @v8i32_arg +; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 17 +define void @v8i32_arg(<8 x i32> addrspace(1)* nocapture %out, <8 x i32> %in) nounwind { +entry: + store <8 x i32> %in, <8 x i32> addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v8f32_arg +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[4].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].X +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[5].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].X +; SI-CHECK-LABEL: @v8f32_arg +; SI-CHECK: S_LOAD_DWORDX8 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 17 +define void @v8f32_arg(<8 x float> addrspace(1)* nocapture %out, <8 x float> %in) nounwind { +entry: + store <8 x float> %in, <8 x float> addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v16i8_arg +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; EG-CHECK: VTX_READ_8 +; SI-CHECK-LABEL: @v16i8_arg +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +define void @v16i8_arg(<16 x i8> addrspace(1)* %out, <16 x i8> %in) { +entry: + store <16 x i8> %in, <16 x i8> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @v16i16_arg +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; EG-CHECK: VTX_READ_16 +; SI-CHECK-LABEL: @v16i16_arg +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +define void @v16i16_arg(<16 x i16> addrspace(1)* %out, <16 x i16> %in) { +entry: + store <16 x i16> %in, <16 x i16> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @v16i32_arg +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X +; SI-CHECK-LABEL: @v16i32_arg +; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 25 +define void @v16i32_arg(<16 x i32> addrspace(1)* nocapture %out, <16 x i32> %in) nounwind { +entry: + store <16 x i32> %in, <16 x i32> addrspace(1)* %out, align 4 + ret void +} + +; EG-CHECK-LABEL: @v16f32_arg +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[6].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].X +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[7].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].X +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[8].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].X +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Y +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].Z +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[9].W +; EG-CHECK-DAG: T{{[0-9]\.[XYZW]}}, KC0[10].X +; SI-CHECK-LABEL: @v16f32_arg +; SI-CHECK: S_LOAD_DWORDX16 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 25 +define void @v16f32_arg(<16 x float> addrspace(1)* nocapture %out, <16 x float> %in) nounwind { +entry: + store <16 x float> %in, <16 x float> addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/R600/lds-output-queue.ll b/test/CodeGen/R600/lds-output-queue.ll new file mode 100644 index 000000000000..63a4332d3c41 --- /dev/null +++ b/test/CodeGen/R600/lds-output-queue.ll @@ -0,0 +1,99 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s +; +; This test checks that the lds input queue will is empty at the end of +; the ALU clause. + +; CHECK-LABEL: @lds_input_queue +; CHECK: LDS_READ_RET * OQAP +; CHECK-NOT: ALU clause +; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP + +@local_mem = internal addrspace(3) unnamed_addr global [2 x i32] [i32 1, i32 2], align 4 + +define void @lds_input_queue(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %index) { +entry: + %0 = getelementptr inbounds [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index + %1 = load i32 addrspace(3)* %0 + call void @llvm.AMDGPU.barrier.local() + + ; This will start a new clause for the vertex fetch + %2 = load i32 addrspace(1)* %in + %3 = add i32 %1, %2 + store i32 %3, i32 addrspace(1)* %out + ret void +} + +declare void @llvm.AMDGPU.barrier.local() + +; The machine scheduler does not do proper alias analysis and assumes that +; loads from global values (Note that a global value is different that a +; value from global memory. A global value is a value that is declared +; outside of a function, it can reside in any address space) alias with +; all other loads. +; +; This is a problem for scheduling the reads from the local data share (lds). +; These reads are implemented using two instructions. The first copies the +; data from lds into the lds output queue, and the second moves the data from +; the input queue into main memory. These two instructions don't have to be +; scheduled one after the other, but they do need to be scheduled in the same +; clause. The aliasing problem mentioned above causes problems when there is a +; load from global memory which immediately follows a load from a global value that +; has been declared in the local memory space: +; +; %0 = getelementptr inbounds [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index +; %1 = load i32 addrspace(3)* %0 +; %2 = load i32 addrspace(1)* %in +; +; The instruction selection phase will generate ISA that looks like this: +; %OQAP = LDS_READ_RET +; %vreg0 = MOV %OQAP +; %vreg1 = VTX_READ_32 +; %vreg2 = ADD_INT %vreg1, %vreg0 +; +; The bottom scheduler will schedule the two ALU instructions first: +; +; UNSCHEDULED: +; %OQAP = LDS_READ_RET +; %vreg1 = VTX_READ_32 +; +; SCHEDULED: +; +; vreg0 = MOV %OQAP +; vreg2 = ADD_INT %vreg1, %vreg2 +; +; The lack of proper aliasing results in the local memory read (LDS_READ_RET) +; to consider the global memory read (VTX_READ_32) has a chain dependency, so +; the global memory read will always be scheduled first. This will give us a +; final program which looks like this: +; +; Alu clause: +; %OQAP = LDS_READ_RET +; VTX clause: +; %vreg1 = VTX_READ_32 +; Alu clause: +; vreg0 = MOV %OQAP +; vreg2 = ADD_INT %vreg1, %vreg2 +; +; This is an illegal program because the OQAP def and use know occur in +; different ALU clauses. +; +; This test checks this scenario and makes sure it doesn't result in an +; illegal program. For now, we have fixed this issue by merging the +; LDS_READ_RET and MOV together during instruction selection and then +; expanding them after scheduling. Once the scheduler has better alias +; analysis, we should be able to keep these instructions sparate before +; scheduling. +; +; CHECK-LABEL: @local_global_alias +; CHECK: LDS_READ_RET +; CHECK-NOT: ALU clause +; CHECK MOV * T{{[0-9]\.[XYZW]}}, OQAP +define void @local_global_alias(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +entry: + %0 = getelementptr inbounds [2 x i32] addrspace(3)* @local_mem, i32 0, i32 0 + %1 = load i32 addrspace(3)* %0 + %2 = load i32 addrspace(1)* %in + %3 = add i32 %2, %1 + store i32 %3, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/lds-size.ll b/test/CodeGen/R600/lds-size.ll new file mode 100644 index 000000000000..2185180fd83f --- /dev/null +++ b/test/CodeGen/R600/lds-size.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; This test makes sure we do not double count global values when they are +; used in different basic blocks. + +; CHECK-LABEL: @test +; CHECK: .long 166120 +; CHECK-NEXT: .long 1 +@lds = internal addrspace(3) unnamed_addr global i32 zeroinitializer, align 4 + +define void @test(i32 addrspace(1)* %out, i32 %cond) { +entry: + %0 = icmp eq i32 %cond, 0 + br i1 %0, label %if, label %else + +if: + store i32 1, i32 addrspace(3)* @lds + br label %endif + +else: + store i32 2, i32 addrspace(3)* @lds + br label %endif + +endif: + ret void +} diff --git a/test/CodeGen/R600/lit.local.cfg b/test/CodeGen/R600/lit.local.cfg index 36ee493e5945..2d8930ad0e88 100644 --- a/test/CodeGen/R600/lit.local.cfg +++ b/test/CodeGen/R600/lit.local.cfg @@ -1,13 +1,3 @@ -config.suffixes = ['.ll', '.c', '.cpp'] - -def getRoot(config): - if not config.parent: - return config - return getRoot(config.parent) - -root = getRoot(config) - -targets = set(root.targets_to_build.split()) +targets = set(config.root.targets_to_build.split()) if not 'R600' in targets: config.unsupported = True - diff --git a/test/CodeGen/R600/literals.ll b/test/CodeGen/R600/literals.ll index 21e5d4c4de9a..47191e0a27fb 100644 --- a/test/CodeGen/R600/literals.ll +++ b/test/CodeGen/R600/literals.ll @@ -2,12 +2,13 @@ ; Test using an integer literal constant. ; Generated ASM should be: -; ADD_INT REG literal.x, 5 +; ADD_INT KC0[2].Z literal.x, 5 ; or -; ADD_INT literal.x REG, 5 +; ADD_INT literal.x KC0[2].Z, 5 ; CHECK: @i32_literal -; CHECK: ADD_INT * {{[A-Z0-9,. ]*}}literal.x +; CHECK: ADD_INT {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x +; CHECK-NEXT: LSHR ; CHECK-NEXT: 5 define void @i32_literal(i32 addrspace(1)* %out, i32 %in) { entry: @@ -18,12 +19,13 @@ entry: ; Test using a float literal constant. ; Generated ASM should be: -; ADD REG literal.x, 5.0 +; ADD KC0[2].Z literal.x, 5.0 ; or -; ADD literal.x REG, 5.0 +; ADD literal.x KC0[2].Z, 5.0 ; CHECK: @float_literal -; CHECK: ADD * {{[A-Z0-9,. ]*}}literal.x +; CHECK: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.0 define void @float_literal(float addrspace(1)* %out, float %in) { entry: @@ -32,168 +34,31 @@ entry: ret void } -; CHECK: @main -; CHECK: -2147483648 -; CHECK-NEXT-NOT: -2147483648 +; Make sure inline literals are folded into REG_SEQUENCE instructions. +; CHECK: @inline_literal_reg_sequence +; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0 +; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0 +; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0 +; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0 -define void @main() #0 { -main_body: - %0 = call float @llvm.R600.load.input(i32 4) - %1 = call float @llvm.R600.load.input(i32 5) - %2 = call float @llvm.R600.load.input(i32 6) - %3 = call float @llvm.R600.load.input(i32 7) - %4 = call float @llvm.R600.load.input(i32 8) - %5 = call float @llvm.R600.load.input(i32 9) - %6 = call float @llvm.R600.load.input(i32 10) - %7 = call float @llvm.R600.load.input(i32 11) - %8 = call float @llvm.R600.load.input(i32 12) - %9 = call float @llvm.R600.load.input(i32 13) - %10 = call float @llvm.R600.load.input(i32 14) - %11 = call float @llvm.R600.load.input(i32 15) - %12 = load <4 x float> addrspace(8)* null - %13 = extractelement <4 x float> %12, i32 0 - %14 = fsub float -0.000000e+00, %13 - %15 = fadd float %0, %14 - %16 = load <4 x float> addrspace(8)* null - %17 = extractelement <4 x float> %16, i32 1 - %18 = fsub float -0.000000e+00, %17 - %19 = fadd float %1, %18 - %20 = load <4 x float> addrspace(8)* null - %21 = extractelement <4 x float> %20, i32 2 - %22 = fsub float -0.000000e+00, %21 - %23 = fadd float %2, %22 - %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %25 = extractelement <4 x float> %24, i32 0 - %26 = fmul float %25, %0 - %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %28 = extractelement <4 x float> %27, i32 1 - %29 = fmul float %28, %0 - %30 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %31 = extractelement <4 x float> %30, i32 2 - %32 = fmul float %31, %0 - %33 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %34 = extractelement <4 x float> %33, i32 3 - %35 = fmul float %34, %0 - %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) - %37 = extractelement <4 x float> %36, i32 0 - %38 = fmul float %37, %1 - %39 = fadd float %38, %26 - %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) - %41 = extractelement <4 x float> %40, i32 1 - %42 = fmul float %41, %1 - %43 = fadd float %42, %29 - %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) - %45 = extractelement <4 x float> %44, i32 2 - %46 = fmul float %45, %1 - %47 = fadd float %46, %32 - %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) - %49 = extractelement <4 x float> %48, i32 3 - %50 = fmul float %49, %1 - %51 = fadd float %50, %35 - %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) - %53 = extractelement <4 x float> %52, i32 0 - %54 = fmul float %53, %2 - %55 = fadd float %54, %39 - %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) - %57 = extractelement <4 x float> %56, i32 1 - %58 = fmul float %57, %2 - %59 = fadd float %58, %43 - %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) - %61 = extractelement <4 x float> %60, i32 2 - %62 = fmul float %61, %2 - %63 = fadd float %62, %47 - %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) - %65 = extractelement <4 x float> %64, i32 3 - %66 = fmul float %65, %2 - %67 = fadd float %66, %51 - %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) - %69 = extractelement <4 x float> %68, i32 0 - %70 = fmul float %69, %3 - %71 = fadd float %70, %55 - %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) - %73 = extractelement <4 x float> %72, i32 1 - %74 = fmul float %73, %3 - %75 = fadd float %74, %59 - %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) - %77 = extractelement <4 x float> %76, i32 2 - %78 = fmul float %77, %3 - %79 = fadd float %78, %63 - %80 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) - %81 = extractelement <4 x float> %80, i32 3 - %82 = fmul float %81, %3 - %83 = fadd float %82, %67 - %84 = insertelement <4 x float> undef, float %15, i32 0 - %85 = insertelement <4 x float> %84, float %19, i32 1 - %86 = insertelement <4 x float> %85, float %23, i32 2 - %87 = insertelement <4 x float> %86, float 0.000000e+00, i32 3 - %88 = insertelement <4 x float> undef, float %15, i32 0 - %89 = insertelement <4 x float> %88, float %19, i32 1 - %90 = insertelement <4 x float> %89, float %23, i32 2 - %91 = insertelement <4 x float> %90, float 0.000000e+00, i32 3 - %92 = call float @llvm.AMDGPU.dp4(<4 x float> %87, <4 x float> %91) - %93 = call float @fabs(float %92) - %94 = call float @llvm.AMDGPU.rsq(float %93) - %95 = fmul float %15, %94 - %96 = fmul float %19, %94 - %97 = fmul float %23, %94 - %98 = insertelement <4 x float> undef, float %4, i32 0 - %99 = insertelement <4 x float> %98, float %5, i32 1 - %100 = insertelement <4 x float> %99, float %6, i32 2 - %101 = insertelement <4 x float> %100, float 0.000000e+00, i32 3 - %102 = insertelement <4 x float> undef, float %4, i32 0 - %103 = insertelement <4 x float> %102, float %5, i32 1 - %104 = insertelement <4 x float> %103, float %6, i32 2 - %105 = insertelement <4 x float> %104, float 0.000000e+00, i32 3 - %106 = call float @llvm.AMDGPU.dp4(<4 x float> %101, <4 x float> %105) - %107 = call float @fabs(float %106) - %108 = call float @llvm.AMDGPU.rsq(float %107) - %109 = fmul float %4, %108 - %110 = fmul float %5, %108 - %111 = fmul float %6, %108 - %112 = insertelement <4 x float> undef, float %95, i32 0 - %113 = insertelement <4 x float> %112, float %96, i32 1 - %114 = insertelement <4 x float> %113, float %97, i32 2 - %115 = insertelement <4 x float> %114, float 0.000000e+00, i32 3 - %116 = insertelement <4 x float> undef, float %109, i32 0 - %117 = insertelement <4 x float> %116, float %110, i32 1 - %118 = insertelement <4 x float> %117, float %111, i32 2 - %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3 - %120 = call float @llvm.AMDGPU.dp4(<4 x float> %115, <4 x float> %119) - %121 = fsub float -0.000000e+00, %120 - %122 = fcmp uge float 0.000000e+00, %121 - %123 = select i1 %122, float 0.000000e+00, float %121 - %124 = insertelement <4 x float> undef, float %8, i32 0 - %125 = insertelement <4 x float> %124, float %9, i32 1 - %126 = insertelement <4 x float> %125, float 5.000000e-01, i32 2 - %127 = insertelement <4 x float> %126, float 1.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %127, i32 60, i32 1) - %128 = insertelement <4 x float> undef, float %71, i32 0 - %129 = insertelement <4 x float> %128, float %75, i32 1 - %130 = insertelement <4 x float> %129, float %79, i32 2 - %131 = insertelement <4 x float> %130, float %83, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %131, i32 0, i32 2) - %132 = insertelement <4 x float> undef, float %123, i32 0 - %133 = insertelement <4 x float> %132, float %96, i32 1 - %134 = insertelement <4 x float> %133, float %97, i32 2 - %135 = insertelement <4 x float> %134, float 0.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %135, i32 1, i32 2) +define void @inline_literal_reg_sequence(<4 x i32> addrspace(1)* %out) { +entry: + store <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> addrspace(1)* %out ret void } -; Function Attrs: readnone -declare float @llvm.R600.load.input(i32) #1 +; CHECK: @inline_literal_dot4 +; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0 +; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0 +; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0 +; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0 +define void @inline_literal_dot4(float addrspace(1)* %out) { +entry: + %0 = call float @llvm.AMDGPU.dp4(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>) + store float %0, float addrspace(1)* %out + ret void +} -; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 -; Function Attrs: readonly -declare float @fabs(float) #2 - -; Function Attrs: readnone -declare float @llvm.AMDGPU.rsq(float) #1 - -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } -attributes #2 = { readonly } diff --git a/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll b/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll new file mode 100644 index 000000000000..8d3c9ca22300 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: GROUP_BARRIER + +define void @test(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tidig.x() + %1 = getelementptr i32 addrspace(1)* %out, i32 %0 + store i32 %0, i32 addrspace(1)* %1 + call void @llvm.AMDGPU.barrier.local() + %2 = call i32 @llvm.r600.read.local.size.x() + %3 = sub i32 %2, 1 + %4 = sub i32 %3, %0 + %5 = getelementptr i32 addrspace(1)* %out, i32 %4 + %6 = load i32 addrspace(1)* %5 + store i32 %6, i32 addrspace(1)* %1 + ret void +} + +declare i32 @llvm.r600.read.tidig.x() #0 +declare void @llvm.AMDGPU.barrier.local() +declare i32 @llvm.r600.read.local.size.x() #0 + +attributes #0 = { readnone } diff --git a/test/CodeGen/R600/llvm.AMDGPU.cube.ll b/test/CodeGen/R600/llvm.AMDGPU.cube.ll new file mode 100644 index 000000000000..110bbfde68b9 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.cube.ll @@ -0,0 +1,59 @@ + +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @cube +; CHECK: CUBE T{{[0-9]}}.X +; CHECK: CUBE T{{[0-9]}}.Y +; CHECK: CUBE T{{[0-9]}}.Z +; CHECK: CUBE * T{{[0-9]}}.W +define void @cube() #0 { +main_body: + %0 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %1 = extractelement <4 x float> %0, i32 3 + %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %3 = extractelement <4 x float> %2, i32 0 + %4 = fdiv float %3, %1 + %5 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %6 = extractelement <4 x float> %5, i32 1 + %7 = fdiv float %6, %1 + %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %9 = extractelement <4 x float> %8, i32 2 + %10 = fdiv float %9, %1 + %11 = insertelement <4 x float> undef, float %4, i32 0 + %12 = insertelement <4 x float> %11, float %7, i32 1 + %13 = insertelement <4 x float> %12, float %10, i32 2 + %14 = insertelement <4 x float> %13, float 1.000000e+00, i32 3 + %15 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %14) + %16 = extractelement <4 x float> %15, i32 0 + %17 = extractelement <4 x float> %15, i32 1 + %18 = extractelement <4 x float> %15, i32 2 + %19 = extractelement <4 x float> %15, i32 3 + %20 = call float @fabs(float %18) + %21 = fdiv float 1.000000e+00, %20 + %22 = fmul float %16, %21 + %23 = fadd float %22, 1.500000e+00 + %24 = fmul float %17, %21 + %25 = fadd float %24, 1.500000e+00 + %26 = insertelement <4 x float> undef, float %25, i32 0 + %27 = insertelement <4 x float> %26, float %23, i32 1 + %28 = insertelement <4 x float> %27, float %19, i32 2 + %29 = insertelement <4 x float> %28, float %25, i32 3 + %30 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %29, i32 16, i32 0, i32 4) + call void @llvm.R600.store.swizzle(<4 x float> %30, i32 0, i32 0) + ret void +} + +; Function Attrs: readnone +declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #1 + +; Function Attrs: readnone +declare float @fabs(float) #1 + +; Function Attrs: readnone +declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { readnone } + diff --git a/test/CodeGen/R600/llvm.AMDGPU.imax.ll b/test/CodeGen/R600/llvm.AMDGPU.imax.ll new file mode 100644 index 000000000000..1336f4eeeedd --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.imax.ll @@ -0,0 +1,21 @@ +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +;CHECK: V_MAX_I32_e32 + +define void @main(i32 %p0, i32 %p1) #0 { +main_body: + %0 = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %p1) + %1 = bitcast i32 %0 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1) + ret void +} + +; Function Attrs: readnone +declare i32 @llvm.AMDGPU.imax(i32, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { readnone } + +!0 = metadata !{metadata !"const", null, i32 1} diff --git a/test/CodeGen/R600/llvm.AMDGPU.imin.ll b/test/CodeGen/R600/llvm.AMDGPU.imin.ll new file mode 100644 index 000000000000..3435ea471e47 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.imin.ll @@ -0,0 +1,21 @@ +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +;CHECK: V_MIN_I32_e32 + +define void @main(i32 %p0, i32 %p1) #0 { +main_body: + %0 = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %p1) + %1 = bitcast i32 %0 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1) + ret void +} + +; Function Attrs: readnone +declare i32 @llvm.AMDGPU.imin(i32, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { readnone } + +!0 = metadata !{metadata !"const", null, i32 1} diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll b/test/CodeGen/R600/llvm.AMDGPU.mul.ll index cc0732b3fffd..83b56a5029d3 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.mul.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.mul.ll @@ -2,16 +2,16 @@ ;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.R600.load.input(i32 1) +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 + %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = call float @llvm.AMDGPU.mul( float %r0, float %r1) - call void @llvm.AMDGPU.store.output(float %r2, i32 0) + %vec = insertelement <4 x float> undef, float %r2, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare float @llvm.R600.load.input(i32) readnone - -declare void @llvm.AMDGPU.store.output(float, i32) - declare float @llvm.AMDGPU.mul(float ,float ) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="0" }
\ No newline at end of file diff --git a/test/CodeGen/R600/llvm.AMDGPU.tex.ll b/test/CodeGen/R600/llvm.AMDGPU.tex.ll index 74331fa26934..aac014bde456 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.tex.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.tex.ll @@ -1,21 +1,21 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 1 -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 2 -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 3 -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 4 -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 5 -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 6 -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 7 -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 8 -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 9 -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 10 -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 11 -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 12 -;CHECK: TEX_SAMPLE_CT{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 13 -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 14 -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 15 -;CHECK: TEX_SAMPLET{{[0-9]+\.XYZW, T[0-9]+\.XYZW}}, 0, 0, 16 +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:UUNN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:UUNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYYW}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYYZ}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %addr = load <4 x float> addrspace(1)* %in diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll index ff22a6919677..e6bb2c4e9455 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll @@ -1,16 +1,16 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -;CHECK: TRUNC * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: @amdgpu_trunc +; R600-CHECK: TRUNC T{{[0-9]+\.[XYZW]}}, KC0[2].Z +; SI-CHECK: @amdgpu_trunc +; SI-CHECK: V_TRUNC_F32 -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.AMDGPU.trunc( float %r0) - call void @llvm.AMDGPU.store.output(float %r1, i32 0) - ret void +define void @amdgpu_trunc(float addrspace(1)* %out, float %x) { +entry: + %0 = call float @llvm.AMDGPU.trunc(float %x) + store float %0, float addrspace(1)* %out + ret void } -declare float @llvm.R600.load.input(i32) readnone - -declare void @llvm.AMDGPU.store.output(float, i32) - declare float @llvm.AMDGPU.trunc(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.umax.ll b/test/CodeGen/R600/llvm.AMDGPU.umax.ll new file mode 100644 index 000000000000..4cfa133208e3 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.umax.ll @@ -0,0 +1,21 @@ +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +;CHECK: V_MAX_U32_e32 + +define void @main(i32 %p0, i32 %p1) #0 { +main_body: + %0 = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %p1) + %1 = bitcast i32 %0 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1) + ret void +} + +; Function Attrs: readnone +declare i32 @llvm.AMDGPU.umax(i32, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { readnone } + +!0 = metadata !{metadata !"const", null, i32 1} diff --git a/test/CodeGen/R600/llvm.AMDGPU.umin.ll b/test/CodeGen/R600/llvm.AMDGPU.umin.ll new file mode 100644 index 000000000000..14af0519bc90 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.umin.ll @@ -0,0 +1,21 @@ +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +;CHECK: V_MIN_U32_e32 + +define void @main(i32 %p0, i32 %p1) #0 { +main_body: + %0 = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %p1) + %1 = bitcast i32 %0 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1) + ret void +} + +; Function Attrs: readnone +declare i32 @llvm.AMDGPU.umin(i32, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { readnone } + +!0 = metadata !{metadata !"const", null, i32 1} diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll index e45722c3fa67..0438eccc8862 100644 --- a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll +++ b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: S_MOV_B32 ;CHECK-NEXT: V_INTERP_MOV_F32 diff --git a/test/CodeGen/R600/llvm.SI.imageload.ll b/test/CodeGen/R600/llvm.SI.imageload.ll new file mode 100644 index 000000000000..59e00f01c96b --- /dev/null +++ b/test/CodeGen/R600/llvm.SI.imageload.ll @@ -0,0 +1,131 @@ +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +;CHECK-DAG: IMAGE_LOAD {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1 +;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0 +;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 2, 0, 0, 0 +;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 1, 0, 0, 0 +;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 4, 0, 0, 0 +;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 8, 0, 0, 0 +;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0 +;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1 +;CHECK-DAG: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0 +;CHECK-DAG: IMAGE_LOAD_MIP {{v[0-9]+}}, 8, 0, 0, -1 + +define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { + %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 + %v2 = insertelement <4 x i32> undef, i32 %a1, i32 1 + %v3 = insertelement <4 x i32> undef, i32 %a1, i32 2 + %v4 = insertelement <4 x i32> undef, i32 %a1, i32 3 + %v5 = insertelement <4 x i32> undef, i32 %a2, i32 0 + %v6 = insertelement <4 x i32> undef, i32 %a2, i32 1 + %v10 = insertelement <4 x i32> undef, i32 %a3, i32 1 + %v11 = insertelement <4 x i32> undef, i32 %a3, i32 2 + %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2 + %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3 + %res1 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v1, + <32 x i8> undef, i32 1) + %res2 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v2, + <32 x i8> undef, i32 2) + %res3 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v3, + <32 x i8> undef, i32 3) + %res4 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v4, + <32 x i8> undef, i32 4) + %res5 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v5, + <32 x i8> undef, i32 5) + %res6 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v6, + <32 x i8> undef, i32 6) + %res10 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v10, + <32 x i8> undef, i32 10) + %res11 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v11, + <32 x i8> undef, i32 11) + %res15 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v15, + <32 x i8> undef, i32 15) + %res16 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v16, + <32 x i8> undef, i32 16) + %e1 = extractelement <4 x i32> %res1, i32 0 + %e2 = extractelement <4 x i32> %res2, i32 1 + %e3 = extractelement <4 x i32> %res3, i32 2 + %e4 = extractelement <4 x i32> %res4, i32 3 + %t0 = extractelement <4 x i32> %res5, i32 0 + %t1 = extractelement <4 x i32> %res5, i32 1 + %e5 = add i32 %t0, %t1 + %t2 = extractelement <4 x i32> %res6, i32 0 + %t3 = extractelement <4 x i32> %res6, i32 2 + %e6 = add i32 %t2, %t3 + %t10 = extractelement <4 x i32> %res10, i32 2 + %t11 = extractelement <4 x i32> %res10, i32 3 + %e10 = add i32 %t10, %t11 + %t12 = extractelement <4 x i32> %res11, i32 0 + %t13 = extractelement <4 x i32> %res11, i32 1 + %t14 = extractelement <4 x i32> %res11, i32 2 + %t15 = add i32 %t12, %t13 + %e11 = add i32 %t14, %t15 + %t28 = extractelement <4 x i32> %res15, i32 0 + %t29 = extractelement <4 x i32> %res15, i32 1 + %t30 = extractelement <4 x i32> %res15, i32 2 + %t31 = extractelement <4 x i32> %res15, i32 3 + %t32 = add i32 %t28, %t29 + %t33 = add i32 %t30, %t31 + %e15 = add i32 %t32, %t33 + %e16 = extractelement <4 x i32> %res16, i32 3 + %s1 = add i32 %e1, %e2 + %s2 = add i32 %s1, %e3 + %s3 = add i32 %s2, %e4 + %s4 = add i32 %s3, %e5 + %s5 = add i32 %s4, %e6 + %s9 = add i32 %s5, %e10 + %s10 = add i32 %s9, %e11 + %s14 = add i32 %s10, %e15 + %s15 = add i32 %s14, %e16 + %s16 = bitcast i32 %s15 to float + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s16, float %s16, float %s16, float %s16) + ret void +} + +; Test that ccordinates are stored in vgprs and not sgprs +; CHECK: vgpr_coords +; CHECK: IMAGE_LOAD_MIP {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}} +define void @vgpr_coords(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +main_body: + %20 = getelementptr float addrspace(2)* addrspace(2)* %0, i32 0 + %21 = load float addrspace(2)* addrspace(2)* %20, !tbaa !2 + %22 = getelementptr float addrspace(2)* %21, i32 0 + %23 = load float addrspace(2)* %22, !tbaa !2, !invariant.load !1 + %24 = getelementptr float addrspace(2)* %21, i32 1 + %25 = load float addrspace(2)* %24, !tbaa !2, !invariant.load !1 + %26 = getelementptr float addrspace(2)* %21, i32 4 + %27 = load float addrspace(2)* %26, !tbaa !2, !invariant.load !1 + %28 = getelementptr <32 x i8> addrspace(2)* %2, i32 0 + %29 = load <32 x i8> addrspace(2)* %28, !tbaa !2 + %30 = bitcast float %27 to i32 + %31 = bitcast float %23 to i32 + %32 = bitcast float %25 to i32 + %33 = insertelement <4 x i32> undef, i32 %31, i32 0 + %34 = insertelement <4 x i32> %33, i32 %32, i32 1 + %35 = insertelement <4 x i32> %34, i32 %30, i32 2 + %36 = insertelement <4 x i32> %35, i32 undef, i32 3 + %37 = call <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32> %36, <32 x i8> %29, i32 2) + %38 = extractelement <4 x i32> %37, i32 0 + %39 = extractelement <4 x i32> %37, i32 1 + %40 = extractelement <4 x i32> %37, i32 2 + %41 = extractelement <4 x i32> %37, i32 3 + %42 = bitcast i32 %38 to float + %43 = bitcast i32 %39 to float + %44 = bitcast i32 %40 to float + %45 = bitcast i32 %41 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %42, float %43, float %44, float %45) + ret void +} + +declare <4 x i32> @llvm.SI.imageload.(<4 x i32>, <32 x i8>, i32) readnone +; Function Attrs: nounwind readnone +declare <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32>, <32 x i8>, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { nounwind readnone } + +!0 = metadata !{metadata !"const", null} +!1 = metadata !{} +!2 = metadata !{metadata !0, metadata !0, i64 0, i32 1} diff --git a/test/CodeGen/R600/llvm.SI.resinfo.ll b/test/CodeGen/R600/llvm.SI.resinfo.ll new file mode 100644 index 000000000000..af3afc1e1d92 --- /dev/null +++ b/test/CodeGen/R600/llvm.SI.resinfo.ll @@ -0,0 +1,110 @@ +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1 +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v[0-9]+}}, 2, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v[0-9]+}}, 1, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v[0-9]+}}, 4, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v[0-9]+}}, 8, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 9, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 6, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 10, 0, 0, -1 +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1 +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 11, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 13, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 14, 0, 0, 0 +;CHECK: IMAGE_GET_RESINFO {{v[0-9]+}}, 8, 0, 0, -1 + +define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, + i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15, i32 %a16) { + %res1 = call <4 x i32> @llvm.SI.resinfo(i32 %a1, <32 x i8> undef, i32 1) + %res2 = call <4 x i32> @llvm.SI.resinfo(i32 %a2, <32 x i8> undef, i32 2) + %res3 = call <4 x i32> @llvm.SI.resinfo(i32 %a3, <32 x i8> undef, i32 3) + %res4 = call <4 x i32> @llvm.SI.resinfo(i32 %a4, <32 x i8> undef, i32 4) + %res5 = call <4 x i32> @llvm.SI.resinfo(i32 %a5, <32 x i8> undef, i32 5) + %res6 = call <4 x i32> @llvm.SI.resinfo(i32 %a6, <32 x i8> undef, i32 6) + %res7 = call <4 x i32> @llvm.SI.resinfo(i32 %a7, <32 x i8> undef, i32 7) + %res8 = call <4 x i32> @llvm.SI.resinfo(i32 %a8, <32 x i8> undef, i32 8) + %res9 = call <4 x i32> @llvm.SI.resinfo(i32 %a9, <32 x i8> undef, i32 9) + %res10 = call <4 x i32> @llvm.SI.resinfo(i32 %a10, <32 x i8> undef, i32 10) + %res11 = call <4 x i32> @llvm.SI.resinfo(i32 %a11, <32 x i8> undef, i32 11) + %res12 = call <4 x i32> @llvm.SI.resinfo(i32 %a12, <32 x i8> undef, i32 12) + %res13 = call <4 x i32> @llvm.SI.resinfo(i32 %a13, <32 x i8> undef, i32 13) + %res14 = call <4 x i32> @llvm.SI.resinfo(i32 %a14, <32 x i8> undef, i32 14) + %res15 = call <4 x i32> @llvm.SI.resinfo(i32 %a15, <32 x i8> undef, i32 15) + %res16 = call <4 x i32> @llvm.SI.resinfo(i32 %a16, <32 x i8> undef, i32 16) + %e1 = extractelement <4 x i32> %res1, i32 0 + %e2 = extractelement <4 x i32> %res2, i32 1 + %e3 = extractelement <4 x i32> %res3, i32 2 + %e4 = extractelement <4 x i32> %res4, i32 3 + %t0 = extractelement <4 x i32> %res5, i32 0 + %t1 = extractelement <4 x i32> %res5, i32 1 + %e5 = add i32 %t0, %t1 + %t2 = extractelement <4 x i32> %res6, i32 0 + %t3 = extractelement <4 x i32> %res6, i32 2 + %e6 = add i32 %t2, %t3 + %t4 = extractelement <4 x i32> %res7, i32 0 + %t5 = extractelement <4 x i32> %res7, i32 3 + %e7 = add i32 %t4, %t5 + %t6 = extractelement <4 x i32> %res8, i32 1 + %t7 = extractelement <4 x i32> %res8, i32 2 + %e8 = add i32 %t6, %t7 + %t8 = extractelement <4 x i32> %res9, i32 1 + %t9 = extractelement <4 x i32> %res9, i32 3 + %e9 = add i32 %t8, %t9 + %t10 = extractelement <4 x i32> %res10, i32 2 + %t11 = extractelement <4 x i32> %res10, i32 3 + %e10 = add i32 %t10, %t11 + %t12 = extractelement <4 x i32> %res11, i32 0 + %t13 = extractelement <4 x i32> %res11, i32 1 + %t14 = extractelement <4 x i32> %res11, i32 2 + %t15 = add i32 %t12, %t13 + %e11 = add i32 %t14, %t15 + %t16 = extractelement <4 x i32> %res12, i32 0 + %t17 = extractelement <4 x i32> %res12, i32 1 + %t18 = extractelement <4 x i32> %res12, i32 3 + %t19 = add i32 %t16, %t17 + %e12 = add i32 %t18, %t19 + %t20 = extractelement <4 x i32> %res13, i32 0 + %t21 = extractelement <4 x i32> %res13, i32 2 + %t22 = extractelement <4 x i32> %res13, i32 3 + %t23 = add i32 %t20, %t21 + %e13 = add i32 %t22, %t23 + %t24 = extractelement <4 x i32> %res14, i32 1 + %t25 = extractelement <4 x i32> %res14, i32 2 + %t26 = extractelement <4 x i32> %res14, i32 3 + %t27 = add i32 %t24, %t25 + %e14 = add i32 %t26, %t27 + %t28 = extractelement <4 x i32> %res15, i32 0 + %t29 = extractelement <4 x i32> %res15, i32 1 + %t30 = extractelement <4 x i32> %res15, i32 2 + %t31 = extractelement <4 x i32> %res15, i32 3 + %t32 = add i32 %t28, %t29 + %t33 = add i32 %t30, %t31 + %e15 = add i32 %t32, %t33 + %e16 = extractelement <4 x i32> %res16, i32 3 + %s1 = add i32 %e1, %e2 + %s2 = add i32 %s1, %e3 + %s3 = add i32 %s2, %e4 + %s4 = add i32 %s3, %e5 + %s5 = add i32 %s4, %e6 + %s6 = add i32 %s5, %e7 + %s7 = add i32 %s6, %e8 + %s8 = add i32 %s7, %e9 + %s9 = add i32 %s8, %e10 + %s10 = add i32 %s9, %e11 + %s11 = add i32 %s10, %e12 + %s12 = add i32 %s11, %e13 + %s13 = add i32 %s12, %e14 + %s14 = add i32 %s13, %e15 + %s15 = add i32 %s14, %e16 + %s16 = bitcast i32 %s15 to float + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s16, float %s16, float %s16, float %s16) + ret void +} + +declare <4 x i32> @llvm.SI.resinfo(i32, <32 x i8>, i32) readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/llvm.SI.sample-masked.ll b/test/CodeGen/R600/llvm.SI.sample-masked.ll new file mode 100644 index 000000000000..e5e4ec4f0674 --- /dev/null +++ b/test/CodeGen/R600/llvm.SI.sample-masked.ll @@ -0,0 +1,93 @@ +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s + +; CHECK-LABEL: @v1 +; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 13 +define void @v1(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) + %2 = extractelement <4 x float> %1, i32 0 + %3 = extractelement <4 x float> %1, i32 2 + %4 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) + ret void +} + +; CHECK-LABEL: @v2 +; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 11 +define void @v2(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) + %2 = extractelement <4 x float> %1, i32 0 + %3 = extractelement <4 x float> %1, i32 1 + %4 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) + ret void +} + +; CHECK-LABEL: @v3 +; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 14 +define void @v3(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) + %2 = extractelement <4 x float> %1, i32 1 + %3 = extractelement <4 x float> %1, i32 2 + %4 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) + ret void +} + +; CHECK-LABEL: @v4 +; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 7 +define void @v4(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) + %2 = extractelement <4 x float> %1, i32 0 + %3 = extractelement <4 x float> %1, i32 1 + %4 = extractelement <4 x float> %1, i32 2 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) + ret void +} + +; CHECK-LABEL: @v5 +; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 10 +define void @v5(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) + %2 = extractelement <4 x float> %1, i32 1 + %3 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) + ret void +} + +; CHECK-LABEL: @v6 +; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 6 +define void @v6(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) + %2 = extractelement <4 x float> %1, i32 1 + %3 = extractelement <4 x float> %1, i32 2 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) + ret void +} + +; CHECK-LABEL: @v7 +; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 9 +define void @v7(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) + %2 = extractelement <4 x float> %1, i32 0 + %3 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) + ret void +} + +declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/llvm.SI.sample.ll b/test/CodeGen/R600/llvm.SI.sample.ll index de06354a5646..d41737c65927 100644 --- a/test/CodeGen/R600/llvm.SI.sample.ll +++ b/test/CodeGen/R600/llvm.SI.sample.ll @@ -1,21 +1,21 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15 -;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 3 -;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 2 -;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 1 -;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 4 -;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8 -;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 5 -;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 9 -;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 6 -;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 10 -;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 12 -;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7 -;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11 -;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13 -;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14 -;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8 +;CHECK-DAG: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 15 +;CHECK-DAG: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 3 +;CHECK-DAG: IMAGE_SAMPLE {{v[0-9]+}}, 2 +;CHECK-DAG: IMAGE_SAMPLE {{v[0-9]+}}, 1 +;CHECK-DAG: IMAGE_SAMPLE {{v[0-9]+}}, 4 +;CHECK-DAG: IMAGE_SAMPLE {{v[0-9]+}}, 8 +;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 5 +;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 9 +;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 6 +;CHECK-DAG: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 10 +;CHECK-DAG: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 12 +;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 7 +;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 11 +;CHECK-DAG: IMAGE_SAMPLE_C {{v\[[0-9]+:[0-9]+\]}}, 13 +;CHECK-DAG: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 14 +;CHECK-DAG: IMAGE_SAMPLE {{v[0-9]+}}, 8 define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 @@ -35,37 +35,37 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2 %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3 %res1 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v1, - <8 x i32> undef, <4 x i32> undef, i32 1) + <32 x i8> undef, <16 x i8> undef, i32 1) %res2 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v2, - <8 x i32> undef, <4 x i32> undef, i32 2) + <32 x i8> undef, <16 x i8> undef, i32 2) %res3 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v3, - <8 x i32> undef, <4 x i32> undef, i32 3) + <32 x i8> undef, <16 x i8> undef, i32 3) %res4 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v4, - <8 x i32> undef, <4 x i32> undef, i32 4) + <32 x i8> undef, <16 x i8> undef, i32 4) %res5 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v5, - <8 x i32> undef, <4 x i32> undef, i32 5) + <32 x i8> undef, <16 x i8> undef, i32 5) %res6 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v6, - <8 x i32> undef, <4 x i32> undef, i32 6) + <32 x i8> undef, <16 x i8> undef, i32 6) %res7 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v7, - <8 x i32> undef, <4 x i32> undef, i32 7) + <32 x i8> undef, <16 x i8> undef, i32 7) %res8 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v8, - <8 x i32> undef, <4 x i32> undef, i32 8) + <32 x i8> undef, <16 x i8> undef, i32 8) %res9 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v9, - <8 x i32> undef, <4 x i32> undef, i32 9) + <32 x i8> undef, <16 x i8> undef, i32 9) %res10 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v10, - <8 x i32> undef, <4 x i32> undef, i32 10) + <32 x i8> undef, <16 x i8> undef, i32 10) %res11 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v11, - <8 x i32> undef, <4 x i32> undef, i32 11) + <32 x i8> undef, <16 x i8> undef, i32 11) %res12 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v12, - <8 x i32> undef, <4 x i32> undef, i32 12) + <32 x i8> undef, <16 x i8> undef, i32 12) %res13 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v13, - <8 x i32> undef, <4 x i32> undef, i32 13) + <32 x i8> undef, <16 x i8> undef, i32 13) %res14 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v14, - <8 x i32> undef, <4 x i32> undef, i32 14) + <32 x i8> undef, <16 x i8> undef, i32 14) %res15 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v15, - <8 x i32> undef, <4 x i32> undef, i32 15) + <32 x i8> undef, <16 x i8> undef, i32 15) %res16 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v16, - <8 x i32> undef, <4 x i32> undef, i32 16) + <32 x i8> undef, <16 x i8> undef, i32 16) %e1 = extractelement <4 x float> %res1, i32 0 %e2 = extractelement <4 x float> %res2, i32 1 %e3 = extractelement <4 x float> %res3, i32 2 @@ -135,6 +135,23 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { ret void } -declare <4 x float> @llvm.SI.sample.(<4 x i32>, <8 x i32>, <4 x i32>, i32) readnone +; CHECK: @v1 +; CHECK: IMAGE_SAMPLE {{v\[[0-9]+:[0-9]+\]}}, 15 +define void @v1(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) + %2 = extractelement <4 x float> %1, i32 0 + %3 = extractelement <4 x float> %1, i32 1 + %4 = extractelement <4 x float> %1, i32 2 + %5 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %5) + ret void +} + + +declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone + +declare <4 x float> @llvm.SI.sample.(<4 x i32>, <32 x i8>, <16 x i8>, i32) readnone declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/llvm.SI.sampled.ll b/test/CodeGen/R600/llvm.SI.sampled.ll new file mode 100644 index 000000000000..21ac725ae039 --- /dev/null +++ b/test/CodeGen/R600/llvm.SI.sampled.ll @@ -0,0 +1,140 @@ +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +;CHECK-DAG: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 15 +;CHECK-DAG: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 3 +;CHECK-DAG: IMAGE_SAMPLE_D {{v[0-9]+}}, 2 +;CHECK-DAG: IMAGE_SAMPLE_D {{v[0-9]+}}, 1 +;CHECK-DAG: IMAGE_SAMPLE_D {{v[0-9]+}}, 4 +;CHECK-DAG: IMAGE_SAMPLE_D {{v[0-9]+}}, 8 +;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 5 +;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 9 +;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 6 +;CHECK-DAG: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 10 +;CHECK-DAG: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 12 +;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 7 +;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 11 +;CHECK-DAG: IMAGE_SAMPLE_C_D {{v\[[0-9]+:[0-9]+\]}}, 13 +;CHECK-DAG: IMAGE_SAMPLE_D {{v\[[0-9]+:[0-9]+\]}}, 14 +;CHECK-DAG: IMAGE_SAMPLE_D {{v[0-9]+}}, 8 + +define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { + %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 + %v2 = insertelement <4 x i32> undef, i32 %a1, i32 1 + %v3 = insertelement <4 x i32> undef, i32 %a1, i32 2 + %v4 = insertelement <4 x i32> undef, i32 %a1, i32 3 + %v5 = insertelement <4 x i32> undef, i32 %a2, i32 0 + %v6 = insertelement <4 x i32> undef, i32 %a2, i32 1 + %v7 = insertelement <4 x i32> undef, i32 %a2, i32 2 + %v8 = insertelement <4 x i32> undef, i32 %a2, i32 3 + %v9 = insertelement <4 x i32> undef, i32 %a3, i32 0 + %v10 = insertelement <4 x i32> undef, i32 %a3, i32 1 + %v11 = insertelement <4 x i32> undef, i32 %a3, i32 2 + %v12 = insertelement <4 x i32> undef, i32 %a3, i32 3 + %v13 = insertelement <4 x i32> undef, i32 %a4, i32 0 + %v14 = insertelement <4 x i32> undef, i32 %a4, i32 1 + %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2 + %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3 + %res1 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v1, + <32 x i8> undef, <16 x i8> undef, i32 1) + %res2 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v2, + <32 x i8> undef, <16 x i8> undef, i32 2) + %res3 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v3, + <32 x i8> undef, <16 x i8> undef, i32 3) + %res4 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v4, + <32 x i8> undef, <16 x i8> undef, i32 4) + %res5 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v5, + <32 x i8> undef, <16 x i8> undef, i32 5) + %res6 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v6, + <32 x i8> undef, <16 x i8> undef, i32 6) + %res7 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v7, + <32 x i8> undef, <16 x i8> undef, i32 7) + %res8 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v8, + <32 x i8> undef, <16 x i8> undef, i32 8) + %res9 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v9, + <32 x i8> undef, <16 x i8> undef, i32 9) + %res10 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v10, + <32 x i8> undef, <16 x i8> undef, i32 10) + %res11 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v11, + <32 x i8> undef, <16 x i8> undef, i32 11) + %res12 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v12, + <32 x i8> undef, <16 x i8> undef, i32 12) + %res13 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v13, + <32 x i8> undef, <16 x i8> undef, i32 13) + %res14 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v14, + <32 x i8> undef, <16 x i8> undef, i32 14) + %res15 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v15, + <32 x i8> undef, <16 x i8> undef, i32 15) + %res16 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v16, + <32 x i8> undef, <16 x i8> undef, i32 16) + %e1 = extractelement <4 x float> %res1, i32 0 + %e2 = extractelement <4 x float> %res2, i32 1 + %e3 = extractelement <4 x float> %res3, i32 2 + %e4 = extractelement <4 x float> %res4, i32 3 + %t0 = extractelement <4 x float> %res5, i32 0 + %t1 = extractelement <4 x float> %res5, i32 1 + %e5 = fadd float %t0, %t1 + %t2 = extractelement <4 x float> %res6, i32 0 + %t3 = extractelement <4 x float> %res6, i32 2 + %e6 = fadd float %t2, %t3 + %t4 = extractelement <4 x float> %res7, i32 0 + %t5 = extractelement <4 x float> %res7, i32 3 + %e7 = fadd float %t4, %t5 + %t6 = extractelement <4 x float> %res8, i32 1 + %t7 = extractelement <4 x float> %res8, i32 2 + %e8 = fadd float %t6, %t7 + %t8 = extractelement <4 x float> %res9, i32 1 + %t9 = extractelement <4 x float> %res9, i32 3 + %e9 = fadd float %t8, %t9 + %t10 = extractelement <4 x float> %res10, i32 2 + %t11 = extractelement <4 x float> %res10, i32 3 + %e10 = fadd float %t10, %t11 + %t12 = extractelement <4 x float> %res11, i32 0 + %t13 = extractelement <4 x float> %res11, i32 1 + %t14 = extractelement <4 x float> %res11, i32 2 + %t15 = fadd float %t12, %t13 + %e11 = fadd float %t14, %t15 + %t16 = extractelement <4 x float> %res12, i32 0 + %t17 = extractelement <4 x float> %res12, i32 1 + %t18 = extractelement <4 x float> %res12, i32 3 + %t19 = fadd float %t16, %t17 + %e12 = fadd float %t18, %t19 + %t20 = extractelement <4 x float> %res13, i32 0 + %t21 = extractelement <4 x float> %res13, i32 2 + %t22 = extractelement <4 x float> %res13, i32 3 + %t23 = fadd float %t20, %t21 + %e13 = fadd float %t22, %t23 + %t24 = extractelement <4 x float> %res14, i32 1 + %t25 = extractelement <4 x float> %res14, i32 2 + %t26 = extractelement <4 x float> %res14, i32 3 + %t27 = fadd float %t24, %t25 + %e14 = fadd float %t26, %t27 + %t28 = extractelement <4 x float> %res15, i32 0 + %t29 = extractelement <4 x float> %res15, i32 1 + %t30 = extractelement <4 x float> %res15, i32 2 + %t31 = extractelement <4 x float> %res15, i32 3 + %t32 = fadd float %t28, %t29 + %t33 = fadd float %t30, %t31 + %e15 = fadd float %t32, %t33 + %e16 = extractelement <4 x float> %res16, i32 3 + %s1 = fadd float %e1, %e2 + %s2 = fadd float %s1, %e3 + %s3 = fadd float %s2, %e4 + %s4 = fadd float %s3, %e5 + %s5 = fadd float %s4, %e6 + %s6 = fadd float %s5, %e7 + %s7 = fadd float %s6, %e8 + %s8 = fadd float %s7, %e9 + %s9 = fadd float %s8, %e10 + %s10 = fadd float %s9, %e11 + %s11 = fadd float %s10, %e12 + %s12 = fadd float %s11, %e13 + %s13 = fadd float %s12, %e14 + %s14 = fadd float %s13, %e15 + %s15 = fadd float %s14, %e16 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s15, float %s15, float %s15, float %s15) + ret void +} + +declare <4 x float> @llvm.SI.sampled.(<4 x i32>, <32 x i8>, <16 x i8>, i32) readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/llvm.SI.tbuffer.store.ll b/test/CodeGen/R600/llvm.SI.tbuffer.store.ll new file mode 100644 index 000000000000..fa7c3cabadc5 --- /dev/null +++ b/test/CodeGen/R600/llvm.SI.tbuffer.store.ll @@ -0,0 +1,44 @@ +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +;CHECK_LABEL: @test1 +;CHECK: TBUFFER_STORE_FORMAT_XYZW {{v\[[0-9]+:[0-9]+\]}}, 32, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 +define void @test1(i32 %a1, i32 %vaddr) { + %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 + call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata, + i32 4, i32 %vaddr, i32 0, i32 32, i32 14, i32 4, i32 1, i32 0, i32 1, + i32 1, i32 0) + ret void +} + +;CHECK_LABEL: @test2 +;CHECK: TBUFFER_STORE_FORMAT_XYZ {{v\[[0-9]+:[0-9]+\]}}, 24, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 +define void @test2(i32 %a1, i32 %vaddr) { + %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 + call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata, + i32 3, i32 %vaddr, i32 0, i32 24, i32 13, i32 4, i32 1, i32 0, i32 1, + i32 1, i32 0) + ret void +} + +;CHECK_LABEL: @test3 +;CHECK: TBUFFER_STORE_FORMAT_XY {{v\[[0-9]+:[0-9]+\]}}, 16, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 +define void @test3(i32 %a1, i32 %vaddr) { + %vdata = insertelement <2 x i32> undef, i32 %a1, i32 0 + call void @llvm.SI.tbuffer.store.v2i32(<16 x i8> undef, <2 x i32> %vdata, + i32 2, i32 %vaddr, i32 0, i32 16, i32 11, i32 4, i32 1, i32 0, i32 1, + i32 1, i32 0) + ret void +} + +;CHECK_LABEL: @test4 +;CHECK: TBUFFER_STORE_FORMAT_X {{v[0-9]+}}, 8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 +define void @test4(i32 %vdata, i32 %vaddr) { + call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata, + i32 1, i32 %vaddr, i32 0, i32 8, i32 4, i32 4, i32 1, i32 0, i32 1, + i32 1, i32 0) + ret void +} + +declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) +declare void @llvm.SI.tbuffer.store.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) +declare void @llvm.SI.tbuffer.store.v4i32(<16 x i8>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) diff --git a/test/CodeGen/R600/llvm.SI.tid.ll b/test/CodeGen/R600/llvm.SI.tid.ll new file mode 100644 index 000000000000..fe17304732ad --- /dev/null +++ b/test/CodeGen/R600/llvm.SI.tid.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +;CHECK: V_MBCNT_LO_U32_B32_e64 +;CHECK: V_MBCNT_HI_U32_B32_e32 + +define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { +main_body: + %4 = call i32 @llvm.SI.tid() + %5 = bitcast i32 %4 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %5, float %5, float %5) + ret void +} + +declare i32 @llvm.SI.tid() readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/llvm.cos.ll b/test/CodeGen/R600/llvm.cos.ll index 9b2816707042..aaf2305dd0ba 100644 --- a/test/CodeGen/R600/llvm.cos.ll +++ b/test/CodeGen/R600/llvm.cos.ll @@ -1,16 +1,19 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: COS * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MULADD_IEEE * +;CHECK: FRACT * +;CHECK: ADD * +;CHECK: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = call float @llvm.cos.f32(float %r0) - call void @llvm.AMDGPU.store.output(float %r1, i32 0) + %vec = insertelement <4 x float> undef, float %r1, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } declare float @llvm.cos.f32(float) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -declare float @llvm.R600.load.input(i32) readnone - -declare void @llvm.AMDGPU.store.output(float, i32) +attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/R600/llvm.floor.ll b/test/CodeGen/R600/llvm.floor.ll new file mode 100644 index 000000000000..f7071cd9b879 --- /dev/null +++ b/test/CodeGen/R600/llvm.floor.ll @@ -0,0 +1,54 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; R600-CHECK: @f32 +; R600-CHECK: FLOOR +; SI-CHECK: @f32 +; SI-CHECK: V_FLOOR_F32_e32 +define void @f32(float addrspace(1)* %out, float %in) { +entry: + %0 = call float @llvm.floor.f32(float %in) + store float %0, float addrspace(1)* %out + ret void +} + +; R600-CHECK: @v2f32 +; R600-CHECK: FLOOR +; R600-CHECK: FLOOR +; SI-CHECK: @v2f32 +; SI-CHECK: V_FLOOR_F32_e32 +; SI-CHECK: V_FLOOR_F32_e32 +define void @v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { +entry: + %0 = call <2 x float> @llvm.floor.v2f32(<2 x float> %in) + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; R600-CHECK: @v4f32 +; R600-CHECK: FLOOR +; R600-CHECK: FLOOR +; R600-CHECK: FLOOR +; R600-CHECK: FLOOR +; SI-CHECK: @v4f32 +; SI-CHECK: V_FLOOR_F32_e32 +; SI-CHECK: V_FLOOR_F32_e32 +; SI-CHECK: V_FLOOR_F32_e32 +; SI-CHECK: V_FLOOR_F32_e32 +define void @v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { +entry: + %0 = call <4 x float> @llvm.floor.v4f32(<4 x float> %in) + store <4 x float> %0, <4 x float> addrspace(1)* %out + ret void +} + +; Function Attrs: nounwind readonly +declare float @llvm.floor.f32(float) #0 + +; Function Attrs: nounwind readonly +declare <2 x float> @llvm.floor.v2f32(<2 x float>) #0 + +; Function Attrs: nounwind readonly +declare <4 x float> @llvm.floor.v4f32(<4 x float>) #0 + +attributes #0 = { nounwind readonly } diff --git a/test/CodeGen/R600/llvm.pow.ll b/test/CodeGen/R600/llvm.pow.ll index 91b774282906..b587d2b2aea1 100644 --- a/test/CodeGen/R600/llvm.pow.ll +++ b/test/CodeGen/R600/llvm.pow.ll @@ -1,19 +1,19 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}} +;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.R600.load.input(i32 1) +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 + %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = call float @llvm.pow.f32( float %r0, float %r1) - call void @llvm.AMDGPU.store.output(float %r2, i32 0) + %vec = insertelement <4 x float> undef, float %r2, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare float @llvm.R600.load.input(i32) readnone - -declare void @llvm.AMDGPU.store.output(float, i32) - declare float @llvm.pow.f32(float ,float ) readonly +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/R600/llvm.rint.ll b/test/CodeGen/R600/llvm.rint.ll new file mode 100644 index 000000000000..c174b335f0e8 --- /dev/null +++ b/test/CodeGen/R600/llvm.rint.ll @@ -0,0 +1,54 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; R600-CHECK: @f32 +; R600-CHECK: RNDNE +; SI-CHECK: @f32 +; SI-CHECK: V_RNDNE_F32_e32 +define void @f32(float addrspace(1)* %out, float %in) { +entry: + %0 = call float @llvm.rint.f32(float %in) + store float %0, float addrspace(1)* %out + ret void +} + +; R600-CHECK: @v2f32 +; R600-CHECK: RNDNE +; R600-CHECK: RNDNE +; SI-CHECK: @v2f32 +; SI-CHECK: V_RNDNE_F32_e32 +; SI-CHECK: V_RNDNE_F32_e32 +define void @v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { +entry: + %0 = call <2 x float> @llvm.rint.v2f32(<2 x float> %in) + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; R600-CHECK: @v4f32 +; R600-CHECK: RNDNE +; R600-CHECK: RNDNE +; R600-CHECK: RNDNE +; R600-CHECK: RNDNE +; SI-CHECK: @v4f32 +; SI-CHECK: V_RNDNE_F32_e32 +; SI-CHECK: V_RNDNE_F32_e32 +; SI-CHECK: V_RNDNE_F32_e32 +; SI-CHECK: V_RNDNE_F32_e32 +define void @v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { +entry: + %0 = call <4 x float> @llvm.rint.v4f32(<4 x float> %in) + store <4 x float> %0, <4 x float> addrspace(1)* %out + ret void +} + +; Function Attrs: nounwind readonly +declare float @llvm.rint.f32(float) #0 + +; Function Attrs: nounwind readonly +declare <2 x float> @llvm.rint.v2f32(<2 x float>) #0 + +; Function Attrs: nounwind readonly +declare <4 x float> @llvm.rint.v4f32(<4 x float>) #0 + +attributes #0 = { nounwind readonly } diff --git a/test/CodeGen/R600/llvm.round.ll b/test/CodeGen/R600/llvm.round.ll new file mode 100644 index 000000000000..e06d45d4a373 --- /dev/null +++ b/test/CodeGen/R600/llvm.round.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 --check-prefix=FUNC + +; FUNC-LABEL: @f32 +; R600: FRACT +; R600-DAG: ADD +; R600-DAG: CEIL +; R600-DAG: FLOOR +; R600: CNDGE +define void @f32(float addrspace(1)* %out, float %in) { +entry: + %0 = call float @llvm.round.f32(float %in) + store float %0, float addrspace(1)* %out + ret void +} + +; The vector tests are really difficult to verify, since it can be hard to +; predict how the scheduler will order the instructions. We already have +; a test for the scalar case, so the vector tests just check that the +; compiler doesn't crash. + +; FUNC-LABEL: v2f32 +; R600: CF_END +define void @v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { +entry: + %0 = call <2 x float> @llvm.round.v2f32(<2 x float> %in) + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: v4f32 +; R600: CF_END +define void @v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { +entry: + %0 = call <4 x float> @llvm.round.v4f32(<4 x float> %in) + store <4 x float> %0, <4 x float> addrspace(1)* %out + ret void +} + +declare float @llvm.round.f32(float) +declare <2 x float> @llvm.round.v2f32(<2 x float>) +declare <4 x float> @llvm.round.v4f32(<4 x float>) diff --git a/test/CodeGen/R600/llvm.sin.ll b/test/CodeGen/R600/llvm.sin.ll index 803dc2d6debc..9eb998315fef 100644 --- a/test/CodeGen/R600/llvm.sin.ll +++ b/test/CodeGen/R600/llvm.sin.ll @@ -1,16 +1,19 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: SIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MULADD_IEEE * +;CHECK: FRACT * +;CHECK: ADD * +;CHECK: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = call float @llvm.sin.f32( float %r0) - call void @llvm.AMDGPU.store.output(float %r1, i32 0) + %vec = insertelement <4 x float> undef, float %r1, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } declare float @llvm.sin.f32(float) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -declare float @llvm.R600.load.input(i32) readnone - -declare void @llvm.AMDGPU.store.output(float, i32) +attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/R600/llvm.sqrt.ll b/test/CodeGen/R600/llvm.sqrt.ll new file mode 100644 index 000000000000..0d0d18618990 --- /dev/null +++ b/test/CodeGen/R600/llvm.sqrt.ll @@ -0,0 +1,54 @@ +; RUN: llc < %s -march=r600 --mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 --mcpu=SI | FileCheck %s --check-prefix=SI-CHECK + +; R600-CHECK-LABEL: @sqrt_f32 +; R600-CHECK: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z +; R600-CHECK: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].Z, PS +; SI-CHECK-LABEL: @sqrt_f32 +; SI-CHECK: V_SQRT_F32_e32 +define void @sqrt_f32(float addrspace(1)* %out, float %in) { +entry: + %0 = call float @llvm.sqrt.f32(float %in) + store float %0, float addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @sqrt_v2f32 +; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].W +; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].W, PS +; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].X +; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].X, PS +; SI-CHECK-LABEL: @sqrt_v2f32 +; SI-CHECK: V_SQRT_F32_e32 +; SI-CHECK: V_SQRT_F32_e32 +define void @sqrt_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { +entry: + %0 = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @sqrt_v4f32 +; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Y +; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Y, PS +; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Z +; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Z, PS +; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].W +; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].W, PS +; R600-CHECK-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[4].X +; R600-CHECK-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[4].X, PS +; SI-CHECK-LABEL: @sqrt_v4f32 +; SI-CHECK: V_SQRT_F32_e32 +; SI-CHECK: V_SQRT_F32_e32 +; SI-CHECK: V_SQRT_F32_e32 +; SI-CHECK: V_SQRT_F32_e32 +define void @sqrt_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { +entry: + %0 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) + store <4 x float> %0, <4 x float> addrspace(1)* %out + ret void +} + +declare float @llvm.sqrt.f32(float %in) +declare <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) +declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) diff --git a/test/CodeGen/R600/load-input-fold.ll b/test/CodeGen/R600/load-input-fold.ll new file mode 100644 index 000000000000..ca86d0e36907 --- /dev/null +++ b/test/CodeGen/R600/load-input-fold.ll @@ -0,0 +1,118 @@ +;RUN: llc < %s -march=r600 -mcpu=cayman +;REQUIRES: asserts + +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 { +main_body: + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg1, i32 3 + %4 = extractelement <4 x float> %reg2, i32 0 + %5 = extractelement <4 x float> %reg2, i32 1 + %6 = extractelement <4 x float> %reg2, i32 2 + %7 = extractelement <4 x float> %reg2, i32 3 + %8 = extractelement <4 x float> %reg3, i32 0 + %9 = extractelement <4 x float> %reg3, i32 1 + %10 = extractelement <4 x float> %reg3, i32 2 + %11 = extractelement <4 x float> %reg3, i32 3 + %12 = load <4 x float> addrspace(8)* null + %13 = extractelement <4 x float> %12, i32 0 + %14 = fmul float %0, %13 + %15 = load <4 x float> addrspace(8)* null + %16 = extractelement <4 x float> %15, i32 1 + %17 = fmul float %0, %16 + %18 = load <4 x float> addrspace(8)* null + %19 = extractelement <4 x float> %18, i32 2 + %20 = fmul float %0, %19 + %21 = load <4 x float> addrspace(8)* null + %22 = extractelement <4 x float> %21, i32 3 + %23 = fmul float %0, %22 + %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %25 = extractelement <4 x float> %24, i32 0 + %26 = fmul float %1, %25 + %27 = fadd float %26, %14 + %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %29 = extractelement <4 x float> %28, i32 1 + %30 = fmul float %1, %29 + %31 = fadd float %30, %17 + %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %33 = extractelement <4 x float> %32, i32 2 + %34 = fmul float %1, %33 + %35 = fadd float %34, %20 + %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %37 = extractelement <4 x float> %36, i32 3 + %38 = fmul float %1, %37 + %39 = fadd float %38, %23 + %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %41 = extractelement <4 x float> %40, i32 0 + %42 = fmul float %2, %41 + %43 = fadd float %42, %27 + %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %45 = extractelement <4 x float> %44, i32 1 + %46 = fmul float %2, %45 + %47 = fadd float %46, %31 + %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %49 = extractelement <4 x float> %48, i32 2 + %50 = fmul float %2, %49 + %51 = fadd float %50, %35 + %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %53 = extractelement <4 x float> %52, i32 3 + %54 = fmul float %2, %53 + %55 = fadd float %54, %39 + %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %57 = extractelement <4 x float> %56, i32 0 + %58 = fmul float %3, %57 + %59 = fadd float %58, %43 + %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %61 = extractelement <4 x float> %60, i32 1 + %62 = fmul float %3, %61 + %63 = fadd float %62, %47 + %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %65 = extractelement <4 x float> %64, i32 2 + %66 = fmul float %3, %65 + %67 = fadd float %66, %51 + %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %69 = extractelement <4 x float> %68, i32 3 + %70 = fmul float %3, %69 + %71 = fadd float %70, %55 + %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %73 = extractelement <4 x float> %72, i32 0 + %74 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %75 = extractelement <4 x float> %74, i32 1 + %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %77 = extractelement <4 x float> %76, i32 2 + %78 = insertelement <4 x float> undef, float %4, i32 0 + %79 = insertelement <4 x float> %78, float %5, i32 1 + %80 = insertelement <4 x float> %79, float %6, i32 2 + %81 = insertelement <4 x float> %80, float 0.000000e+00, i32 3 + %82 = insertelement <4 x float> undef, float %73, i32 0 + %83 = insertelement <4 x float> %82, float %75, i32 1 + %84 = insertelement <4 x float> %83, float %77, i32 2 + %85 = insertelement <4 x float> %84, float 0.000000e+00, i32 3 + %86 = call float @llvm.AMDGPU.dp4(<4 x float> %81, <4 x float> %85) + %87 = insertelement <4 x float> undef, float %86, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %87, i32 2, i32 2) + ret void +} + +; Function Attrs: readnone +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 + +; Function Attrs: readonly +declare float @fabs(float) #2 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.rsq(float) #1 + +; Function Attrs: readnone +declare float @llvm.AMDIL.clamp.(float, float, float) #1 + +; Function Attrs: nounwind readonly +declare float @llvm.pow.f32(float, float) #3 + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } +attributes #1 = { readnone } +attributes #2 = { readonly } +attributes #3 = { nounwind readonly } diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll index b03245ae87b3..e4492d7d6e7b 100644 --- a/test/CodeGen/R600/load.ll +++ b/test/CodeGen/R600/load.ll @@ -1,8 +1,17 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s + +;===------------------------------------------------------------------------===; +; GLOBAL ADDRESS SPACE +;===------------------------------------------------------------------------===; ; Load an i8 value from the global address space. -; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +; R600-CHECK-LABEL: @load_i8 +; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI-CHECK-LABEL: @load_i8 +; SI-CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { %1 = load i8 addrspace(1)* %in %2 = zext i8 %1 to i32 @@ -10,11 +19,665 @@ define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { ret void } +; R600-CHECK-LABEL: @load_i8_sext +; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] +; R600-CHECK: 24 +; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] +; R600-CHECK: 24 +; SI-CHECK-LABEL: @load_i8_sext +; SI-CHECK: BUFFER_LOAD_SBYTE +define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { +entry: + %0 = load i8 addrspace(1)* %in + %1 = sext i8 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v2i8 +; R600-CHECK: VTX_READ_8 +; R600-CHECK: VTX_READ_8 +; SI-CHECK-LABEL: @load_v2i8 +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +define void @load_v2i8(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) { +entry: + %0 = load <2 x i8> addrspace(1)* %in + %1 = zext <2 x i8> %0 to <2 x i32> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v2i8_sext +; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] +; R600-CHECK-DAG: 24 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] +; R600-CHECK-DAG: 24 +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] +; R600-CHECK-DAG: 24 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] +; R600-CHECK-DAG: 24 +; SI-CHECK-LABEL: @load_v2i8_sext +; SI-CHECK: BUFFER_LOAD_SBYTE +; SI-CHECK: BUFFER_LOAD_SBYTE +define void @load_v2i8_sext(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) { +entry: + %0 = load <2 x i8> addrspace(1)* %in + %1 = sext <2 x i8> %0 to <2 x i32> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v4i8 +; R600-CHECK: VTX_READ_8 +; R600-CHECK: VTX_READ_8 +; R600-CHECK: VTX_READ_8 +; R600-CHECK: VTX_READ_8 +; SI-CHECK-LABEL: @load_v4i8 +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +; SI-CHECK: BUFFER_LOAD_UBYTE +define void @load_v4i8(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) { +entry: + %0 = load <4 x i8> addrspace(1)* %in + %1 = zext <4 x i8> %0 to <4 x i32> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v4i8_sext +; R600-CHECK-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; R600-CHECK-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; R600-CHECK-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] +; R600-CHECK-DAG: VTX_READ_8 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] +; R600-CHECK-DAG: 24 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] +; R600-CHECK-DAG: 24 +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] +; R600-CHECK-DAG: 24 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] +; R600-CHECK-DAG: 24 +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]] +; R600-CHECK-DAG: 24 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]] +; R600-CHECK-DAG: 24 +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]] +; R600-CHECK-DAG: 24 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]] +; R600-CHECK-DAG: 24 +; SI-CHECK-LABEL: @load_v4i8_sext +; SI-CHECK: BUFFER_LOAD_SBYTE +; SI-CHECK: BUFFER_LOAD_SBYTE +; SI-CHECK: BUFFER_LOAD_SBYTE +; SI-CHECK: BUFFER_LOAD_SBYTE +define void @load_v4i8_sext(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) { +entry: + %0 = load <4 x i8> addrspace(1)* %in + %1 = sext <4 x i8> %0 to <4 x i32> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out + ret void +} + +; Load an i16 value from the global address space. +; R600-CHECK-LABEL: @load_i16 +; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI-CHECK-LABEL: @load_i16 +; SI-CHECK: BUFFER_LOAD_USHORT +define void @load_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) { +entry: + %0 = load i16 addrspace(1)* %in + %1 = zext i16 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_i16_sext +; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] +; R600-CHECK: 16 +; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] +; R600-CHECK: 16 +; SI-CHECK-LABEL: @load_i16_sext +; SI-CHECK: BUFFER_LOAD_SSHORT +define void @load_i16_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) { +entry: + %0 = load i16 addrspace(1)* %in + %1 = sext i16 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v2i16 +; R600-CHECK: VTX_READ_16 +; R600-CHECK: VTX_READ_16 +; SI-CHECK-LABEL: @load_v2i16 +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +define void @load_v2i16(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { +entry: + %0 = load <2 x i16> addrspace(1)* %in + %1 = zext <2 x i16> %0 to <2 x i32> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v2i16_sext +; R600-CHECK-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; R600-CHECK-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] +; R600-CHECK-DAG: 16 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] +; R600-CHECK-DAG: 16 +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] +; R600-CHECK-DAG: 16 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] +; R600-CHECK-DAG: 16 +; SI-CHECK-LABEL: @load_v2i16_sext +; SI-CHECK: BUFFER_LOAD_SSHORT +; SI-CHECK: BUFFER_LOAD_SSHORT +define void @load_v2i16_sext(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { +entry: + %0 = load <2 x i16> addrspace(1)* %in + %1 = sext <2 x i16> %0 to <2 x i32> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v4i16 +; R600-CHECK: VTX_READ_16 +; R600-CHECK: VTX_READ_16 +; R600-CHECK: VTX_READ_16 +; R600-CHECK: VTX_READ_16 +; SI-CHECK-LABEL: @load_v4i16 +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +; SI-CHECK: BUFFER_LOAD_USHORT +define void @load_v4i16(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { +entry: + %0 = load <4 x i16> addrspace(1)* %in + %1 = zext <4 x i16> %0 to <4 x i32> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v4i16_sext +; R600-CHECK-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; R600-CHECK-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; R600-CHECK-DAG: VTX_READ_16 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] +; R600-CHECK-DAG: VTX_READ_16 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_X_CHAN:[XYZW]]], [[DST_X]] +; R600-CHECK-DAG: 16 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_X_CHAN]] +; R600-CHECK-DAG: 16 +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Y_CHAN:[XYZW]]], [[DST_Y]] +; R600-CHECK-DAG: 16 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Y_CHAN]] +; R600-CHECK-DAG: 16 +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_Z_CHAN:[XYZW]]], [[DST_Z]] +; R600-CHECK-DAG: 16 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_Z_CHAN]] +; R600-CHECK-DAG: 16 +; R600-CHECK-DAG: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_W_CHAN:[XYZW]]], [[DST_W]] +; R600-CHECK-DAG: 16 +; R600-CHECK-DAG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_W_CHAN]] +; R600-CHECK-DAG: 16 +; SI-CHECK-LABEL: @load_v4i16_sext +; SI-CHECK: BUFFER_LOAD_SSHORT +; SI-CHECK: BUFFER_LOAD_SSHORT +; SI-CHECK: BUFFER_LOAD_SSHORT +; SI-CHECK: BUFFER_LOAD_SSHORT +define void @load_v4i16_sext(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { +entry: + %0 = load <4 x i16> addrspace(1)* %in + %1 = sext <4 x i16> %0 to <4 x i32> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out + ret void +} + +; load an i32 value from the global address space. +; R600-CHECK-LABEL: @load_i32 +; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 + +; SI-CHECK-LABEL: @load_i32 +; SI-CHECK: BUFFER_LOAD_DWORD v{{[0-9]+}} +define void @load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +entry: + %0 = load i32 addrspace(1)* %in + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; load a f32 value from the global address space. +; R600-CHECK-LABEL: @load_f32 +; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 + +; SI-CHECK-LABEL: @load_f32 +; SI-CHECK: BUFFER_LOAD_DWORD v{{[0-9]+}} +define void @load_f32(float addrspace(1)* %out, float addrspace(1)* %in) { +entry: + %0 = load float addrspace(1)* %in + store float %0, float addrspace(1)* %out + ret void +} + +; load a v2f32 value from the global address space +; R600-CHECK-LABEL: @load_v2f32 +; R600-CHECK: VTX_READ_64 + +; SI-CHECK-LABEL: @load_v2f32 +; SI-CHECK: BUFFER_LOAD_DWORDX2 +define void @load_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) { +entry: + %0 = load <2 x float> addrspace(1)* %in + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_i64 +; R600-CHECK: MEM_RAT +; R600-CHECK: MEM_RAT + +; SI-CHECK-LABEL: @load_i64 +; SI-CHECK: BUFFER_LOAD_DWORDX2 +define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { +entry: + %0 = load i64 addrspace(1)* %in + store i64 %0, i64 addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_i64_sext +; R600-CHECK: MEM_RAT +; R600-CHECK: MEM_RAT +; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.x +; R600-CHECK: 31 +; SI-CHECK-LABEL: @load_i64_sext +; SI-CHECK: BUFFER_LOAD_DWORDX2 [[VAL:v\[[0-9]:[0-9]\]]] + +define void @load_i64_sext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { +entry: + %0 = load i32 addrspace(1)* %in + %1 = sext i32 %0 to i64 + store i64 %1, i64 addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_i64_zext +; R600-CHECK: MEM_RAT +; R600-CHECK: MEM_RAT +define void @load_i64_zext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { +entry: + %0 = load i32 addrspace(1)* %in + %1 = zext i32 %0 to i64 + store i64 %1, i64 addrspace(1)* %out + ret void +} + +;===------------------------------------------------------------------------===; +; CONSTANT ADDRESS SPACE +;===------------------------------------------------------------------------===; + +; Load a sign-extended i8 value +; R600-CHECK-LABEL: @load_const_i8_sext +; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] +; R600-CHECK: 24 +; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] +; R600-CHECK: 24 +; SI-CHECK-LABEL: @load_const_i8_sext +; SI-CHECK: BUFFER_LOAD_SBYTE v{{[0-9]+}}, +define void @load_const_i8_sext(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { +entry: + %0 = load i8 addrspace(2)* %in + %1 = sext i8 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; Load an aligned i8 value +; R600-CHECK-LABEL: @load_const_i8_aligned +; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI-CHECK-LABEL: @load_const_i8_aligned +; SI-CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, +define void @load_const_i8_aligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { +entry: + %0 = load i8 addrspace(2)* %in + %1 = zext i8 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; Load an un-aligned i8 value +; R600-CHECK-LABEL: @load_const_i8_unaligned +; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI-CHECK-LABEL: @load_const_i8_unaligned +; SI-CHECK: BUFFER_LOAD_UBYTE v{{[0-9]+}}, +define void @load_const_i8_unaligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { +entry: + %0 = getelementptr i8 addrspace(2)* %in, i32 1 + %1 = load i8 addrspace(2)* %0 + %2 = zext i8 %1 to i32 + store i32 %2, i32 addrspace(1)* %out + ret void +} + +; Load a sign-extended i16 value +; R600-CHECK-LABEL: @load_const_i16_sext +; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]] +; R600-CHECK: 16 +; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]] +; R600-CHECK: 16 +; SI-CHECK-LABEL: @load_const_i16_sext +; SI-CHECK: BUFFER_LOAD_SSHORT +define void @load_const_i16_sext(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { +entry: + %0 = load i16 addrspace(2)* %in + %1 = sext i16 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; Load an aligned i16 value +; R600-CHECK-LABEL: @load_const_i16_aligned +; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI-CHECK-LABEL: @load_const_i16_aligned +; SI-CHECK: BUFFER_LOAD_USHORT +define void @load_const_i16_aligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { +entry: + %0 = load i16 addrspace(2)* %in + %1 = zext i16 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; Load an un-aligned i16 value +; R600-CHECK-LABEL: @load_const_i16_unaligned +; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} +; SI-CHECK-LABEL: @load_const_i16_unaligned +; SI-CHECK: BUFFER_LOAD_USHORT +define void @load_const_i16_unaligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { +entry: + %0 = getelementptr i16 addrspace(2)* %in, i32 1 + %1 = load i16 addrspace(2)* %0 + %2 = zext i16 %1 to i32 + store i32 %2, i32 addrspace(1)* %out + ret void +} + +; Load an i32 value from the constant address space. +; R600-CHECK-LABEL: @load_const_addrspace_i32 +; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 + +; SI-CHECK-LABEL: @load_const_addrspace_i32 +; SI-CHECK: S_LOAD_DWORD s{{[0-9]+}} +define void @load_const_addrspace_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { +entry: + %0 = load i32 addrspace(2)* %in + store i32 %0, i32 addrspace(1)* %out + ret void +} + ; Load a f32 value from the constant address space. -; CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}} +; R600-CHECK-LABEL: @load_const_addrspace_f32 +; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +; SI-CHECK-LABEL: @load_const_addrspace_f32 +; SI-CHECK: S_LOAD_DWORD s{{[0-9]+}} define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) { %1 = load float addrspace(2)* %in store float %1, float addrspace(1)* %out ret void } + +;===------------------------------------------------------------------------===; +; LOCAL ADDRESS SPACE +;===------------------------------------------------------------------------===; + +; Load an i8 value from the local address space. +; R600-CHECK-LABEL: @load_i8_local +; R600-CHECK: LDS_UBYTE_READ_RET +; SI-CHECK-LABEL: @load_i8_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_U8 +define void @load_i8_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) { + %1 = load i8 addrspace(3)* %in + %2 = zext i8 %1 to i32 + store i32 %2, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_i8_sext_local +; R600-CHECK: LDS_UBYTE_READ_RET +; R600-CHECK: ASHR +; SI-CHECK-LABEL: @load_i8_sext_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_I8 +define void @load_i8_sext_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) { +entry: + %0 = load i8 addrspace(3)* %in + %1 = sext i8 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v2i8_local +; R600-CHECK: LDS_UBYTE_READ_RET +; R600-CHECK: LDS_UBYTE_READ_RET +; SI-CHECK-LABEL: @load_v2i8_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_U8 +; SI-CHECK: DS_READ_U8 +define void @load_v2i8_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) { +entry: + %0 = load <2 x i8> addrspace(3)* %in + %1 = zext <2 x i8> %0 to <2 x i32> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v2i8_sext_local +; R600-CHECK-DAG: LDS_UBYTE_READ_RET +; R600-CHECK-DAG: LDS_UBYTE_READ_RET +; R600-CHECK-DAG: ASHR +; R600-CHECK-DAG: ASHR +; SI-CHECK-LABEL: @load_v2i8_sext_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_I8 +; SI-CHECK: DS_READ_I8 +define void @load_v2i8_sext_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) { +entry: + %0 = load <2 x i8> addrspace(3)* %in + %1 = sext <2 x i8> %0 to <2 x i32> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v4i8_local +; R600-CHECK: LDS_UBYTE_READ_RET +; R600-CHECK: LDS_UBYTE_READ_RET +; R600-CHECK: LDS_UBYTE_READ_RET +; R600-CHECK: LDS_UBYTE_READ_RET +; SI-CHECK-LABEL: @load_v4i8_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_U8 +; SI-CHECK: DS_READ_U8 +; SI-CHECK: DS_READ_U8 +; SI-CHECK: DS_READ_U8 +define void @load_v4i8_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) { +entry: + %0 = load <4 x i8> addrspace(3)* %in + %1 = zext <4 x i8> %0 to <4 x i32> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v4i8_sext_local +; R600-CHECK-DAG: LDS_UBYTE_READ_RET +; R600-CHECK-DAG: LDS_UBYTE_READ_RET +; R600-CHECK-DAG: LDS_UBYTE_READ_RET +; R600-CHECK-DAG: LDS_UBYTE_READ_RET +; R600-CHECK-DAG: ASHR +; R600-CHECK-DAG: ASHR +; R600-CHECK-DAG: ASHR +; R600-CHECK-DAG: ASHR +; SI-CHECK-LABEL: @load_v4i8_sext_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_I8 +; SI-CHECK: DS_READ_I8 +; SI-CHECK: DS_READ_I8 +; SI-CHECK: DS_READ_I8 +define void @load_v4i8_sext_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) { +entry: + %0 = load <4 x i8> addrspace(3)* %in + %1 = sext <4 x i8> %0 to <4 x i32> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out + ret void +} + +; Load an i16 value from the local address space. +; R600-CHECK-LABEL: @load_i16_local +; R600-CHECK: LDS_USHORT_READ_RET +; SI-CHECK-LABEL: @load_i16_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_U16 +define void @load_i16_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) { +entry: + %0 = load i16 addrspace(3)* %in + %1 = zext i16 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_i16_sext_local +; R600-CHECK: LDS_USHORT_READ_RET +; R600-CHECK: ASHR +; SI-CHECK-LABEL: @load_i16_sext_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_I16 +define void @load_i16_sext_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) { +entry: + %0 = load i16 addrspace(3)* %in + %1 = sext i16 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v2i16_local +; R600-CHECK: LDS_USHORT_READ_RET +; R600-CHECK: LDS_USHORT_READ_RET +; SI-CHECK-LABEL: @load_v2i16_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_U16 +; SI-CHECK: DS_READ_U16 +define void @load_v2i16_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) { +entry: + %0 = load <2 x i16> addrspace(3)* %in + %1 = zext <2 x i16> %0 to <2 x i32> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v2i16_sext_local +; R600-CHECK-DAG: LDS_USHORT_READ_RET +; R600-CHECK-DAG: LDS_USHORT_READ_RET +; R600-CHECK-DAG: ASHR +; R600-CHECK-DAG: ASHR +; SI-CHECK-LABEL: @load_v2i16_sext_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_I16 +; SI-CHECK: DS_READ_I16 +define void @load_v2i16_sext_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) { +entry: + %0 = load <2 x i16> addrspace(3)* %in + %1 = sext <2 x i16> %0 to <2 x i32> + store <2 x i32> %1, <2 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v4i16_local +; R600-CHECK: LDS_USHORT_READ_RET +; R600-CHECK: LDS_USHORT_READ_RET +; R600-CHECK: LDS_USHORT_READ_RET +; R600-CHECK: LDS_USHORT_READ_RET +; SI-CHECK-LABEL: @load_v4i16_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_U16 +; SI-CHECK: DS_READ_U16 +; SI-CHECK: DS_READ_U16 +; SI-CHECK: DS_READ_U16 +define void @load_v4i16_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) { +entry: + %0 = load <4 x i16> addrspace(3)* %in + %1 = zext <4 x i16> %0 to <4 x i32> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @load_v4i16_sext_local +; R600-CHECK-DAG: LDS_USHORT_READ_RET +; R600-CHECK-DAG: LDS_USHORT_READ_RET +; R600-CHECK-DAG: LDS_USHORT_READ_RET +; R600-CHECK-DAG: LDS_USHORT_READ_RET +; R600-CHECK-DAG: ASHR +; R600-CHECK-DAG: ASHR +; R600-CHECK-DAG: ASHR +; R600-CHECK-DAG: ASHR +; SI-CHECK-LABEL: @load_v4i16_sext_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_I16 +; SI-CHECK: DS_READ_I16 +; SI-CHECK: DS_READ_I16 +; SI-CHECK: DS_READ_I16 +define void @load_v4i16_sext_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) { +entry: + %0 = load <4 x i16> addrspace(3)* %in + %1 = sext <4 x i16> %0 to <4 x i32> + store <4 x i32> %1, <4 x i32> addrspace(1)* %out + ret void +} + +; load an i32 value from the glocal address space. +; R600-CHECK-LABEL: @load_i32_local +; R600-CHECK: LDS_READ_RET +; SI-CHECK-LABEL: @load_i32_local +; SI-CHECK-NOT: S_WQM_B64 +; SI-CHECK: DS_READ_B32 +define void @load_i32_local(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { +entry: + %0 = load i32 addrspace(3)* %in + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; load a f32 value from the global address space. +; R600-CHECK-LABEL: @load_f32_local +; R600-CHECK: LDS_READ_RET +; SI-CHECK-LABEL: @load_f32_local +; SI-CHECK: DS_READ_B32 +define void @load_f32_local(float addrspace(1)* %out, float addrspace(3)* %in) { +entry: + %0 = load float addrspace(3)* %in + store float %0, float addrspace(1)* %out + ret void +} + +; load a v2f32 value from the local address space +; R600-CHECK-LABEL: @load_v2f32_local +; R600-CHECK: LDS_READ_RET +; R600-CHECK: LDS_READ_RET +; SI-CHECK-LABEL: @load_v2f32_local +; SI-CHECK: DS_READ_B32 +; SI-CHECK: DS_READ_B32 +define void @load_v2f32_local(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %in) { +entry: + %0 = load <2 x float> addrspace(3)* %in + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/load.vec.ll b/test/CodeGen/R600/load.vec.ll new file mode 100644 index 000000000000..81a6310bbcc9 --- /dev/null +++ b/test/CodeGen/R600/load.vec.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s + +; load a v2i32 value from the global address space. +; EG-CHECK: @load_v2i32 +; EG-CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0 +; SI-CHECK: @load_v2i32 +; SI-CHECK: BUFFER_LOAD_DWORDX2 v[{{[0-9]+:[0-9]+}}] +define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %a = load <2 x i32> addrspace(1) * %in + store <2 x i32> %a, <2 x i32> addrspace(1)* %out + ret void +} + +; load a v4i32 value from the global address space. +; EG-CHECK: @load_v4i32 +; EG-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0 +; SI-CHECK: @load_v4i32 +; SI-CHECK: BUFFER_LOAD_DWORDX4 v[{{[0-9]+:[0-9]+}}] +define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %a = load <4 x i32> addrspace(1) * %in + store <4 x i32> %a, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/load64.ll b/test/CodeGen/R600/load64.ll new file mode 100644 index 000000000000..e351e4135a7d --- /dev/null +++ b/test/CodeGen/R600/load64.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s + +; load a f64 value from the global address space. +; CHECK: @load_f64 +; CHECK: BUFFER_LOAD_DWORDX2 v[{{[0-9]+:[0-9]+}}] +define void @load_f64(double addrspace(1)* %out, double addrspace(1)* %in) { +entry: + %0 = load double addrspace(1)* %in + store double %0, double addrspace(1)* %out + ret void +} + +; Load a f64 value from the constant address space. +; CHECK: @load_const_addrspace_f64 +; CHECK: S_LOAD_DWORDX2 s[{{[0-9]+:[0-9]+}}] +define void @load_const_addrspace_f64(double addrspace(1)* %out, double addrspace(2)* %in) { + %1 = load double addrspace(2)* %in + store double %1, double addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/local-memory-two-objects.ll b/test/CodeGen/R600/local-memory-two-objects.ll new file mode 100644 index 000000000000..e2d840645d01 --- /dev/null +++ b/test/CodeGen/R600/local-memory-two-objects.ll @@ -0,0 +1,58 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s + +@local_memory_two_objects.local_mem0 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4 +@local_memory_two_objects.local_mem1 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4 + +; EG-CHECK: @local_memory_two_objects + +; Check that the LDS size emitted correctly +; EG-CHECK: .long 166120 +; EG-CHECK-NEXT: .long 8 +; SI-CHECK: .long 47180 +; SI-CHECK-NEXT: .long 32768 + +; We would like to check the the lds writes are using different +; addresses, but due to variations in the scheduler, we can't do +; this consistently on evergreen GPUs. +; EG-CHECK: LDS_WRITE +; EG-CHECK: LDS_WRITE +; SI-CHECK: DS_WRITE_B32 0, {{v[0-9]*}}, v[[ADDRW:[0-9]*]] +; SI-CHECK-NOT: DS_WRITE_B32 0, {{v[0-9]*}}, v[[ADDRW]] + +; GROUP_BARRIER must be the last instruction in a clause +; EG-CHECK: GROUP_BARRIER +; EG-CHECK-NEXT: ALU clause + +; Make sure the lds reads are using different addresses. +; EG-CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]] +; EG-CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]] +; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, 0, [[ADDRR:v[0-9]+]] +; SI-CHECK-NOT: DS_READ_B32 {{v[0-9]+}}, 0, [[ADDRR]] + +define void @local_memory_two_objects(i32 addrspace(1)* %out) { +entry: + %x.i = call i32 @llvm.r600.read.tidig.x() #0 + %arrayidx = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i + store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4 + %mul = shl nsw i32 %x.i, 1 + %arrayidx1 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i + store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4 + %sub = sub nsw i32 3, %x.i + call void @llvm.AMDGPU.barrier.local() + %arrayidx2 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub + %0 = load i32 addrspace(3)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %x.i + store i32 %0, i32 addrspace(1)* %arrayidx3, align 4 + %arrayidx4 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub + %1 = load i32 addrspace(3)* %arrayidx4, align 4 + %add = add nsw i32 %x.i, 4 + %arrayidx5 = getelementptr inbounds i32 addrspace(1)* %out, i32 %add + store i32 %1, i32 addrspace(1)* %arrayidx5, align 4 + ret void +} + +declare i32 @llvm.r600.read.tidig.x() #0 +declare void @llvm.AMDGPU.barrier.local() + +attributes #0 = { readnone } diff --git a/test/CodeGen/R600/local-memory.ll b/test/CodeGen/R600/local-memory.ll new file mode 100644 index 000000000000..2168a3d0bd27 --- /dev/null +++ b/test/CodeGen/R600/local-memory.ll @@ -0,0 +1,50 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=CI-CHECK %s + +@local_memory.local_mem = internal addrspace(3) unnamed_addr global [128 x i32] zeroinitializer, align 4 + +; EG-CHECK-LABEL: @local_memory +; SI-CHECK-LABEL: @local_memory +; CI-CHECK-LABEL: @local_memory + +; Check that the LDS size emitted correctly +; EG-CHECK: .long 166120 +; EG-CHECK-NEXT: .long 128 +; SI-CHECK: .long 47180 +; SI-CHECK-NEXT: .long 65536 +; CI-CHECK: .long 47180 +; CI-CHECK-NEXT: .long 32768 + +; EG-CHECK: LDS_WRITE +; SI-CHECK_NOT: S_WQM_B64 +; SI-CHECK: DS_WRITE_B32 0 + +; GROUP_BARRIER must be the last instruction in a clause +; EG-CHECK: GROUP_BARRIER +; EG-CHECK-NEXT: ALU clause +; SI-CHECK: S_BARRIER + +; EG-CHECK: LDS_READ_RET +; SI-CHECK: DS_READ_B32 {{v[0-9]+}}, 0 + +define void @local_memory(i32 addrspace(1)* %out) { +entry: + %y.i = call i32 @llvm.r600.read.tidig.x() #0 + %arrayidx = getelementptr inbounds [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %y.i + store i32 %y.i, i32 addrspace(3)* %arrayidx, align 4 + %add = add nsw i32 %y.i, 1 + %cmp = icmp eq i32 %add, 16 + %.add = select i1 %cmp, i32 0, i32 %add + call void @llvm.AMDGPU.barrier.local() + %arrayidx1 = getelementptr inbounds [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %.add + %0 = load i32 addrspace(3)* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %out, i32 %y.i + store i32 %0, i32 addrspace(1)* %arrayidx2, align 4 + ret void +} + +declare i32 @llvm.r600.read.tidig.x() #0 +declare void @llvm.AMDGPU.barrier.local() + +attributes #0 = { readnone } diff --git a/test/CodeGen/R600/loop-address.ll b/test/CodeGen/R600/loop-address.ll index 8a5458b89809..b46d8e9dfb04 100644 --- a/test/CodeGen/R600/loop-address.ll +++ b/test/CodeGen/R600/loop-address.ll @@ -1,13 +1,9 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: TEX ;CHECK: ALU_PUSH -;CHECK: JUMP @4 -;CHECK: ELSE @16 -;CHECK: TEX -;CHECK: LOOP_START_DX10 @15 -;CHECK: LOOP_BREAK @14 -;CHECK: POP @16 +;CHECK: LOOP_START_DX10 @11 +;CHECK: LOOP_BREAK @10 +;CHECK: POP @10 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64" target triple = "r600--" diff --git a/test/CodeGen/R600/lshl.ll b/test/CodeGen/R600/lshl.ll index fb698da62719..216283910009 100644 --- a/test/CodeGen/R600/lshl.ll +++ b/test/CodeGen/R600/lshl.ll @@ -1,6 +1,6 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: V_LSHLREV_B32_e32 VGPR0, 1, VGPR0 +;CHECK: S_LSHL_B32 s{{[0-9]}}, s{{[0-9]}}, 1 define void @test(i32 %p) { %i = mul i32 %p, 2 diff --git a/test/CodeGen/R600/lshr.ll b/test/CodeGen/R600/lshr.ll index e0ed3ac07866..886d1c4854df 100644 --- a/test/CodeGen/R600/lshr.ll +++ b/test/CodeGen/R600/lshr.ll @@ -1,6 +1,6 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0 +;CHECK: S_LSHR_B32 s{{[0-9]}}, s{{[0-9]}}, 1 define void @test(i32 %p) { %i = udiv i32 %p, 2 diff --git a/test/CodeGen/R600/mad_int24.ll b/test/CodeGen/R600/mad_int24.ll new file mode 100644 index 000000000000..df063ece35ae --- /dev/null +++ b/test/CodeGen/R600/mad_int24.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; EG-CHECK: @i32_mad24 +; Signed 24-bit multiply is not supported on pre-Cayman GPUs. +; EG-CHECK: MULLO_INT +; CM-CHECK: MULADD_INT24 {{[ *]*}}T{{[0-9].[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X +; SI-CHECK: V_MAD_I32_I24 +define void @i32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { +entry: + %0 = shl i32 %a, 8 + %a_24 = ashr i32 %0, 8 + %1 = shl i32 %b, 8 + %b_24 = ashr i32 %1, 8 + %2 = mul i32 %a_24, %b_24 + %3 = add i32 %2, %c + store i32 %3, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/mad_uint24.ll b/test/CodeGen/R600/mad_uint24.ll new file mode 100644 index 000000000000..66a070ed9d4a --- /dev/null +++ b/test/CodeGen/R600/mad_uint24.ll @@ -0,0 +1,70 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; EG-CHECK-LABEL: @u32_mad24 +; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X +; SI-CHECK-LABEL: @u32_mad24 +; SI-CHECK: V_MAD_U32_U24 + +define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { +entry: + %0 = shl i32 %a, 8 + %a_24 = lshr i32 %0, 8 + %1 = shl i32 %b, 8 + %b_24 = lshr i32 %1, 8 + %2 = mul i32 %a_24, %b_24 + %3 = add i32 %2, %c + store i32 %3, i32 addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @i16_mad24 +; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40 +; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44 +; EG-CHECK-DAG: VTX_READ_16 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48 +; The order of A and B does not matter. +; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]] +; The result must be sign-extended +; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x +; EG-CHECK: 16 +; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x +; EG-CHECK: 16 +; SI-CHECK-LABEL: @i16_mad24 +; SI-CHECK: V_MAD_U32_U24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}} +; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 16, [[MAD]] +; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 16, [[LSHL]] + +define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) { +entry: + %0 = mul i16 %a, %b + %1 = add i16 %0, %c + %2 = sext i16 %1 to i32 + store i32 %2, i32 addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @i8_mad24 +; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40 +; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44 +; EG-CHECK-DAG: VTX_READ_8 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48 +; The order of A and B does not matter. +; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]] +; The result must be sign-extended +; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x +; EG-CHECK: 24 +; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x +; EG-CHECK: 24 +; SI-CHECK-LABEL: @i8_mad24 +; SI-CHECK: V_MAD_U32_U24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} +; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 24, [[MUL]] +; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 24, [[LSHL]] + +define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) { +entry: + %0 = mul i8 %a, %b + %1 = add i8 %0, %c + %2 = sext i8 %1 to i32 + store i32 %2, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/max-literals.ll b/test/CodeGen/R600/max-literals.ll new file mode 100644 index 000000000000..65a6d2b5fc95 --- /dev/null +++ b/test/CodeGen/R600/max-literals.ll @@ -0,0 +1,67 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @main +; CHECK: ADD * + +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { +main_body: + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg1, i32 3 + %4 = extractelement <4 x float> %reg2, i32 0 + %5 = fadd float %0, 2.0 + %6 = fadd float %1, 3.0 + %7 = fadd float %2, 4.0 + %8 = fadd float %3, 5.0 + %9 = bitcast float %4 to i32 + %10 = mul i32 %9, 6 + %11 = bitcast i32 %10 to float + %12 = insertelement <4 x float> undef, float %5, i32 0 + %13 = insertelement <4 x float> %12, float %6, i32 1 + %14 = insertelement <4 x float> %13, float %7, i32 2 + %15 = insertelement <4 x float> %14, float %8, i32 3 + %16 = insertelement <4 x float> %15, float %11, i32 3 + + %17 = call float @llvm.AMDGPU.dp4(<4 x float> %15,<4 x float> %16) + %18 = insertelement <4 x float> undef, float %17, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) + ret void +} + +; CHECK: @main +; CHECK-NOT: ADD * + +define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { +main_body: + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg1, i32 3 + %4 = extractelement <4 x float> %reg2, i32 0 + %5 = fadd float %0, 2.0 + %6 = fadd float %1, 3.0 + %7 = fadd float %2, 4.0 + %8 = fadd float %3, 2.0 + %9 = bitcast float %4 to i32 + %10 = mul i32 %9, 6 + %11 = bitcast i32 %10 to float + %12 = insertelement <4 x float> undef, float %5, i32 0 + %13 = insertelement <4 x float> %12, float %6, i32 1 + %14 = insertelement <4 x float> %13, float %7, i32 2 + %15 = insertelement <4 x float> %14, float %8, i32 3 + %16 = insertelement <4 x float> %15, float %11, i32 3 + + %17 = call float @llvm.AMDGPU.dp4(<4 x float> %15,<4 x float> %16) + %18 = insertelement <4 x float> undef, float %17, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) + ret void +} + +; Function Attrs: readnone +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } +attributes #1 = { readnone } diff --git a/test/CodeGen/R600/mul.ll b/test/CodeGen/R600/mul.ll index 7278e9039840..8c27e28df164 100644 --- a/test/CodeGen/R600/mul.ll +++ b/test/CodeGen/R600/mul.ll @@ -1,12 +1,38 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ; mul24 and mad24 are affected -;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +;EG-CHECK: @test2 +;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK: @test2 +;SI-CHECK: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 + %a = load <2 x i32> addrspace(1) * %in + %b = load <2 x i32> addrspace(1) * %b_ptr + %result = mul <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +;EG-CHECK: @test4 +;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK: @test4 +;SI-CHECK: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_MUL_LO_I32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 %a = load <4 x i32> addrspace(1) * %in %b = load <4 x i32> addrspace(1) * %b_ptr diff --git a/test/CodeGen/R600/mul_int24.ll b/test/CodeGen/R600/mul_int24.ll new file mode 100644 index 000000000000..66a1a9e5bd99 --- /dev/null +++ b/test/CodeGen/R600/mul_int24.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; EG-CHECK: @i32_mul24 +; Signed 24-bit multiply is not supported on pre-Cayman GPUs. +; EG-CHECK: MULLO_INT +; CM-CHECK: MUL_INT24 {{[ *]*}}T{{[0-9].[XYZW]}}, KC0[2].Z, KC0[2].W +; SI-CHECK: V_MUL_I32_I24 +define void @i32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = shl i32 %a, 8 + %a_24 = ashr i32 %0, 8 + %1 = shl i32 %b, 8 + %b_24 = ashr i32 %1, 8 + %2 = mul i32 %a_24, %b_24 + store i32 %2, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/mul_uint24.ll b/test/CodeGen/R600/mul_uint24.ll new file mode 100644 index 000000000000..6e6d5496789f --- /dev/null +++ b/test/CodeGen/R600/mul_uint24.ll @@ -0,0 +1,65 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; EG-CHECK-LABEL: @u32_mul24 +; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W +; SI-CHECK-LABEL: @u32_mul24 +; SI-CHECK: V_MUL_U32_U24 + +define void @u32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = shl i32 %a, 8 + %a_24 = lshr i32 %0, 8 + %1 = shl i32 %b, 8 + %b_24 = lshr i32 %1, 8 + %2 = mul i32 %a_24, %b_24 + store i32 %2, i32 addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @i16_mul24 +; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40 +; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44 +; The order of A and B does not matter. +; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]] +; The result must be sign-extended +; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MUL_CHAN]], literal.x +; EG-CHECK: 16 +; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x +; EG-CHECK: 16 +; SI-CHECK-LABEL: @i16_mul24 +; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} +; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 16, [[MUL]] +; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 16, [[LSHL]] + +define void @i16_mul24(i32 addrspace(1)* %out, i16 %a, i16 %b) { +entry: + %0 = mul i16 %a, %b + %1 = sext i16 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @i8_mul24 +; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40 +; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44 +; The order of A and B does not matter. +; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]] +; The result must be sign-extended +; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MUL_CHAN]], literal.x +; EG-CHECK: 24 +; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x +; EG-CHECK: 24 +; SI-CHECK-LABEL: @i8_mul24 +; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}} +; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:v[0-9]]], 24, [[MUL]] +; SI-CHECK: V_ASHRREV_I32_e32 v{{[0-9]}}, 24, [[LSHL]] + +define void @i8_mul24(i32 addrspace(1)* %out, i8 %a, i8 %b) { +entry: + %0 = mul i8 %a, %b + %1 = sext i8 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/mulhu.ll b/test/CodeGen/R600/mulhu.ll index bc17a597873e..d5fc01412123 100644 --- a/test/CodeGen/R600/mulhu.ll +++ b/test/CodeGen/R600/mulhu.ll @@ -1,8 +1,8 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: V_MOV_B32_e32 VGPR1, -1431655765 -;CHECK-NEXT: V_MUL_HI_U32 VGPR0, VGPR0, VGPR1, 0, 0, 0, 0, 0 -;CHECK-NEXT: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0 +;CHECK: V_MOV_B32_e32 v{{[0-9]+}}, -1431655765 +;CHECK: V_MUL_HI_U32 v0, {{[sv][0-9]+}}, {{v[0-9]+}} +;CHECK-NEXT: V_LSHRREV_B32_e32 v0, 1, v0 define void @test(i32 %p) { %i = udiv i32 %p, 3 diff --git a/test/CodeGen/R600/or.ll b/test/CodeGen/R600/or.ll index b0dbb021e822..35d23b3d27ad 100644 --- a/test/CodeGen/R600/or.ll +++ b/test/CodeGen/R600/or.ll @@ -1,13 +1,53 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; CHECK: @or_v4i32 -; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG-CHECK-LABEL: @or_v2i32 +; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { +;SI-CHECK-LABEL: @or_v2i32 +;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 + %a = load <2 x i32> addrspace(1) * %in + %b = load <2 x i32> addrspace(1) * %b_ptr + %result = or <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @or_v4i32 +; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK-LABEL: @or_v4i32 +;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_OR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 + %a = load <4 x i32> addrspace(1) * %in + %b = load <4 x i32> addrspace(1) * %b_ptr %result = or <4 x i32> %a, %b store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } + +; EG-CHECK-LABEL: @or_i64 +; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y +; EG-CHECK-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z +; SI-CHECK-LABEL: @or_i64 +; SI-CHECK: V_OR_B32_e32 v{{[0-9]}} +; SI-CHECK: V_OR_B32_e32 v{{[0-9]}} +define void @or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = or i64 %a, %b + store i64 %0, i64 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/packetizer.ll b/test/CodeGen/R600/packetizer.ll new file mode 100644 index 000000000000..0a405c57ea93 --- /dev/null +++ b/test/CodeGen/R600/packetizer.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s + +; CHECK: @test +; CHECK: BIT_ALIGN_INT T{{[0-9]}}.X +; CHECK: BIT_ALIGN_INT T{{[0-9]}}.Y +; CHECK: BIT_ALIGN_INT T{{[0-9]}}.Z +; CHECK: BIT_ALIGN_INT * T{{[0-9]}}.W + +define void @test(i32 addrspace(1)* %out, i32 %x_arg, i32 %y_arg, i32 %z_arg, i32 %w_arg, i32 %e) { +entry: + %shl = sub i32 32, %e + %x = add i32 %x_arg, 1 + %x.0 = shl i32 %x, %shl + %x.1 = lshr i32 %x, %e + %x.2 = or i32 %x.0, %x.1 + %y = add i32 %y_arg, 1 + %y.0 = shl i32 %y, %shl + %y.1 = lshr i32 %y, %e + %y.2 = or i32 %y.0, %y.1 + %z = add i32 %z_arg, 1 + %z.0 = shl i32 %z, %shl + %z.1 = lshr i32 %z, %e + %z.2 = or i32 %z.0, %z.1 + %w = add i32 %w_arg, 1 + %w.0 = shl i32 %w, %shl + %w.1 = lshr i32 %w, %e + %w.2 = or i32 %w.0, %w.1 + %xy = or i32 %x.2, %y.2 + %zw = or i32 %z.2, %w.2 + %xyzw = or i32 %xy, %zw + store i32 %xyzw, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/parallelandifcollapse.ll b/test/CodeGen/R600/parallelandifcollapse.ll new file mode 100644 index 000000000000..4afaf684bfce --- /dev/null +++ b/test/CodeGen/R600/parallelandifcollapse.ll @@ -0,0 +1,54 @@ +; Function Attrs: nounwind +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; +; CFG flattening should use parallel-and mode to generate branch conditions and +; then merge if-regions with the same bodies. +; +; CHECK: AND_INT +; CHECK-NEXT: AND_INT +; CHECK-NEXT: OR_INT +define void @_Z9chk1D_512v() #0 { +entry: + %a0 = alloca i32, align 4 + %b0 = alloca i32, align 4 + %c0 = alloca i32, align 4 + %d0 = alloca i32, align 4 + %a1 = alloca i32, align 4 + %b1 = alloca i32, align 4 + %c1 = alloca i32, align 4 + %d1 = alloca i32, align 4 + %data = alloca i32, align 4 + %0 = load i32* %a0, align 4 + %1 = load i32* %b0, align 4 + %cmp = icmp ne i32 %0, %1 + br i1 %cmp, label %land.lhs.true, label %if.end + +land.lhs.true: ; preds = %entry + %2 = load i32* %c0, align 4 + %3 = load i32* %d0, align 4 + %cmp1 = icmp ne i32 %2, %3 + br i1 %cmp1, label %if.then, label %if.end + +if.then: ; preds = %land.lhs.true + store i32 1, i32* %data, align 4 + br label %if.end + +if.end: ; preds = %if.then, %land.lhs.true, %entry + %4 = load i32* %a1, align 4 + %5 = load i32* %b1, align 4 + %cmp2 = icmp ne i32 %4, %5 + br i1 %cmp2, label %land.lhs.true3, label %if.end6 + +land.lhs.true3: ; preds = %if.end + %6 = load i32* %c1, align 4 + %7 = load i32* %d1, align 4 + %cmp4 = icmp ne i32 %6, %7 + br i1 %cmp4, label %if.then5, label %if.end6 + +if.then5: ; preds = %land.lhs.true3 + store i32 1, i32* %data, align 4 + br label %if.end6 + +if.end6: ; preds = %if.then5, %land.lhs.true3, %if.end + ret void +} diff --git a/test/CodeGen/R600/parallelorifcollapse.ll b/test/CodeGen/R600/parallelorifcollapse.ll new file mode 100644 index 000000000000..b0db7cdd0671 --- /dev/null +++ b/test/CodeGen/R600/parallelorifcollapse.ll @@ -0,0 +1,61 @@ +; Function Attrs: nounwind +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; +; CFG flattening should use parallel-or to generate branch conditions and +; then merge if-regions with the same bodies. +; +; CHECK: OR_INT +; CHECK-NEXT: OR_INT +; CHECK-NEXT: OR_INT +define void @_Z9chk1D_512v() #0 { +entry: + %a0 = alloca i32, align 4 + %b0 = alloca i32, align 4 + %c0 = alloca i32, align 4 + %d0 = alloca i32, align 4 + %a1 = alloca i32, align 4 + %b1 = alloca i32, align 4 + %c1 = alloca i32, align 4 + %d1 = alloca i32, align 4 + %data = alloca i32, align 4 + %0 = load i32* %a0, align 4 + %1 = load i32* %b0, align 4 + %cmp = icmp ne i32 %0, %1 + br i1 %cmp, label %land.lhs.true, label %if.else + +land.lhs.true: ; preds = %entry + %2 = load i32* %c0, align 4 + %3 = load i32* %d0, align 4 + %cmp1 = icmp ne i32 %2, %3 + br i1 %cmp1, label %if.then, label %if.else + +if.then: ; preds = %land.lhs.true + br label %if.end + +if.else: ; preds = %land.lhs.true, %entry + store i32 1, i32* %data, align 4 + br label %if.end + +if.end: ; preds = %if.else, %if.then + %4 = load i32* %a1, align 4 + %5 = load i32* %b1, align 4 + %cmp2 = icmp ne i32 %4, %5 + br i1 %cmp2, label %land.lhs.true3, label %if.else6 + +land.lhs.true3: ; preds = %if.end + %6 = load i32* %c1, align 4 + %7 = load i32* %d1, align 4 + %cmp4 = icmp ne i32 %6, %7 + br i1 %cmp4, label %if.then5, label %if.else6 + +if.then5: ; preds = %land.lhs.true3 + br label %if.end7 + +if.else6: ; preds = %land.lhs.true3, %if.end + store i32 1, i32* %data, align 4 + br label %if.end7 + +if.end7: ; preds = %if.else6, %if.then5 + ret void +} + diff --git a/test/CodeGen/R600/predicate-dp4.ll b/test/CodeGen/R600/predicate-dp4.ll new file mode 100644 index 000000000000..e48d6a7aa9a8 --- /dev/null +++ b/test/CodeGen/R600/predicate-dp4.ll @@ -0,0 +1,27 @@ +;RUN: llc < %s -march=r600 -mcpu=cayman + +; CHECK-LABEL: @main +; CHECK: PRED_SETE_INT * Pred, +; CHECK: DOT4 T{{[0-9]+}}.X, T0.X, T0.X, Pred_sel_one +define void @main(<4 x float> inreg) #0 { +main_body: + %1 = extractelement <4 x float> %0, i32 0 + %2 = bitcast float %1 to i32 + %3 = icmp eq i32 %2, 0 + br i1 %3, label %IF, label %ENDIF + +IF: ; preds = %main_body + %4 = call float @llvm.AMDGPU.dp4(<4 x float> %0, <4 x float> %0) + br label %ENDIF + +ENDIF: ; preds = %IF, %main_body + %5 = phi float [%4, %IF], [0.000000e+00, %main_body] + %6 = insertelement <4 x float> undef, float %5, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %6, i32 0, i32 0) + ret void +} + +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +attributes #1 = { readnone } +attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/R600/predicates.ll b/test/CodeGen/R600/predicates.ll index 0d3eeef26307..902508ff9e05 100644 --- a/test/CodeGen/R600/predicates.ll +++ b/test/CodeGen/R600/predicates.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mattr=disable-irstructurizer -mcpu=redwood | FileCheck %s ; These tests make sure the compiler is optimizing branches using predicates ; when it is legal to do so. diff --git a/test/CodeGen/R600/private-memory.ll b/test/CodeGen/R600/private-memory.ll new file mode 100644 index 000000000000..48a013c8e549 --- /dev/null +++ b/test/CodeGen/R600/private-memory.ll @@ -0,0 +1,115 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK + +; This test checks that uses and defs of the AR register happen in the same +; instruction clause. + +; R600-CHECK-LABEL: @mova_same_clause +; R600-CHECK: MOVA_INT +; R600-CHECK-NOT: ALU clause +; R600-CHECK: 0 + AR.x +; R600-CHECK: MOVA_INT +; R600-CHECK-NOT: ALU clause +; R600-CHECK: 0 + AR.x + +; SI-CHECK-LABEL: @mova_same_clause +; SI-CHECK: V_READFIRSTLANE +; SI-CHECK: V_MOVRELD +; SI-CHECK: S_CBRANCH +; SI-CHECK: V_READFIRSTLANE +; SI-CHECK: V_MOVRELD +; SI-CHECK: S_CBRANCH +define void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { +entry: + %stack = alloca [5 x i32], align 4 + %0 = load i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %in, i32 1 + %1 = load i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 0 + %2 = load i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32]* %stack, i32 0, i32 1 + %3 = load i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} + +; This test checks that the stack offset is calculated correctly for structs. +; All register loads/stores should be optimized away, so there shouldn't be +; any MOVA instructions. +; +; XXX: This generated code has unnecessary MOVs, we should be able to optimize +; this. + +; R600-CHECK-LABEL: @multiple_structs +; R600-CHECK-NOT: MOVA_INT +; SI-CHECK-LABEL: @multiple_structs +; SI-CHECK-NOT: V_MOVREL +%struct.point = type { i32, i32 } + +define void @multiple_structs(i32 addrspace(1)* %out) { +entry: + %a = alloca %struct.point + %b = alloca %struct.point + %a.x.ptr = getelementptr %struct.point* %a, i32 0, i32 0 + %a.y.ptr = getelementptr %struct.point* %a, i32 0, i32 1 + %b.x.ptr = getelementptr %struct.point* %b, i32 0, i32 0 + %b.y.ptr = getelementptr %struct.point* %b, i32 0, i32 1 + store i32 0, i32* %a.x.ptr + store i32 1, i32* %a.y.ptr + store i32 2, i32* %b.x.ptr + store i32 3, i32* %b.y.ptr + %a.indirect.ptr = getelementptr %struct.point* %a, i32 0, i32 0 + %b.indirect.ptr = getelementptr %struct.point* %b, i32 0, i32 0 + %a.indirect = load i32* %a.indirect.ptr + %b.indirect = load i32* %b.indirect.ptr + %0 = add i32 %a.indirect, %b.indirect + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; Test direct access of a private array inside a loop. The private array +; loads and stores should be lowered to copies, so there shouldn't be any +; MOVA instructions. + +; R600-CHECK-LABLE: @direct_loop +; R600-CHECK-NOT: MOVA_INT +; SI-CHECK-LABEL: @direct_loop +; SI-CHECK-NOT: V_MOVREL + +define void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +entry: + %prv_array_const = alloca [2 x i32] + %prv_array = alloca [2 x i32] + %a = load i32 addrspace(1)* %in + %b_src_ptr = getelementptr i32 addrspace(1)* %in, i32 1 + %b = load i32 addrspace(1)* %b_src_ptr + %a_dst_ptr = getelementptr [2 x i32]* %prv_array_const, i32 0, i32 0 + store i32 %a, i32* %a_dst_ptr + %b_dst_ptr = getelementptr [2 x i32]* %prv_array_const, i32 0, i32 1 + store i32 %b, i32* %b_dst_ptr + br label %for.body + +for.body: + %inc = phi i32 [0, %entry], [%count, %for.body] + %x_ptr = getelementptr [2 x i32]* %prv_array_const, i32 0, i32 0 + %x = load i32* %x_ptr + %y_ptr = getelementptr [2 x i32]* %prv_array, i32 0, i32 0 + %y = load i32* %y_ptr + %xy = add i32 %x, %y + store i32 %xy, i32* %y_ptr + %count = add i32 %inc, 1 + %done = icmp eq i32 %count, 4095 + br i1 %done, label %for.end, label %for.body + +for.end: + %value_ptr = getelementptr [2 x i32]* %prv_array, i32 0, i32 0 + %value = load i32* %value_ptr + store i32 %value, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/pv-packing.ll b/test/CodeGen/R600/pv-packing.ll new file mode 100644 index 000000000000..e5615b99728e --- /dev/null +++ b/test/CodeGen/R600/pv-packing.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s + +;CHECK: DOT4 T{{[0-9]\.X}} +;CHECK: MULADD_IEEE * T{{[0-9]\.W}} + +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 { +main_body: + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg2, i32 0 + %4 = extractelement <4 x float> %reg2, i32 1 + %5 = extractelement <4 x float> %reg2, i32 2 + %6 = extractelement <4 x float> %reg3, i32 0 + %7 = extractelement <4 x float> %reg3, i32 1 + %8 = extractelement <4 x float> %reg3, i32 2 + %9 = load <4 x float> addrspace(8)* null + %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %11 = call float @llvm.AMDGPU.dp4(<4 x float> %9, <4 x float> %9) + %12 = fmul float %0, %3 + %13 = fadd float %12, %6 + %14 = fmul float %1, %4 + %15 = fadd float %14, %7 + %16 = fmul float %2, %5 + %17 = fadd float %16, %8 + %18 = fmul float %11, %11 + %19 = fadd float %18, %0 + %20 = insertelement <4 x float> undef, float %13, i32 0 + %21 = insertelement <4 x float> %20, float %15, i32 1 + %22 = insertelement <4 x float> %21, float %17, i32 2 + %23 = insertelement <4 x float> %22, float %19, i32 3 + %24 = call float @llvm.AMDGPU.dp4(<4 x float> %23, <4 x float> %10) + %25 = insertelement <4 x float> undef, float %24, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %25, i32 0, i32 2) + ret void +} + +; Function Attrs: readnone +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 + + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } +attributes #1 = { readnone } diff --git a/test/CodeGen/R600/pv.ll b/test/CodeGen/R600/pv.ll index 37c3d9d7d6d1..5a930b292682 100644 --- a/test/CodeGen/R600/pv.ll +++ b/test/CodeGen/R600/pv.ll @@ -1,38 +1,38 @@ ; RUN: llc < %s -march=r600 | FileCheck %s ;CHECK: DOT4 * T{{[0-9]\.W}} (MASKED) -;CHECK-NEXT: CNDGE T{{[0-9].[XYZW]}}, PV.x +;CHECK: MAX T{{[0-9].[XYZW]}}, 0.0, PV.X -define void @main() #0 { +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) #0 { main_body: - %0 = call float @llvm.R600.load.input(i32 4) - %1 = call float @llvm.R600.load.input(i32 5) - %2 = call float @llvm.R600.load.input(i32 6) - %3 = call float @llvm.R600.load.input(i32 7) - %4 = call float @llvm.R600.load.input(i32 8) - %5 = call float @llvm.R600.load.input(i32 9) - %6 = call float @llvm.R600.load.input(i32 10) - %7 = call float @llvm.R600.load.input(i32 11) - %8 = call float @llvm.R600.load.input(i32 12) - %9 = call float @llvm.R600.load.input(i32 13) - %10 = call float @llvm.R600.load.input(i32 14) - %11 = call float @llvm.R600.load.input(i32 15) - %12 = call float @llvm.R600.load.input(i32 16) - %13 = call float @llvm.R600.load.input(i32 17) - %14 = call float @llvm.R600.load.input(i32 18) - %15 = call float @llvm.R600.load.input(i32 19) - %16 = call float @llvm.R600.load.input(i32 20) - %17 = call float @llvm.R600.load.input(i32 21) - %18 = call float @llvm.R600.load.input(i32 22) - %19 = call float @llvm.R600.load.input(i32 23) - %20 = call float @llvm.R600.load.input(i32 24) - %21 = call float @llvm.R600.load.input(i32 25) - %22 = call float @llvm.R600.load.input(i32 26) - %23 = call float @llvm.R600.load.input(i32 27) - %24 = call float @llvm.R600.load.input(i32 28) - %25 = call float @llvm.R600.load.input(i32 29) - %26 = call float @llvm.R600.load.input(i32 30) - %27 = call float @llvm.R600.load.input(i32 31) + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg1, i32 3 + %4 = extractelement <4 x float> %reg2, i32 0 + %5 = extractelement <4 x float> %reg2, i32 1 + %6 = extractelement <4 x float> %reg2, i32 2 + %7 = extractelement <4 x float> %reg2, i32 3 + %8 = extractelement <4 x float> %reg3, i32 0 + %9 = extractelement <4 x float> %reg3, i32 1 + %10 = extractelement <4 x float> %reg3, i32 2 + %11 = extractelement <4 x float> %reg3, i32 3 + %12 = extractelement <4 x float> %reg4, i32 0 + %13 = extractelement <4 x float> %reg4, i32 1 + %14 = extractelement <4 x float> %reg4, i32 2 + %15 = extractelement <4 x float> %reg4, i32 3 + %16 = extractelement <4 x float> %reg5, i32 0 + %17 = extractelement <4 x float> %reg5, i32 1 + %18 = extractelement <4 x float> %reg5, i32 2 + %19 = extractelement <4 x float> %reg5, i32 3 + %20 = extractelement <4 x float> %reg6, i32 0 + %21 = extractelement <4 x float> %reg6, i32 1 + %22 = extractelement <4 x float> %reg6, i32 2 + %23 = extractelement <4 x float> %reg6, i32 3 + %24 = extractelement <4 x float> %reg7, i32 0 + %25 = extractelement <4 x float> %reg7, i32 1 + %26 = extractelement <4 x float> %reg7, i32 2 + %27 = extractelement <4 x float> %reg7, i32 3 %28 = load <4 x float> addrspace(8)* null %29 = extractelement <4 x float> %28, i32 0 %30 = fmul float %0, %29 @@ -219,9 +219,6 @@ main_body: } ; Function Attrs: readnone -declare float @llvm.R600.load.input(i32) #1 - -; Function Attrs: readnone declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly diff --git a/test/CodeGen/R600/r600-encoding.ll b/test/CodeGen/R600/r600-encoding.ll index c8040a1b4cd5..b760c882f4e3 100644 --- a/test/CodeGen/R600/r600-encoding.ll +++ b/test/CodeGen/R600/r600-encoding.ll @@ -5,20 +5,21 @@ ; the VLIW4/5 GPUs. ; EG-CHECK: @test -; EG-CHECK: MUL_IEEE {{[ *TXYZW.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}] +; EG-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}] ; R600-CHECK: @test -; R600-CHECK: MUL_IEEE {{[ *TXYZW.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}] +; R600-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}] -define void @test() { +define void @test(<4 x float> inreg %reg0) #0 { entry: - %0 = call float @llvm.R600.load.input(i32 0) - %1 = call float @llvm.R600.load.input(i32 1) - %2 = fmul float %0, %1 - call void @llvm.AMDGPU.store.output(float %2, i32 0) + %r0 = extractelement <4 x float> %reg0, i32 0 + %r1 = extractelement <4 x float> %reg0, i32 1 + %r2 = fmul float %r0, %r1 + %vec = insertelement <4 x float> undef, float %r2, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare float @llvm.R600.load.input(i32) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -declare void @llvm.AMDGPU.store.output(float, i32) +attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/R600/r600-export-fix.ll b/test/CodeGen/R600/r600-export-fix.ll new file mode 100644 index 000000000000..73bc0635ab21 --- /dev/null +++ b/test/CodeGen/R600/r600-export-fix.ll @@ -0,0 +1,142 @@ +; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s + +;CHECK: EXPORT T{{[0-9]}}.XYZW +;CHECK: EXPORT T{{[0-9]}}.0000 +;CHECK: EXPORT T{{[0-9]}}.0000 +;CHECK: EXPORT T{{[0-9]}}.0XZW +;CHECK: EXPORT T{{[0-9]}}.XYZW +;CHECK: EXPORT T{{[0-9]}}.YX00 +;CHECK: EXPORT T{{[0-9]}}.0000 +;CHECK: EXPORT T{{[0-9]}}.0000 + + +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +main_body: + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg1, i32 3 + %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %5 = extractelement <4 x float> %4, i32 0 + %6 = fmul float %5, %0 + %7 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %8 = extractelement <4 x float> %7, i32 1 + %9 = fmul float %8, %0 + %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %11 = extractelement <4 x float> %10, i32 2 + %12 = fmul float %11, %0 + %13 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %14 = extractelement <4 x float> %13, i32 3 + %15 = fmul float %14, %0 + %16 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %17 = extractelement <4 x float> %16, i32 0 + %18 = fmul float %17, %1 + %19 = fadd float %18, %6 + %20 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %21 = extractelement <4 x float> %20, i32 1 + %22 = fmul float %21, %1 + %23 = fadd float %22, %9 + %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %25 = extractelement <4 x float> %24, i32 2 + %26 = fmul float %25, %1 + %27 = fadd float %26, %12 + %28 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %29 = extractelement <4 x float> %28, i32 3 + %30 = fmul float %29, %1 + %31 = fadd float %30, %15 + %32 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) + %33 = extractelement <4 x float> %32, i32 0 + %34 = fmul float %33, %2 + %35 = fadd float %34, %19 + %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) + %37 = extractelement <4 x float> %36, i32 1 + %38 = fmul float %37, %2 + %39 = fadd float %38, %23 + %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) + %41 = extractelement <4 x float> %40, i32 2 + %42 = fmul float %41, %2 + %43 = fadd float %42, %27 + %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) + %45 = extractelement <4 x float> %44, i32 3 + %46 = fmul float %45, %2 + %47 = fadd float %46, %31 + %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %49 = extractelement <4 x float> %48, i32 0 + %50 = fmul float %49, %3 + %51 = fadd float %50, %35 + %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %53 = extractelement <4 x float> %52, i32 1 + %54 = fmul float %53, %3 + %55 = fadd float %54, %39 + %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %57 = extractelement <4 x float> %56, i32 2 + %58 = fmul float %57, %3 + %59 = fadd float %58, %43 + %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %61 = extractelement <4 x float> %60, i32 3 + %62 = fmul float %61, %3 + %63 = fadd float %62, %47 + %64 = load <4 x float> addrspace(8)* null + %65 = extractelement <4 x float> %64, i32 0 + %66 = load <4 x float> addrspace(8)* null + %67 = extractelement <4 x float> %66, i32 1 + %68 = load <4 x float> addrspace(8)* null + %69 = extractelement <4 x float> %68, i32 2 + %70 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %71 = extractelement <4 x float> %70, i32 0 + %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %73 = extractelement <4 x float> %72, i32 1 + %74 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %75 = extractelement <4 x float> %74, i32 2 + %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %77 = extractelement <4 x float> %76, i32 0 + %78 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %79 = extractelement <4 x float> %78, i32 1 + %80 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %81 = extractelement <4 x float> %80, i32 2 + %82 = insertelement <4 x float> undef, float %51, i32 0 + %83 = insertelement <4 x float> %82, float %55, i32 1 + %84 = insertelement <4 x float> %83, float %59, i32 2 + %85 = insertelement <4 x float> %84, float %63, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %85, i32 60, i32 1) + %86 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 + %87 = insertelement <4 x float> %86, float 0.000000e+00, i32 1 + %88 = insertelement <4 x float> %87, float 0.000000e+00, i32 2 + %89 = insertelement <4 x float> %88, float 0.000000e+00, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %89, i32 0, i32 2) + %90 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 + %91 = insertelement <4 x float> %90, float 0.000000e+00, i32 1 + %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 2 + %93 = insertelement <4 x float> %92, float 0.000000e+00, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %93, i32 1, i32 2) + %94 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 + %95 = insertelement <4 x float> %94, float %65, i32 1 + %96 = insertelement <4 x float> %95, float %67, i32 2 + %97 = insertelement <4 x float> %96, float %69, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %97, i32 2, i32 2) + %98 = insertelement <4 x float> undef, float %77, i32 0 + %99 = insertelement <4 x float> %98, float %79, i32 1 + %100 = insertelement <4 x float> %99, float %81, i32 2 + %101 = insertelement <4 x float> %100, float %71, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %101, i32 3, i32 2) + %102 = insertelement <4 x float> undef, float %73, i32 0 + %103 = insertelement <4 x float> %102, float %75, i32 1 + %104 = insertelement <4 x float> %103, float 0.000000e+00, i32 2 + %105 = insertelement <4 x float> %104, float 0.000000e+00, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %105, i32 4, i32 2) + %106 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 + %107 = insertelement <4 x float> %106, float 0.000000e+00, i32 1 + %108 = insertelement <4 x float> %107, float 0.000000e+00, i32 2 + %109 = insertelement <4 x float> %108, float 0.000000e+00, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %109, i32 5, i32 2) + %110 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 + %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 1 + %112 = insertelement <4 x float> %111, float 0.000000e+00, i32 2 + %113 = insertelement <4 x float> %112, float 0.000000e+00, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %113, i32 6, i32 2) + ret void +} + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } diff --git a/test/CodeGen/R600/r600cfg.ll b/test/CodeGen/R600/r600cfg.ll new file mode 100644 index 000000000000..6dee3ef89cf5 --- /dev/null +++ b/test/CodeGen/R600/r600cfg.ll @@ -0,0 +1,120 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood +;REQUIRES: asserts + +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +main_body: + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg1, i32 3 + %4 = bitcast float %0 to i32 + %5 = icmp eq i32 %4, 0 + %6 = sext i1 %5 to i32 + %7 = bitcast i32 %6 to float + %8 = bitcast float %7 to i32 + %9 = icmp ne i32 %8, 0 + %. = select i1 %9, float 0x36A0000000000000, float %0 + br label %LOOP + +LOOP: ; preds = %LOOP47, %main_body + %temp12.0 = phi float [ 0x36A0000000000000, %main_body ], [ %temp12.1, %LOOP47 ] + %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %38, %LOOP47 ] + %temp4.1 = phi float [ %., %main_body ], [ %52, %LOOP47 ] + %10 = bitcast float %temp4.1 to i32 + %11 = icmp eq i32 %10, 1 + %12 = sext i1 %11 to i32 + %13 = bitcast i32 %12 to float + %14 = bitcast float %13 to i32 + %15 = icmp ne i32 %14, 0 + br i1 %15, label %IF41, label %ENDIF40 + +IF41: ; preds = %LOOP + %16 = insertelement <4 x float> undef, float %0, i32 0 + %17 = insertelement <4 x float> %16, float %temp8.0, i32 1 + %18 = insertelement <4 x float> %17, float %temp12.0, i32 2 + %19 = insertelement <4 x float> %18, float 0.000000e+00, i32 3 + call void @llvm.R600.store.stream.output(<4 x float> %19, i32 0, i32 0, i32 1) + %20 = insertelement <4 x float> undef, float %0, i32 0 + %21 = insertelement <4 x float> %20, float %temp8.0, i32 1 + %22 = insertelement <4 x float> %21, float %temp12.0, i32 2 + %23 = insertelement <4 x float> %22, float 0.000000e+00, i32 3 + call void @llvm.R600.store.stream.output(<4 x float> %23, i32 0, i32 0, i32 2) + %24 = insertelement <4 x float> undef, float %0, i32 0 + %25 = insertelement <4 x float> %24, float %temp8.0, i32 1 + %26 = insertelement <4 x float> %25, float %temp12.0, i32 2 + %27 = insertelement <4 x float> %26, float 0.000000e+00, i32 3 + call void @llvm.R600.store.stream.output(<4 x float> %27, i32 0, i32 0, i32 4) + %28 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 + %29 = insertelement <4 x float> %28, float 0.000000e+00, i32 1 + %30 = insertelement <4 x float> %29, float 0.000000e+00, i32 2 + %31 = insertelement <4 x float> %30, float 0.000000e+00, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %31, i32 60, i32 1) + %32 = insertelement <4 x float> undef, float %0, i32 0 + %33 = insertelement <4 x float> %32, float %temp8.0, i32 1 + %34 = insertelement <4 x float> %33, float %temp12.0, i32 2 + %35 = insertelement <4 x float> %34, float 0.000000e+00, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %35, i32 0, i32 2) + ret void + +ENDIF40: ; preds = %LOOP + %36 = bitcast float %temp8.0 to i32 + %37 = add i32 %36, 1 + %38 = bitcast i32 %37 to float + %39 = bitcast float %temp4.1 to i32 + %40 = urem i32 %39, 2 + %41 = bitcast i32 %40 to float + %42 = bitcast float %41 to i32 + %43 = icmp eq i32 %42, 0 + %44 = sext i1 %43 to i32 + %45 = bitcast i32 %44 to float + %46 = bitcast float %45 to i32 + %47 = icmp ne i32 %46, 0 + %48 = bitcast float %temp4.1 to i32 + br i1 %47, label %IF44, label %ELSE45 + +IF44: ; preds = %ENDIF40 + %49 = udiv i32 %48, 2 + br label %ENDIF43 + +ELSE45: ; preds = %ENDIF40 + %50 = mul i32 3, %48 + %51 = add i32 %50, 1 + br label %ENDIF43 + +ENDIF43: ; preds = %ELSE45, %IF44 + %.sink = phi i32 [ %49, %IF44 ], [ %51, %ELSE45 ] + %52 = bitcast i32 %.sink to float + %53 = load <4 x float> addrspace(8)* null + %54 = extractelement <4 x float> %53, i32 0 + %55 = bitcast float %54 to i32 + br label %LOOP47 + +LOOP47: ; preds = %ENDIF48, %ENDIF43 + %temp12.1 = phi float [ %temp12.0, %ENDIF43 ], [ %67, %ENDIF48 ] + %temp28.0 = phi float [ 0.000000e+00, %ENDIF43 ], [ %70, %ENDIF48 ] + %56 = bitcast float %temp28.0 to i32 + %57 = icmp uge i32 %56, %55 + %58 = sext i1 %57 to i32 + %59 = bitcast i32 %58 to float + %60 = bitcast float %59 to i32 + %61 = icmp ne i32 %60, 0 + br i1 %61, label %LOOP, label %ENDIF48 + +ENDIF48: ; preds = %LOOP47 + %62 = bitcast float %temp12.1 to i32 + %63 = mul i32 %62, 2 + %64 = bitcast i32 %63 to float + %65 = bitcast float %64 to i32 + %66 = urem i32 %65, 2147483647 + %67 = bitcast i32 %66 to float + %68 = bitcast float %temp28.0 to i32 + %69 = add i32 %68, 1 + %70 = bitcast i32 %69 to float + br label %LOOP47 +} + +declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } diff --git a/test/CodeGen/R600/reciprocal.ll b/test/CodeGen/R600/reciprocal.ll index 27839296703f..b4ac47afced7 100644 --- a/test/CodeGen/R600/reciprocal.ll +++ b/test/CodeGen/R600/reciprocal.ll @@ -2,15 +2,14 @@ ;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test() { - %r0 = call float @llvm.R600.load.input(i32 0) +define void @test(<4 x float> inreg %reg0) #0 { + %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = fdiv float 1.0, %r0 - call void @llvm.AMDGPU.store.output(float %r1, i32 0) + %vec = insertelement <4 x float> undef, float %r1, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare float @llvm.R600.load.input(i32) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -declare void @llvm.AMDGPU.store.output(float, i32) - -declare float @llvm.AMDGPU.rcp(float ) readnone +attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/R600/rotr.ll b/test/CodeGen/R600/rotr.ll new file mode 100644 index 000000000000..edf7aeebea0f --- /dev/null +++ b/test/CodeGen/R600/rotr.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s + +; R600-CHECK-LABEL: @rotr: +; R600-CHECK: BIT_ALIGN_INT + +; SI-CHECK-LABEL: @rotr: +; SI-CHECK: V_ALIGNBIT_B32 +define void @rotr(i32 addrspace(1)* %in, i32 %x, i32 %y) { +entry: + %0 = sub i32 32, %y + %1 = shl i32 %x, %0 + %2 = lshr i32 %x, %y + %3 = or i32 %1, %2 + store i32 %3, i32 addrspace(1)* %in + ret void +} + +; R600-CHECK-LABEL: @rotl: +; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x +; R600-CHECK-NEXT: 32 +; R600-CHECK: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}} + + +; SI-CHECK-LABEL: @rotl: +; SI-CHECK: S_SUB_I32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}} +; SI-CHECK: V_MOV_B32_e32 [[VDST:v[0-9]+]], [[SDST]] +; SI-CHECK: V_ALIGNBIT_B32 {{v[0-9]+, [s][0-9]+, v[0-9]+}}, [[VDST]] +define void @rotl(i32 addrspace(1)* %in, i32 %x, i32 %y) { +entry: + %0 = shl i32 %x, %y + %1 = sub i32 32, %y + %2 = lshr i32 %x, %1 + %3 = or i32 %0, %2 + store i32 %3, i32 addrspace(1)* %in + ret void +} diff --git a/test/CodeGen/R600/rv7x0_count3.ll b/test/CodeGen/R600/rv7x0_count3.ll new file mode 100644 index 000000000000..c3fd923e4593 --- /dev/null +++ b/test/CodeGen/R600/rv7x0_count3.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s + +; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80] + +define void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { + %1 = extractelement <4 x float> %reg1, i32 0 + %2 = extractelement <4 x float> %reg1, i32 1 + %3 = extractelement <4 x float> %reg1, i32 2 + %4 = extractelement <4 x float> %reg1, i32 3 + %5 = insertelement <4 x float> undef, float %1, i32 0 + %6 = insertelement <4 x float> %5, float %2, i32 1 + %7 = insertelement <4 x float> %6, float %3, i32 2 + %8 = insertelement <4 x float> %7, float %4, i32 3 + %9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1) + %10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 1, i32 0, i32 1) + %11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 2, i32 0, i32 1) + %12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 3, i32 0, i32 1) + %13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 4, i32 0, i32 1) + %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 5, i32 0, i32 1) + %15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 6, i32 0, i32 1) + %16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 7, i32 0, i32 1) + %17 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 8, i32 0, i32 1) + %18 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 9, i32 0, i32 1) + %19 = fadd <4 x float> %9, %10 + %20 = fadd <4 x float> %19, %11 + %21 = fadd <4 x float> %20, %12 + %22 = fadd <4 x float> %21, %13 + %23 = fadd <4 x float> %22, %14 + %24 = fadd <4 x float> %23, %15 + %25 = fadd <4 x float> %24, %16 + %26 = fadd <4 x float> %25, %17 + %27 = fadd <4 x float> %26, %18 + call void @llvm.R600.store.swizzle(<4 x float> %27, i32 0, i32 2) + ret void +} + +declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } diff --git a/test/CodeGen/R600/schedule-fs-loop-nested-if.ll b/test/CodeGen/R600/schedule-fs-loop-nested-if.ll index ba9620c40a49..11e8f5176f44 100644 --- a/test/CodeGen/R600/schedule-fs-loop-nested-if.ll +++ b/test/CodeGen/R600/schedule-fs-loop-nested-if.ll @@ -1,12 +1,12 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched +;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts -define void @main() { +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #1 { main_body: - %0 = call float @llvm.R600.interp.input(i32 0, i32 0) - %1 = call float @llvm.R600.interp.input(i32 1, i32 0) - %2 = call float @llvm.R600.interp.input(i32 2, i32 0) - %3 = call float @llvm.R600.interp.input(i32 3, i32 0) + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg1, i32 3 %4 = fcmp ult float %1, 0.000000e+00 %5 = select i1 %4, float 1.000000e+00, float 0.000000e+00 %6 = fsub float -0.000000e+00, %5 @@ -74,10 +74,9 @@ ELSE17: ; preds = %ELSE br label %ENDIF } -declare float @llvm.R600.interp.input(i32, i32) #0 - declare float @llvm.AMDIL.clamp.(float, float, float) #0 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { readnone } +attributes #1 = { "ShaderType"="1" } diff --git a/test/CodeGen/R600/schedule-fs-loop-nested.ll b/test/CodeGen/R600/schedule-fs-loop-nested.ll index 5e875c49ab51..b917ec6413e9 100644 --- a/test/CodeGen/R600/schedule-fs-loop-nested.ll +++ b/test/CodeGen/R600/schedule-fs-loop-nested.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched +;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts define void @main() { diff --git a/test/CodeGen/R600/schedule-fs-loop.ll b/test/CodeGen/R600/schedule-fs-loop.ll index d142cacd4335..d6c194b19b27 100644 --- a/test/CodeGen/R600/schedule-fs-loop.ll +++ b/test/CodeGen/R600/schedule-fs-loop.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched +;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts define void @main() { diff --git a/test/CodeGen/R600/schedule-if-2.ll b/test/CodeGen/R600/schedule-if-2.ll index 6afd6772926b..38aad1850f81 100644 --- a/test/CodeGen/R600/schedule-if-2.ll +++ b/test/CodeGen/R600/schedule-if-2.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched +;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts define void @main() { diff --git a/test/CodeGen/R600/schedule-if.ll b/test/CodeGen/R600/schedule-if.ll index 347d92fd6a0e..f960c9323940 100644 --- a/test/CodeGen/R600/schedule-if.ll +++ b/test/CodeGen/R600/schedule-if.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched +;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts define void @main() { diff --git a/test/CodeGen/R600/schedule-vs-if-nested-loop.ll b/test/CodeGen/R600/schedule-vs-if-nested-loop.ll index 44b7c2f68002..33b20d36737b 100644 --- a/test/CodeGen/R600/schedule-vs-if-nested-loop.ll +++ b/test/CodeGen/R600/schedule-vs-if-nested-loop.ll @@ -1,12 +1,12 @@ ;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched ;REQUIRES: asserts -define void @main() { +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { main_body: - %0 = call float @llvm.R600.load.input(i32 4) - %1 = call float @llvm.R600.load.input(i32 5) - %2 = call float @llvm.R600.load.input(i32 6) - %3 = call float @llvm.R600.load.input(i32 7) + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg1, i32 3 %4 = fcmp ult float %0, 0.000000e+00 %5 = select i1 %4, float 1.000000e+00, float 0.000000e+00 %6 = fsub float -0.000000e+00, %5 @@ -127,8 +127,6 @@ ENDIF19: ; preds = %ENDIF16 br label %LOOP } -declare float @llvm.R600.load.input(i32) #0 - declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { readnone } +attributes #0 = { "ShaderType"="1" } diff --git a/test/CodeGen/R600/select.ll b/test/CodeGen/R600/select.ll new file mode 100644 index 000000000000..f9401424ac12 --- /dev/null +++ b/test/CodeGen/R600/select.ll @@ -0,0 +1,46 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; Normally icmp + select is optimized to select_cc, when this happens the +; DAGLegalizer never sees the select and doesn't have a chance to leaglize it. +; +; In order to avoid the select_cc optimization, this test case calculates the +; condition for the select in a separate basic block. + +; CHECK-LABEL: @select +; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X +; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.X +; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY +; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY +; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW +; CHECK-DAG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW +define void @select (i32 addrspace(1)* %i32out, float addrspace(1)* %f32out, + <2 x i32> addrspace(1)* %v2i32out, <2 x float> addrspace(1)* %v2f32out, + <4 x i32> addrspace(1)* %v4i32out, <4 x float> addrspace(1)* %v4f32out, + i32 %cond) { +entry: + br label %for +body: + %inc = add i32 %i, 1 + %br_cmp.i = icmp eq i1 %br_cmp, 0 + br label %for +for: + %i = phi i32 [ %inc, %body], [ 0, %entry ] + %br_cmp = phi i1 [ %br_cmp.i, %body ], [ 0, %entry ] + %0 = icmp eq i32 %cond, %i + %1 = select i1 %br_cmp, i32 2, i32 3 + %2 = select i1 %br_cmp, float 2.0 , float 5.0 + %3 = select i1 %br_cmp, <2 x i32> <i32 2, i32 3>, <2 x i32> <i32 4, i32 5> + %4 = select i1 %br_cmp, <2 x float> <float 2.0, float 3.0>, <2 x float> <float 4.0, float 5.0> + %5 = select i1 %br_cmp, <4 x i32> <i32 2 , i32 3, i32 4, i32 5>, <4 x i32> <i32 6, i32 7, i32 8, i32 9> + %6 = select i1 %br_cmp, <4 x float> <float 2.0, float 3.0, float 4.0, float 5.0>, <4 x float> <float 6.0, float 7.0, float 8.0, float 9.0> + br i1 %0, label %body, label %done + +done: + store i32 %1, i32 addrspace(1)* %i32out + store float %2, float addrspace(1)* %f32out + store <2 x i32> %3, <2 x i32> addrspace(1)* %v2i32out + store <2 x float> %4, <2 x float> addrspace(1)* %v2f32out + store <4 x i32> %5, <4 x i32> addrspace(1)* %v4i32out + store <4 x float> %6, <4 x float> addrspace(1)* %v4f32out + ret void +} diff --git a/test/CodeGen/R600/selectcc-cnd.ll b/test/CodeGen/R600/selectcc-cnd.ll index d7287b487896..0bfca6937488 100644 --- a/test/CodeGen/R600/selectcc-cnd.ll +++ b/test/CodeGen/R600/selectcc-cnd.ll @@ -1,8 +1,8 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;CHECK-NOT: SETE -;CHECK: CNDE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x, -;CHECK-NEXT: {{[-0-9]+\(2.0}} +;CHECK: CNDE {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x, +;CHECK: 1073741824 define void @test(float addrspace(1)* %out, float addrspace(1)* %in) { %1 = load float addrspace(1)* %in %2 = fcmp oeq float %1, 0.0 diff --git a/test/CodeGen/R600/selectcc-cnde-int.ll b/test/CodeGen/R600/selectcc-cnde-int.ll index 768dc7dbf418..d568888f7cb2 100644 --- a/test/CodeGen/R600/selectcc-cnde-int.ll +++ b/test/CodeGen/R600/selectcc-cnde-int.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;CHECK-NOT: SETE_INT -;CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x, +;CHECK: CNDE_INT {{\*?}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x, ;CHECK-NEXT: 2 define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %1 = load i32 addrspace(1)* %in diff --git a/test/CodeGen/R600/selectcc-opt.ll b/test/CodeGen/R600/selectcc-opt.ll index 02d935390423..834c03069522 100644 --- a/test/CodeGen/R600/selectcc-opt.ll +++ b/test/CodeGen/R600/selectcc-opt.ll @@ -6,7 +6,7 @@ define void @test_a(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp ult float %in, 0.000000e+00 + %0 = fcmp olt float %in, 0.000000e+00 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+00 %2 = fsub float -0.000000e+00, %1 %3 = fptosi float %2 to i32 @@ -31,9 +31,10 @@ ENDIF: ; CHECK: @test_b ; CHECK: SET{{[GTEQN]+}}_DX10 ; CHECK-NEXT: PRED_ +; CHECK-NEXT: ALU clause starting define void @test_b(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp ult float %in, 0.0 + %0 = fcmp olt float %in, 0.0 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+00 %2 = fsub float -0.000000e+00, %1 %3 = fptosi float %2 to i32 diff --git a/test/CodeGen/R600/set-dx10.ll b/test/CodeGen/R600/set-dx10.ll index eb6e9d2f2ba5..5c7d4998d07c 100644 --- a/test/CodeGen/R600/set-dx10.ll +++ b/test/CodeGen/R600/set-dx10.ll @@ -5,7 +5,8 @@ ; SET*DX10 instructions. ; CHECK: @fcmp_une_select_fptosi -; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK: SETNE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_une_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: @@ -18,7 +19,8 @@ entry: } ; CHECK: @fcmp_une_select_i32 -; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK: SETNE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_une_select_i32(i32 addrspace(1)* %out, float %in) { entry: @@ -28,12 +30,13 @@ entry: ret void } -; CHECK: @fcmp_ueq_select_fptosi -; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK: @fcmp_oeq_select_fptosi +; CHECK: SETE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @fcmp_ueq_select_fptosi(i32 addrspace(1)* %out, float %in) { +define void @fcmp_oeq_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp ueq float %in, 5.0 + %0 = fcmp oeq float %in, 5.0 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+00 %2 = fsub float -0.000000e+00, %1 %3 = fptosi float %2 to i32 @@ -41,23 +44,25 @@ entry: ret void } -; CHECK: @fcmp_ueq_select_i32 -; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK: @fcmp_oeq_select_i32 +; CHECK: SETE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @fcmp_ueq_select_i32(i32 addrspace(1)* %out, float %in) { +define void @fcmp_oeq_select_i32(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp ueq float %in, 5.0 + %0 = fcmp oeq float %in, 5.0 %1 = select i1 %0, i32 -1, i32 0 store i32 %1, i32 addrspace(1)* %out ret void } -; CHECK: @fcmp_ugt_select_fptosi -; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK: @fcmp_ogt_select_fptosi +; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @fcmp_ugt_select_fptosi(i32 addrspace(1)* %out, float %in) { +define void @fcmp_ogt_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp ugt float %in, 5.0 + %0 = fcmp ogt float %in, 5.0 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+00 %2 = fsub float -0.000000e+00, %1 %3 = fptosi float %2 to i32 @@ -65,23 +70,25 @@ entry: ret void } -; CHECK: @fcmp_ugt_select_i32 -; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK: @fcmp_ogt_select_i32 +; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @fcmp_ugt_select_i32(i32 addrspace(1)* %out, float %in) { +define void @fcmp_ogt_select_i32(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp ugt float %in, 5.0 + %0 = fcmp ogt float %in, 5.0 %1 = select i1 %0, i32 -1, i32 0 store i32 %1, i32 addrspace(1)* %out ret void } -; CHECK: @fcmp_uge_select_fptosi -; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK: @fcmp_oge_select_fptosi +; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @fcmp_uge_select_fptosi(i32 addrspace(1)* %out, float %in) { +define void @fcmp_oge_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp uge float %in, 5.0 + %0 = fcmp oge float %in, 5.0 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+00 %2 = fsub float -0.000000e+00, %1 %3 = fptosi float %2 to i32 @@ -89,23 +96,25 @@ entry: ret void } -; CHECK: @fcmp_uge_select_i32 -; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK: @fcmp_oge_select_i32 +; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @fcmp_uge_select_i32(i32 addrspace(1)* %out, float %in) { +define void @fcmp_oge_select_i32(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp uge float %in, 5.0 + %0 = fcmp oge float %in, 5.0 %1 = select i1 %0, i32 -1, i32 0 store i32 %1, i32 addrspace(1)* %out ret void } -; CHECK: @fcmp_ule_select_fptosi -; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, +; CHECK: @fcmp_ole_select_fptosi +; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @fcmp_ule_select_fptosi(i32 addrspace(1)* %out, float %in) { +define void @fcmp_ole_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp ule float %in, 5.0 + %0 = fcmp ole float %in, 5.0 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+00 %2 = fsub float -0.000000e+00, %1 %3 = fptosi float %2 to i32 @@ -113,23 +122,25 @@ entry: ret void } -; CHECK: @fcmp_ule_select_i32 -; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, +; CHECK: @fcmp_ole_select_i32 +; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @fcmp_ule_select_i32(i32 addrspace(1)* %out, float %in) { +define void @fcmp_ole_select_i32(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp ule float %in, 5.0 + %0 = fcmp ole float %in, 5.0 %1 = select i1 %0, i32 -1, i32 0 store i32 %1, i32 addrspace(1)* %out ret void } -; CHECK: @fcmp_ult_select_fptosi -; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, +; CHECK: @fcmp_olt_select_fptosi +; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @fcmp_ult_select_fptosi(i32 addrspace(1)* %out, float %in) { +define void @fcmp_olt_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp ult float %in, 5.0 + %0 = fcmp olt float %in, 5.0 %1 = select i1 %0, float 1.000000e+00, float 0.000000e+00 %2 = fsub float -0.000000e+00, %1 %3 = fptosi float %2 to i32 @@ -137,12 +148,13 @@ entry: ret void } -; CHECK: @fcmp_ult_select_i32 -; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, +; CHECK: @fcmp_olt_select_i32 +; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z, +; CHECK-NEXT: LSHR ; CHECK-NEXT: 1084227584(5.000000e+00) -define void @fcmp_ult_select_i32(i32 addrspace(1)* %out, float %in) { +define void @fcmp_olt_select_i32(i32 addrspace(1)* %out, float %in) { entry: - %0 = fcmp ult float %in, 5.0 + %0 = fcmp olt float %in, 5.0 %1 = select i1 %0, i32 -1, i32 0 store i32 %1, i32 addrspace(1)* %out ret void diff --git a/test/CodeGen/R600/setcc.ll b/test/CodeGen/R600/setcc.ll index 0752f2e63dbf..8d34c4ad4fe5 100644 --- a/test/CodeGen/R600/setcc.ll +++ b/test/CodeGen/R600/setcc.ll @@ -1,7 +1,24 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: SETE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI --check-prefix=FUNC %s -define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +; FUNC-LABEL: @setcc_v2i32 +; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z +; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[2].W, KC0[3].Y + +define void @setcc_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) { + %result = icmp eq <2 x i32> %a, %b + %sext = sext <2 x i1> %result to <2 x i32> + store <2 x i32> %sext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @setcc_v4i32 +; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @setcc_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 %a = load <4 x i32> addrspace(1) * %in %b = load <4 x i32> addrspace(1) * %b_ptr @@ -10,3 +27,307 @@ define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { store <4 x i32> %sext, <4 x i32> addrspace(1)* %out ret void } + +;;;==========================================================================;;; +;; Float comparisons +;;;==========================================================================;;; + +; FUNC-LABEL: @f32_oeq +; R600: SETE_DX10 +; SI: V_CMP_EQ_F32 +define void @f32_oeq(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp oeq float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_ogt +; R600: SETGT_DX10 +; SI: V_CMP_GT_F32 +define void @f32_ogt(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp ogt float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_oge +; R600: SETGE_DX10 +; SI: V_CMP_GE_F32 +define void @f32_oge(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp oge float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_olt +; R600: SETGT_DX10 +; SI: V_CMP_LT_F32 +define void @f32_olt(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp olt float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_ole +; R600: SETGE_DX10 +; SI: V_CMP_LE_F32 +define void @f32_ole(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp ole float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_one +; R600-DAG: SETE_DX10 +; R600-DAG: SETE_DX10 +; R600-DAG: AND_INT +; R600-DAG: SETNE_DX10 +; R600-DAG: AND_INT +; R600-DAG: SETNE_INT +; SI: V_CMP_O_F32 +; SI: V_CMP_NEQ_F32 +; SI: S_AND_B64 +define void @f32_one(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp one float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_ord +; R600-DAG: SETE_DX10 +; R600-DAG: SETE_DX10 +; R600-DAG: AND_INT +; R600-DAG: SETNE_INT +; SI: V_CMP_O_F32 +define void @f32_ord(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp ord float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_ueq +; R600-DAG: SETNE_DX10 +; R600-DAG: SETNE_DX10 +; R600-DAG: OR_INT +; R600-DAG: SETE_DX10 +; R600-DAG: OR_INT +; R600-DAG: SETNE_INT +; SI: V_CMP_U_F32 +; SI: V_CMP_EQ_F32 +; SI: S_OR_B64 +define void @f32_ueq(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp ueq float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_ugt +; R600: SETGE +; R600: SETE_DX10 +; SI: V_CMP_U_F32 +; SI: V_CMP_GT_F32 +; SI: S_OR_B64 +define void @f32_ugt(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp ugt float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_uge +; R600: SETGT +; R600: SETE_DX10 +; SI: V_CMP_U_F32 +; SI: V_CMP_GE_F32 +; SI: S_OR_B64 +define void @f32_uge(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp uge float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_ult +; R600: SETGE +; R600: SETE_DX10 +; SI: V_CMP_U_F32 +; SI: V_CMP_LT_F32 +; SI: S_OR_B64 +define void @f32_ult(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp ult float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_ule +; R600: SETGT +; R600: SETE_DX10 +; SI: V_CMP_U_F32 +; SI: V_CMP_LE_F32 +; SI: S_OR_B64 +define void @f32_ule(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp ule float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_une +; R600: SETNE_DX10 +; SI: V_CMP_NEQ_F32 +define void @f32_une(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp une float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f32_uno +; R600: SETNE_DX10 +; R600: SETNE_DX10 +; R600: OR_INT +; R600: SETNE_INT +; SI: V_CMP_U_F32 +define void @f32_uno(i32 addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fcmp uno float %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +;;;==========================================================================;;; +;; 32-bit integer comparisons +;;;==========================================================================;;; + +; FUNC-LABEL: @i32_eq +; R600: SETE_INT +; SI: V_CMP_EQ_I32 +define void @i32_eq(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = icmp eq i32 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i32_ne +; R600: SETNE_INT +; SI: V_CMP_NE_I32 +define void @i32_ne(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = icmp ne i32 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i32_ugt +; R600: SETGT_UINT +; SI: V_CMP_GT_U32 +define void @i32_ugt(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = icmp ugt i32 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i32_uge +; R600: SETGE_UINT +; SI: V_CMP_GE_U32 +define void @i32_uge(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = icmp uge i32 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i32_ult +; R600: SETGT_UINT +; SI: V_CMP_LT_U32 +define void @i32_ult(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = icmp ult i32 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i32_ule +; R600: SETGE_UINT +; SI: V_CMP_LE_U32 +define void @i32_ule(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = icmp ule i32 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i32_sgt +; R600: SETGT_INT +; SI: V_CMP_GT_I32 +define void @i32_sgt(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = icmp sgt i32 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i32_sge +; R600: SETGE_INT +; SI: V_CMP_GE_I32 +define void @i32_sge(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = icmp sge i32 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i32_slt +; R600: SETGT_INT +; SI: V_CMP_LT_I32 +define void @i32_slt(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = icmp slt i32 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i32_sle +; R600: SETGE_INT +; SI: V_CMP_LE_I32 +define void @i32_sle(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = icmp sle i32 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/setcc64.ll b/test/CodeGen/R600/setcc64.ll new file mode 100644 index 000000000000..9202fc01f555 --- /dev/null +++ b/test/CodeGen/R600/setcc64.ll @@ -0,0 +1,263 @@ +;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI --check-prefix=FUNC %s + +; XXX: Merge this into setcc, once R600 supports 64-bit operations + +;;;==========================================================================;;; +;; Double comparisons +;;;==========================================================================;;; + +; FUNC-LABEL: @f64_oeq +; SI: V_CMP_EQ_F64 +define void @f64_oeq(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp oeq double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_ogt +; SI: V_CMP_GT_F64 +define void @f64_ogt(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp ogt double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_oge +; SI: V_CMP_GE_F64 +define void @f64_oge(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp oge double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_olt +; SI: V_CMP_LT_F64 +define void @f64_olt(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp olt double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_ole +; SI: V_CMP_LE_F64 +define void @f64_ole(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp ole double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_one +; SI: V_CMP_O_F64 +; SI: V_CMP_NEQ_F64 +; SI: S_AND_B64 +define void @f64_one(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp one double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_ord +; SI: V_CMP_O_F64 +define void @f64_ord(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp ord double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_ueq +; SI: V_CMP_U_F64 +; SI: V_CMP_EQ_F64 +; SI: S_OR_B64 +define void @f64_ueq(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp ueq double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_ugt +; SI: V_CMP_U_F64 +; SI: V_CMP_GT_F64 +; SI: S_OR_B64 +define void @f64_ugt(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp ugt double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_uge +; SI: V_CMP_U_F64 +; SI: V_CMP_GE_F64 +; SI: S_OR_B64 +define void @f64_uge(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp uge double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_ult +; SI: V_CMP_U_F64 +; SI: V_CMP_LT_F64 +; SI: S_OR_B64 +define void @f64_ult(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp ult double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_ule +; SI: V_CMP_U_F64 +; SI: V_CMP_LE_F64 +; SI: S_OR_B64 +define void @f64_ule(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp ule double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_une +; SI: V_CMP_NEQ_F64 +define void @f64_une(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp une double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @f64_uno +; SI: V_CMP_U_F64 +define void @f64_uno(i32 addrspace(1)* %out, double %a, double %b) { +entry: + %0 = fcmp uno double %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +;;;==========================================================================;;; +;; 64-bit integer comparisons +;;;==========================================================================;;; + +; FUNC-LABEL: @i64_eq +; SI: V_CMP_EQ_I64 +define void @i64_eq(i32 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = icmp eq i64 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i64_ne +; SI: V_CMP_NE_I64 +define void @i64_ne(i32 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = icmp ne i64 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i64_ugt +; SI: V_CMP_GT_U64 +define void @i64_ugt(i32 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = icmp ugt i64 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i64_uge +; SI: V_CMP_GE_U64 +define void @i64_uge(i32 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = icmp uge i64 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i64_ult +; SI: V_CMP_LT_U64 +define void @i64_ult(i32 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = icmp ult i64 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i64_ule +; SI: V_CMP_LE_U64 +define void @i64_ule(i32 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = icmp ule i64 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i64_sgt +; SI: V_CMP_GT_I64 +define void @i64_sgt(i32 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = icmp sgt i64 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i64_sge +; SI: V_CMP_GE_I64 +define void @i64_sge(i32 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = icmp sge i64 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i64_slt +; SI: V_CMP_LT_I64 +define void @i64_slt(i32 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = icmp slt i64 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: @i64_sle +; SI: V_CMP_LE_I64 +define void @i64_sle(i32 addrspace(1)* %out, i64 %a, i64 %b) { +entry: + %0 = icmp sle i64 %a, %b + %1 = sext i1 %0 to i32 + store i32 %1, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/seto.ll b/test/CodeGen/R600/seto.ll index 4622203ffdbc..8633a4b804af 100644 --- a/test/CodeGen/R600/seto.ll +++ b/test/CodeGen/R600/seto.ll @@ -1,6 +1,6 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0 +;CHECK: V_CMP_O_F32_e64 s[0:1], {{[sv][0-9]+, [sv][0-9]+}}, 0, 0, 0, 0 define void @main(float %p) { main_body: diff --git a/test/CodeGen/R600/setuo.ll b/test/CodeGen/R600/setuo.ll index 0bf5801b1c33..c77a37e19041 100644 --- a/test/CodeGen/R600/setuo.ll +++ b/test/CodeGen/R600/setuo.ll @@ -1,6 +1,6 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s -;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0 +;CHECK: V_CMP_U_F32_e64 s[0:1], {{[sv][0-9]+, [sv][0-9]+}}, 0, 0, 0, 0 define void @main(float %p) { main_body: diff --git a/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll b/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll new file mode 100644 index 000000000000..d74161bf6dc1 --- /dev/null +++ b/test/CodeGen/R600/sgpr-copy-duplicate-operand.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s + +; Copy VGPR -> SGPR used twice as an instruction operand, which is then +; used in an REG_SEQUENCE that also needs to be handled. + +; SI-LABEL: @test_dup_operands: +; SI: V_ADD_I32_e32 +define void @test_dup_operands(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %in) { + %a = load <2 x i32> addrspace(1)* %in + %lo = extractelement <2 x i32> %a, i32 0 + %hi = extractelement <2 x i32> %a, i32 1 + %add = add i32 %lo, %lo + %vec0 = insertelement <2 x i32> undef, i32 %add, i32 0 + %vec1 = insertelement <2 x i32> %vec0, i32 %hi, i32 1 + store <2 x i32> %vec1, <2 x i32> addrspace(1)* %out, align 8 + ret void +} + diff --git a/test/CodeGen/R600/sgpr-copy.ll b/test/CodeGen/R600/sgpr-copy.ll new file mode 100644 index 000000000000..5472c1bb1ca9 --- /dev/null +++ b/test/CodeGen/R600/sgpr-copy.ll @@ -0,0 +1,327 @@ +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s + +; This test checks that no VGPR to SGPR copies are created by the register +; allocator. +; CHECK-LABEL: @phi1 +; CHECK: S_BUFFER_LOAD_DWORD [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0 +; CHECK: V_MOV_B32_e32 v{{[0-9]}}, [[DST]] + +define void @phi1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +main_body: + %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0 + %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1 + %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0) + %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16) + %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32) + %25 = fptosi float %23 to i32 + %26 = icmp ne i32 %25, 0 + br i1 %26, label %ENDIF, label %ELSE + +ELSE: ; preds = %main_body + %27 = fsub float -0.000000e+00, %22 + br label %ENDIF + +ENDIF: ; preds = %main_body, %ELSE + %temp.0 = phi float [ %27, %ELSE ], [ %22, %main_body ] + %28 = fadd float %temp.0, %24 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %28, float %28, float 0.000000e+00, float 1.000000e+00) + ret void +} + +; Make sure this program doesn't crash +; CHECK-LABEL: @phi2 +define void @phi2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +main_body: + %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0 + %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1 + %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16) + %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32) + %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36) + %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40) + %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48) + %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52) + %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56) + %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64) + %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68) + %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72) + %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76) + %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80) + %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84) + %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88) + %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92) + %37 = getelementptr <32 x i8> addrspace(2)* %2, i32 0 + %38 = load <32 x i8> addrspace(2)* %37, !tbaa !1 + %39 = getelementptr <16 x i8> addrspace(2)* %1, i32 0 + %40 = load <16 x i8> addrspace(2)* %39, !tbaa !1 + %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5) + %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5) + %43 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5) + %44 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5) + %45 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5) + %46 = bitcast float %41 to i32 + %47 = bitcast float %42 to i32 + %48 = insertelement <2 x i32> undef, i32 %46, i32 0 + %49 = insertelement <2 x i32> %48, i32 %47, i32 1 + %50 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %38, <16 x i8> %40, i32 2) + %51 = extractelement <4 x float> %50, i32 2 + %52 = call float @fabs(float %51) + %53 = fmul float %43, %43 + %54 = fmul float %44, %44 + %55 = fadd float %54, %53 + %56 = fmul float %45, %45 + %57 = fadd float %55, %56 + %58 = call float @llvm.AMDGPU.rsq(float %57) + %59 = fmul float %43, %58 + %60 = fmul float %44, %58 + %61 = fmul float %45, %58 + %62 = fmul float %59, %23 + %63 = fmul float %60, %24 + %64 = fadd float %63, %62 + %65 = fmul float %61, %25 + %66 = fadd float %64, %65 + %67 = fsub float -0.000000e+00, %26 + %68 = fmul float %66, %52 + %69 = fadd float %68, %67 + %70 = fmul float %27, %69 + %71 = fmul float %28, %69 + %72 = call float @fabs(float %70) + %73 = fcmp olt float 0x3EE4F8B580000000, %72 + %74 = sext i1 %73 to i32 + %75 = bitcast i32 %74 to float + %76 = bitcast float %75 to i32 + %77 = icmp ne i32 %76, 0 + br i1 %77, label %IF, label %ENDIF + +IF: ; preds = %main_body + %78 = fsub float -0.000000e+00, %70 + %79 = call float @llvm.AMDIL.exp.(float %78) + %80 = fsub float -0.000000e+00, %79 + %81 = fadd float 1.000000e+00, %80 + %82 = fdiv float 1.000000e+00, %70 + %83 = fmul float %81, %82 + %84 = fmul float %32, %83 + br label %ENDIF + +ENDIF: ; preds = %main_body, %IF + %temp4.0 = phi float [ %84, %IF ], [ %32, %main_body ] + %85 = call float @fabs(float %71) + %86 = fcmp olt float 0x3EE4F8B580000000, %85 + %87 = sext i1 %86 to i32 + %88 = bitcast i32 %87 to float + %89 = bitcast float %88 to i32 + %90 = icmp ne i32 %89, 0 + br i1 %90, label %IF25, label %ENDIF24 + +IF25: ; preds = %ENDIF + %91 = fsub float -0.000000e+00, %71 + %92 = call float @llvm.AMDIL.exp.(float %91) + %93 = fsub float -0.000000e+00, %92 + %94 = fadd float 1.000000e+00, %93 + %95 = fdiv float 1.000000e+00, %71 + %96 = fmul float %94, %95 + %97 = fmul float %36, %96 + br label %ENDIF24 + +ENDIF24: ; preds = %ENDIF, %IF25 + %temp8.0 = phi float [ %97, %IF25 ], [ %36, %ENDIF ] + %98 = fmul float %29, %temp4.0 + %99 = fmul float %30, %temp4.0 + %100 = fmul float %31, %temp4.0 + %101 = fmul float %33, %temp8.0 + %102 = fadd float %101, %98 + %103 = fmul float %34, %temp8.0 + %104 = fadd float %103, %99 + %105 = fmul float %35, %temp8.0 + %106 = fadd float %105, %100 + %107 = call float @llvm.pow.f32(float %52, float %22) + %108 = fsub float -0.000000e+00, %102 + %109 = fmul float %108, %107 + %110 = fsub float -0.000000e+00, %104 + %111 = fmul float %110, %107 + %112 = fsub float -0.000000e+00, %106 + %113 = fmul float %112, %107 + %114 = call i32 @llvm.SI.packf16(float %109, float %111) + %115 = bitcast i32 %114 to float + %116 = call i32 @llvm.SI.packf16(float %113, float 1.000000e+00) + %117 = bitcast i32 %116 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %115, float %117, float %115, float %117) + ret void +} + +; We just want ot make sure the program doesn't crash +; CHECK-LABEL: @loop + +define void @loop(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +main_body: + %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0 + %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1 + %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0) + %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4) + %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8) + %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12) + %26 = fptosi float %25 to i32 + %27 = bitcast i32 %26 to float + %28 = bitcast float %27 to i32 + br label %LOOP + +LOOP: ; preds = %ENDIF, %main_body + %temp4.0 = phi float [ %22, %main_body ], [ %temp5.0, %ENDIF ] + %temp5.0 = phi float [ %23, %main_body ], [ %temp6.0, %ENDIF ] + %temp6.0 = phi float [ %24, %main_body ], [ %temp4.0, %ENDIF ] + %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %37, %ENDIF ] + %29 = bitcast float %temp8.0 to i32 + %30 = icmp sge i32 %29, %28 + %31 = sext i1 %30 to i32 + %32 = bitcast i32 %31 to float + %33 = bitcast float %32 to i32 + %34 = icmp ne i32 %33, 0 + br i1 %34, label %IF, label %ENDIF + +IF: ; preds = %LOOP + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00) + ret void + +ENDIF: ; preds = %LOOP + %35 = bitcast float %temp8.0 to i32 + %36 = add i32 %35, 1 + %37 = bitcast i32 %36 to float + br label %LOOP +} + +; Function Attrs: nounwind readnone +declare float @llvm.SI.load.const(<16 x i8>, i32) #1 + +; Function Attrs: readonly +declare float @fabs(float) #2 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { nounwind readnone } +attributes #2 = { readonly } +attributes #3 = { readnone } +attributes #4 = { nounwind readonly } + +!0 = metadata !{metadata !"const", null} +!1 = metadata !{metadata !0, metadata !0, i64 0, i32 1} + +; Function Attrs: nounwind readnone +declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 + +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.rsq(float) #3 + +; Function Attrs: readnone +declare float @llvm.AMDIL.exp.(float) #3 + +; Function Attrs: nounwind readonly +declare float @llvm.pow.f32(float, float) #4 + +; Function Attrs: nounwind readnone +declare i32 @llvm.SI.packf16(float, float) #1 + +; This checks for a bug in the FixSGPRCopies pass where VReg96 +; registers were being identified as an SGPR regclass which was causing +; an assertion failure. + +; CHECK-LABEL: @sample_v3 +; CHECK: IMAGE_SAMPLE +; CHECK: IMAGE_SAMPLE +; CHECK: EXP +; CHECK: S_ENDPGM +define void @sample_v3([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { + +entry: + %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 + %22 = load <16 x i8> addrspace(2)* %21, !tbaa !2 + %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16) + %24 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 + %25 = load <32 x i8> addrspace(2)* %24, !tbaa !2 + %26 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 + %27 = load <16 x i8> addrspace(2)* %26, !tbaa !2 + %28 = fcmp oeq float %23, 0.0 + br i1 %28, label %if, label %else + +if: + %val.if = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> <i32 0, i32 0>, <32 x i8> %25, <16 x i8> %27, i32 2) + %val.if.0 = extractelement <4 x float> %val.if, i32 0 + %val.if.1 = extractelement <4 x float> %val.if, i32 1 + %val.if.2 = extractelement <4 x float> %val.if, i32 2 + br label %endif + +else: + %val.else = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> <i32 1, i32 0>, <32 x i8> %25, <16 x i8> %27, i32 2) + %val.else.0 = extractelement <4 x float> %val.else, i32 0 + %val.else.1 = extractelement <4 x float> %val.else, i32 1 + %val.else.2 = extractelement <4 x float> %val.else, i32 2 + br label %endif + +endif: + %val.0 = phi float [%val.if.0, %if], [%val.else.0, %else] + %val.1 = phi float [%val.if.1, %if], [%val.else.1, %else] + %val.2 = phi float [%val.if.2, %if], [%val.else.2, %else] + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %val.0, float %val.1, float %val.2, float 0.0) + ret void +} + +!2 = metadata !{metadata !"const", null, i32 1} + +; CHECK-LABEL: @copy1 +; CHECK: BUFFER_LOAD_DWORD +; CHECK: V_ADD +; CHECK: S_ENDPGM +define void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) { +entry: + %0 = load float addrspace(1)* %in0 + %1 = fcmp oeq float %0, 0.0 + br i1 %1, label %if0, label %endif + +if0: + %2 = bitcast float %0 to i32 + %3 = fcmp olt float %0, 0.0 + br i1 %3, label %if1, label %endif + +if1: + %4 = add i32 %2, 1 + br label %endif + +endif: + %5 = phi i32 [ 0, %entry ], [ %2, %if0 ], [ %4, %if1 ] + %6 = bitcast i32 %5 to float + store float %6, float addrspace(1)* %out + ret void +} + +; This test is just checking that we don't crash / assertion fail. +; CHECK-LABEL: @copy2 +; CHECK: S_ENDPGM + +define void @copy2([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +entry: + br label %LOOP68 + +LOOP68: + %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ] + %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ] + %g = icmp eq i32 0, %t + %l = bitcast float %temp4.7 to i32 + br i1 %g, label %IF70, label %ENDIF69 + +IF70: + %q = icmp ne i32 %l, 13 + %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) + ret void + +ENDIF69: + %u = add i32 %l, %t + %v = bitcast i32 %u to float + %x = add i32 %t, -1 + br label %LOOP68 +} + +attributes #0 = { "ShaderType"="0" } + diff --git a/test/CodeGen/R600/shared-op-cycle.ll b/test/CodeGen/R600/shared-op-cycle.ll new file mode 100644 index 000000000000..0484fc9a8563 --- /dev/null +++ b/test/CodeGen/R600/shared-op-cycle.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @main +; CHECK: MULADD_IEEE * +; CHECK-NOT: MULADD_IEEE * + +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { + %w0 = extractelement <4 x float> %reg0, i32 3 + %w1 = extractelement <4 x float> %reg1, i32 3 + %w2 = extractelement <4 x float> %reg2, i32 3 + %sq0 = fmul float %w0, %w0 + %r0 = fadd float %sq0, 2.0 + %sq1 = fmul float %w1, %w1 + %r1 = fadd float %sq1, 2.0 + %sq2 = fmul float %w2, %w2 + %r2 = fadd float %sq2, 2.0 + %v0 = insertelement <4 x float> undef, float %r0, i32 0 + %v1 = insertelement <4 x float> %v0, float %r1, i32 1 + %v2 = insertelement <4 x float> %v1, float %r2, i32 2 + %res = call float @llvm.AMDGPU.dp4(<4 x float> %v2, <4 x float> %v2) + %vecres = insertelement <4 x float> undef, float %res, i32 0 + call void @llvm.R600.store.swizzle(<4 x float> %vecres, i32 0, i32 2) + ret void +} + +; Function Attrs: readnone +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } +attributes #1 = { readnone }
\ No newline at end of file diff --git a/test/CodeGen/R600/shl.ll b/test/CodeGen/R600/shl.ll index 43cc1e26fc01..4a6aab4a104a 100644 --- a/test/CodeGen/R600/shl.ll +++ b/test/CodeGen/R600/shl.ll @@ -1,13 +1,43 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; CHECK: @shl_v4i32 -; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: @shl_v2i32 +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { +;SI-CHECK: @shl_v2i32 +;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 + %a = load <2 x i32> addrspace(1) * %in + %b = load <2 x i32> addrspace(1) * %b_ptr + %result = shl <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +;EG-CHECK: @shl_v4i32 +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK: @shl_v4i32 +;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_LSHL_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 + %a = load <4 x i32> addrspace(1) * %in + %b = load <4 x i32> addrspace(1) * %b_ptr %result = shl <4 x i32> %a, %b store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } + +; XXX: Add SI test for i64 shl once i64 stores and i64 function arguments are +; supported. diff --git a/test/CodeGen/R600/short-args.ll b/test/CodeGen/R600/short-args.ll deleted file mode 100644 index b69e327bf6df..000000000000 --- a/test/CodeGen/R600/short-args.ll +++ /dev/null @@ -1,41 +0,0 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -; CHECK: @i8_arg -; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} - -define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind { -entry: - %0 = zext i8 %in to i32 - store i32 %0, i32 addrspace(1)* %out, align 4 - ret void -} - -; CHECK: @i8_zext_arg -; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} - -define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind { -entry: - %0 = zext i8 %in to i32 - store i32 %0, i32 addrspace(1)* %out, align 4 - ret void -} - -; CHECK: @i16_arg -; CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} - -define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind { -entry: - %0 = zext i16 %in to i32 - store i32 %0, i32 addrspace(1)* %out, align 4 - ret void -} - -; CHECK: @i16_zext_arg -; CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} - -define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind { -entry: - %0 = zext i16 %in to i32 - store i32 %0, i32 addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/R600/si-annotate-cf-assertion.ll b/test/CodeGen/R600/si-annotate-cf-assertion.ll new file mode 100644 index 000000000000..9886fe9169bb --- /dev/null +++ b/test/CodeGen/R600/si-annotate-cf-assertion.ll @@ -0,0 +1,23 @@ +; XFAIL: * +; RUN: llc -march=r600 -mcpu=SI -asm-verbose=false < %s | FileCheck %s + + +define void @test(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind { +; CHECK-LABEL: @test: + +entry: + switch i32 %x, label %sw.default [ + i32 0, label %sw.bb + i32 60, label %sw.bb + ] + +sw.bb: + unreachable + +sw.default: + unreachable + +sw.epilog: + ret void +} + diff --git a/test/CodeGen/R600/si-lod-bias.ll b/test/CodeGen/R600/si-lod-bias.ll new file mode 100644 index 000000000000..8d7a79cdbda0 --- /dev/null +++ b/test/CodeGen/R600/si-lod-bias.ll @@ -0,0 +1,51 @@ +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +; This shader has the potential to generated illegal VGPR to SGPR copies if +; the wrong register class is used for the REG_SEQUENCE instructions. + +; CHECK: @main +; CHECK: IMAGE_SAMPLE_B v{{\[[0-9]:[0-9]\]}}, 15, 0, 0, 0, 0, 0, 0, 0, v{{\[[0-9]:[0-9]\]}} + +define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +main_body: + %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0 + %21 = load <16 x i8> addrspace(2)* %20, !tbaa !1 + %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16) + %23 = getelementptr <32 x i8> addrspace(2)* %2, i32 0 + %24 = load <32 x i8> addrspace(2)* %23, !tbaa !1 + %25 = getelementptr <16 x i8> addrspace(2)* %1, i32 0 + %26 = load <16 x i8> addrspace(2)* %25, !tbaa !1 + %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5) + %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5) + %29 = bitcast float %22 to i32 + %30 = bitcast float %27 to i32 + %31 = bitcast float %28 to i32 + %32 = insertelement <4 x i32> undef, i32 %29, i32 0 + %33 = insertelement <4 x i32> %32, i32 %30, i32 1 + %34 = insertelement <4 x i32> %33, i32 %31, i32 2 + %35 = insertelement <4 x i32> %34, i32 undef, i32 3 + %36 = call <4 x float> @llvm.SI.sampleb.v4i32(<4 x i32> %35, <32 x i8> %24, <16 x i8> %26, i32 2) + %37 = extractelement <4 x float> %36, i32 0 + %38 = extractelement <4 x float> %36, i32 1 + %39 = extractelement <4 x float> %36, i32 2 + %40 = extractelement <4 x float> %36, i32 3 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %37, float %38, float %39, float %40) + ret void +} + +; Function Attrs: nounwind readnone +declare float @llvm.SI.load.const(<16 x i8>, i32) #1 + +; Function Attrs: nounwind readnone +declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 + +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.SI.sampleb.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { nounwind readnone } + +!0 = metadata !{metadata !"const", null} +!1 = metadata !{metadata !0, metadata !0, i64 0, i32 1} diff --git a/test/CodeGen/R600/si-sgpr-spill.ll b/test/CodeGen/R600/si-sgpr-spill.ll new file mode 100644 index 000000000000..05c5e31f3fad --- /dev/null +++ b/test/CodeGen/R600/si-sgpr-spill.ll @@ -0,0 +1,692 @@ +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck %s + +; XXX: Enable when spilling is supported +; XFAIL: * + +; These tests check that the compiler won't crash when it needs to spill +; SGPRs. + +; CHECK-LABEL: @main +; Writing to M0 from an SMRD instruction will hang the GPU. +; CHECK-NOT: S_BUFFER_LOAD_DWORD m0 +; CHECK: S_ENDPGM +@ddxy_lds = external addrspace(3) global [64 x i32] + +define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +main_body: + %21 = getelementptr [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 + %22 = load <16 x i8> addrspace(2)* %21, !tbaa !0 + %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 96) + %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 100) + %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 104) + %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 112) + %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 116) + %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 120) + %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 128) + %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 132) + %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 140) + %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 144) + %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 160) + %34 = call float @llvm.SI.load.const(<16 x i8> %22, i32 176) + %35 = call float @llvm.SI.load.const(<16 x i8> %22, i32 180) + %36 = call float @llvm.SI.load.const(<16 x i8> %22, i32 184) + %37 = call float @llvm.SI.load.const(<16 x i8> %22, i32 192) + %38 = call float @llvm.SI.load.const(<16 x i8> %22, i32 196) + %39 = call float @llvm.SI.load.const(<16 x i8> %22, i32 200) + %40 = call float @llvm.SI.load.const(<16 x i8> %22, i32 208) + %41 = call float @llvm.SI.load.const(<16 x i8> %22, i32 212) + %42 = call float @llvm.SI.load.const(<16 x i8> %22, i32 216) + %43 = call float @llvm.SI.load.const(<16 x i8> %22, i32 224) + %44 = call float @llvm.SI.load.const(<16 x i8> %22, i32 240) + %45 = call float @llvm.SI.load.const(<16 x i8> %22, i32 244) + %46 = call float @llvm.SI.load.const(<16 x i8> %22, i32 248) + %47 = call float @llvm.SI.load.const(<16 x i8> %22, i32 256) + %48 = call float @llvm.SI.load.const(<16 x i8> %22, i32 272) + %49 = call float @llvm.SI.load.const(<16 x i8> %22, i32 276) + %50 = call float @llvm.SI.load.const(<16 x i8> %22, i32 280) + %51 = call float @llvm.SI.load.const(<16 x i8> %22, i32 288) + %52 = call float @llvm.SI.load.const(<16 x i8> %22, i32 292) + %53 = call float @llvm.SI.load.const(<16 x i8> %22, i32 296) + %54 = call float @llvm.SI.load.const(<16 x i8> %22, i32 304) + %55 = call float @llvm.SI.load.const(<16 x i8> %22, i32 308) + %56 = call float @llvm.SI.load.const(<16 x i8> %22, i32 312) + %57 = call float @llvm.SI.load.const(<16 x i8> %22, i32 368) + %58 = call float @llvm.SI.load.const(<16 x i8> %22, i32 372) + %59 = call float @llvm.SI.load.const(<16 x i8> %22, i32 376) + %60 = call float @llvm.SI.load.const(<16 x i8> %22, i32 384) + %61 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 + %62 = load <32 x i8> addrspace(2)* %61, !tbaa !0 + %63 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 + %64 = load <16 x i8> addrspace(2)* %63, !tbaa !0 + %65 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 + %66 = load <32 x i8> addrspace(2)* %65, !tbaa !0 + %67 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 + %68 = load <16 x i8> addrspace(2)* %67, !tbaa !0 + %69 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2 + %70 = load <32 x i8> addrspace(2)* %69, !tbaa !0 + %71 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2 + %72 = load <16 x i8> addrspace(2)* %71, !tbaa !0 + %73 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3 + %74 = load <32 x i8> addrspace(2)* %73, !tbaa !0 + %75 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3 + %76 = load <16 x i8> addrspace(2)* %75, !tbaa !0 + %77 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4 + %78 = load <32 x i8> addrspace(2)* %77, !tbaa !0 + %79 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4 + %80 = load <16 x i8> addrspace(2)* %79, !tbaa !0 + %81 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5 + %82 = load <32 x i8> addrspace(2)* %81, !tbaa !0 + %83 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5 + %84 = load <16 x i8> addrspace(2)* %83, !tbaa !0 + %85 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6 + %86 = load <32 x i8> addrspace(2)* %85, !tbaa !0 + %87 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6 + %88 = load <16 x i8> addrspace(2)* %87, !tbaa !0 + %89 = getelementptr [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7 + %90 = load <32 x i8> addrspace(2)* %89, !tbaa !0 + %91 = getelementptr [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7 + %92 = load <16 x i8> addrspace(2)* %91, !tbaa !0 + %93 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) + %94 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) + %95 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6) + %96 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6) + %97 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %4, <2 x i32> %6) + %98 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %4, <2 x i32> %6) + %99 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %4, <2 x i32> %6) + %100 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %4, <2 x i32> %6) + %101 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %4, <2 x i32> %6) + %102 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %4, <2 x i32> %6) + %103 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %4, <2 x i32> %6) + %104 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %4, <2 x i32> %6) + %105 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %4, <2 x i32> %6) + %106 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %4, <2 x i32> %6) + %107 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %4, <2 x i32> %6) + %108 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %4, <2 x i32> %6) + %109 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %4, <2 x i32> %6) + %110 = call i32 @llvm.SI.tid() + %111 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %110 + %112 = bitcast float %93 to i32 + store i32 %112, i32 addrspace(3)* %111 + %113 = bitcast float %94 to i32 + store i32 %113, i32 addrspace(3)* %111 + %114 = call i32 @llvm.SI.tid() + %115 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %114 + %116 = and i32 %114, -4 + %117 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %116 + %118 = add i32 %116, 1 + %119 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %118 + %120 = bitcast float %93 to i32 + store i32 %120, i32 addrspace(3)* %115 + %121 = load i32 addrspace(3)* %117 + %122 = bitcast i32 %121 to float + %123 = load i32 addrspace(3)* %119 + %124 = bitcast i32 %123 to float + %125 = fsub float %124, %122 + %126 = bitcast float %94 to i32 + store i32 %126, i32 addrspace(3)* %115 + %127 = load i32 addrspace(3)* %117 + %128 = bitcast i32 %127 to float + %129 = load i32 addrspace(3)* %119 + %130 = bitcast i32 %129 to float + %131 = fsub float %130, %128 + %132 = insertelement <4 x float> undef, float %125, i32 0 + %133 = insertelement <4 x float> %132, float %131, i32 1 + %134 = insertelement <4 x float> %133, float %131, i32 2 + %135 = insertelement <4 x float> %134, float %131, i32 3 + %136 = extractelement <4 x float> %135, i32 0 + %137 = extractelement <4 x float> %135, i32 1 + %138 = fmul float %60, %93 + %139 = fmul float %60, %94 + %140 = fmul float %60, %94 + %141 = fmul float %60, %94 + %142 = call i32 @llvm.SI.tid() + %143 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %142 + %144 = bitcast float %138 to i32 + store i32 %144, i32 addrspace(3)* %143 + %145 = bitcast float %139 to i32 + store i32 %145, i32 addrspace(3)* %143 + %146 = bitcast float %140 to i32 + store i32 %146, i32 addrspace(3)* %143 + %147 = bitcast float %141 to i32 + store i32 %147, i32 addrspace(3)* %143 + %148 = call i32 @llvm.SI.tid() + %149 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %148 + %150 = and i32 %148, -4 + %151 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %150 + %152 = add i32 %150, 2 + %153 = getelementptr [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %152 + %154 = bitcast float %138 to i32 + store i32 %154, i32 addrspace(3)* %149 + %155 = load i32 addrspace(3)* %151 + %156 = bitcast i32 %155 to float + %157 = load i32 addrspace(3)* %153 + %158 = bitcast i32 %157 to float + %159 = fsub float %158, %156 + %160 = bitcast float %139 to i32 + store i32 %160, i32 addrspace(3)* %149 + %161 = load i32 addrspace(3)* %151 + %162 = bitcast i32 %161 to float + %163 = load i32 addrspace(3)* %153 + %164 = bitcast i32 %163 to float + %165 = fsub float %164, %162 + %166 = bitcast float %140 to i32 + store i32 %166, i32 addrspace(3)* %149 + %167 = load i32 addrspace(3)* %151 + %168 = bitcast i32 %167 to float + %169 = load i32 addrspace(3)* %153 + %170 = bitcast i32 %169 to float + %171 = fsub float %170, %168 + %172 = bitcast float %141 to i32 + store i32 %172, i32 addrspace(3)* %149 + %173 = load i32 addrspace(3)* %151 + %174 = bitcast i32 %173 to float + %175 = load i32 addrspace(3)* %153 + %176 = bitcast i32 %175 to float + %177 = fsub float %176, %174 + %178 = insertelement <4 x float> undef, float %159, i32 0 + %179 = insertelement <4 x float> %178, float %165, i32 1 + %180 = insertelement <4 x float> %179, float %171, i32 2 + %181 = insertelement <4 x float> %180, float %177, i32 3 + %182 = extractelement <4 x float> %181, i32 0 + %183 = extractelement <4 x float> %181, i32 1 + %184 = fdiv float 1.000000e+00, %97 + %185 = fmul float %33, %184 + %186 = fcmp uge float 1.000000e+00, %185 + %187 = select i1 %186, float %185, float 1.000000e+00 + %188 = fmul float %187, %30 + %189 = call float @ceil(float %188) + %190 = fcmp uge float 3.000000e+00, %189 + %191 = select i1 %190, float 3.000000e+00, float %189 + %192 = fdiv float 1.000000e+00, %191 + %193 = fdiv float 1.000000e+00, %30 + %194 = fmul float %191, %193 + %195 = fmul float %31, %194 + %196 = fmul float %95, %95 + %197 = fmul float %96, %96 + %198 = fadd float %197, %196 + %199 = fmul float %97, %97 + %200 = fadd float %198, %199 + %201 = call float @llvm.AMDGPU.rsq(float %200) + %202 = fmul float %95, %201 + %203 = fmul float %96, %201 + %204 = fmul float %202, %29 + %205 = fmul float %203, %29 + %206 = fmul float %204, -1.000000e+00 + %207 = fmul float %205, 1.000000e+00 + %208 = fmul float %206, %32 + %209 = fmul float %207, %32 + %210 = fsub float -0.000000e+00, %208 + %211 = fadd float %93, %210 + %212 = fsub float -0.000000e+00, %209 + %213 = fadd float %94, %212 + %214 = fmul float %206, %192 + %215 = fmul float %207, %192 + %216 = fmul float -1.000000e+00, %192 + %217 = bitcast float %136 to i32 + %218 = bitcast float %182 to i32 + %219 = bitcast float %137 to i32 + %220 = bitcast float %183 to i32 + %221 = insertelement <8 x i32> undef, i32 %217, i32 0 + %222 = insertelement <8 x i32> %221, i32 %218, i32 1 + %223 = insertelement <8 x i32> %222, i32 %219, i32 2 + %224 = insertelement <8 x i32> %223, i32 %220, i32 3 + br label %LOOP + +LOOP: ; preds = %ENDIF, %main_body + %temp24.0 = phi float [ 1.000000e+00, %main_body ], [ %258, %ENDIF ] + %temp28.0 = phi float [ %211, %main_body ], [ %253, %ENDIF ] + %temp29.0 = phi float [ %213, %main_body ], [ %255, %ENDIF ] + %temp30.0 = phi float [ 1.000000e+00, %main_body ], [ %257, %ENDIF ] + %225 = fcmp oge float %temp24.0, %191 + %226 = sext i1 %225 to i32 + %227 = bitcast i32 %226 to float + %228 = bitcast float %227 to i32 + %229 = icmp ne i32 %228, 0 + br i1 %229, label %IF, label %ENDIF + +IF: ; preds = %LOOP + %230 = bitcast float %136 to i32 + %231 = bitcast float %182 to i32 + %232 = bitcast float %137 to i32 + %233 = bitcast float %183 to i32 + %234 = insertelement <8 x i32> undef, i32 %230, i32 0 + %235 = insertelement <8 x i32> %234, i32 %231, i32 1 + %236 = insertelement <8 x i32> %235, i32 %232, i32 2 + %237 = insertelement <8 x i32> %236, i32 %233, i32 3 + br label %LOOP65 + +ENDIF: ; preds = %LOOP + %238 = bitcast float %temp28.0 to i32 + %239 = bitcast float %temp29.0 to i32 + %240 = insertelement <8 x i32> %224, i32 %238, i32 4 + %241 = insertelement <8 x i32> %240, i32 %239, i32 5 + %242 = insertelement <8 x i32> %241, i32 undef, i32 6 + %243 = insertelement <8 x i32> %242, i32 undef, i32 7 + %244 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %243, <32 x i8> %62, <16 x i8> %64, i32 2) + %245 = extractelement <4 x float> %244, i32 3 + %246 = fcmp oge float %temp30.0, %245 + %247 = sext i1 %246 to i32 + %248 = bitcast i32 %247 to float + %249 = bitcast float %248 to i32 + %250 = and i32 %249, 1065353216 + %251 = bitcast i32 %250 to float + %252 = fmul float %214, %251 + %253 = fadd float %252, %temp28.0 + %254 = fmul float %215, %251 + %255 = fadd float %254, %temp29.0 + %256 = fmul float %216, %251 + %257 = fadd float %256, %temp30.0 + %258 = fadd float %temp24.0, 1.000000e+00 + br label %LOOP + +LOOP65: ; preds = %ENDIF66, %IF + %temp24.1 = phi float [ 0.000000e+00, %IF ], [ %610, %ENDIF66 ] + %temp28.1 = phi float [ %temp28.0, %IF ], [ %605, %ENDIF66 ] + %temp29.1 = phi float [ %temp29.0, %IF ], [ %607, %ENDIF66 ] + %temp30.1 = phi float [ %temp30.0, %IF ], [ %609, %ENDIF66 ] + %temp32.0 = phi float [ 1.000000e+00, %IF ], [ %611, %ENDIF66 ] + %259 = fcmp oge float %temp24.1, %195 + %260 = sext i1 %259 to i32 + %261 = bitcast i32 %260 to float + %262 = bitcast float %261 to i32 + %263 = icmp ne i32 %262, 0 + br i1 %263, label %IF67, label %ENDIF66 + +IF67: ; preds = %LOOP65 + %264 = bitcast float %136 to i32 + %265 = bitcast float %182 to i32 + %266 = bitcast float %137 to i32 + %267 = bitcast float %183 to i32 + %268 = bitcast float %temp28.1 to i32 + %269 = bitcast float %temp29.1 to i32 + %270 = insertelement <8 x i32> undef, i32 %264, i32 0 + %271 = insertelement <8 x i32> %270, i32 %265, i32 1 + %272 = insertelement <8 x i32> %271, i32 %266, i32 2 + %273 = insertelement <8 x i32> %272, i32 %267, i32 3 + %274 = insertelement <8 x i32> %273, i32 %268, i32 4 + %275 = insertelement <8 x i32> %274, i32 %269, i32 5 + %276 = insertelement <8 x i32> %275, i32 undef, i32 6 + %277 = insertelement <8 x i32> %276, i32 undef, i32 7 + %278 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %277, <32 x i8> %66, <16 x i8> %68, i32 2) + %279 = extractelement <4 x float> %278, i32 0 + %280 = extractelement <4 x float> %278, i32 1 + %281 = extractelement <4 x float> %278, i32 2 + %282 = extractelement <4 x float> %278, i32 3 + %283 = fmul float %282, %47 + %284 = bitcast float %136 to i32 + %285 = bitcast float %182 to i32 + %286 = bitcast float %137 to i32 + %287 = bitcast float %183 to i32 + %288 = bitcast float %temp28.1 to i32 + %289 = bitcast float %temp29.1 to i32 + %290 = insertelement <8 x i32> undef, i32 %284, i32 0 + %291 = insertelement <8 x i32> %290, i32 %285, i32 1 + %292 = insertelement <8 x i32> %291, i32 %286, i32 2 + %293 = insertelement <8 x i32> %292, i32 %287, i32 3 + %294 = insertelement <8 x i32> %293, i32 %288, i32 4 + %295 = insertelement <8 x i32> %294, i32 %289, i32 5 + %296 = insertelement <8 x i32> %295, i32 undef, i32 6 + %297 = insertelement <8 x i32> %296, i32 undef, i32 7 + %298 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %297, <32 x i8> %82, <16 x i8> %84, i32 2) + %299 = extractelement <4 x float> %298, i32 0 + %300 = extractelement <4 x float> %298, i32 1 + %301 = extractelement <4 x float> %298, i32 2 + %302 = bitcast float %136 to i32 + %303 = bitcast float %182 to i32 + %304 = bitcast float %137 to i32 + %305 = bitcast float %183 to i32 + %306 = bitcast float %temp28.1 to i32 + %307 = bitcast float %temp29.1 to i32 + %308 = insertelement <8 x i32> undef, i32 %302, i32 0 + %309 = insertelement <8 x i32> %308, i32 %303, i32 1 + %310 = insertelement <8 x i32> %309, i32 %304, i32 2 + %311 = insertelement <8 x i32> %310, i32 %305, i32 3 + %312 = insertelement <8 x i32> %311, i32 %306, i32 4 + %313 = insertelement <8 x i32> %312, i32 %307, i32 5 + %314 = insertelement <8 x i32> %313, i32 undef, i32 6 + %315 = insertelement <8 x i32> %314, i32 undef, i32 7 + %316 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %315, <32 x i8> %78, <16 x i8> %80, i32 2) + %317 = extractelement <4 x float> %316, i32 0 + %318 = extractelement <4 x float> %316, i32 1 + %319 = extractelement <4 x float> %316, i32 2 + %320 = fmul float %317, %23 + %321 = fmul float %318, %24 + %322 = fmul float %319, %25 + %323 = fmul float %299, %26 + %324 = fadd float %323, %320 + %325 = fmul float %300, %27 + %326 = fadd float %325, %321 + %327 = fmul float %301, %28 + %328 = fadd float %327, %322 + %329 = fadd float %279, %324 + %330 = fadd float %280, %326 + %331 = fadd float %281, %328 + %332 = bitcast float %136 to i32 + %333 = bitcast float %182 to i32 + %334 = bitcast float %137 to i32 + %335 = bitcast float %183 to i32 + %336 = bitcast float %temp28.1 to i32 + %337 = bitcast float %temp29.1 to i32 + %338 = insertelement <8 x i32> undef, i32 %332, i32 0 + %339 = insertelement <8 x i32> %338, i32 %333, i32 1 + %340 = insertelement <8 x i32> %339, i32 %334, i32 2 + %341 = insertelement <8 x i32> %340, i32 %335, i32 3 + %342 = insertelement <8 x i32> %341, i32 %336, i32 4 + %343 = insertelement <8 x i32> %342, i32 %337, i32 5 + %344 = insertelement <8 x i32> %343, i32 undef, i32 6 + %345 = insertelement <8 x i32> %344, i32 undef, i32 7 + %346 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %345, <32 x i8> %62, <16 x i8> %64, i32 2) + %347 = extractelement <4 x float> %346, i32 0 + %348 = extractelement <4 x float> %346, i32 1 + %349 = extractelement <4 x float> %346, i32 2 + %350 = fadd float %347, -5.000000e-01 + %351 = fadd float %348, -5.000000e-01 + %352 = fadd float %349, -5.000000e-01 + %353 = fmul float %350, %350 + %354 = fmul float %351, %351 + %355 = fadd float %354, %353 + %356 = fmul float %352, %352 + %357 = fadd float %355, %356 + %358 = call float @llvm.AMDGPU.rsq(float %357) + %359 = fmul float %350, %358 + %360 = fmul float %351, %358 + %361 = fmul float %352, %358 + %362 = bitcast float %136 to i32 + %363 = bitcast float %182 to i32 + %364 = bitcast float %137 to i32 + %365 = bitcast float %183 to i32 + %366 = bitcast float %temp28.1 to i32 + %367 = bitcast float %temp29.1 to i32 + %368 = insertelement <8 x i32> undef, i32 %362, i32 0 + %369 = insertelement <8 x i32> %368, i32 %363, i32 1 + %370 = insertelement <8 x i32> %369, i32 %364, i32 2 + %371 = insertelement <8 x i32> %370, i32 %365, i32 3 + %372 = insertelement <8 x i32> %371, i32 %366, i32 4 + %373 = insertelement <8 x i32> %372, i32 %367, i32 5 + %374 = insertelement <8 x i32> %373, i32 undef, i32 6 + %375 = insertelement <8 x i32> %374, i32 undef, i32 7 + %376 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %375, <32 x i8> %70, <16 x i8> %72, i32 2) + %377 = extractelement <4 x float> %376, i32 0 + %378 = extractelement <4 x float> %376, i32 1 + %379 = extractelement <4 x float> %376, i32 2 + %380 = extractelement <4 x float> %376, i32 3 + %381 = fsub float -0.000000e+00, %95 + %382 = fsub float -0.000000e+00, %96 + %383 = fsub float -0.000000e+00, %97 + %384 = fmul float %359, %381 + %385 = fmul float %360, %382 + %386 = fadd float %385, %384 + %387 = fmul float %361, %383 + %388 = fadd float %386, %387 + %389 = fmul float %388, %359 + %390 = fmul float %388, %360 + %391 = fmul float %388, %361 + %392 = fmul float 2.000000e+00, %389 + %393 = fmul float 2.000000e+00, %390 + %394 = fmul float 2.000000e+00, %391 + %395 = fsub float -0.000000e+00, %392 + %396 = fadd float %381, %395 + %397 = fsub float -0.000000e+00, %393 + %398 = fadd float %382, %397 + %399 = fsub float -0.000000e+00, %394 + %400 = fadd float %383, %399 + %401 = fmul float %396, %98 + %402 = fmul float %396, %99 + %403 = fmul float %396, %100 + %404 = fmul float %398, %101 + %405 = fadd float %404, %401 + %406 = fmul float %398, %102 + %407 = fadd float %406, %402 + %408 = fmul float %398, %103 + %409 = fadd float %408, %403 + %410 = fmul float %400, %104 + %411 = fadd float %410, %405 + %412 = fmul float %400, %105 + %413 = fadd float %412, %407 + %414 = fmul float %400, %106 + %415 = fadd float %414, %409 + %416 = bitcast float %136 to i32 + %417 = bitcast float %182 to i32 + %418 = bitcast float %137 to i32 + %419 = bitcast float %183 to i32 + %420 = bitcast float %temp28.1 to i32 + %421 = bitcast float %temp29.1 to i32 + %422 = insertelement <8 x i32> undef, i32 %416, i32 0 + %423 = insertelement <8 x i32> %422, i32 %417, i32 1 + %424 = insertelement <8 x i32> %423, i32 %418, i32 2 + %425 = insertelement <8 x i32> %424, i32 %419, i32 3 + %426 = insertelement <8 x i32> %425, i32 %420, i32 4 + %427 = insertelement <8 x i32> %426, i32 %421, i32 5 + %428 = insertelement <8 x i32> %427, i32 undef, i32 6 + %429 = insertelement <8 x i32> %428, i32 undef, i32 7 + %430 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %429, <32 x i8> %86, <16 x i8> %88, i32 2) + %431 = extractelement <4 x float> %430, i32 0 + %432 = extractelement <4 x float> %430, i32 1 + %433 = extractelement <4 x float> %430, i32 2 + %434 = fmul float %48, %411 + %435 = fmul float %49, %411 + %436 = fmul float %50, %411 + %437 = fmul float %51, %413 + %438 = fadd float %437, %434 + %439 = fmul float %52, %413 + %440 = fadd float %439, %435 + %441 = fmul float %53, %413 + %442 = fadd float %441, %436 + %443 = fmul float %54, %415 + %444 = fadd float %443, %438 + %445 = fmul float %55, %415 + %446 = fadd float %445, %440 + %447 = fmul float %56, %415 + %448 = fadd float %447, %442 + %449 = insertelement <4 x float> undef, float %444, i32 0 + %450 = insertelement <4 x float> %449, float %446, i32 1 + %451 = insertelement <4 x float> %450, float %448, i32 2 + %452 = insertelement <4 x float> %451, float %195, i32 3 + %453 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %452) + %454 = extractelement <4 x float> %453, i32 0 + %455 = extractelement <4 x float> %453, i32 1 + %456 = extractelement <4 x float> %453, i32 2 + %457 = extractelement <4 x float> %453, i32 3 + %458 = call float @fabs(float %456) + %459 = fdiv float 1.000000e+00, %458 + %460 = fmul float %454, %459 + %461 = fadd float %460, 1.500000e+00 + %462 = fmul float %455, %459 + %463 = fadd float %462, 1.500000e+00 + %464 = bitcast float %463 to i32 + %465 = bitcast float %461 to i32 + %466 = bitcast float %457 to i32 + %467 = insertelement <4 x i32> undef, i32 %464, i32 0 + %468 = insertelement <4 x i32> %467, i32 %465, i32 1 + %469 = insertelement <4 x i32> %468, i32 %466, i32 2 + %470 = insertelement <4 x i32> %469, i32 undef, i32 3 + %471 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %470, <32 x i8> %90, <16 x i8> %92, i32 4) + %472 = extractelement <4 x float> %471, i32 0 + %473 = extractelement <4 x float> %471, i32 1 + %474 = extractelement <4 x float> %471, i32 2 + %475 = fmul float %431, %472 + %476 = fadd float %475, %329 + %477 = fmul float %432, %473 + %478 = fadd float %477, %330 + %479 = fmul float %433, %474 + %480 = fadd float %479, %331 + %481 = fmul float %107, %107 + %482 = fmul float %108, %108 + %483 = fadd float %482, %481 + %484 = fmul float %109, %109 + %485 = fadd float %483, %484 + %486 = call float @llvm.AMDGPU.rsq(float %485) + %487 = fmul float %107, %486 + %488 = fmul float %108, %486 + %489 = fmul float %109, %486 + %490 = fmul float %377, %40 + %491 = fmul float %378, %41 + %492 = fmul float %379, %42 + %493 = fmul float %359, %487 + %494 = fmul float %360, %488 + %495 = fadd float %494, %493 + %496 = fmul float %361, %489 + %497 = fadd float %495, %496 + %498 = fmul float %497, %359 + %499 = fmul float %497, %360 + %500 = fmul float %497, %361 + %501 = fmul float 2.000000e+00, %498 + %502 = fmul float 2.000000e+00, %499 + %503 = fmul float 2.000000e+00, %500 + %504 = fsub float -0.000000e+00, %501 + %505 = fadd float %487, %504 + %506 = fsub float -0.000000e+00, %502 + %507 = fadd float %488, %506 + %508 = fsub float -0.000000e+00, %503 + %509 = fadd float %489, %508 + %510 = fmul float %95, %95 + %511 = fmul float %96, %96 + %512 = fadd float %511, %510 + %513 = fmul float %97, %97 + %514 = fadd float %512, %513 + %515 = call float @llvm.AMDGPU.rsq(float %514) + %516 = fmul float %95, %515 + %517 = fmul float %96, %515 + %518 = fmul float %97, %515 + %519 = fmul float %505, %516 + %520 = fmul float %507, %517 + %521 = fadd float %520, %519 + %522 = fmul float %509, %518 + %523 = fadd float %521, %522 + %524 = fsub float -0.000000e+00, %523 + %525 = fcmp uge float %524, 0.000000e+00 + %526 = select i1 %525, float %524, float 0.000000e+00 + %527 = fmul float %43, %380 + %528 = fadd float %527, 1.000000e+00 + %529 = call float @llvm.pow.f32(float %526, float %528) + %530 = fmul float %476, %37 + %531 = fmul float %478, %38 + %532 = fmul float %480, %39 + %533 = fmul float %359, %487 + %534 = fmul float %360, %488 + %535 = fadd float %534, %533 + %536 = fmul float %361, %489 + %537 = fadd float %535, %536 + %538 = fcmp uge float %537, 0.000000e+00 + %539 = select i1 %538, float %537, float 0.000000e+00 + %540 = fmul float %530, %539 + %541 = fmul float %531, %539 + %542 = fmul float %532, %539 + %543 = fmul float %490, %529 + %544 = fadd float %543, %540 + %545 = fmul float %491, %529 + %546 = fadd float %545, %541 + %547 = fmul float %492, %529 + %548 = fadd float %547, %542 + %549 = fmul float %476, %34 + %550 = fmul float %478, %35 + %551 = fmul float %480, %36 + %552 = fmul float %544, %57 + %553 = fadd float %552, %549 + %554 = fmul float %546, %58 + %555 = fadd float %554, %550 + %556 = fmul float %548, %59 + %557 = fadd float %556, %551 + %558 = bitcast float %136 to i32 + %559 = bitcast float %182 to i32 + %560 = bitcast float %137 to i32 + %561 = bitcast float %183 to i32 + %562 = bitcast float %temp28.1 to i32 + %563 = bitcast float %temp29.1 to i32 + %564 = insertelement <8 x i32> undef, i32 %558, i32 0 + %565 = insertelement <8 x i32> %564, i32 %559, i32 1 + %566 = insertelement <8 x i32> %565, i32 %560, i32 2 + %567 = insertelement <8 x i32> %566, i32 %561, i32 3 + %568 = insertelement <8 x i32> %567, i32 %562, i32 4 + %569 = insertelement <8 x i32> %568, i32 %563, i32 5 + %570 = insertelement <8 x i32> %569, i32 undef, i32 6 + %571 = insertelement <8 x i32> %570, i32 undef, i32 7 + %572 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %571, <32 x i8> %74, <16 x i8> %76, i32 2) + %573 = extractelement <4 x float> %572, i32 0 + %574 = extractelement <4 x float> %572, i32 1 + %575 = extractelement <4 x float> %572, i32 2 + %576 = fmul float %573, %44 + %577 = fadd float %576, %553 + %578 = fmul float %574, %45 + %579 = fadd float %578, %555 + %580 = fmul float %575, %46 + %581 = fadd float %580, %557 + %582 = call i32 @llvm.SI.packf16(float %577, float %579) + %583 = bitcast i32 %582 to float + %584 = call i32 @llvm.SI.packf16(float %581, float %283) + %585 = bitcast i32 %584 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %583, float %585, float %583, float %585) + ret void + +ENDIF66: ; preds = %LOOP65 + %586 = bitcast float %temp28.1 to i32 + %587 = bitcast float %temp29.1 to i32 + %588 = insertelement <8 x i32> %237, i32 %586, i32 4 + %589 = insertelement <8 x i32> %588, i32 %587, i32 5 + %590 = insertelement <8 x i32> %589, i32 undef, i32 6 + %591 = insertelement <8 x i32> %590, i32 undef, i32 7 + %592 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %591, <32 x i8> %62, <16 x i8> %64, i32 2) + %593 = extractelement <4 x float> %592, i32 3 + %594 = fcmp oge float %temp30.1, %593 + %595 = sext i1 %594 to i32 + %596 = bitcast i32 %595 to float + %597 = bitcast float %596 to i32 + %598 = and i32 %597, 1065353216 + %599 = bitcast i32 %598 to float + %600 = fmul float 5.000000e-01, %temp32.0 + %601 = fsub float -0.000000e+00, %600 + %602 = fmul float %599, %temp32.0 + %603 = fadd float %602, %601 + %604 = fmul float %214, %603 + %605 = fadd float %604, %temp28.1 + %606 = fmul float %215, %603 + %607 = fadd float %606, %temp29.1 + %608 = fmul float %216, %603 + %609 = fadd float %608, %temp30.1 + %610 = fadd float %temp24.1, 1.000000e+00 + %611 = fmul float %temp32.0, 5.000000e-01 + br label %LOOP65 +} + +; Function Attrs: nounwind readnone +declare float @llvm.SI.load.const(<16 x i8>, i32) #1 + +; Function Attrs: nounwind readnone +declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 + +; Function Attrs: readnone +declare i32 @llvm.SI.tid() #2 + +; Function Attrs: readonly +declare float @ceil(float) #3 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.rsq(float) #2 + +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.SI.sampled.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32) #1 + +; Function Attrs: readnone +declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2 + +; Function Attrs: readnone +declare float @fabs(float) #2 + +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1 + +; Function Attrs: nounwind readonly +declare float @llvm.pow.f32(float, float) #4 + +; Function Attrs: nounwind readnone +declare i32 @llvm.SI.packf16(float, float) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } +attributes #1 = { nounwind readnone } +attributes #2 = { readnone } +attributes #3 = { readonly } +attributes #4 = { nounwind readonly } + +!0 = metadata !{metadata !"const", null, i32 1} diff --git a/test/CodeGen/R600/si-vector-hang.ll b/test/CodeGen/R600/si-vector-hang.ll new file mode 100644 index 000000000000..093234f71958 --- /dev/null +++ b/test/CodeGen/R600/si-vector-hang.ll @@ -0,0 +1,107 @@ +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s + +; CHECK: @test_8_min_char +; CHECK: BUFFER_STORE_BYTE +; CHECK: BUFFER_STORE_BYTE +; CHECK: BUFFER_STORE_BYTE +; CHECK: BUFFER_STORE_BYTE +; CHECK: BUFFER_STORE_BYTE +; CHECK: BUFFER_STORE_BYTE +; CHECK: BUFFER_STORE_BYTE +; CHECK: BUFFER_STORE_BYTE +; ModuleID = 'radeon' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64" +target triple = "r600--" + +; Function Attrs: nounwind +define void @test_8_min_char(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture readonly %in0, i8 addrspace(1)* nocapture readonly %in1) #0 { +entry: + %0 = load i8 addrspace(1)* %in0, align 1 + %1 = insertelement <8 x i8> undef, i8 %0, i32 0 + %arrayidx2.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 1 + %2 = load i8 addrspace(1)* %arrayidx2.i.i, align 1 + %3 = insertelement <8 x i8> %1, i8 %2, i32 1 + %arrayidx6.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 2 + %4 = load i8 addrspace(1)* %arrayidx6.i.i, align 1 + %5 = insertelement <8 x i8> %3, i8 %4, i32 2 + %arrayidx10.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 3 + %6 = load i8 addrspace(1)* %arrayidx10.i.i, align 1 + %7 = insertelement <8 x i8> %5, i8 %6, i32 3 + %arrayidx.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 4 + %8 = load i8 addrspace(1)* %arrayidx.i.i, align 1 + %9 = insertelement <8 x i8> undef, i8 %8, i32 0 + %arrayidx2.i9.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 5 + %10 = load i8 addrspace(1)* %arrayidx2.i9.i, align 1 + %11 = insertelement <8 x i8> %9, i8 %10, i32 1 + %arrayidx6.i11.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 6 + %12 = load i8 addrspace(1)* %arrayidx6.i11.i, align 1 + %13 = insertelement <8 x i8> %11, i8 %12, i32 2 + %arrayidx10.i13.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 7 + %14 = load i8 addrspace(1)* %arrayidx10.i13.i, align 1 + %15 = insertelement <8 x i8> %13, i8 %14, i32 3 + %vecinit5.i = shufflevector <8 x i8> %7, <8 x i8> %15, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> + %16 = load i8 addrspace(1)* %in1, align 1 + %17 = insertelement <8 x i8> undef, i8 %16, i32 0 + %arrayidx2.i.i4 = getelementptr inbounds i8 addrspace(1)* %in1, i64 1 + %18 = load i8 addrspace(1)* %arrayidx2.i.i4, align 1 + %19 = insertelement <8 x i8> %17, i8 %18, i32 1 + %arrayidx6.i.i5 = getelementptr inbounds i8 addrspace(1)* %in1, i64 2 + %20 = load i8 addrspace(1)* %arrayidx6.i.i5, align 1 + %21 = insertelement <8 x i8> %19, i8 %20, i32 2 + %arrayidx10.i.i6 = getelementptr inbounds i8 addrspace(1)* %in1, i64 3 + %22 = load i8 addrspace(1)* %arrayidx10.i.i6, align 1 + %23 = insertelement <8 x i8> %21, i8 %22, i32 3 + %arrayidx.i.i7 = getelementptr inbounds i8 addrspace(1)* %in1, i64 4 + %24 = load i8 addrspace(1)* %arrayidx.i.i7, align 1 + %25 = insertelement <8 x i8> undef, i8 %24, i32 0 + %arrayidx2.i9.i8 = getelementptr inbounds i8 addrspace(1)* %in1, i64 5 + %26 = load i8 addrspace(1)* %arrayidx2.i9.i8, align 1 + %27 = insertelement <8 x i8> %25, i8 %26, i32 1 + %arrayidx6.i11.i9 = getelementptr inbounds i8 addrspace(1)* %in1, i64 6 + %28 = load i8 addrspace(1)* %arrayidx6.i11.i9, align 1 + %29 = insertelement <8 x i8> %27, i8 %28, i32 2 + %arrayidx10.i13.i10 = getelementptr inbounds i8 addrspace(1)* %in1, i64 7 + %30 = load i8 addrspace(1)* %arrayidx10.i13.i10, align 1 + %31 = insertelement <8 x i8> %29, i8 %30, i32 3 + %vecinit5.i11 = shufflevector <8 x i8> %23, <8 x i8> %31, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> + %cmp.i = icmp slt <8 x i8> %vecinit5.i, %vecinit5.i11 + %cond.i = select <8 x i1> %cmp.i, <8 x i8> %vecinit5.i, <8 x i8> %vecinit5.i11 + %32 = extractelement <8 x i8> %cond.i, i32 0 + store i8 %32, i8 addrspace(1)* %out, align 1 + %33 = extractelement <8 x i8> %cond.i, i32 1 + %arrayidx2.i.i.i = getelementptr inbounds i8 addrspace(1)* %out, i64 1 + store i8 %33, i8 addrspace(1)* %arrayidx2.i.i.i, align 1 + %34 = extractelement <8 x i8> %cond.i, i32 2 + %arrayidx.i.i.i = getelementptr inbounds i8 addrspace(1)* %out, i64 2 + store i8 %34, i8 addrspace(1)* %arrayidx.i.i.i, align 1 + %35 = extractelement <8 x i8> %cond.i, i32 3 + %arrayidx2.i6.i.i = getelementptr inbounds i8 addrspace(1)* %out, i64 3 + store i8 %35, i8 addrspace(1)* %arrayidx2.i6.i.i, align 1 + %arrayidx.i.i3 = getelementptr inbounds i8 addrspace(1)* %out, i64 4 + %36 = extractelement <8 x i8> %cond.i, i32 4 + store i8 %36, i8 addrspace(1)* %arrayidx.i.i3, align 1 + %37 = extractelement <8 x i8> %cond.i, i32 5 + %arrayidx2.i.i6.i = getelementptr inbounds i8 addrspace(1)* %out, i64 5 + store i8 %37, i8 addrspace(1)* %arrayidx2.i.i6.i, align 1 + %38 = extractelement <8 x i8> %cond.i, i32 6 + %arrayidx.i.i7.i = getelementptr inbounds i8 addrspace(1)* %out, i64 6 + store i8 %38, i8 addrspace(1)* %arrayidx.i.i7.i, align 1 + %39 = extractelement <8 x i8> %cond.i, i32 7 + %arrayidx2.i6.i8.i = getelementptr inbounds i8 addrspace(1)* %out, i64 7 + store i8 %39, i8 addrspace(1)* %arrayidx2.i6.i8.i, align 1 + ret void +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!opencl.kernels = !{!0, !1, !2, !3, !4, !5, !6, !7, !8} + +!0 = metadata !{null} +!1 = metadata !{null} +!2 = metadata !{null} +!3 = metadata !{void (i8 addrspace(1)*, i8 addrspace(1)*, i8 addrspace(1)*)* @test_8_min_char} +!4 = metadata !{null} +!5 = metadata !{null} +!6 = metadata !{null} +!7 = metadata !{null} +!8 = metadata !{null} diff --git a/test/CodeGen/R600/sign_extend.ll b/test/CodeGen/R600/sign_extend.ll new file mode 100644 index 000000000000..1212cee9446e --- /dev/null +++ b/test/CodeGen/R600/sign_extend.ll @@ -0,0 +1,12 @@ + +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s + +; CHECK: V_ASHR +define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { +entry: + %0 = mul i32 %a, %b + %1 = add i32 %0, %c + %2 = sext i32 %1 to i64 + store i64 %2, i64 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/sint_to_fp.ll b/test/CodeGen/R600/sint_to_fp.ll index 91a8eb7f57b4..9241799091c0 100644 --- a/test/CodeGen/R600/sint_to_fp.ll +++ b/test/CodeGen/R600/sint_to_fp.ll @@ -1,11 +1,28 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; CHECK: @sint_to_fp_v4i32 -; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: @sint_to_fp_v2i32 +; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W +; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X +; SI-CHECK: @sint_to_fp_v2i32 +; SI-CHECK: V_CVT_F32_I32_e32 +; SI-CHECK: V_CVT_F32_I32_e32 +define void @sint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) { + %result = sitofp <2 x i32> %in to <2 x float> + store <2 x float> %result, <2 x float> addrspace(1)* %out + ret void +} +; R600-CHECK: @sint_to_fp_v4i32 +; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; SI-CHECK: @sint_to_fp_v4i32 +; SI-CHECK: V_CVT_F32_I32_e32 +; SI-CHECK: V_CVT_F32_I32_e32 +; SI-CHECK: V_CVT_F32_I32_e32 +; SI-CHECK: V_CVT_F32_I32_e32 define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %value = load <4 x i32> addrspace(1) * %in %result = sitofp <4 x i32> %value to <4 x float> diff --git a/test/CodeGen/R600/sint_to_fp64.ll b/test/CodeGen/R600/sint_to_fp64.ll new file mode 100644 index 000000000000..5abc9d15965d --- /dev/null +++ b/test/CodeGen/R600/sint_to_fp64.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=CHECK + +; CHECK: @sint_to_fp64 +; CHECK: V_CVT_F64_I32_e32 +define void @sint_to_fp64(double addrspace(1)* %out, i32 %in) { + %result = sitofp i32 %in to double + store double %result, double addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll index 972542d346f4..fe9df104ae11 100644 --- a/test/CodeGen/R600/sra.ll +++ b/test/CodeGen/R600/sra.ll @@ -1,13 +1,54 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; CHECK: @ashr_v4i32 -; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK-LABEL: @ashr_v2i32 +;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { +;SI-CHECK-LABEL: @ashr_v2i32 +;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 + %a = load <2 x i32> addrspace(1) * %in + %b = load <2 x i32> addrspace(1) * %b_ptr + %result = ashr <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +;EG-CHECK-LABEL: @ashr_v4i32 +;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK-LABEL: @ashr_v4i32 +;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 + %a = load <4 x i32> addrspace(1) * %in + %b = load <4 x i32> addrspace(1) * %b_ptr %result = ashr <4 x i32> %a, %b store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } + +;EG-CHECK-LABEL: @ashr_i64 +;EG-CHECK: ASHR + +;SI-CHECK-LABEL: @ashr_i64 +;SI-CHECK: S_ASHR_I64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 +define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) { +entry: + %0 = sext i32 %in to i64 + %1 = ashr i64 %0, 8 + store i64 %1, i64 addrspace(1)* %out + ret void +} + diff --git a/test/CodeGen/R600/srl.ll b/test/CodeGen/R600/srl.ll index 5f63600b75f0..76373552fb16 100644 --- a/test/CodeGen/R600/srl.ll +++ b/test/CodeGen/R600/srl.ll @@ -1,12 +1,40 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; CHECK: @lshr_v4i32 -; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: @lshr_v2i32 +;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { +;SI-CHECK: @lshr_v2i32 +;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 + %a = load <2 x i32> addrspace(1) * %in + %b = load <2 x i32> addrspace(1) * %b_ptr + %result = lshr <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + + +;EG-CHECK: @lshr_v4i32 +;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK: @lshr_v4i32 +;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_LSHR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 + %a = load <4 x i32> addrspace(1) * %in + %b = load <4 x i32> addrspace(1) * %b_ptr %result = lshr <4 x i32> %a, %b store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void diff --git a/test/CodeGen/R600/store-vector-ptrs.ll b/test/CodeGen/R600/store-vector-ptrs.ll new file mode 100644 index 000000000000..01210ce1f944 --- /dev/null +++ b/test/CodeGen/R600/store-vector-ptrs.ll @@ -0,0 +1,8 @@ +; XFAIL: * +; RUN: llc -march=r600 -mcpu=SI < %s + +define void @store_vector_ptrs(<4 x i32*>* %out, <4 x [1024 x i32]*> %array) nounwind { + %p = getelementptr <4 x [1024 x i32]*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16> + store <4 x i32*> %p, <4 x i32*>* %out + ret void +}
\ No newline at end of file diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll index 4d673f3ea326..5e51d5691747 100644 --- a/test/CodeGen/R600/store.ll +++ b/test/CodeGen/R600/store.ll @@ -1,13 +1,282 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s -; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s + +;===------------------------------------------------------------------------===; +; Global Address Space +;===------------------------------------------------------------------------===; + +; i8 store +; EG-CHECK-LABEL: @store_i8 +; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X +; EG-CHECK: VTX_READ_8 [[VAL:T[0-9]\.X]], [[VAL]] +; IG 0: Get the byte index and truncate the value +; EG-CHECK: AND_INT T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; EG-CHECK-NEXT: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.y +; EG-CHECK-NEXT: 3(4.203895e-45), 255(3.573311e-43) +; IG 1: Truncate the calculated the shift amount for the mask +; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x +; EG-CHECK-NEXT: 3 +; IG 2: Shift the value and the mask +; EG-CHECK: LSHL T[[RW_GPR]].X, T{{[0-9]}}.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]] +; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] +; EG-CHECK-NEXT: 255 +; IG 3: Initialize the Y and Z channels to zero +; XXX: An optimal scheduler should merge this into one of the prevous IGs. +; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0 +; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0 + +; SI-CHECK-LABEL: @store_i8 +; SI-CHECK: BUFFER_STORE_BYTE + +define void @store_i8(i8 addrspace(1)* %out, i8 %in) { +entry: + store i8 %in, i8 addrspace(1)* %out + ret void +} + +; i16 store +; EG-CHECK-LABEL: @store_i16 +; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X +; EG-CHECK: VTX_READ_16 [[VAL:T[0-9]\.X]], [[VAL]] +; IG 0: Get the byte index and truncate the value +; EG-CHECK: AND_INT T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.y +; EG-CHECK-NEXT: 3(4.203895e-45), 65535(9.183409e-41) +; IG 1: Truncate the calculated the shift amount for the mask +; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x +; EG-CHECK: 3 +; IG 2: Shift the value and the mask +; EG-CHECK: LSHL T[[RW_GPR]].X, T{{[0-9]}}.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]] +; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] +; EG-CHECK-NEXT: 65535 +; IG 3: Initialize the Y and Z channels to zero +; XXX: An optimal scheduler should merge this into one of the prevous IGs. +; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0 +; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0 + +; SI-CHECK-LABEL: @store_i16 +; SI-CHECK: BUFFER_STORE_SHORT +define void @store_i16(i16 addrspace(1)* %out, i16 %in) { +entry: + store i16 %in, i16 addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @store_v2i8 +; EG-CHECK: MEM_RAT MSKOR +; EG-CHECK-NOT: MEM_RAT MSKOR +; SI-CHECK-LABEL: @store_v2i8 +; SI-CHECK: BUFFER_STORE_BYTE +; SI-CHECK: BUFFER_STORE_BYTE +define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) { +entry: + %0 = trunc <2 x i32> %in to <2 x i8> + store <2 x i8> %0, <2 x i8> addrspace(1)* %out + ret void +} + + +; EG-CHECK-LABEL: @store_v2i16 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW +; CM-CHECK-LABEL: @store_v2i16 +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD +; SI-CHECK-LABEL: @store_v2i16 +; SI-CHECK: BUFFER_STORE_SHORT +; SI-CHECK: BUFFER_STORE_SHORT +define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) { +entry: + %0 = trunc <2 x i32> %in to <2 x i16> + store <2 x i16> %0, <2 x i16> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @store_v4i8 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW +; CM-CHECK-LABEL: @store_v4i8 +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD +; SI-CHECK-LABEL: @store_v4i8 +; SI-CHECK: BUFFER_STORE_BYTE +; SI-CHECK: BUFFER_STORE_BYTE +; SI-CHECK: BUFFER_STORE_BYTE +; SI-CHECK: BUFFER_STORE_BYTE +define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) { +entry: + %0 = trunc <4 x i32> %in to <4 x i8> + store <4 x i8> %0, <4 x i8> addrspace(1)* %out + ret void +} ; floating-point store -; EG-CHECK: @store_f32 -; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1 -; SI-CHECK: @store_f32 +; EG-CHECK-LABEL: @store_f32 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1 +; CM-CHECK-LABEL: @store_f32 +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} +; SI-CHECK-LABEL: @store_f32 ; SI-CHECK: BUFFER_STORE_DWORD define void @store_f32(float addrspace(1)* %out, float %in) { store float %in, float addrspace(1)* %out ret void } + +; EG-CHECK-LABEL: @store_v4i16 +; EG-CHECK: MEM_RAT MSKOR +; EG-CHECK: MEM_RAT MSKOR +; EG-CHECK: MEM_RAT MSKOR +; EG-CHECK: MEM_RAT MSKOR +; EG-CHECK-NOT: MEM_RAT MSKOR +; SI-CHECK-LABEL: @store_v4i16 +; SI-CHECK: BUFFER_STORE_SHORT +; SI-CHECK: BUFFER_STORE_SHORT +; SI-CHECK: BUFFER_STORE_SHORT +; SI-CHECK: BUFFER_STORE_SHORT +; SI-CHECK-NOT: BUFFER_STORE_BYTE +define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) { +entry: + %0 = trunc <4 x i32> %in to <4 x i16> + store <4 x i16> %0, <4 x i16> addrspace(1)* %out + ret void +} + +; vec2 floating-point stores +; EG-CHECK-LABEL: @store_v2f32 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW +; CM-CHECK-LABEL: @store_v2f32 +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD +; SI-CHECK-LABEL: @store_v2f32 +; SI-CHECK: BUFFER_STORE_DWORDX2 + +define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) { +entry: + %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0 + %1 = insertelement <2 x float> %0, float %b, i32 1 + store <2 x float> %1, <2 x float> addrspace(1)* %out + ret void +} + +; EG-CHECK-LABEL: @store_v4i32 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW +; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW +; CM-CHECK-LABEL: @store_v4i32 +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD +; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD +; SI-CHECK-LABEL: @store_v4i32 +; SI-CHECK: BUFFER_STORE_DWORDX4 +define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) { +entry: + store <4 x i32> %in, <4 x i32> addrspace(1)* %out + ret void +} + +;===------------------------------------------------------------------------===; +; Local Address Space +;===------------------------------------------------------------------------===; + +; EG-CHECK-LABEL: @store_local_i8 +; EG-CHECK: LDS_BYTE_WRITE +; SI-CHECK-LABEL: @store_local_i8 +; SI-CHECK: DS_WRITE_B8 +define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) { + store i8 %in, i8 addrspace(3)* %out + ret void +} + +; EG-CHECK-LABEL: @store_local_i16 +; EG-CHECK: LDS_SHORT_WRITE +; SI-CHECK-LABEL: @store_local_i16 +; SI-CHECK: DS_WRITE_B16 +define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) { + store i16 %in, i16 addrspace(3)* %out + ret void +} + +; EG-CHECK-LABEL: @store_local_v2i16 +; EG-CHECK: LDS_WRITE +; CM-CHECK-LABEL: @store_local_v2i16 +; CM-CHECK: LDS_WRITE +; SI-CHECK-LABEL: @store_local_v2i16 +; SI-CHECK: DS_WRITE_B16 +; SI-CHECK: DS_WRITE_B16 +define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) { +entry: + store <2 x i16> %in, <2 x i16> addrspace(3)* %out + ret void +} + +; EG-CHECK-LABEL: @store_local_v4i8 +; EG-CHECK: LDS_WRITE +; CM-CHECK-LABEL: @store_local_v4i8 +; CM-CHECK: LDS_WRITE +; SI-CHECK-LABEL: @store_local_v4i8 +; SI-CHECK: DS_WRITE_B8 +; SI-CHECK: DS_WRITE_B8 +; SI-CHECK: DS_WRITE_B8 +; SI-CHECK: DS_WRITE_B8 +define void @store_local_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> %in) { +entry: + store <4 x i8> %in, <4 x i8> addrspace(3)* %out + ret void +} + +; EG-CHECK-LABEL: @store_local_v2i32 +; EG-CHECK: LDS_WRITE +; EG-CHECK: LDS_WRITE +; CM-CHECK-LABEL: @store_local_v2i32 +; CM-CHECK: LDS_WRITE +; CM-CHECK: LDS_WRITE +; SI-CHECK-LABEL: @store_local_v2i32 +; SI-CHECK: DS_WRITE_B32 +; SI-CHECK: DS_WRITE_B32 +define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) { +entry: + store <2 x i32> %in, <2 x i32> addrspace(3)* %out + ret void +} + +; EG-CHECK-LABEL: @store_local_v4i32 +; EG-CHECK: LDS_WRITE +; EG-CHECK: LDS_WRITE +; EG-CHECK: LDS_WRITE +; EG-CHECK: LDS_WRITE +; CM-CHECK-LABEL: @store_local_v4i32 +; CM-CHECK: LDS_WRITE +; CM-CHECK: LDS_WRITE +; CM-CHECK: LDS_WRITE +; CM-CHECK: LDS_WRITE +; SI-CHECK-LABEL: @store_local_v4i32 +; SI-CHECK: DS_WRITE_B32 +; SI-CHECK: DS_WRITE_B32 +; SI-CHECK: DS_WRITE_B32 +; SI-CHECK: DS_WRITE_B32 +define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) { +entry: + store <4 x i32> %in, <4 x i32> addrspace(3)* %out + ret void +} + +; The stores in this function are combined by the optimizer to create a +; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer +; should not try to split the 64-bit store back into 2 32-bit stores. +; +; Evergreen / Northern Islands don't support 64-bit stores yet, so there should +; be two 32-bit stores. + +; EG-CHECK-LABEL: @vecload2 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW +; CM-CHECK-LABEL: @vecload2 +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD +; SI-CHECK-LABEL: @vecload2 +; SI-CHECK: BUFFER_STORE_DWORDX2 +define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { +entry: + %0 = load i32 addrspace(2)* %mem, align 4 + %arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1 + %1 = load i32 addrspace(2)* %arrayidx1.i, align 4 + store i32 %0, i32 addrspace(1)* %out, align 4 + %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1 + store i32 %1, i32 addrspace(1)* %arrayidx1, align 4 + ret void +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/R600/store.r600.ll b/test/CodeGen/R600/store.r600.ll index 5ffb7f1809f8..00589a0c6c86 100644 --- a/test/CodeGen/R600/store.r600.ll +++ b/test/CodeGen/R600/store.r600.ll @@ -4,7 +4,7 @@ ; v4i32 store ; EG-CHECK: @store_v4i32 -; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %1 = load <4 x i32> addrspace(1) * %in @@ -14,7 +14,7 @@ define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* % ; v4f32 store ; EG-CHECK: @store_v4f32 -; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 define void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %1 = load <4 x float> addrspace(1) * %in store <4 x float> %1, <4 x float> addrspace(1)* %out diff --git a/test/CodeGen/R600/structurize.ll b/test/CodeGen/R600/structurize.ll new file mode 100644 index 000000000000..c2acd938ad05 --- /dev/null +++ b/test/CodeGen/R600/structurize.ll @@ -0,0 +1,83 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood -mattr=disable-irstructurizer | FileCheck %s +; Test case for a crash in the AMDILCFGStructurizer from a CFG like this: +; +; entry +; / \ +; diamond_head branch_from +; / \ | +; diamond_false diamond_true +; \ / +; done +; +; When the diamond_true branch had more than 100 instructions. +; +; + +; CHECK-LABEL: @branch_into_diamond +; === entry block: +; CHECK: ALU_PUSH_BEFORE +; === Branch instruction (IF): +; CHECK: JUMP + ; === branch_from block + ; CHECK: ALU + ; === Duplicated diamond_true block (There can be more than one ALU clause): + ; === XXX: We should be able to optimize this so the basic block is not + ; === duplicated. See comments in + ; === AMDGPUCFGStructurizer::improveSimpleJumpintoIf() + ; CHECK: ALU +; === Branch instruction (ELSE): +; CHECK: ELSE + ; === diamond_head block: + ; CHECK: ALU_PUSH_BEFORE + ; === Branch instruction (IF): + ; CHECK: JUMP + ; === diamond_true block (There can be more than one ALU clause): + ; ALU + ; === Branch instruction (ELSE): + ; CHECK: ELSE + ; === diamond_false block plus implicit ENDIF + ; CHECK: ALU_POP_AFTER +; === Branch instruction (ENDIF): +; CHECK: POP +; === done block: +; CHECK: ALU +; CHECK: MEM_RAT_CACHELESS +; CHECK: CF_END + + +define void @branch_into_diamond(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { +entry: +%0 = icmp ne i32 %a, 0 + br i1 %0, label %diamond_head, label %branch_from + +diamond_head: + %1 = icmp ne i32 %a, 1 + br i1 %1, label %diamond_true, label %diamond_false + +branch_from: + %2 = add i32 %a, 1 + br label %diamond_true + +diamond_false: + %3 = add i32 %a, 2 + br label %done + +diamond_true: + %4 = phi i32 [%2, %branch_from], [%a, %diamond_head] + ; This block needs to be > 100 ISA instructions to hit the bug, + ; so we'll use udiv instructions. + %div0 = udiv i32 %a, %b + %div1 = udiv i32 %div0, %4 + %div2 = udiv i32 %div1, 11 + %div3 = udiv i32 %div2, %a + %div4 = udiv i32 %div3, %b + %div5 = udiv i32 %div4, %c + %div6 = udiv i32 %div5, %div0 + %div7 = udiv i32 %div6, %div1 + br label %done + +done: + %5 = phi i32 [%3, %diamond_false], [%div7, %diamond_true] + store i32 %5, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/structurize1.ll b/test/CodeGen/R600/structurize1.ll new file mode 100644 index 000000000000..8c10301a1686 --- /dev/null +++ b/test/CodeGen/R600/structurize1.ll @@ -0,0 +1,62 @@ +; RUN: llc < %s -march=r600 -mattr=disable-ifcvt -mcpu=redwood | FileCheck %s + +; This tests for abug where the AMDILCFGStructurizer was crashing on loops +; like this: +; +; for (i = 0; i < x; i++) { +; if (cond0) { +; if (cond1) { +; +; } else { +; +; } +; if (cond2) { +; +; } +; } +; } + +; CHECK-LABEL: @if_inside_loop +; CHECK: LOOP_START_DX10 +; CHECK: END_LOOP +define void @if_inside_loop(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) { +entry: + br label %for.body + +for.body: + %0 = phi i32 [0, %entry], [%inc, %for.inc] + %val = phi i32 [0, %entry], [%val.for.inc, %for.inc] + %inc = add i32 %0, 1 + %1 = icmp ult i32 10, %a + br i1 %1, label %for.inc, label %if.then + +if.then: + %2 = icmp ne i32 0, %b + br i1 %2, label %if.then.true, label %if.then.false + +if.then.true: + %3 = add i32 %a, %val + br label %if + +if.then.false: + %4 = mul i32 %a, %val + br label %if + +if: + %val.if = phi i32 [%3, %if.then.true], [%4, %if.then.false] + %5 = icmp ne i32 0, %c + br i1 %5, label %if.true, label %for.inc + +if.true: + %6 = add i32 %a, %val.if + br label %for.inc + +for.inc: + %val.for.inc = phi i32 [%val, %for.body], [%val.if, %if], [%6, %if.true] + %7 = icmp ne i32 0, %d + br i1 %7, label %for.body, label %exit + +exit: + store i32 %val.for.inc, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll index 12bfba39753e..5fdd2b820c1a 100644 --- a/test/CodeGen/R600/sub.ll +++ b/test/CodeGen/R600/sub.ll @@ -1,11 +1,36 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -;CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: @test2 +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +;SI-CHECK: @test2 +;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 + %a = load <2 x i32> addrspace(1) * %in + %b = load <2 x i32> addrspace(1) * %b_ptr + %result = sub <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +;EG-CHECK: @test4 +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK: @test4 +;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_SUB_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + +define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 %a = load <4 x i32> addrspace(1) * %in %b = load <4 x i32> addrspace(1) * %b_ptr diff --git a/test/CodeGen/R600/swizzle-export.ll b/test/CodeGen/R600/swizzle-export.ll new file mode 100644 index 000000000000..16c3f191935c --- /dev/null +++ b/test/CodeGen/R600/swizzle-export.ll @@ -0,0 +1,129 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s + +;EG-CHECK: @main +;EG-CHECK: EXPORT T{{[0-9]+}}.XYXX +;EG-CHECK: EXPORT T{{[0-9]+}}.ZXXX +;EG-CHECK: EXPORT T{{[0-9]+}}.XXWX +;EG-CHECK: EXPORT T{{[0-9]+}}.XXXW + +define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +main_body: + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = extractelement <4 x float> %reg1, i32 2 + %3 = extractelement <4 x float> %reg1, i32 3 + %4 = load <4 x float> addrspace(8)* null + %5 = extractelement <4 x float> %4, i32 1 + %6 = load <4 x float> addrspace(8)* null + %7 = extractelement <4 x float> %6, i32 2 + %8 = load <4 x float> addrspace(8)* null + %9 = extractelement <4 x float> %8, i32 0 + %10 = fmul float 0.000000e+00, %9 + %11 = load <4 x float> addrspace(8)* null + %12 = extractelement <4 x float> %11, i32 0 + %13 = fmul float %5, %12 + %14 = load <4 x float> addrspace(8)* null + %15 = extractelement <4 x float> %14, i32 0 + %16 = fmul float 0.000000e+00, %15 + %17 = load <4 x float> addrspace(8)* null + %18 = extractelement <4 x float> %17, i32 0 + %19 = fmul float 0.000000e+00, %18 + %20 = load <4 x float> addrspace(8)* null + %21 = extractelement <4 x float> %20, i32 0 + %22 = fmul float %7, %21 + %23 = load <4 x float> addrspace(8)* null + %24 = extractelement <4 x float> %23, i32 0 + %25 = fmul float 0.000000e+00, %24 + %26 = load <4 x float> addrspace(8)* null + %27 = extractelement <4 x float> %26, i32 0 + %28 = fmul float 0.000000e+00, %27 + %29 = load <4 x float> addrspace(8)* null + %30 = extractelement <4 x float> %29, i32 0 + %31 = fmul float 0.000000e+00, %30 + %32 = load <4 x float> addrspace(8)* null + %33 = extractelement <4 x float> %32, i32 0 + %34 = fmul float 0.000000e+00, %33 + %35 = load <4 x float> addrspace(8)* null + %36 = extractelement <4 x float> %35, i32 0 + %37 = fmul float 0.000000e+00, %36 + %38 = load <4 x float> addrspace(8)* null + %39 = extractelement <4 x float> %38, i32 0 + %40 = fmul float 1.000000e+00, %39 + %41 = load <4 x float> addrspace(8)* null + %42 = extractelement <4 x float> %41, i32 0 + %43 = fmul float 0.000000e+00, %42 + %44 = load <4 x float> addrspace(8)* null + %45 = extractelement <4 x float> %44, i32 0 + %46 = fmul float 0.000000e+00, %45 + %47 = load <4 x float> addrspace(8)* null + %48 = extractelement <4 x float> %47, i32 0 + %49 = fmul float 0.000000e+00, %48 + %50 = load <4 x float> addrspace(8)* null + %51 = extractelement <4 x float> %50, i32 0 + %52 = fmul float 0.000000e+00, %51 + %53 = load <4 x float> addrspace(8)* null + %54 = extractelement <4 x float> %53, i32 0 + %55 = fmul float 1.000000e+00, %54 + %56 = insertelement <4 x float> undef, float %0, i32 0 + %57 = insertelement <4 x float> %56, float %1, i32 1 + %58 = insertelement <4 x float> %57, float %2, i32 2 + %59 = insertelement <4 x float> %58, float %3, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %59, i32 60, i32 1) + %60 = insertelement <4 x float> undef, float %10, i32 0 + %61 = insertelement <4 x float> %60, float %13, i32 1 + %62 = insertelement <4 x float> %61, float %16, i32 2 + %63 = insertelement <4 x float> %62, float %19, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %63, i32 0, i32 2) + %64 = insertelement <4 x float> undef, float %22, i32 0 + %65 = insertelement <4 x float> %64, float %25, i32 1 + %66 = insertelement <4 x float> %65, float %28, i32 2 + %67 = insertelement <4 x float> %66, float %31, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %67, i32 1, i32 2) + %68 = insertelement <4 x float> undef, float %34, i32 0 + %69 = insertelement <4 x float> %68, float %37, i32 1 + %70 = insertelement <4 x float> %69, float %40, i32 2 + %71 = insertelement <4 x float> %70, float %43, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %71, i32 2, i32 2) + %72 = insertelement <4 x float> undef, float %46, i32 0 + %73 = insertelement <4 x float> %72, float %49, i32 1 + %74 = insertelement <4 x float> %73, float %52, i32 2 + %75 = insertelement <4 x float> %74, float %55, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %75, i32 3, i32 2) + ret void +} + +; EG-CHECK: @main2 +; EG-CHECK: T{{[0-9]+}}.XY__ +; EG-CHECK: T{{[0-9]+}}.YXZ0 + +define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +main_body: + %0 = extractelement <4 x float> %reg1, i32 0 + %1 = extractelement <4 x float> %reg1, i32 1 + %2 = fadd float %0, 2.5 + %3 = fmul float %1, 3.5 + %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %5 = extractelement <4 x float> %4, i32 0 + %6 = call float @llvm.cos.f32(float %5) + %7 = load <4 x float> addrspace(8)* null + %8 = extractelement <4 x float> %7, i32 0 + %9 = load <4 x float> addrspace(8)* null + %10 = extractelement <4 x float> %9, i32 1 + %11 = insertelement <4 x float> undef, float %2, i32 0 + %12 = insertelement <4 x float> %11, float %3, i32 1 + call void @llvm.R600.store.swizzle(<4 x float> %12, i32 60, i32 1) + %13 = insertelement <4 x float> undef, float %6, i32 0 + %14 = insertelement <4 x float> %13, float %8, i32 1 + %15 = insertelement <4 x float> %14, float %10, i32 2 + %16 = insertelement <4 x float> %15, float 0.000000e+00, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %16, i32 0, i32 2) + ret void +} + +; Function Attrs: nounwind readonly +declare float @llvm.cos.f32(float) #1 + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } +attributes #1 = { nounwind readonly } diff --git a/test/CodeGen/R600/tex-clause-antidep.ll b/test/CodeGen/R600/tex-clause-antidep.ll new file mode 100644 index 000000000000..cbb9c50974a4 --- /dev/null +++ b/test/CodeGen/R600/tex-clause-antidep.ll @@ -0,0 +1,25 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: TEX +;CHECK-NEXT: ALU + +define void @test(<4 x float> inreg %reg0) #0 { + %1 = extractelement <4 x float> %reg0, i32 0 + %2 = extractelement <4 x float> %reg0, i32 1 + %3 = extractelement <4 x float> %reg0, i32 2 + %4 = extractelement <4 x float> %reg0, i32 3 + %5 = insertelement <4 x float> undef, float %1, i32 0 + %6 = insertelement <4 x float> %5, float %2, i32 1 + %7 = insertelement <4 x float> %6, float %3, i32 2 + %8 = insertelement <4 x float> %7, float %4, i32 3 + %9 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %10 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %11 = fadd <4 x float> %9, %10 + call void @llvm.R600.store.swizzle(<4 x float> %11, i32 0, i32 0) + ret void +} + +declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" }
\ No newline at end of file diff --git a/test/CodeGen/R600/texture-input-merge.ll b/test/CodeGen/R600/texture-input-merge.ll new file mode 100644 index 000000000000..789538af5821 --- /dev/null +++ b/test/CodeGen/R600/texture-input-merge.ll @@ -0,0 +1,31 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK-NOT: MOV + +define void @test(<4 x float> inreg %reg0) #0 { + %1 = extractelement <4 x float> %reg0, i32 0 + %2 = extractelement <4 x float> %reg0, i32 1 + %3 = extractelement <4 x float> %reg0, i32 2 + %4 = extractelement <4 x float> %reg0, i32 3 + %5 = fmul float %1, 3.0 + %6 = fmul float %2, 3.0 + %7 = fmul float %3, 3.0 + %8 = fmul float %4, 3.0 + %9 = insertelement <4 x float> undef, float %5, i32 0 + %10 = insertelement <4 x float> %9, float %6, i32 1 + %11 = insertelement <4 x float> undef, float %7, i32 0 + %12 = insertelement <4 x float> %11, float %5, i32 1 + %13 = insertelement <4 x float> undef, float %8, i32 0 + %14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %17 = fadd <4 x float> %14, %15 + %18 = fadd <4 x float> %17, %16 + call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0) + ret void +} + +declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" }
\ No newline at end of file diff --git a/test/CodeGen/R600/trunc-vector-store-assertion-failure.ll b/test/CodeGen/R600/trunc-vector-store-assertion-failure.ll new file mode 100644 index 000000000000..ec959c21798a --- /dev/null +++ b/test/CodeGen/R600/trunc-vector-store-assertion-failure.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; This tests for a bug in the SelectionDAG where custom lowered truncated +; vector stores at the end of a basic block were not being added to the +; LegalizedNodes list, which triggered an assertion failure. + +; CHECK-LABEL: @test +; CHECK: MEM_RAT_CACHELESS STORE_RAW +define void @test(<4 x i8> addrspace(1)* %out, i32 %cond, <4 x i8> %in) { +entry: + %0 = icmp eq i32 %cond, 0 + br i1 %0, label %if, label %done + +if: + store <4 x i8> %in, <4 x i8> addrspace(1)* %out + br label %done + +done: + ret void +} diff --git a/test/CodeGen/R600/trunc.ll b/test/CodeGen/R600/trunc.ll new file mode 100644 index 000000000000..0bd320ad9ceb --- /dev/null +++ b/test/CodeGen/R600/trunc.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s + +define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) { +; SI-LABEL: @trunc_i64_to_i32_store +; SI: S_LOAD_DWORD s0, s[0:1], 11 +; SI: V_MOV_B32_e32 v0, s0 +; SI: BUFFER_STORE_DWORD v0 + +; EG-LABEL: @trunc_i64_to_i32_store +; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 +; EG: LSHR +; EG-NEXT: 2( + + %result = trunc i64 %in to i32 store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: @trunc_shl_i64: +; SI: S_LOAD_DWORDX2 +; SI: S_LOAD_DWORDX2 [[SREG:s\[[0-9]+:[0-9]+\]]] +; SI: S_LSHL_B64 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, [[SREG]], 2 +; SI: MOV_B32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]] +; SI: BUFFER_STORE_DWORD v[[LO_VREG]], +define void @trunc_shl_i64(i32 addrspace(1)* %out, i64 %a) { + %b = shl i64 %a, 2 + %result = trunc i64 %b to i32 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/R600/udiv.ll b/test/CodeGen/R600/udiv.ll index b81e3667ce89..53713217a1c0 100644 --- a/test/CodeGen/R600/udiv.ll +++ b/test/CodeGen/R600/udiv.ll @@ -1,11 +1,43 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s + +;EG-CHECK-LABEL: @test +;EG-CHECK-NOT: SETGE_INT +;EG-CHECK: CF_END + +define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1 + %a = load i32 addrspace(1) * %in + %b = load i32 addrspace(1) * %b_ptr + %result = udiv i32 %a, %b + store i32 %result, i32 addrspace(1)* %out + ret void +} ;The code generated by udiv is long and complex and may frequently change. ;The goal of this test is to make sure the ISel doesn't fail when it gets ;a v4i32 udiv -;CHECK: CF_END -define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +;EG-CHECK-LABEL: @test2 +;EG-CHECK: CF_END +;SI-CHECK-LABEL: @test2 +;SI-CHECK: S_ENDPGM + +define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 + %a = load <2 x i32> addrspace(1) * %in + %b = load <2 x i32> addrspace(1) * %b_ptr + %result = udiv <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +;EG-CHECK-LABEL: @test4 +;EG-CHECK: CF_END +;SI-CHECK-LABEL: @test4 +;SI-CHECK: S_ENDPGM + +define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 %a = load <4 x i32> addrspace(1) * %in %b = load <4 x i32> addrspace(1) * %b_ptr diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll index 9054fc4c2cc8..a5ac3555afde 100644 --- a/test/CodeGen/R600/uint_to_fp.ll +++ b/test/CodeGen/R600/uint_to_fp.ll @@ -1,14 +1,46 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; CHECK: @uint_to_fp_v4i32 -; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK-LABEL: @uint_to_fp_v2i32 +; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W +; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X +; SI-CHECK-LABEL: @uint_to_fp_v2i32 +; SI-CHECK: V_CVT_F32_U32_e32 +; SI-CHECK: V_CVT_F32_U32_e32 +define void @uint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) { + %result = uitofp <2 x i32> %in to <2 x float> + store <2 x float> %result, <2 x float> addrspace(1)* %out + ret void +} +; R600-CHECK-LABEL: @uint_to_fp_v4i32 +; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; SI-CHECK-LABEL: @uint_to_fp_v4i32 +; SI-CHECK: V_CVT_F32_U32_e32 +; SI-CHECK: V_CVT_F32_U32_e32 +; SI-CHECK: V_CVT_F32_U32_e32 +; SI-CHECK: V_CVT_F32_U32_e32 define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %value = load <4 x i32> addrspace(1) * %in %result = uitofp <4 x i32> %value to <4 x float> store <4 x float> %result, <4 x float> addrspace(1)* %out ret void } + +; R600-CHECK-LABEL: @uint_to_fp_i64_f32 +; R600-CHECK: UINT_TO_FLT +; R600-CHECK: UINT_TO_FLT +; R600-CHECK: MULADD_IEEE +; SI-CHECK-LABEL: @uint_to_fp_i64_f32 +; SI-CHECK: V_CVT_F32_U32_e32 +; SI-CHECK: V_CVT_F32_U32_e32 +; SI-CHECK: V_MAD_F32 +define void @uint_to_fp_i64_f32(float addrspace(1)* %out, i64 %in) { +entry: + %0 = uitofp i64 %in to float + store float %0, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/unaligned-load-store.ll b/test/CodeGen/R600/unaligned-load-store.ll new file mode 100644 index 000000000000..2824ff8a88c5 --- /dev/null +++ b/test/CodeGen/R600/unaligned-load-store.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s + +; SI-LABEL: @unaligned_load_store_i32: +; DS_READ_U32 {{v[0-9]+}}, 0, [[REG]] +define void @unaligned_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind { + %v = load i32 addrspace(3)* %p, align 1 + store i32 %v, i32 addrspace(3)* %r, align 1 + ret void +} + +; SI-LABEL: @unaligned_load_store_v4i32: +; DS_READ_U32 {{v[0-9]+}}, 0, [[REG]] +define void @unaligned_load_store_v4i32(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind { + %v = load <4 x i32> addrspace(3)* %p, align 1 + store <4 x i32> %v, <4 x i32> addrspace(3)* %r, align 1 + ret void +} diff --git a/test/CodeGen/R600/unsupported-cc.ll b/test/CodeGen/R600/unsupported-cc.ll index b311f4cfa7f9..f986a0251dce 100644 --- a/test/CodeGen/R600/unsupported-cc.ll +++ b/test/CodeGen/R600/unsupported-cc.ll @@ -2,8 +2,9 @@ ; These tests are for condition codes that are not supported by the hardware -; CHECK: @slt -; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-LABEL: @slt +; CHECK: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z +; CHECK-NEXT: LSHR ; CHECK-NEXT: 5(7.006492e-45) define void @slt(i32 addrspace(1)* %out, i32 %in) { entry: @@ -13,8 +14,9 @@ entry: ret void } -; CHECK: @ult_i32 -; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-LABEL: @ult_i32 +; CHECK: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z +; CHECK-NEXT: LSHR ; CHECK-NEXT: 5(7.006492e-45) define void @ult_i32(i32 addrspace(1)* %out, i32 %in) { entry: @@ -24,9 +26,11 @@ entry: ret void } -; CHECK: @ult_float -; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-LABEL: @ult_float +; CHECK: SETGE * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x ; CHECK-NEXT: 1084227584(5.000000e+00) +; CHECK-NEXT: SETE T{{[0-9]\.[XYZW]}}, PV.[[CHAN]], 0.0 +; CHECK-NEXT: LSHR * define void @ult_float(float addrspace(1)* %out, float %in) { entry: %0 = fcmp ult float %in, 5.0 @@ -35,9 +39,22 @@ entry: ret void } -; CHECK: @olt -; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, -;CHECK-NEXT: 1084227584(5.000000e+00) +; CHECK-LABEL: @ult_float_native +; CHECK: SETGE T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x +; CHECK-NEXT: LSHR * +; CHECK-NEXT: 1084227584(5.000000e+00) +define void @ult_float_native(float addrspace(1)* %out, float %in) { +entry: + %0 = fcmp ult float %in, 5.0 + %1 = select i1 %0, float 0.0, float 1.0 + store float %1, float addrspace(1)* %out + ret void +} + +; CHECK-LABEL: @olt +; CHECK: SETGT T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z +; CHECK-NEXT: LSHR * +; CHECK-NEXT: 1084227584(5.000000e+00) define void @olt(float addrspace(1)* %out, float %in) { entry: %0 = fcmp olt float %in, 5.0 @@ -46,8 +63,9 @@ entry: ret void } -; CHECK: @sle -; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-LABEL: @sle +; CHECK: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z +; CHECK-NEXT: LSHR ; CHECK-NEXT: 6(8.407791e-45) define void @sle(i32 addrspace(1)* %out, i32 %in) { entry: @@ -57,8 +75,9 @@ entry: ret void } -; CHECK: @ule_i32 -; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-LABEL: @ule_i32 +; CHECK: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z +; CHECK-NEXT: LSHR ; CHECK-NEXT: 6(8.407791e-45) define void @ule_i32(i32 addrspace(1)* %out, i32 %in) { entry: @@ -68,9 +87,11 @@ entry: ret void } -; CHECK: @ule_float -; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-LABEL: @ule_float +; CHECK: SETGT * T{{[0-9]}}.[[CHAN:[XYZW]]], KC0[2].Z, literal.x ; CHECK-NEXT: 1084227584(5.000000e+00) +; CHECK-NEXT: SETE T{{[0-9]\.[XYZW]}}, PV.[[CHAN]], 0.0 +; CHECK-NEXT: LSHR * define void @ule_float(float addrspace(1)* %out, float %in) { entry: %0 = fcmp ule float %in, 5.0 @@ -79,8 +100,21 @@ entry: ret void } -; CHECK: @ole -; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-LABEL: @ule_float_native +; CHECK: SETGT T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x +; CHECK-NEXT: LSHR * +; CHECK-NEXT: 1084227584(5.000000e+00) +define void @ule_float_native(float addrspace(1)* %out, float %in) { +entry: + %0 = fcmp ule float %in, 5.0 + %1 = select i1 %0, float 0.0, float 1.0 + store float %1, float addrspace(1)* %out + ret void +} + +; CHECK-LABEL: @ole +; CHECK: SETGE T{{[0-9]\.[XYZW]}}, literal.x, KC0[2].Z +; CHECK-NEXT: LSHR * ; CHECK-NEXT:1084227584(5.000000e+00) define void @ole(float addrspace(1)* %out, float %in) { entry: diff --git a/test/CodeGen/R600/urecip.ll b/test/CodeGen/R600/urecip.ll index dad02dd76f0a..e808e3d2cf19 100644 --- a/test/CodeGen/R600/urecip.ll +++ b/test/CodeGen/R600/urecip.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s ;CHECK: V_RCP_IFLAG_F32_e32 diff --git a/test/CodeGen/R600/urem.ll b/test/CodeGen/R600/urem.ll index a2cc0bd2e84e..8045145bd10d 100644 --- a/test/CodeGen/R600/urem.ll +++ b/test/CodeGen/R600/urem.ll @@ -1,11 +1,30 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s ;The code generated by urem is long and complex and may frequently change. ;The goal of this test is to make sure the ISel doesn't fail when it gets -;a v4i32 urem -;CHECK: CF_END +;a v2i32/v4i32 urem -define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +;EG-CHECK: @test2 +;EG-CHECK: CF_END +;SI-CHECK: @test2 +;SI-CHECK: S_ENDPGM + +define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 + %a = load <2 x i32> addrspace(1) * %in + %b = load <2 x i32> addrspace(1) * %b_ptr + %result = urem <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +;EG-CHECK: @test4 +;EG-CHECK: CF_END +;SI-CHECK: @test4 +;SI-CHECK: S_ENDPGM + +define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 %a = load <4 x i32> addrspace(1) * %in %b = load <4 x i32> addrspace(1) * %b_ptr diff --git a/test/CodeGen/R600/vertex-fetch-encoding.ll b/test/CodeGen/R600/vertex-fetch-encoding.ll new file mode 100644 index 000000000000..7ea7a5c079cf --- /dev/null +++ b/test/CodeGen/R600/vertex-fetch-encoding.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=barts | FileCheck --check-prefix=NI-CHECK %s +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s + +; NI-CHECK: @vtx_fetch32 +; NI-CHECK: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00 +; CM-CHECK: @vtx_fetch32 +; CM-CHECK: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00 + +define void @vtx_fetch32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +entry: + %0 = load i32 addrspace(1)* %in + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; NI-CHECK: @vtx_fetch128 +; NI-CHECK: VTX_READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0 ; encoding: [0x40,0x01,0x0[[SRC]],0x40,0x0[[DST]],0x10,0x8d,0x18,0x00,0x00,0x08,0x00 +; XXX: Add a case for Cayman when v4i32 stores are supported. + +define void @vtx_fetch128(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +entry: + %0 = load <4 x i32> addrspace(1)* %in + store <4 x i32> %0, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll index 6e459df847e7..dca7b067b26e 100644 --- a/test/CodeGen/R600/vselect.ll +++ b/test/CodeGen/R600/vselect.ll @@ -1,10 +1,53 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; CHECK: @test_select_v4i32 -; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: @test_select_v2i32 +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK: @test_select_v2i32 +;SI-CHECK: V_CNDMASK_B32_e64 +;SI-CHECK: V_CNDMASK_B32_e64 + +define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) { +entry: + %0 = load <2 x i32> addrspace(1)* %in0 + %1 = load <2 x i32> addrspace(1)* %in1 + %cmp = icmp ne <2 x i32> %0, %1 + %result = select <2 x i1> %cmp, <2 x i32> %0, <2 x i32> %1 + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +;EG-CHECK: @test_select_v2f32 +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK: @test_select_v2f32 +;SI-CHECK: V_CNDMASK_B32_e64 +;SI-CHECK: V_CNDMASK_B32_e64 + +define void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) { +entry: + %0 = load <2 x float> addrspace(1)* %in0 + %1 = load <2 x float> addrspace(1)* %in1 + %cmp = fcmp une <2 x float> %0, %1 + %result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1 + store <2 x float> %result, <2 x float> addrspace(1)* %out + ret void +} + +;EG-CHECK: @test_select_v4i32 +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK: @test_select_v4i32 +;SI-CHECK: V_CNDMASK_B32_e64 +;SI-CHECK: V_CNDMASK_B32_e64 +;SI-CHECK: V_CNDMASK_B32_e64 +;SI-CHECK: V_CNDMASK_B32_e64 define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) { entry: @@ -15,3 +58,19 @@ entry: store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } + +;EG-CHECK: @test_select_v4f32 +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) { +entry: + %0 = load <4 x float> addrspace(1)* %in0 + %1 = load <4 x float> addrspace(1)* %in1 + %cmp = fcmp une <4 x float> %0, %1 + %result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1 + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/vselect64.ll b/test/CodeGen/R600/vselect64.ll new file mode 100644 index 000000000000..604695b4fa6b --- /dev/null +++ b/test/CodeGen/R600/vselect64.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; XXX: Merge this test into vselect.ll once SI supports 64-bit select. + +; CHECK-LABEL: @test_select_v4i64 +; Make sure the vectors aren't being stored on the stack. We know they are +; being stored on the stack if the shaders uses at leat 10 registers. +; CHECK-NOT: {{\**}} MOV T{{[0-9][0-9]}}.X +define void @test_select_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> %c) { +entry: + %cmp = icmp ne <4 x i32> %c, <i32 0, i32 0, i32 0, i32 0> + %result = select <4 x i1> %cmp, <4 x i64> <i64 0, i64 1, i64 2, i64 3>, <4 x i64> <i64 4, i64 5, i64 6, i64 7> + store <4 x i64> %result, <4 x i64> addrspace(1)* %out + ret void +} + diff --git a/test/CodeGen/R600/vtx-schedule.ll b/test/CodeGen/R600/vtx-schedule.ll new file mode 100644 index 000000000000..97d37ed84ce2 --- /dev/null +++ b/test/CodeGen/R600/vtx-schedule.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; This test is for a scheduler bug where VTX_READ instructions that used +; the result of another VTX_READ instruction were being grouped in the +; same fetch clasue. + +; CHECK: @test +; CHECK: Fetch clause +; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0 +; CHECK: Fetch clause +; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0 +define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* addrspace(1)* nocapture %in0) { +entry: + %0 = load i32 addrspace(1)* addrspace(1)* %in0 + %1 = load i32 addrspace(1)* %0 + store i32 %1, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/wait.ll b/test/CodeGen/R600/wait.ll new file mode 100644 index 000000000000..2cf88fe9f735 --- /dev/null +++ b/test/CodeGen/R600/wait.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=r600 -mcpu=SI --verify-machineinstrs | FileCheck %s + +;CHECK-LABEL: @main +;CHECK: S_WAITCNT lgkmcnt(0) +;CHECK: S_WAITCNT vmcnt(0) +;CHECK: S_WAITCNT expcnt(0) lgkmcnt(0) + +define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { +main_body: + %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0 + %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 + %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) + %13 = extractelement <4 x float> %12, i32 0 + %14 = extractelement <4 x float> %12, i32 1 + %15 = extractelement <4 x float> %12, i32 2 + %16 = extractelement <4 x float> %12, i32 3 + %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1 + %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 + %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) + %20 = extractelement <4 x float> %19, i32 0 + %21 = extractelement <4 x float> %19, i32 1 + %22 = extractelement <4 x float> %19, i32 2 + %23 = extractelement <4 x float> %19, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) + ret void +} + +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="1" } +attributes #1 = { nounwind readnone } + +!0 = metadata !{metadata !"const", null, i32 1} diff --git a/test/CodeGen/R600/work-item-intrinsics.ll b/test/CodeGen/R600/work-item-intrinsics.ll new file mode 100644 index 000000000000..9618d7fb1970 --- /dev/null +++ b/test/CodeGen/R600/work-item-intrinsics.ll @@ -0,0 +1,211 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s + +; R600-CHECK: @ngroups_x +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; R600-CHECK: MOV [[VAL]], KC0[0].X +; SI-CHECK: @ngroups_x +; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0 +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @ngroups_x (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.ngroups.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK: @ngroups_y +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; R600-CHECK: MOV [[VAL]], KC0[0].Y +; SI-CHECK: @ngroups_y +; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 1 +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @ngroups_y (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.ngroups.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK: @ngroups_z +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; R600-CHECK: MOV [[VAL]], KC0[0].Z +; SI-CHECK: @ngroups_z +; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 2 +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @ngroups_z (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.ngroups.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK: @global_size_x +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; R600-CHECK: MOV [[VAL]], KC0[0].W +; SI-CHECK: @global_size_x +; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 3 +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @global_size_x (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.global.size.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK: @global_size_y +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; R600-CHECK: MOV [[VAL]], KC0[1].X +; SI-CHECK: @global_size_y +; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 4 +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @global_size_y (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.global.size.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK: @global_size_z +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; R600-CHECK: MOV [[VAL]], KC0[1].Y +; SI-CHECK: @global_size_z +; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 5 +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @global_size_z (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.global.size.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK: @local_size_x +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; R600-CHECK: MOV [[VAL]], KC0[1].Z +; SI-CHECK: @local_size_x +; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 6 +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @local_size_x (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.local.size.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK: @local_size_y +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; R600-CHECK: MOV [[VAL]], KC0[1].W +; SI-CHECK: @local_size_y +; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 7 +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @local_size_y (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.local.size.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; R600-CHECK: @local_size_z +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; R600-CHECK: MOV [[VAL]], KC0[2].X +; SI-CHECK: @local_size_z +; SI-CHECK: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 8 +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @local_size_z (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.local.size.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; The tgid values are stored in ss offset by the number of user ss. +; Currently we always use exactly 2 user ss for the pointer to the +; kernel arguments, but this may change in the future. + +; SI-CHECK: @tgid_x +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s2 +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @tgid_x (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tgid.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; SI-CHECK: @tgid_y +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s3 +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @tgid_y (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tgid.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; SI-CHECK: @tgid_z +; SI-CHECK: V_MOV_B32_e32 [[VVAL:v[0-9]+]], s4 +; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]] +define void @tgid_z (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tgid.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; SI-CHECK: @tidig_x +; SI-CHECK: BUFFER_STORE_DWORD v0 +define void @tidig_x (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tidig.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; SI-CHECK: @tidig_y +; SI-CHECK: BUFFER_STORE_DWORD v1 +define void @tidig_y (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tidig.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; SI-CHECK: @tidig_z +; SI-CHECK: BUFFER_STORE_DWORD v2 +define void @tidig_z (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tidig.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +declare i32 @llvm.r600.read.ngroups.x() #0 +declare i32 @llvm.r600.read.ngroups.y() #0 +declare i32 @llvm.r600.read.ngroups.z() #0 + +declare i32 @llvm.r600.read.global.size.x() #0 +declare i32 @llvm.r600.read.global.size.y() #0 +declare i32 @llvm.r600.read.global.size.z() #0 + +declare i32 @llvm.r600.read.local.size.x() #0 +declare i32 @llvm.r600.read.local.size.y() #0 +declare i32 @llvm.r600.read.local.size.z() #0 + +declare i32 @llvm.r600.read.tgid.x() #0 +declare i32 @llvm.r600.read.tgid.y() #0 +declare i32 @llvm.r600.read.tgid.z() #0 + +declare i32 @llvm.r600.read.tidig.x() #0 +declare i32 @llvm.r600.read.tidig.y() #0 +declare i32 @llvm.r600.read.tidig.z() #0 + +attributes #0 = { readnone } diff --git a/test/CodeGen/R600/wrong-transalu-pos-fix.ll b/test/CodeGen/R600/wrong-transalu-pos-fix.ll new file mode 100644 index 000000000000..b1cbe3ffbc41 --- /dev/null +++ b/test/CodeGen/R600/wrong-transalu-pos-fix.ll @@ -0,0 +1,86 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; We want all MULLO_INT inst to be last in their instruction group +;CHECK: @fill3d +;CHECK-NOT: MULLO_INT T[0-9]+ + +; ModuleID = 'radeon' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64" +target triple = "r600--" + +; Function Attrs: nounwind +define void @fill3d(i32 addrspace(1)* nocapture %out) #0 { +entry: + %x.i = tail call i32 @llvm.r600.read.global.size.x() #1 + %y.i18 = tail call i32 @llvm.r600.read.global.size.y() #1 + %mul = mul i32 %y.i18, %x.i + %z.i17 = tail call i32 @llvm.r600.read.global.size.z() #1 + %mul3 = mul i32 %mul, %z.i17 + %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1 + %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1 + %mul26.i = mul i32 %x.i12.i, %x.i.i + %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %add.i16 = add i32 %x.i4.i, %mul26.i + %mul7 = mul i32 %add.i16, %y.i18 + %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1 + %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1 + %mul30.i = mul i32 %y.i14.i, %y.i.i + %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1 + %add.i14 = add i32 %mul30.i, %mul7 + %mul819 = add i32 %add.i14, %y.i6.i + %add = mul i32 %mul819, %z.i17 + %z.i.i = tail call i32 @llvm.r600.read.tgid.z() #1 + %z.i16.i = tail call i32 @llvm.r600.read.local.size.z() #1 + %mul33.i = mul i32 %z.i16.i, %z.i.i + %z.i8.i = tail call i32 @llvm.r600.read.tidig.z() #1 + %add.i = add i32 %z.i8.i, %mul33.i + %add13 = add i32 %add.i, %add + %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %add13 + store i32 %mul3, i32 addrspace(1)* %arrayidx, align 4 + ret void +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.tgid.x() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.tgid.y() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.tgid.z() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.local.size.x() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.local.size.y() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.local.size.z() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.tidig.x() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.tidig.y() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.tidig.z() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.global.size.x() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.global.size.y() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.global.size.z() #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!opencl.kernels = !{!0, !1, !2} + +!0 = metadata !{null} +!1 = metadata !{null} +!2 = metadata !{void (i32 addrspace(1)*)* @fill3d} diff --git a/test/CodeGen/R600/xor.ll b/test/CodeGen/R600/xor.ll index cf612e0a1fbe..c12b0c1ce2c9 100644 --- a/test/CodeGen/R600/xor.ll +++ b/test/CodeGen/R600/xor.ll @@ -1,13 +1,56 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -; CHECK: @xor_v4i32 -; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: @xor_v2i32 +;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { +;SI-CHECK: @xor_v2i32 +;SI-CHECK: V_XOR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_XOR_B32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} + + +define void @xor_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) { + %a = load <2 x i32> addrspace(1) * %in0 + %b = load <2 x i32> addrspace(1) * %in1 + %result = xor <2 x i32> %a, %b + store <2 x i32> %result, <2 x i32> addrspace(1)* %out + ret void +} + +;EG-CHECK: @xor_v4i32 +;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +;SI-CHECK: @xor_v4i32 +;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: V_XOR_B32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}} + +define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) { + %a = load <4 x i32> addrspace(1) * %in0 + %b = load <4 x i32> addrspace(1) * %in1 %result = xor <4 x i32> %a, %b store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } + +;EG-CHECK: @xor_i1 +;EG-CHECK: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}} + +;SI-CHECK: @xor_i1 +;SI-CHECK: S_XOR_B64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] + +define void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) { + %a = load float addrspace(1) * %in0 + %b = load float addrspace(1) * %in1 + %acmp = fcmp oge float %a, 0.000000e+00 + %bcmp = fcmp oge float %b, 0.000000e+00 + %xor = xor i1 %acmp, %bcmp + %result = select i1 %xor, float %a, float %b + store float %result, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/zero_extend.ll b/test/CodeGen/R600/zero_extend.ll new file mode 100644 index 000000000000..481b3b328259 --- /dev/null +++ b/test/CodeGen/R600/zero_extend.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK + +; R600-CHECK: @test +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW +; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW + +; SI-CHECK: @test +; SI-CHECK: V_MOV_B32_e32 v[[ZERO:[0-9]]], 0 +; SI-CHECK: BUFFER_STORE_DWORDX2 v[0:[[ZERO]]{{\]}} +define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { +entry: + %0 = mul i32 %a, %b + %1 = add i32 %0, %c + %2 = zext i32 %1 to i64 + store i64 %2, i64 addrspace(1)* %out + ret void +} |