vendor/llvm/llvm-release_361-r237755vendor/llvm/llvm-3.6.x

14 files changed, 556 insertions, 48 deletions

diff --git a/test/CodeGen/X86/and-load-fold.ll b/test/CodeGen/X86/and-load-fold.ll
new file mode 100644
index 000000000000..d6f68b3bc433
--- /dev/null
+++ b/test/CodeGen/X86/and-load-fold.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic < %s | FileCheck %s
+
+; Verify that the DAGCombiner doesn't wrongly remove the 'and' from the dag.
+
+define i8 @foo(<4 x i8>* %V) {
+; CHECK-LABEL: foo:
+; CHECK: pand
+; CHECK: ret
+entry:
+  %Vp = bitcast <4 x i8>* %V to <3 x i8>*
+  %V3i8 = load <3 x i8>* %Vp, align 4
+  %0 = and <3 x i8> %V3i8, <i8 undef, i8 undef, i8 95>
+  %1 = extractelement <3 x i8> %0, i64 2
+  ret i8 %1
+}
diff --git a/test/CodeGen/X86/avx-vperm2x128.ll b/test/CodeGen/X86/avx-vperm2x128.ll
index 43303ca57c4f..7ca5939fa74a 100644
--- a/test/CodeGen/X86/avx-vperm2x128.ll
+++ b/test/CodeGen/X86/avx-vperm2x128.ll
@@ -172,13 +172,83 @@ entry:
 define <8 x float> @F(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
 ; ALL-LABEL: F:
 ; ALL:       ## BB#0: ## %entry
-; ALL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm1[0,1,0,1]
+; ALL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[0,1]
 ; ALL-NEXT:    retq
 entry:
   %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 9, i32 undef, i32 11>
   ret <8 x float> %shuffle
 }
 
+define <8 x float> @F2(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
+; ALL-LABEL: F2:
+; ALL:       ## BB#0: ## %entry
+; ALL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,2,3]
+; ALL-NEXT:    retq
+entry:
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 6, i32 7>
+  ret <8 x float> %shuffle
+}
+
+define <8 x float> @F3(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
+; ALL-LABEL: F3:
+; ALL:       ## BB#0: ## %entry
+; ALL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[0,1]
+; ALL-NEXT:    retq
+entry:
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 10, i32 11>
+  ret <8 x float> %shuffle
+}
+
+define <8 x float> @F4(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
+; ALL-LABEL: F4:
+; ALL:       ## BB#0: ## %entry
+; ALL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
+; ALL-NEXT:    retq
+entry:
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 undef, i32 14, i32 15>
+  ret <8 x float> %shuffle
+}
+
+define <8 x float> @F5(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
+; ALL-LABEL: F5:
+; ALL:       ## BB#0: ## %entry
+; ALL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,2,3]
+; ALL-NEXT:    retq
+entry:
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 undef, i32 undef, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x float> %shuffle
+}
+
+define <8 x float> @F6(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
+; ALL-LABEL: F6:
+; ALL:       ## BB#0: ## %entry
+; ALL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[0,1]
+; ALL-NEXT:    retq
+entry:
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
+  ret <8 x float> %shuffle
+}
+
+define <8 x float> @F7(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
+; ALL-LABEL: F7:
+; ALL:       ## BB#0: ## %entry
+; ALL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3,2,3]
+; ALL-NEXT:    retq
+entry:
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 6, i32 7>
+  ret <8 x float> %shuffle
+}
+
+define <8 x float> @F8(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
+; ALL-LABEL: F8:
+; ALL:       ## BB#0: ## %entry
+; ALL-NEXT:    vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm1[2,3]
+; ALL-NEXT:    retq
+entry:
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 14, i32 15>
+  ret <8 x float> %shuffle
+}
+
 ;;;; Cases we must not select vperm2f128
 
 define <8 x float> @G(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
diff --git a/test/CodeGen/X86/avx2-intrinsics-x86.ll b/test/CodeGen/X86/avx2-intrinsics-x86.ll
index 79a3361bfe86..ca5ab3723c11 100644
--- a/test/CodeGen/X86/avx2-intrinsics-x86.ll
+++ b/test/CodeGen/X86/avx2-intrinsics-x86.ll
@@ -785,7 +785,10 @@ declare <4 x i64> @llvm.x86.avx2.pbroadcastq.256(<2 x i64>) nounwind readonly
 
 
 define <8 x i32> @test_x86_avx2_permd(<8 x i32> %a0, <8 x i32> %a1) {
-  ; CHECK: vpermd
+  ; Check that the arguments are swapped between the intrinsic definition
+  ; and its lowering. Indeed, the offsets are the first source in
+  ; the instruction.
+  ; CHECK: vpermd %ymm0, %ymm1, %ymm0
   %res = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1]
   ret <8 x i32> %res
 }
@@ -793,7 +796,10 @@ declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>) nounwind readonly
 
 
 define <8 x float> @test_x86_avx2_permps(<8 x float> %a0, <8 x float> %a1) {
-  ; CHECK: vpermps
+  ; Check that the arguments are swapped between the intrinsic definition
+  ; and its lowering. Indeed, the offsets are the first source in
+  ; the instruction.
+  ; CHECK: vpermps %ymm0, %ymm1, %ymm0
   %res = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
   ret <8 x float> %res
 }
diff --git a/test/CodeGen/X86/dag-optnone.ll b/test/CodeGen/X86/dag-optnone.ll
new file mode 100644
index 000000000000..897de31a6fd3
--- /dev/null
+++ b/test/CodeGen/X86/dag-optnone.ll
@@ -0,0 +1,73 @@
+; RUN: llc < %s -mtriple=x86_64-pc-win32 -O0 -mattr=+avx | FileCheck %s
+
+; Background:
+; If fast-isel bails out to normal selection, then the DAG combiner will run,
+; even at -O0. In principle this should not happen (those are optimizations,
+; and we said -O0) but as a practical matter there are some instruction
+; selection patterns that depend on the legalizations and transforms that the
+; DAG combiner does.
+;
+; The 'optnone' attribute implicitly sets -O0 and fast-isel for the function.
+; The DAG combiner was disabled for 'optnone' (but not -O0) by r221168, then
+; re-enabled in r233153 because of problems with instruction selection patterns
+; mentioned above. (Note: because 'optnone' is supposed to match -O0, r221168
+; really should have disabled the combiner for both.)
+;
+; If instruction selection eventually becomes smart enough to run without DAG
+; combiner, then the combiner can be turned off for -O0 (not just 'optnone')
+; and this test can go away. (To be replaced by a different test that verifies
+; the DAG combiner does *not* run at -O0 or for 'optnone' functions.)
+;
+; In the meantime, this test wants to make sure the combiner stays enabled for
+; 'optnone' functions, just as it is for -O0.
+
+
+; The test cases @foo[WithOptnone] prove that the same DAG combine happens
+; with -O0 and with 'optnone' set.  To prove this, we use a Windows triple to
+; cause fast-isel to bail out (because something about the calling convention
+; is not handled in fast-isel).  Then we have a repeated fadd that can be
+; combined into an fmul.  We show that this happens in both the non-optnone
+; function and the optnone function.
+
+define float @foo(float %x) #0 {
+entry:
+  %add = fadd fast float %x, %x
+  %add1 = fadd fast float %add, %x
+  ret float %add1
+}
+
+; CHECK-LABEL: @foo
+; CHECK-NOT:   add
+; CHECK:       mul
+; CHECK-NEXT:  ret
+
+define float @fooWithOptnone(float %x) #1 {
+entry:
+  %add = fadd fast float %x, %x
+  %add1 = fadd fast float %add, %x
+  ret float %add1
+}
+
+; CHECK-LABEL: @fooWithOptnone
+; CHECK-NOT:   add
+; CHECK:       mul
+; CHECK-NEXT:  ret
+
+
+; The test case @bar is derived from an instruction selection failure case
+; that was solved by r233153. It depends on -mattr=+avx.
+; Really all we're trying to prove is that it doesn't crash any more.
+
+@id84 = common global <16 x i32> zeroinitializer, align 64
+
+define void @bar() #1 {
+entry:
+  %id83 = alloca <16 x i8>, align 16
+  %0 = load <16 x i32>* @id84, align 64
+  %conv = trunc <16 x i32> %0 to <16 x i8>
+  store <16 x i8> %conv, <16 x i8>* %id83, align 16
+  ret void
+}
+
+attributes #0 = { "unsafe-fp-math"="true" }
+attributes #1 = { noinline optnone "unsafe-fp-math"="true" }
diff --git a/test/CodeGen/X86/fastmath-optnone.ll b/test/CodeGen/X86/fastmath-optnone.ll
deleted file mode 100644
index 0caadff89167..000000000000
--- a/test/CodeGen/X86/fastmath-optnone.ll
+++ /dev/null
@@ -1,35 +0,0 @@
-; RUN: llc < %s -mcpu=corei7 -march=x86-64 -mattr=+sse2 | FileCheck %s
-; Verify that floating-point operations inside 'optnone' functions
-; are not optimized even if unsafe-fp-math is set.
-
-define float @foo(float %x) #0 {
-entry:
-  %add = fadd fast float %x, %x
-  %add1 = fadd fast float %add, %x
-  ret float %add1
-}
-
-; CHECK-LABEL: @foo
-; CHECK-NOT: add
-; CHECK: mul
-; CHECK-NOT: add
-; CHECK: ret
-
-define float @fooWithOptnone(float %x) #1 {
-entry:
-  %add = fadd fast float %x, %x
-  %add1 = fadd fast float %add, %x
-  ret float %add1
-}
-
-; CHECK-LABEL: @fooWithOptnone
-; CHECK-NOT: mul
-; CHECK: add
-; CHECK-NOT: mul
-; CHECK: add
-; CHECK-NOT: mul
-; CHECK: ret
-
-
-attributes #0 = { "unsafe-fp-math"="true" }
-attributes #1 = { noinline optnone "unsafe-fp-math"="true" }
diff --git a/test/CodeGen/X86/getelementptr.ll b/test/CodeGen/X86/getelementptr.ll
new file mode 100644
index 000000000000..f403212700a6
--- /dev/null
+++ b/test/CodeGen/X86/getelementptr.ll
@@ -0,0 +1,80 @@
+; RUN: llc < %s -O0 -march=x86
+; RUN: llc < %s -O0 -march=x86-64
+; RUN: llc < %s -O2 -march=x86
+; RUN: llc < %s -O2 -march=x86-64
+
+
+; Test big index trunc to pointer size:
+
+define i8* @test_trunc65(i8* %ptr) nounwind {
+; CHECK-LABEL: test_trunc65
+; CHECK: 3
+  %d = getelementptr i8* %ptr, i65 18446744073709551619 ; 2^64 + 3
+  ret i8* %d
+}
+
+define i8* @test_trunc128(i8* %ptr) nounwind {
+; CHECK-LABEL: test_trunc128
+; CHECK: 5
+  %d = getelementptr i8* %ptr, i128 18446744073709551621 ; 2^64 + 5
+  ret i8* %d
+}
+
+define i8* @test_trunc160(i8* %ptr) nounwind {
+; CHECK-LABEL: test_trunc160
+; CHECK: 8
+  %d = getelementptr i8* %ptr, i160 18446744073709551624 ; 2^64 + 8
+  ret i8* %d
+}
+
+define i8* @test_trunc256(i8* %ptr) nounwind {
+; CHECK-LABEL: test_trunc256
+; CHECK: 13
+  %d = getelementptr i8* %ptr, i256 18446744073709551629 ; 2^64 + 13
+  ret i8* %d
+}
+
+define i8* @test_trunc2048(i8* %ptr) nounwind {
+; CHECK-LABEL: test_trunc2048
+; CHECK: 21
+  %d = getelementptr i8* %ptr, i2048 18446744073709551637 ; 2^64 + 21
+  ret i8* %d
+}
+
+
+; Test small index sext to pointer size
+
+define i8* @test_sext3(i8* %ptr) nounwind {
+; CHECK-LABEL: test_sext3
+; CHECK: -3
+  %d = getelementptr i8* %ptr, i3 -3
+  ret i8* %d
+}
+
+define i8* @test_sext5(i8* %ptr) nounwind {
+; CHECK-LABEL: test_sext5
+; CHECK: -5
+  %d = getelementptr i8* %ptr, i5 -5
+  ret i8* %d
+}
+
+define i8* @test_sext8(i8* %ptr) nounwind {
+; CHECK-LABEL: test_sext8
+; CHECK: -8
+  %d = getelementptr i8* %ptr, i8 -8
+  ret i8* %d
+}
+
+define i8* @test_sext13(i8* %ptr) nounwind {
+; CHECK-LABEL: test_sext13
+; CHECK: -13
+  %d = getelementptr i8* %ptr, i8 -13
+  ret i8* %d
+}
+
+define i8* @test_sext16(i8* %ptr) nounwind {
+; CHECK-LABEL: test_sext16
+; CHECK: -21
+  %d = getelementptr i8* %ptr, i8 -21
+  ret i8* %d
+}
diff --git a/test/CodeGen/X86/inalloca-stdcall.ll b/test/CodeGen/X86/inalloca-stdcall.ll
index e5b07e262c7b..65a0f77c9a6f 100644
--- a/test/CodeGen/X86/inalloca-stdcall.ll
+++ b/test/CodeGen/X86/inalloca-stdcall.ll
@@ -6,6 +6,7 @@ declare x86_stdcallcc void @f(%Foo* inalloca %a)
 declare x86_stdcallcc void @i(i32 %a)
 
 define void @g() {
+; CHECK-LABEL: _g:
   %b = alloca inalloca %Foo
 ; CHECK: movl    $8, %eax
 ; CHECK: calll   __chkstk
diff --git a/test/CodeGen/X86/lower-vec-shuffle-bug.ll b/test/CodeGen/X86/lower-vec-shuffle-bug.ll
new file mode 100644
index 000000000000..5918e8045f62
--- /dev/null
+++ b/test/CodeGen/X86/lower-vec-shuffle-bug.ll
@@ -0,0 +1,41 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s
+
+define <4 x double> @test1(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test1:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 undef, i32 1, i32 undef, i32 5>
+  ret <4 x double> %0
+}
+
+define <4 x double> @test2(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test2:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 undef, i32 1, i32 undef, i32 1>
+  ret <4 x double> %0
+}
+
+define <4 x double> @test3(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test3:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 0, i32 1, i32 undef, i32 5>
+  ret <4 x double> %0
+}
+
+define <4 x double> @test4(<4 x double> %A, <4 x double> %B) {
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32> <i32 0, i32 1, i32 undef, i32 1>
+  ret <4 x double> %0
+}
diff --git a/test/CodeGen/X86/pr22774.ll b/test/CodeGen/X86/pr22774.ll
new file mode 100644
index 000000000000..426fcc43e308
--- /dev/null
+++ b/test/CodeGen/X86/pr22774.ll
@@ -0,0 +1,20 @@
+; RUN: llc -mattr=avx %s -o - | FileCheck %s

+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+

+@in = global <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, align 32
+@out = global <2 x i64> zeroinitializer, align 16
+
+define i32 @_Z3foov() {
+entry:
+; CHECK: {{vmovdqa|vmovaps}} in(%rip), %ymm0
+; CHECK-NEXT: vmovq %xmm0, %xmm0
+; CHECK-NEXT: {{vmovdqa|vmovaps}} %xmm0, out(%rip)
+  %0 = load <4 x i64>* @in, align 32
+  %vecext = extractelement <4 x i64> %0, i32 0
+  %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
+  %vecinit1 = insertelement <2 x i64> %vecinit, i64 0, i32 1
+  store <2 x i64> %vecinit1, <2 x i64>* @out, align 16
+  ret i32 0
+}
diff --git a/test/CodeGen/X86/scheduler-backtracking.ll b/test/CodeGen/X86/scheduler-backtracking.ll
new file mode 100644
index 000000000000..98471ee90d53
--- /dev/null
+++ b/test/CodeGen/X86/scheduler-backtracking.ll
@@ -0,0 +1,51 @@
+; RUN: llc -march=x86-64 < %s -pre-RA-sched=list-ilp    | FileCheck %s
+; RUN: llc -march=x86-64 < %s -pre-RA-sched=list-hybrid | FileCheck %s
+; RUN: llc -march=x86-64 < %s -pre-RA-sched=source      | FileCheck %s
+; RUN: llc -march=x86-64 < %s -pre-RA-sched=list-burr   | FileCheck %s
+; RUN: llc -march=x86-64 < %s -pre-RA-sched=linearize   | FileCheck %s
+
+; PR22304 https://llvm.org/bugs/show_bug.cgi?id=22304
+; Tests checking backtracking in source scheduler. llc used to crash on them.
+
+; CHECK-LABEL: test1
+define i256 @test1(i256 %a) {
+  %b = add i256 %a, 1 
+  %m = shl i256 %b, 1
+  %p = add i256 %m, 1
+  %v = lshr i256 %b, %p
+  %t = trunc i256 %v to i1
+  %c = shl i256 1, %p
+  %f = select i1 %t, i256 undef, i256 %c
+  ret i256 %f
+}
+
+; CHECK-LABEL: test2
+define i256 @test2(i256 %a) {
+  %b = sub i256 0, %a
+  %c = and i256 %b, %a
+  %d = call i256 @llvm.ctlz.i256(i256 %c, i1 false)
+  ret i256 %d
+}
+
+; CHECK-LABEL: test3
+define i256 @test3(i256 %n) {
+  %m = sub i256 -1, %n
+  %x = sub i256 0, %n
+  %y = and i256 %x, %m
+  %z = call i256 @llvm.ctlz.i256(i256 %y, i1 false)
+  ret i256 %z
+}
+
+declare i256 @llvm.ctlz.i256(i256, i1) nounwind readnone
+
+; CHECK-LABEL: test4
+define i64 @test4(i64 %a, i64 %b) {
+  %r = zext i64 %b to i256
+  %u = add i256 %r, 1
+  %w = and i256 %u, 1461501637330902918203684832716283019655932542975
+  %x = zext i64 %a to i256
+  %c = icmp uge i256 %w, %x
+  %y = select i1 %c, i64 0, i64 1
+  %z = add i64 %y, 1
+  ret i64 %z
+}
diff --git a/test/CodeGen/X86/setcc-combine.ll b/test/CodeGen/X86/setcc-combine.ll
new file mode 100644
index 000000000000..c6ad5e0031ed
--- /dev/null
+++ b/test/CodeGen/X86/setcc-combine.ll
@@ -0,0 +1,166 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic < %s | FileCheck %s
+
+define i32 @test_eq_1(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_eq_1:
+; CHECK: pcmpgtd %xmm0, %xmm1
+; CHECK-NEXT: pxor {{.*}}(%rip), %xmm1
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %A, %B
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp eq <4 x i32> %sext, zeroinitializer
+  %0 = extractelement <4 x i1> %cmp1, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_ne_1(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_ne_1:
+; CHECK: pcmpgtd %xmm0, %xmm1
+; CHECK-NOT: pxor
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %A, %B
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp ne <4 x i32> %sext, zeroinitializer
+  %0 = extractelement <4 x i1> %cmp1, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_le_1(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_le_1:
+; CHECK: movl $-1, %eax
+; CHECK-NEXT: retq
+entry:
+  %cmp = icmp slt <4 x i32> %A, %B
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp sle <4 x i32> %sext, zeroinitializer
+  %0 = extractelement <4 x i1> %cmp1, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_ge_1(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_ge_1:
+; CHECK: pcmpgtd %xmm0, %xmm1
+; CHECK: pxor {{.*}}(%rip), %xmm1
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %A, %B
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp sge <4 x i32> %sext, zeroinitializer
+  %0 = extractelement <4 x i1> %cmp1, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_lt_1(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_lt_1:
+; CHECK: pcmpgtd %xmm0, %xmm1
+; CHECK-NOT: pxor
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %A, %B
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp slt <4 x i32> %sext, zeroinitializer
+  %0 = extractelement <4 x i1> %cmp, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_gt_1(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_gt_1:
+; CHECK: xorl %eax, %eax
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %A, %B
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp sgt <4 x i32> %sext, zeroinitializer
+  %0 = extractelement <4 x i1> %cmp1, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_eq_2(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_eq_2:
+; CHECK: pcmpgtd %xmm1, %xmm0
+; CHECK-NEXT: pxor {{.*}}(%rip), %xmm0
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %B, %A
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp eq <4 x i32> %sext, zeroinitializer
+  %0 = extractelement <4 x i1> %cmp1, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_ne_2(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_ne_2:
+; CHECK: pcmpgtd %xmm1, %xmm0
+; CHECK-NOT: pxor
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %B, %A
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp ne <4 x i32> %sext, zeroinitializer
+  %0 = extractelement <4 x i1> %cmp1, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_le_2(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_le_2:
+; CHECK: pcmpgtd %xmm1, %xmm0
+; CHECK: pxor {{.*}}(%rip), %xmm0
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %B, %A
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp sle <4 x i32> zeroinitializer, %sext
+  %0 = extractelement <4 x i1> %cmp1, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_ge_2(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_ge_2:
+; CHECK: movl $-1, %eax
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %B, %A
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp sge <4 x i32> zeroinitializer, %sext
+  %0 = extractelement <4 x i1> %cmp1, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_lt_2(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_lt_2:
+; CHECK: pcmpgtd %xmm1, %xmm0
+; CHECK-NOT: pxor
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %B, %A
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp slt <4 x i32> zeroinitializer, %sext
+  %0 = extractelement <4 x i1> %cmp, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
+
+define i32 @test_gt_2(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_gt_2:
+; CHECK: pcmpgtd %xmm1, %xmm0
+; CHECK-NOT: pxor
+; CHECK: retq
+entry:
+  %cmp = icmp slt <4 x i32> %B, %A
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp1 = icmp sgt <4 x i32> zeroinitializer, %sext
+  %0 = extractelement <4 x i1> %cmp1, i32 1
+  %1 = sext i1 %0 to i32
+  ret i32 %1
+}
diff --git a/test/CodeGen/X86/vector-shuffle-512-v8.ll b/test/CodeGen/X86/vector-shuffle-512-v8.ll
index fd4c9cb72bad..9edd62d7d92a 100644
--- a/test/CodeGen/X86/vector-shuffle-512-v8.ll
+++ b/test/CodeGen/X86/vector-shuffle-512-v8.ll
@@ -687,7 +687,7 @@ define <8 x double> @shuffle_v8f64_c348cda0(<8 x double> %a, <8 x double> %b) {
 ; ALL-LABEL: shuffle_v8f64_c348cda0:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vextractf64x4 $1, %zmm0, %ymm2 
-; ALL-NEXT:    vperm2f128 {{.*#+}} ymm2 = ymm0[0,1],ymm2[0,1]
+; ALL-NEXT:    vperm2f128 {{.*#+}} ymm2 = ymm0[2,3],ymm2[0,1]
 ; ALL-NEXT:    vextractf64x4 $1, %zmm1, %ymm3 
 ; ALL-NEXT:    vbroadcastsd %xmm1, %ymm4
 ; ALL-NEXT:    vblendpd {{.*#+}} ymm4 = ymm3[0,1,2],ymm4[3]
@@ -1405,15 +1405,14 @@ define <8 x i64> @shuffle_v8i64_6caa87e5(<8 x i64> %a, <8 x i64> %b) {
 ; ALL-LABEL: shuffle_v8i64_6caa87e5:
 ; ALL:       # BB#0:
 ; ALL-NEXT:    vextracti64x4 $1, %zmm0, %ymm0 
-; ALL-NEXT:    vperm2i128 {{.*#+}} ymm2 = ymm0[0,1,0,1]
-; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm3 
-; ALL-NEXT:    vpblendd {{.*#+}} ymm4 = ymm1[0,1,2,3],ymm3[4,5],ymm1[6,7]
-; ALL-NEXT:    vpblendd {{.*#+}} ymm2 = ymm4[0,1],ymm2[2,3],ymm4[4,5],ymm2[6,7]
 ; ALL-NEXT:    vperm2i128 {{.*#+}} ymm0 = ymm0[2,3,0,1]
-; ALL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7]
+; ALL-NEXT:    vextracti64x4 $1, %zmm1, %ymm2
+; ALL-NEXT:    vpblendd {{.*#+}} ymm3 = ymm1[0,1,2,3],ymm2[4,5],ymm1[6,7]
+; ALL-NEXT:    vpblendd {{.*#+}} ymm3 = ymm3[0,1],ymm0[2,3],ymm3[4,5],ymm0[6,7]
+; ALL-NEXT:    vpblendd {{.*#+}} ymm1 = ymm2[0,1,2,3],ymm1[4,5,6,7]
 ; ALL-NEXT:    vpshufd {{.*#+}} ymm1 = ymm1[0,1,0,1,4,5,4,5]
 ; ALL-NEXT:    vpblendd {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3,4,5,6,7]
-; ALL-NEXT:    vinserti64x4 $1, %ymm2, %zmm0, %zmm0
+; ALL-NEXT:    vinserti64x4 $1, %ymm3, %zmm0, %zmm0
 ; ALL-NEXT:    retq
   %shuffle = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32> <i32 6, i32 12, i32 10, i32 10, i32 8, i32 7, i32 14, i32 5>
   ret <8 x i64> %shuffle
diff --git a/test/CodeGen/X86/win64_alloca_dynalloca.ll b/test/CodeGen/X86/win64_alloca_dynalloca.ll
index a6b6536f906c..aab2eea7ce44 100644
--- a/test/CodeGen/X86/win64_alloca_dynalloca.ll
+++ b/test/CodeGen/X86/win64_alloca_dynalloca.ll
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -mcpu=generic -enable-misched=false -mtriple=x86_64-mingw32     | FileCheck %s -check-prefix=M64
 ; RUN: llc < %s -mcpu=generic -enable-misched=false -mtriple=x86_64-win32       | FileCheck %s -check-prefix=W64
+; RUN: llc < %s -mcpu=generic -enable-misched=false -mtriple=x86_64-win32 -code-model=large | FileCheck %s -check-prefix=L64
 ; RUN: llc < %s -mcpu=generic -enable-misched=false -mtriple=x86_64-win32-macho | FileCheck %s -check-prefix=EFI
 ; PR8777
 ; PR8778
@@ -24,6 +25,13 @@ entry:
 ; W64: callq __chkstk
 ; W64: subq  %rax, %rsp
 
+; Use %r11 for the large model.
+; L64: movq  %rsp, %rbp
+; L64:       $4096, %rax
+; L64: movabsq $__chkstk, %r11
+; L64: callq *%r11
+; L64: subq  %rax, %rsp
+
 ; Freestanding
 ; EFI: movq  %rsp, %rbp
 ; EFI:       $[[B0OFS:4096|4104]], %rsp
@@ -33,8 +41,8 @@ entry:
 
 ; M64: leaq  15(%{{.*}}), %rax
 ; M64: andq  $-16, %rax
-; M64: callq ___chkstk
-; M64-NOT:   %rsp
+; M64: callq ___chkstk_ms
+; M64: subq  %rax, %rsp
 ; M64: movq  %rsp, %rax
 
 ; W64: leaq  15(%{{.*}}), %rax
@@ -43,6 +51,13 @@ entry:
 ; W64: subq  %rax, %rsp
 ; W64: movq  %rsp, %rax
 
+; L64: leaq  15(%{{.*}}), %rax
+; L64: andq  $-16, %rax
+; L64: movabsq $__chkstk, %r11
+; L64: callq *%r11
+; L64: subq  %rax, %rsp
+; L64: movq  %rsp, %rax
+
 ; EFI: leaq  15(%{{.*}}), [[R1:%r.*]]
 ; EFI: andq  $-16, [[R1]]
 ; EFI: movq  %rsp, [[R64:%r.*]]
@@ -84,7 +99,8 @@ entry:
 
 ; M64: leaq  15(%{{.*}}), %rax
 ; M64: andq  $-16, %rax
-; M64: callq ___chkstk
+; M64: callq ___chkstk_ms
+; M64: subq  %rax, %rsp
 ; M64: movq  %rsp, [[R2:%r.*]]
 ; M64: andq  $-128, [[R2]]
 ; M64: movq  [[R2]], %rsp
diff --git a/test/CodeGen/X86/win_chkstk.ll b/test/CodeGen/X86/win_chkstk.ll
index 0c02c1a11d18..4edc89f623ad 100644
--- a/test/CodeGen/X86/win_chkstk.ll
+++ b/test/CodeGen/X86/win_chkstk.ll
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN_X32
 ; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=WIN_X64
+; RUN: llc < %s -mtriple=x86_64-pc-win32 -code-model=large | FileCheck %s -check-prefix=WIN64_LARGE
 ; RUN: llc < %s -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X32
 ; RUN: llc < %s -mtriple=x86_64-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X64
 ; RUN: llc < %s -mtriple=i386-pc-linux | FileCheck %s -check-prefix=LINUX
@@ -16,6 +17,8 @@ define i32 @main4k() nounwind {
 entry:
 ; WIN_X32:    calll __chkstk
 ; WIN_X64:    callq __chkstk
+; WIN64_LARGE: movabsq $__chkstk, %r11
+; WIN64_LARGE: callq *%r11
 ; MINGW_X32:  calll __alloca
 ; MINGW_X64:  callq ___chkstk_ms
 ; LINUX-NOT:  call __chkstk
@@ -52,6 +55,8 @@ define x86_64_win64cc i32 @main4k_win64() nounwind {
 entry:
 ; WIN_X32:    calll __chkstk
 ; WIN_X64:    callq __chkstk
+; WIN64_LARGE: movabsq $__chkstk, %r11
+; WIN64_LARGE: callq *%r11
 ; MINGW_X32:  calll __alloca
 ; MINGW_X64:  callq ___chkstk_ms
 ; LINUX-NOT:  call __chkstk