diff options
| author | Roman Divacky <rdivacky@FreeBSD.org> | 2010-03-16 16:51:38 +0000 |
|---|---|---|
| committer | Roman Divacky <rdivacky@FreeBSD.org> | 2010-03-16 16:51:38 +0000 |
| commit | c69102774f9739c81ae1285ed9ae62405071c63c (patch) | |
| tree | 458dd25677a43aef6390ecadb4423817f00e08b0 /test/CodeGen/XCore | |
| parent | ea5b2dd11c0526581803e7eb58224a2eabf191e6 (diff) | |
Notes
Diffstat (limited to 'test/CodeGen/XCore')
| -rw-r--r-- | test/CodeGen/XCore/addsub64.ll | 15 | ||||
| -rw-r--r-- | test/CodeGen/XCore/indirectbr.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/XCore/mul64.ll | 13 |
3 files changed, 29 insertions, 1 deletions
diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll index 0432e5e712e6..d06248022e31 100644 --- a/test/CodeGen/XCore/addsub64.ll +++ b/test/CodeGen/XCore/addsub64.ll @@ -42,3 +42,18 @@ entry: ; CHECK: maccs: ; CHECK: maccs r1, r0, r3, r2 ; CHECK-NEXT: retsp 0 + +define i64 @lmul(i32 %a, i32 %b, i32 %c, i32 %d) { +entry: + %0 = zext i32 %a to i64 + %1 = zext i32 %b to i64 + %2 = zext i32 %c to i64 + %3 = zext i32 %d to i64 + %4 = mul i64 %1, %0 + %5 = add i64 %4, %2 + %6 = add i64 %5, %3 + ret i64 %6 +} +; CHECK: lmul: +; CHECK: lmul r1, r0, r1, r0, r2, r3 +; CHECK-NEXT: retsp 0 diff --git a/test/CodeGen/XCore/indirectbr.ll b/test/CodeGen/XCore/indirectbr.ll index a8f00cc497fc..92690029cd0e 100644 --- a/test/CodeGen/XCore/indirectbr.ll +++ b/test/CodeGen/XCore/indirectbr.ll @@ -38,7 +38,7 @@ L2: ; preds = %L3, %bb2 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] -; CHECK: ldap r11, .LBA3_foo_L5 +; CHECK: ldap r11, .Ltmp0 ; CHECK: stw r11, dp[nextaddr] store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 ret i32 %res.3 diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll index 329e214d1d23..1dc94712507e 100644 --- a/test/CodeGen/XCore/mul64.ll +++ b/test/CodeGen/XCore/mul64.ll @@ -37,3 +37,16 @@ entry: ; CHECK-NEXT: mul r0, r0, r3 ; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0 ; CHECK-NEXT: mov r0, r4 + +define i64 @mul64_2(i64 %a, i32 %b) { +entry: + %0 = zext i32 %b to i64 + %1 = mul i64 %a, %0 + ret i64 %1 +} +; CHECK: mul64_2: +; CHECK: ldc r3, 0 +; CHECK-NEXT: lmul r3, r0, r0, r2, r3, r3 +; CHECK-NEXT: mul r1, r1, r2 +; CHECK-NEXT: add r1, r3, r1 +; CHECK-NEXT: retsp 0 |
