vendor/clang/clang-trunk-r302418

9 files changed, 689 insertions, 91 deletions

diff --git a/test/CodeGen/aarch64-args.cpp b/test/CodeGen/aarch64-args.cpp
new file mode 100644
index 000000000000..409773627261
--- /dev/null
+++ b/test/CodeGen/aarch64-args.cpp
@@ -0,0 +1,67 @@
+// RUN: %clang_cc1 -triple arm64-apple-ios7.0 -target-abi darwinpcs -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - -x c %s | FileCheck %s --check-prefix=CHECK-GNU-C
+// RUN: %clang_cc1 -triple aarch64-linux-gnu -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-GNU-CXX
+
+// Empty structs are ignored for PCS purposes on Darwin and in C mode elsewhere.
+// In C++ mode on ELF they consume a register slot though. Functions are
+// slightly bigger than minimal to make confirmation against actual GCC
+// behaviour easier.
+
+#if __cplusplus
+#define EXTERNC extern "C"
+#else
+#define EXTERNC
+#endif
+
+struct Empty {};
+
+// CHECK: define i32 @empty_arg(i32 %a)
+// CHECK-GNU-C: define i32 @empty_arg(i32 %a)
+// CHECK-GNU-CXX: define i32 @empty_arg(i8 %e.coerce, i32 %a)
+EXTERNC int empty_arg(struct Empty e, int a) {
+  return a;
+}
+
+// CHECK: define void @empty_ret()
+// CHECK-GNU-C: define void @empty_ret()
+// CHECK-GNU-CXX: define void @empty_ret()
+EXTERNC struct Empty empty_ret() {
+  struct Empty e;
+  return e;
+}
+
+// However, what counts as "empty" is a baroque mess. This is super-empty, it's
+// ignored even in C++ mode. It also has sizeof == 0, violating C++, but that's
+// legacy for you:
+
+struct SuperEmpty {
+  int arr[0];
+};
+
+// CHECK: define i32 @super_empty_arg(i32 %a)
+// CHECK-GNU-C: define i32 @super_empty_arg(i32 %a)
+// CHECK-GNU-CXX: define i32 @super_empty_arg(i32 %a)
+EXTERNC int super_empty_arg(struct SuperEmpty e, int a) {
+  return a;
+}
+
+// This is not empty. It has 0 size but consumes a register slot for GCC.
+
+struct SortOfEmpty {
+  struct SuperEmpty e;
+};
+
+// CHECK: define i32 @sort_of_empty_arg(i32 %a)
+// CHECK-GNU-C: define i32 @sort_of_empty_arg(i32 %a)
+// CHECK-GNU-CXX: define i32 @sort_of_empty_arg(i8 %e.coerce, i32 %a)
+EXTERNC int sort_of_empty_arg(struct Empty e, int a) {
+  return a;
+}
+
+// CHECK: define void @sort_of_empty_ret()
+// CHECK-GNU-C: define void @sort_of_empty_ret()
+// CHECK-GNU-CXX: define void @sort_of_empty_ret()
+EXTERNC struct SortOfEmpty sort_of_empty_ret() {
+  struct SortOfEmpty e;
+  return e;
+}
diff --git a/test/CodeGen/arm_acle.c b/test/CodeGen/arm_acle.c
index b4f39bef1572..7c8a5aa8adb0 100644
--- a/test/CodeGen/arm_acle.c
+++ b/test/CodeGen/arm_acle.c
@@ -76,7 +76,7 @@ void test_dbg(void) {
 // AArch32: call i32 @llvm.arm.strex
 // AArch64: call i64 @llvm.aarch64.ldxr
 // AArch64: call i32 @llvm.aarch64.stxr
-uint32_t test_swp(uint32_t x, volatile void *p) {
+void test_swp(uint32_t x, volatile void *p) {
   __swp(x, p);
 }
 
@@ -118,6 +118,7 @@ void test_nop(void) {
 }
 
 /* 9 DATA-PROCESSING INTRINSICS */
+
 /* 9.2 Miscellaneous data-processing intrinsics */
 // ARM-LABEL: test_ror
 // ARM: lshr
@@ -266,8 +267,7 @@ uint64_t test_rbitll(uint64_t t) {
 }
 
 /* 9.4 Saturating intrinsics */
-#ifdef __ARM_32BIT_STATE
-
+#ifdef __ARM_FEATURE_SAT
 /* 9.4.1 Width-specified saturation intrinsics */
 // AArch32-LABEL: test_ssat
 // AArch32: call i32 @llvm.arm.ssat(i32 %t, i32 1)
@@ -277,11 +277,13 @@ int32_t test_ssat(int32_t t) {
 
 // AArch32-LABEL: test_usat
 // AArch32: call i32 @llvm.arm.usat(i32 %t, i32 2)
-int32_t test_usat(int32_t t) {
+uint32_t test_usat(int32_t t) {
   return __usat(t, 2);
 }
+#endif
 
 /* 9.4.2 Saturating addition and subtraction intrinsics */
+#ifdef __ARM_FEATURE_DSP
 // AArch32-LABEL: test_qadd
 // AArch32: call i32 @llvm.arm.qadd(i32 %a, i32 %b)
 int32_t test_qadd(int32_t a, int32_t b) {
@@ -304,6 +306,389 @@ int32_t test_qdbl() {
 }
 #endif
 
+/*
+ * 9.3 16-bit multiplications
+ */
+#if __ARM_FEATURE_DSP
+// AArch32-LABEL: test_smulbb
+// AArch32: call i32 @llvm.arm.smulbb
+int32_t test_smulbb(int32_t a, int32_t b) {
+  return __smulbb(a, b);
+}
+// AArch32-LABEL: test_smulbt
+// AArch32: call i32 @llvm.arm.smulbt
+int32_t test_smulbt(int32_t a, int32_t b) {
+  return __smulbt(a, b);
+}
+// AArch32-LABEL: test_smultb
+// AArch32: call i32 @llvm.arm.smultb
+int32_t test_smultb(int32_t a, int32_t b) {
+  return __smultb(a, b);
+}
+// AArch32-LABEL: test_smultt
+// AArch32: call i32 @llvm.arm.smultt
+int32_t test_smultt(int32_t a, int32_t b) {
+  return __smultt(a, b);
+}
+// AArch32-LABEL: test_smulwb
+// AArch32: call i32 @llvm.arm.smulwb
+int32_t test_smulwb(int32_t a, int32_t b) {
+  return __smulwb(a, b);
+}
+// AArch32-LABEL: test_smulwt
+// AArch32: call i32 @llvm.arm.smulwt
+int32_t test_smulwt(int32_t a, int32_t b) {
+  return __smulwt(a, b);
+}
+#endif
+
+/* 9.4.3 Accumultating multiplications */
+#if __ARM_FEATURE_DSP
+// AArch32-LABEL: test_smlabb
+// AArch32: call i32 @llvm.arm.smlabb(i32 %a, i32 %b, i32 %c)
+int32_t test_smlabb(int32_t a, int32_t b, int32_t c) {
+  return __smlabb(a, b, c);
+}
+// AArch32-LABEL: test_smlabt
+// AArch32: call i32 @llvm.arm.smlabt(i32 %a, i32 %b, i32 %c)
+int32_t test_smlabt(int32_t a, int32_t b, int32_t c) {
+  return __smlabt(a, b, c);
+}
+// AArch32-LABEL: test_smlatb
+// AArch32: call i32 @llvm.arm.smlatb(i32 %a, i32 %b, i32 %c)
+int32_t test_smlatb(int32_t a, int32_t b, int32_t c) {
+  return __smlatb(a, b, c);
+}
+// AArch32-LABEL: test_smlatt
+// AArch32: call i32 @llvm.arm.smlatt(i32 %a, i32 %b, i32 %c)
+int32_t test_smlatt(int32_t a, int32_t b, int32_t c) {
+  return __smlatt(a, b, c);
+}
+// AArch32-LABEL: test_smlawb
+// AArch32: call i32 @llvm.arm.smlawb(i32 %a, i32 %b, i32 %c)
+int32_t test_smlawb(int32_t a, int32_t b, int32_t c) {
+  return __smlawb(a, b, c);
+}
+// AArch32-LABEL: test_smlawt
+// AArch32: call i32 @llvm.arm.smlawt(i32 %a, i32 %b, i32 %c)
+int32_t test_smlawt(int32_t a, int32_t b, int32_t c) {
+  return __smlawt(a, b, c);
+}
+#endif
+
+/* 9.5.4 Parallel 16-bit saturation */
+#if __ARM_FEATURE_SIMD32
+// AArch32-LABEL: test_ssat16
+// AArch32: call i32 @llvm.arm.ssat16
+int16x2_t test_ssat16(int16x2_t a) {
+  return __ssat16(a, 15);
+}
+// AArch32-LABEL: test_usat16
+// AArch32: call i32 @llvm.arm.usat16
+uint16x2_t test_usat16(int16x2_t a) {
+  return __usat16(a, 15);
+}
+#endif
+
+/* 9.5.5 Packing and unpacking */
+#if __ARM_FEATURE_SIMD32
+// AArch32-LABEL: test_sxtab16
+// AArch32: call i32 @llvm.arm.sxtab16
+int16x2_t test_sxtab16(int16x2_t a, int8x4_t b) {
+  return __sxtab16(a, b);
+}
+// AArch32-LABEL: test_sxtb16
+// AArch32: call i32 @llvm.arm.sxtb16
+int16x2_t test_sxtb16(int8x4_t a) {
+  return __sxtb16(a);
+}
+// AArch32-LABEL: test_uxtab16
+// AArch32: call i32 @llvm.arm.uxtab16
+int16x2_t test_uxtab16(int16x2_t a, int8x4_t b) {
+  return __uxtab16(a, b);
+}
+// AArch32-LABEL: test_uxtb16
+// AArch32: call i32 @llvm.arm.uxtb16
+int16x2_t test_uxtb16(int8x4_t a) {
+  return __uxtb16(a);
+}
+#endif
+
+/* 9.5.6 Parallel selection */
+#if __ARM_FEATURE_SIMD32
+// AArch32-LABEL: test_sel
+// AArch32: call i32 @llvm.arm.sel
+uint8x4_t test_sel(uint8x4_t a, uint8x4_t b) {
+  return __sel(a, b);
+}
+#endif
+
+/* 9.5.7 Parallel 8-bit addition and subtraction */
+#if __ARM_FEATURE_SIMD32
+// AArch32-LABEL: test_qadd8
+// AArch32: call i32 @llvm.arm.qadd8
+int16x2_t test_qadd8(int8x4_t a, int8x4_t b) {
+  return __qadd8(a, b);
+}
+// AArch32-LABEL: test_qsub8
+// AArch32: call i32 @llvm.arm.qsub8
+int8x4_t test_qsub8(int8x4_t a, int8x4_t b) {
+  return __qsub8(a, b);
+}
+// AArch32-LABEL: test_sadd8
+// AArch32: call i32 @llvm.arm.sadd8
+int8x4_t test_sadd8(int8x4_t a, int8x4_t b) {
+  return __sadd8(a, b);
+}
+// AArch32-LABEL: test_shadd8
+// AArch32: call i32 @llvm.arm.shadd8
+int8x4_t test_shadd8(int8x4_t a, int8x4_t b) {
+  return __shadd8(a, b);
+}
+// AArch32-LABEL: test_shsub8
+// AArch32: call i32 @llvm.arm.shsub8
+int8x4_t test_shsub8(int8x4_t a, int8x4_t b) {
+  return __shsub8(a, b);
+}
+// AArch32-LABEL: test_ssub8
+// AArch32: call i32 @llvm.arm.ssub8
+int8x4_t test_ssub8(int8x4_t a, int8x4_t b) {
+  return __ssub8(a, b);
+}
+// AArch32-LABEL: test_uadd8
+// AArch32: call i32 @llvm.arm.uadd8
+uint8x4_t test_uadd8(uint8x4_t a, uint8x4_t b) {
+  return __uadd8(a, b);
+}
+// AArch32-LABEL: test_uhadd8
+// AArch32: call i32 @llvm.arm.uhadd8
+uint8x4_t test_uhadd8(uint8x4_t a, uint8x4_t b) {
+  return __uhadd8(a, b);
+}
+// AArch32-LABEL: test_uhsub8
+// AArch32: call i32 @llvm.arm.uhsub8
+uint8x4_t test_uhsub8(uint8x4_t a, uint8x4_t b) {
+  return __uhsub8(a, b);
+}
+// AArch32-LABEL: test_uqadd8
+// AArch32: call i32 @llvm.arm.uqadd8
+uint8x4_t test_uqadd8(uint8x4_t a, uint8x4_t b) {
+  return __uqadd8(a, b);
+}
+// AArch32-LABEL: test_uqsub8
+// AArch32: call i32 @llvm.arm.uqsub8
+uint8x4_t test_uqsub8(uint8x4_t a, uint8x4_t b) {
+  return __uqsub8(a, b);
+}
+// AArch32-LABEL: test_usub8
+// AArch32: call i32 @llvm.arm.usub8
+uint8x4_t test_usub8(uint8x4_t a, uint8x4_t b) {
+  return __usub8(a, b);
+}
+#endif
+
+/* 9.5.8 Sum of 8-bit absolute differences */
+#if __ARM_FEATURE_SIMD32
+// AArch32-LABEL: test_usad8
+// AArch32: call i32 @llvm.arm.usad8
+uint32_t test_usad8(uint8x4_t a, uint8x4_t b) {
+  return __usad8(a, b);
+}
+// AArch32-LABEL: test_usada8
+// AArch32: call i32 @llvm.arm.usada8
+uint32_t test_usada8(uint8_t a, uint8_t b, uint8_t c) {
+  return __usada8(a, b, c);
+}
+#endif
+
+/* 9.5.9 Parallel 16-bit addition and subtraction */
+#if __ARM_FEATURE_SIMD32
+// AArch32-LABEL: test_qadd16
+// AArch32: call i32 @llvm.arm.qadd16
+int16x2_t test_qadd16(int16x2_t a, int16x2_t b) {
+  return __qadd16(a, b);
+}
+// AArch32-LABEL: test_qasx
+// AArch32: call i32 @llvm.arm.qasx
+int16x2_t test_qasx(int16x2_t a, int16x2_t b) {
+  return __qasx(a, b);
+}
+// AArch32-LABEL: test_qsax
+// AArch32: call i32 @llvm.arm.qsax
+int16x2_t test_qsax(int16x2_t a, int16x2_t b) {
+  return __qsax(a, b);
+}
+// AArch32-LABEL: test_qsub16
+// AArch32: call i32 @llvm.arm.qsub16
+int16x2_t test_qsub16(int16x2_t a, int16x2_t b) {
+  return __qsub16(a, b);
+}
+// AArch32-LABEL: test_sadd16
+// AArch32: call i32 @llvm.arm.sadd16
+int16x2_t test_sadd16(int16x2_t a, int16x2_t b) {
+  return __sadd16(a, b);
+}
+// AArch32-LABEL: test_sasx
+// AArch32: call i32 @llvm.arm.sasx
+int16x2_t test_sasx(int16x2_t a, int16x2_t b) {
+  return __sasx(a, b);
+}
+// AArch32-LABEL: test_shadd16
+// AArch32: call i32 @llvm.arm.shadd16
+int16x2_t test_shadd16(int16x2_t a, int16x2_t b) {
+  return __shadd16(a, b);
+}
+// AArch32-LABEL: test_shasx
+// AArch32: call i32 @llvm.arm.shasx
+int16x2_t test_shasx(int16x2_t a, int16x2_t b) {
+  return __shasx(a, b);
+}
+// AArch32-LABEL: test_shsax
+// AArch32: call i32 @llvm.arm.shsax
+int16x2_t test_shsax(int16x2_t a, int16x2_t b) {
+  return __shsax(a, b);
+}
+// AArch32-LABEL: test_shsub16
+// AArch32: call i32 @llvm.arm.shsub16
+int16x2_t test_shsub16(int16x2_t a, int16x2_t b) {
+  return __shsub16(a, b);
+}
+// AArch32-LABEL: test_ssax
+// AArch32: call i32 @llvm.arm.ssax
+int16x2_t test_ssax(int16x2_t a, int16x2_t b) {
+  return __ssax(a, b);
+}
+// AArch32-LABEL: test_ssub16
+// AArch32: call i32 @llvm.arm.ssub16
+int16x2_t test_ssub16(int16x2_t a, int16x2_t b) {
+  return __ssub16(a, b);
+}
+// AArch32-LABEL: test_uadd16
+// AArch32: call i32 @llvm.arm.uadd16
+uint16x2_t test_uadd16(uint16x2_t a, uint16x2_t b) {
+  return __uadd16(a, b);
+}
+// AArch32-LABEL: test_uasx
+// AArch32: call i32 @llvm.arm.uasx
+uint16x2_t test_uasx(uint16x2_t a, uint16x2_t b) {
+  return __uasx(a, b);
+}
+// AArch32-LABEL: test_uhadd16
+// AArch32: call i32 @llvm.arm.uhadd16
+uint16x2_t test_uhadd16(uint16x2_t a, uint16x2_t b) {
+  return __uhadd16(a, b);
+}
+// AArch32-LABEL: test_uhasx
+// AArch32: call i32 @llvm.arm.uhasx
+uint16x2_t test_uhasx(uint16x2_t a, uint16x2_t b) {
+  return __uhasx(a, b);
+}
+// AArch32-LABEL: test_uhsax
+// AArch32: call i32 @llvm.arm.uhsax
+uint16x2_t test_uhsax(uint16x2_t a, uint16x2_t b) {
+  return __uhsax(a, b);
+}
+// AArch32-LABEL: test_uhsub16
+// AArch32: call i32 @llvm.arm.uhsub16
+uint16x2_t test_uhsub16(uint16x2_t a, uint16x2_t b) {
+  return __uhsub16(a, b);
+}
+// AArch32-LABEL: test_uqadd16
+// AArch32: call i32 @llvm.arm.uqadd16
+uint16x2_t test_uqadd16(uint16x2_t a, uint16x2_t b) {
+  return __uqadd16(a, b);
+}
+// AArch32-LABEL: test_uqasx
+// AArch32: call i32 @llvm.arm.uqasx
+uint16x2_t test_uqasx(uint16x2_t a, uint16x2_t b) {
+  return __uqasx(a, b);
+}
+// AArch32-LABEL: test_uqsax
+// AArch32: call i32 @llvm.arm.uqsax
+uint16x2_t test_uqsax(uint16x2_t a, uint16x2_t b) {
+  return __uqsax(a, b);
+}
+// AArch32-LABEL: test_uqsub16
+// AArch32: call i32 @llvm.arm.uqsub16
+uint16x2_t test_uqsub16(uint16x2_t a, uint16x2_t b) {
+  return __uqsub16(a, b);
+}
+// AArch32-LABEL: test_usax
+// AArch32: call i32 @llvm.arm.usax
+uint16x2_t test_usax(uint16x2_t a, uint16x2_t b) {
+  return __usax(a, b);
+}
+// AArch32-LABEL: test_usub16
+// AArch32: call i32 @llvm.arm.usub16
+uint16x2_t test_usub16(uint16x2_t a, uint16x2_t b) {
+  return __usub16(a, b);
+}
+#endif
+
+/* 9.5.10 Parallel 16-bit multiplications */
+#if __ARM_FEATURE_SIMD32
+// AArch32-LABEL: test_smlad
+// AArch32: call i32 @llvm.arm.smlad
+int32_t test_smlad(int16x2_t a, int16x2_t b, int32_t c) {
+  return __smlad(a, b, c);
+}
+// AArch32-LABEL: test_smladx
+// AArch32: call i32 @llvm.arm.smladx
+int32_t test_smladx(int16x2_t a, int16x2_t b, int32_t c) {
+  return __smladx(a, b, c);
+}
+// AArch32-LABEL: test_smlald
+// AArch32: call i64 @llvm.arm.smlald
+int64_t test_smlald(int16x2_t a, int16x2_t b, int64_t c) {
+  return __smlald(a, b, c);
+}
+// AArch32-LABEL: test_smlaldx
+// AArch32: call i64 @llvm.arm.smlaldx
+int64_t test_smlaldx(int16x2_t a, int16x2_t b, int64_t c) {
+  return __smlaldx(a, b, c);
+}
+// AArch32-LABEL: test_smlsd
+// AArch32: call i32 @llvm.arm.smlsd
+int32_t test_smlsd(int16x2_t a, int16x2_t b, int32_t c) {
+  return __smlsd(a, b, c);
+}
+// AArch32-LABEL: test_smlsdx
+// AArch32: call i32 @llvm.arm.smlsdx
+int32_t test_smlsdx(int16x2_t a, int16x2_t b, int32_t c) {
+  return __smlsdx(a, b, c);
+}
+// AArch32-LABEL: test_smlsld
+// AArch32: call i64 @llvm.arm.smlsld
+int64_t test_smlsld(int16x2_t a, int16x2_t b, int64_t c) {
+  return __smlsld(a, b, c);
+}
+// AArch32-LABEL: test_smlsldx
+// AArch32: call i64 @llvm.arm.smlsldx
+int64_t test_smlsldx(int16x2_t a, int16x2_t b, int64_t c) {
+  return __smlsldx(a, b, c);
+}
+// AArch32-LABEL: test_smuad
+// AArch32: call i32 @llvm.arm.smuad
+int32_t test_smuad(int16x2_t a, int16x2_t b) {
+  return __smuad(a, b);
+}
+// AArch32-LABEL: test_smuadx
+// AArch32: call i32 @llvm.arm.smuadx
+int32_t test_smuadx(int16x2_t a, int16x2_t b) {
+  return __smuadx(a, b);
+}
+// AArch32-LABEL: test_smusd
+// AArch32: call i32 @llvm.arm.smusd
+int32_t test_smusd(int16x2_t a, int16x2_t b) {
+  return __smusd(a, b);
+}
+// AArch32-LABEL: test_smusdx
+// AArch32: call i32 @llvm.arm.smusdx
+int32_t test_smusdx(int16x2_t a, int16x2_t b) {
+  return __smusdx(a, b);
+}
+#endif
+
 /* 9.7 CRC32 intrinsics */
 // ARM-LABEL: test_crc32b
 // AArch32: call i32 @llvm.arm.crc32b
diff --git a/test/CodeGen/lwp-builtins.c b/test/CodeGen/lwp-builtins.c
new file mode 100644
index 000000000000..c689c3974d4b
--- /dev/null
+++ b/test/CodeGen/lwp-builtins.c
@@ -0,0 +1,39 @@
+// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +lwp -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include <x86intrin.h>
+
+void test_llwpcb(void *ptr) {
+  // CHECK-LABEL: @test_llwpcb
+  // CHECK: call void @llvm.x86.llwpcb(i8* %{{.*}})
+  __llwpcb(ptr);
+}
+
+void* test_slwpcb() {
+  // CHECK-LABEL: @test_slwpcb
+  // CHECK: call i8* @llvm.x86.slwpcb()
+  return __slwpcb();
+}
+
+unsigned char test_lwpins32(unsigned val2, unsigned val1) {
+  // CHECK-LABEL: @test_lwpins32
+  // CHECK: call i8 @llvm.x86.lwpins32(i32
+  return __lwpins32(val2, val1, 0x01234);
+}
+
+unsigned char test_lwpins64(unsigned long long val2, unsigned val1) {
+  // CHECK-LABEL: @test_lwpins64
+  // CHECK: call i8 @llvm.x86.lwpins64(i64
+  return __lwpins64(val2, val1, 0x56789);
+}
+
+void test_lwpval32(unsigned val2, unsigned val1) {
+  // CHECK-LABEL: @test_lwpval32
+  // CHECK: call void @llvm.x86.lwpval32(i32
+  __lwpval32(val2, val1, 0x01234);
+}
+
+void test_lwpval64(unsigned long long val2, unsigned val1) {
+  // CHECK-LABEL: @test_lwpval64
+  // CHECK: call void @llvm.x86.lwpval64(i64
+  __lwpval64(val2, val1, 0xABCDEF);
+}
diff --git a/test/CodeGen/mozilla-ms-inline-asm.c b/test/CodeGen/mozilla-ms-inline-asm.c
index 3335a87fefe5..26e8ebce1e28 100644
--- a/test/CodeGen/mozilla-ms-inline-asm.c
+++ b/test/CodeGen/mozilla-ms-inline-asm.c
@@ -18,25 +18,25 @@ void invoke(void* that, unsigned methodIndex,
 // CHECK: store i32 %2, i32* %7, align 4
 // CHECK: store i8* %3, i8** %8, align 4
 // CHECK: call void asm sideeffect inteldialect
-// CHECK: mov edx,dword ptr $1
-// CHECK: test edx,edx
-// CHECK: jz {{[^_]*}}__MSASMLABEL_.${:uid}__noparams
-//             ^ Can't use {{.*}} here because the matching is greedy.
-// CHECK: mov eax,edx
-// CHECK: shl eax,$$3
-// CHECK: sub esp,eax
-// CHECK: mov ecx,esp
-// CHECK: push dword ptr $0
-// CHECK: call dword ptr $2
-// CHECK: {{.*}}__MSASMLABEL_.${:uid}__noparams:
-// CHECK: mov ecx,dword ptr $3
-// CHECK: push ecx
-// CHECK: mov edx,[ecx]
-// CHECK: mov eax,dword ptr $4
-// CHECK: call dword ptr[edx+eax*$$4]
-// CHECK: mov esp,ebp
-// CHECK: pop ebp
-// CHECK: ret
+// CHECK-SAME: mov edx,$1
+// CHECK-SAME: test edx,edx
+// CHECK-SAME: jz {{[^_]*}}__MSASMLABEL_.${:uid}__noparams
+//                ^ Can't use {{.*}} here because the matching is greedy.
+// CHECK-SAME: mov eax,edx
+// CHECK-SAME: shl eax,$$3
+// CHECK-SAME: sub esp,eax
+// CHECK-SAME: mov ecx,esp
+// CHECK-SAME: push $0
+// CHECK-SAME: call dword ptr $2
+// CHECK-SAME: {{.*}}__MSASMLABEL_.${:uid}__noparams:
+// CHECK-SAME: mov ecx,$3
+// CHECK-SAME: push ecx
+// CHECK-SAME: mov edx,[ecx]
+// CHECK-SAME: mov eax,$4
+// CHECK-SAME: call dword ptr[edx+eax*$$4]
+// CHECK-SAME: mov esp,ebp
+// CHECK-SAME: pop ebp
+// CHECK-SAME: ret
 // CHECK: "=*m,*m,*m,*m,*m,~{eax},~{ebp},~{ecx},~{edx},~{flags},~{esp},~{dirflag},~{fpsr},~{flags}"
 // CHECK: (i8** %8, i32* %7, void (...)* bitcast (void ()* @invoke_copy_to_stack to void (...)*), i8** %5, i32* %6)
 // CHECK: ret void
diff --git a/test/CodeGen/ms-inline-asm-64.c b/test/CodeGen/ms-inline-asm-64.c
index d6f6e2ee0e0e..69828feb3623 100644
--- a/test/CodeGen/ms-inline-asm-64.c
+++ b/test/CodeGen/ms-inline-asm-64.c
@@ -5,14 +5,18 @@ void t1() {
   int var = 10;
   __asm mov rax, offset var ; rax = address of myvar
 // CHECK: t1
-// CHECK: call void asm sideeffect inteldialect "mov rax, $0", "r,~{rax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: mov rax, $0
+// CHECK-SAME: "r,~{rax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
 }
 
 void t2() {
   int var = 10;
   __asm mov [eax], offset var
 // CHECK: t2
-// CHECK: call void asm sideeffect inteldialect "mov [eax], $0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: mov [eax], $0
+// CHECK-SAME: "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
 }
 
 struct t3_type { int a, b; };
@@ -28,7 +32,11 @@ int t3() {
   }
   return foo.b;
 // CHECK: t3
-// CHECK: call void asm sideeffect inteldialect "lea ebx, qword ptr $0\0A\09mov eax, [ebx].0\0A\09mov [ebx].4, ecx", "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t3_type* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: lea ebx, $0
+// CHECK-SAME: mov eax, [ebx].0
+// CHECK-SAME: mov [ebx].4, ecx
+// CHECK-SAME: "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t3_type* %{{.*}})
 }
 
 int t4() {
@@ -44,5 +52,9 @@ int t4() {
   }
   return foo.b;
 // CHECK: t4
-// CHECK: call void asm sideeffect inteldialect "lea ebx, qword ptr $0\0A\09mov eax, [ebx].0\0A\09mov [ebx].4, ecx", "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t3_type* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: lea ebx, $0
+// CHECK-SAME: mov eax, [ebx].0
+// CHECK-SAME: mov [ebx].4, ecx
+// CHECK-SAME: "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t3_type* %{{.*}})
 }
diff --git a/test/CodeGen/ms-inline-asm-avx512.c b/test/CodeGen/ms-inline-asm-avx512.c
index c1b783a2107c..6189e50d2116 100644
--- a/test/CodeGen/ms-inline-asm-avx512.c
+++ b/test/CodeGen/ms-inline-asm-avx512.c
@@ -1,5 +1,5 @@
 // REQUIRES: x86-registered-target
-// RUN: %clang_cc1 %s -triple x86_64-pc-windows-msvc -target-cpu knl -fasm-blocks -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 %s -triple x86_64-pc-windows-msvc -target-cpu skylake-avx512 -fasm-blocks -emit-llvm -o - | FileCheck %s
 
 void t1() {
 // CHECK: @t1
@@ -19,3 +19,16 @@ void t2() {
 	  vaddpd zmm8 {k1}, zmm27, zmm6
   }
 }
+
+void ignore_fe_size() {
+  // CHECK-LABEL: define void @ignore_fe_size()
+  char c;
+  // CHECK: vaddps xmm1, xmm2, $1{1to4}
+  __asm vaddps xmm1, xmm2, [c]{1to4}
+  // CHECK: vaddps xmm1, xmm2, $2
+  __asm vaddps xmm1, xmm2, [c]
+  // CHECK: mov eax, $3
+  __asm mov eax, [c]
+  // CHECK: mov $0, rax
+  __asm mov [c], rax
+}
diff --git a/test/CodeGen/ms-inline-asm.c b/test/CodeGen/ms-inline-asm.c
index c4fe08a3e13b..5182d7f2e81a 100644
--- a/test/CodeGen/ms-inline-asm.c
+++ b/test/CodeGen/ms-inline-asm.c
@@ -92,7 +92,11 @@ void t9() {
     __asm { pop ebx }
   }
 // CHECK: t9
-// CHECK: call void asm sideeffect inteldialect "push ebx\0A\09mov ebx, $$0x07\0A\09pop ebx\0A\09", "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: push ebx
+// CHECK-SAME: mov ebx, $$0x07
+// CHECK-SAME: pop ebx
+// CHECK-SAME: "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
 }
 
 unsigned t10(void) {
@@ -107,7 +111,10 @@ unsigned t10(void) {
 // CHECK: [[I:%[a-zA-Z0-9]+]] = alloca i32, align 4
 // CHECK: [[J:%[a-zA-Z0-9]+]] = alloca i32, align 4
 // CHECK: store i32 1, i32* [[I]], align 4
-// CHECK: call i32 asm sideeffect inteldialect "mov eax, dword ptr $2\0A\09mov dword ptr $0, eax", "=*m,={eax},*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}})
+// CHECK: call i32 asm sideeffect inteldialect
+// CHECK-SAME: mov eax, $2
+// CHECK-SAME: mov $0, eax
+// CHECK-SAME: "=*m,={eax},*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}})
 // CHECK: [[RET:%[a-zA-Z0-9]+]] = load i32, i32* [[J]], align 4
 // CHECK: ret i32 [[RET]]
 }
@@ -128,7 +135,12 @@ unsigned t12(void) {
   }
   return j + m;
 // CHECK: t12
-// CHECK: call i32 asm sideeffect inteldialect "mov eax, dword ptr $3\0A\09mov dword ptr $0, eax\0A\09mov eax, dword ptr $4\0A\09mov dword ptr $1, eax", "=*m,=*m,={eax},*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}})
+// CHECK: call i32 asm sideeffect inteldialect
+// CHECK-SAME: mov eax, $3
+// CHECK-SAME: mov $0, eax
+// CHECK-SAME: mov eax, $4
+// CHECK-SAME: mov $1, eax
+// CHECK-SAME: "=*m,=*m,={eax},*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}})
 }
 
 void t13() {
@@ -136,8 +148,23 @@ void t13() {
   short j = 2;
   __asm movzx eax, i
   __asm movzx eax, j
-// CHECK: t13
-// CHECK: call void asm sideeffect inteldialect "movzx eax, byte ptr $0\0A\09movzx eax, word ptr $1", "*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i8* %{{.*}}i, i16* %{{.*}}j)
+// CHECK-LABEL: define void @t13()
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: movzx eax, byte ptr $0
+// CHECK-SAME: movzx eax, word ptr $1
+// CHECK-SAME: "*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i8* %{{.*}}i, i16* %{{.*}}j)
+}
+
+void t13_brac() {
+  char i = 1;
+  short j = 2;
+  __asm movzx eax, [i]
+  __asm movzx eax, [j]
+// CHECK-LABEL: define void @t13_brac()
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: movzx eax, byte ptr $0
+// CHECK-SAME: movzx eax, word ptr $1
+// CHECK-SAME: "*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i8* %{{.*}}i, i16* %{{.*}}j)
 }
 
 void t14() {
@@ -150,7 +177,7 @@ void t14() {
     .endif
   }
 // CHECK: t14
-// CHECK: call void asm sideeffect inteldialect ".if 1\0A\09mov eax, dword ptr $0\0A\09.else\0A\09mov ebx, j\0A\09.endif", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect ".if 1\0A\09mov eax, $0\0A\09.else\0A\09mov ebx, j\0A\09.endif", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
 }
 
 int gvar = 10;
@@ -158,7 +185,7 @@ void t15() {
 // CHECK: t15
   int lvar = 10;
   __asm mov eax, lvar        ; eax = 10
-// CHECK: mov eax, dword ptr $0
+// CHECK: mov eax, $0
   __asm mov eax, offset lvar ; eax = address of lvar
 // CHECK: mov eax, $1
   __asm mov eax, offset gvar ; eax = address of gvar
@@ -236,7 +263,11 @@ void t21() {
     __asm pop ebx
   }
 // CHECK: t21
-// CHECK: call void asm sideeffect inteldialect "push ebx\0A\09mov ebx, $$07H\0A\09pop ebx", "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: push ebx
+// CHECK-SAME: mov ebx, $$07H
+// CHECK-SAME: pop ebx
+// CHECK-SAME: "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
 }
 
 extern void t22_helper(int x);
@@ -252,9 +283,15 @@ void t22() {
     __asm pop ebx
   }
 // CHECK: t22
-// CHECK: call void asm sideeffect inteldialect "push ebx\0A\09mov ebx, esp", "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: push ebx
+// CHECK-SAME: mov ebx, esp
+// CHECK-SAME: "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
 // CHECK: call void @t22_helper
-// CHECK: call void asm sideeffect inteldialect "mov esp, ebx\0A\09pop ebx", "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: mov esp, ebx
+// CHECK-SAME: pop ebx
+// CHECK-SAME: "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t23() {
@@ -342,9 +379,9 @@ int *t30()
 {
   int *res;
   __asm lea edi, results
-// CHECK: lea edi, dword ptr $2
+// CHECK: lea edi, $2
   __asm mov res, edi
-// CHECK: mov dword ptr $0, edi
+// CHECK: mov $0, edi
   return res;
 // CHECK: "=*m,={eax},*m,~{edi},~{dirflag},~{fpsr},~{flags}"(i32** %{{.*}}, [2 x i32]* @{{.*}})
 }
@@ -362,7 +399,7 @@ void t32() {
 // CHECK: t32
   int i;
   __asm mov eax, i
-// CHECK: mov eax, dword ptr $0
+// CHECK: mov eax, $0
   __asm mov eax, dword ptr i
 // CHECK: mov eax, dword ptr $1
   __asm mov ax, word ptr i
@@ -376,7 +413,7 @@ void t33() {
 // CHECK: t33
   int i;
   __asm mov eax, [i]
-// CHECK: mov eax, dword ptr $0
+// CHECK: mov eax, $0
   __asm mov eax, dword ptr [i]
 // CHECK: mov eax, dword ptr $1
   __asm mov ax, word ptr [i]
@@ -409,31 +446,31 @@ void t36() {
   int arr[4];
   // Work around PR20368: These should be single line blocks
   __asm { mov eax, 4[arr] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 4[arr + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 8[arr + 4 + 32*2 - 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$72$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$72$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 12[4 + arr] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$16$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$16$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 4[4 + arr + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$12$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$12$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 4[64 + arr + (2*32)] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$132$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$132$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 4[64 + arr - 2*32] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, [arr + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, [arr + 4 + 32*2 - 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$64$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$64$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, [4 + arr] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, [4 + arr + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, [64 + arr + (2*32)] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$128$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$128$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, [64 + arr - 2*32] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
 }
 
 void t37() {
@@ -464,21 +501,21 @@ void t38() {
   int arr[4];
   // Work around PR20368: These should be single line blocks
   __asm { mov eax, 4+4[arr] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, (4+4)[arr + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$12$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$12$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 8*2[arr + 4 + 32*2 - 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$80$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$80$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 12+20[4 + arr] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$36$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$36$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 4*16+4[4 + arr + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$76$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$76$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 4*4[64 + arr + (2*32)] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$144$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$144$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 4*(4-2)[64 + arr - 2*32] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 32*(4-2)[arr - 2*32] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$0$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$0$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
 }
 
 void cpuid() {
@@ -554,7 +591,7 @@ void t42() {
 // CHECK-LABEL: define void @t42
   int flags;
   __asm mov flags, eax
-// CHECK: mov dword ptr $0, eax
+// CHECK: mov $0, eax
 // CHECK: "=*m,~{dirflag},~{fpsr},~{flags}"(i32* %flags)
 }
 
@@ -563,31 +600,31 @@ void t43() {
   C strct;
 // Work around PR20368: These should be single line blocks
  __asm { mov eax, 4[strct.c1] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, 4[strct.c3 + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, 8[strct.c2.a + 4 + 32*2 - 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$72$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$72$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, 12[4 + strct.c2.b] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$16$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$16$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, 4[4 + strct.c4.b2.b + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$12$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$12$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, 4[64 + strct.c1 + (2*32)] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$132$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$132$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, 4[64 + strct.c2.a - 2*32] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, [strct.c4.b1 + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, [strct.c4.b2.a + 4 + 32*2 - 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$64$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$64$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, [4 + strct.c1] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, [4 + strct.c2.b + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, [64 + strct.c3 + (2*32)] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $$128$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$128$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
   __asm { mov eax, [64 + strct.c4.b2.b - 2*32] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
 }
 
 void call_clobber() {
@@ -662,7 +699,7 @@ void mxcsr() {
   __asm fxrstor buf
 }
 // CHECK-LABEL: define void @mxcsr
-// CHECK: call void asm sideeffect inteldialect "fxrstor byte ptr $0", "=*m,~{dirflag},~{fpsr},~{flags}"
+// CHECK: call void asm sideeffect inteldialect "fxrstor $0", "=*m,~{dirflag},~{fpsr},~{flags}"
 
 typedef union _LARGE_INTEGER {
   struct {
@@ -680,7 +717,7 @@ int test_indirect_field(LARGE_INTEGER LargeInteger) {
     __asm mov     eax, LargeInteger.LowPart
 }
 // CHECK-LABEL: define i32 @test_indirect_field(
-// CHECK: call i32 asm sideeffect inteldialect "mov eax, dword ptr $1",
+// CHECK: call i32 asm sideeffect inteldialect "mov eax, $1",
 
 // MS ASM containing labels must not be duplicated (PR23715).
 // CHECK: attributes [[ATTR1]] = {
diff --git a/test/CodeGen/ms-inline-asm.cpp b/test/CodeGen/ms-inline-asm.cpp
index 424c1992cc2c..a435e4b826d8 100644
--- a/test/CodeGen/ms-inline-asm.cpp
+++ b/test/CodeGen/ms-inline-asm.cpp
@@ -14,15 +14,21 @@ struct Foo {
 };
 
 void t1() {
+// CHECK-LABEL: define void @_Z2t1v()
   Foo::ptr = (int *)0xDEADBEEF;
   Foo::Bar::ptr = (int *)0xDEADBEEF;
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: mov eax, $0
+// CHECK-SAME: mov eax, $1
+// CHECK-SAME: mov eax, $2
+// CHECK-SAME: mov eax, dword ptr $3
+// CHECK-SAME: mov eax, dword ptr $4
+// CHECK-SAME: "*m,*m,*m,*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3Bar3ptrE, i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3ptrE)
   __asm mov eax, Foo ::ptr
   __asm mov eax, Foo :: Bar :: ptr
   __asm mov eax, [Foo:: ptr]
   __asm mov eax, dword ptr [Foo :: ptr]
   __asm mov eax, dword ptr [Foo :: ptr]
-// CHECK: @_Z2t1v
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $0\0A\09mov eax, dword ptr $1\0A\09mov eax, dword ptr $2\0A\09mov eax, dword ptr $3\0A\09mov eax, dword ptr $4", "*m,*m,*m,*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3Bar3ptrE, i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3ptrE)
 }
 
 int gvar = 10;
@@ -30,8 +36,11 @@ void t2() {
   int lvar = 10;
   __asm mov eax, offset Foo::ptr
   __asm mov eax, offset Foo::Bar::ptr
-// CHECK: t2
-// CHECK: call void asm sideeffect inteldialect "mov eax, $0\0A\09mov eax, $1", "r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3Bar3ptrE)
+// CHECK-LABEL: define void @_Z2t2v()
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: mov eax, $0
+// CHECK-SAME: mov eax, $1
+// CHECK-SAME: "r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3Bar3ptrE)
 }
 
 // CHECK-LABEL: define void @_Z2t3v()
@@ -50,7 +59,20 @@ void t3() {
   __asm mov eax, SIZE Foo::Bar::ptr
   __asm mov eax, SIZE Foo::arr
   __asm mov eax, SIZE Foo::Bar::arr
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$1\0A\09mov eax, $$1\0A\09mov eax, $$4\0A\09mov eax, $$2\0A\09mov eax, $$4\0A\09mov eax, $$4\0A\09mov eax, $$4\0A\09mov eax, $$1\0A\09mov eax, $$4\0A\09mov eax, $$4\0A\09mov eax, $$16\0A\09mov eax, $$2", "~{eax},~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: mov eax, $$1
+// CHECK-SAME: mov eax, $$1
+// CHECK-SAME: mov eax, $$4
+// CHECK-SAME: mov eax, $$2
+// CHECK-SAME: mov eax, $$4
+// CHECK-SAME: mov eax, $$4
+// CHECK-SAME: mov eax, $$4
+// CHECK-SAME: mov eax, $$1
+// CHECK-SAME: mov eax, $$4
+// CHECK-SAME: mov eax, $$4
+// CHECK-SAME: mov eax, $$16
+// CHECK-SAME: mov eax, $$2
+// CHECK-SAME: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 
 }
 
@@ -67,7 +89,10 @@ void T4::test() {
 // CHECK: [[X:%.*]] = getelementptr inbounds [[T4]], [[T4]]* [[THIS]], i32 0, i32 0
   __asm mov eax, x;
   __asm mov y, eax;
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $1\0A\09mov dword ptr $0, eax", "=*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* @_ZN2T41yE, i32* {{.*}})
+// CHECK: call void asm sideeffect inteldialect
+// CHECK-SAME: mov eax, $1
+// CHECK-SAME: mov $0, eax
+// CHECK-SAME: "=*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* @_ZN2T41yE, i32* {{.*}})
 }
 
 template <class T> struct T5 {
@@ -82,7 +107,11 @@ void test5() {
   __asm push y
   __asm call T5<int>::create<float>
   __asm mov x, eax
-  // CHECK: call void asm sideeffect inteldialect "push dword ptr $0\0A\09call dword ptr $2\0A\09mov dword ptr $1, eax", "=*m,=*m,*m,~{esp},~{dirflag},~{fpsr},~{flags}"(i32* %y, i32* %x, i32 (float)* @_ZN2T5IiE6createIfEEiT_)
+  // CHECK: call void asm sideeffect inteldialect
+  // CHECK-SAME: push $0
+  // CHECK-SAME: call dword ptr $2
+  // CHECK-SAME: mov $1, eax
+  // CHECK-SAME: "=*m,=*m,*m,~{esp},~{dirflag},~{fpsr},~{flags}"(i32* %y, i32* %x, i32 (float)* @_ZN2T5IiE6createIfEEiT_)
 }
 
 // Just verify this doesn't emit an error.
@@ -100,7 +129,9 @@ void t7_struct() {
   };
   __asm mov eax, [eax].A.b
   // CHECK-LABEL: define void @_Z9t7_structv
-  // CHECK: call void asm sideeffect inteldialect "mov eax, [eax].4", "~{eax},~{dirflag},~{fpsr},~{flags}"()
+  // CHECK: call void asm sideeffect inteldialect
+  // CHECK-SAME: mov eax, [eax].4
+  // CHECK-SAME: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t7_typedef() {
@@ -110,7 +141,9 @@ void t7_typedef() {
   } A;
   __asm mov eax, [eax].A.b
   // CHECK-LABEL: define void @_Z10t7_typedefv
-  // CHECK: call void asm sideeffect inteldialect "mov eax, [eax].4", "~{eax},~{dirflag},~{fpsr},~{flags}"()
+  // CHECK: call void asm sideeffect inteldialect
+  // CHECK-SAME: mov eax, [eax].4
+  // CHECK-SAME: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t7_using() {
@@ -120,20 +153,28 @@ void t7_using() {
   };
   __asm mov eax, [eax].A.b
   // CHECK-LABEL: define void @_Z8t7_usingv
-  // CHECK: call void asm sideeffect inteldialect "mov eax, [eax].4", "~{eax},~{dirflag},~{fpsr},~{flags}"()
+  // CHECK: call void asm sideeffect inteldialect
+  // CHECK-SAME: mov eax, [eax].4
+  // CHECK-SAME: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t8() {
   __asm some_label:
   // CHECK-LABEL: define void @_Z2t8v()
-  // CHECK: call void asm sideeffect inteldialect "L__MSASMLABEL_.${:uid}__some_label:", "~{dirflag},~{fpsr},~{flags}"()
+  // CHECK: call void asm sideeffect inteldialect
+  // CHECK-SAME: L__MSASMLABEL_.${:uid}__some_label:
+  // CHECK-SAME: "~{dirflag},~{fpsr},~{flags}"()
   struct A {
     static void g() {
       __asm jmp some_label ; This should jump forwards
       __asm some_label:
       __asm nop
       // CHECK-LABEL: define internal void @_ZZ2t8vEN1A1gEv()
-      // CHECK: call void asm sideeffect inteldialect "jmp L__MSASMLABEL_.${:uid}__some_label\0A\09L__MSASMLABEL_.${:uid}__some_label:\0A\09nop", "~{dirflag},~{fpsr},~{flags}"()
+      // CHECK: call void asm sideeffect inteldialect
+      // CHECK-SAME: jmp L__MSASMLABEL_.${:uid}__some_label
+      // CHECK-SAME: L__MSASMLABEL_.${:uid}__some_label:
+      // CHECK-SAME: nop
+      // CHECK-SAME: "~{dirflag},~{fpsr},~{flags}"()
     }
   };
   A::g();
diff --git a/test/CodeGen/thinlto_backend.ll b/test/CodeGen/thinlto_backend.ll
index ac0b3b76ef7d..813bb62c1a29 100644
--- a/test/CodeGen/thinlto_backend.ll
+++ b/test/CodeGen/thinlto_backend.ll
@@ -35,8 +35,12 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 declare void @f2()
+declare i8* @f3()
 
 define void @f1() {
   call void @f2()
+  ; Make sure that the backend can handle undefined references.
+  ; Do an indirect call so that the undefined ref shows up in the combined index.
+  call void bitcast (i8*()* @f3 to void()*)()
   ret void
 }