diff options
| author | Roman Divacky <rdivacky@FreeBSD.org> | 2009-12-01 11:07:05 +0000 |
|---|---|---|
| committer | Roman Divacky <rdivacky@FreeBSD.org> | 2009-12-01 11:07:05 +0000 |
| commit | 06f9d4012fb8acea3e9861d5722b5965dbb724d9 (patch) | |
| tree | ffe0478472eaa0686f11cb02c6df7d257b8719b0 /test/CodeGen | |
| parent | 76e2e0ebfdd3d91b07a75822865ea3e9121a99ce (diff) | |
Notes
Diffstat (limited to 'test/CodeGen')
68 files changed, 1108 insertions, 292 deletions
diff --git a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll index dd2845fe6aa5..7aae3acd76e6 100644 --- a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll +++ b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll @@ -13,7 +13,7 @@ entry: %4 = fadd float 0.000000e+00, %3 ; <float> [#uses=1] %5 = fsub float 1.000000e+00, %4 ; <float> [#uses=1] ; CHECK: foo: -; CHECK: fconsts s{{[0-9]+}}, #112 +; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00 %6 = fsub float 1.000000e+00, undef ; <float> [#uses=2] %7 = fsub float %2, undef ; <float> [#uses=1] %8 = fsub float 0.000000e+00, undef ; <float> [#uses=3] diff --git a/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll b/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll new file mode 100644 index 000000000000..efe74cfd1387 --- /dev/null +++ b/test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll @@ -0,0 +1,41 @@ +; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s +; PR5614 + +%"als" = type { i32 (...)** } +%"av" = type { %"als" } +%"c" = type { %"lsm", %"Vec3", %"av"*, float, i8, float, %"lsm", i8, %"Vec3", %"Vec3", %"Vec3", float, float, float, %"Vec3", %"Vec3" } +%"lsm" = type { %"als", %"Vec3", %"Vec3", %"Vec3", %"Vec3" } +%"Vec3" = type { float, float, float } + +define arm_aapcs_vfpcc void @foo(%"c"* %this, %"Vec3"* nocapture %adjustment) { +entry: + switch i32 undef, label %return [ + i32 1, label %bb + i32 2, label %bb72 + i32 3, label %bb31 + i32 4, label %bb79 + i32 5, label %bb104 + ] + +bb: ; preds = %entry + ret void + +bb31: ; preds = %entry + %0 = call arm_aapcs_vfpcc %"Vec3" undef(%"lsm"* undef) ; <%"Vec3"> [#uses=1] + %mrv_gr69 = extractvalue %"Vec3" %0, 1 ; <float> [#uses=1] + %1 = fsub float %mrv_gr69, undef ; <float> [#uses=1] + store float %1, float* undef, align 4 + ret void + +bb72: ; preds = %entry + ret void + +bb79: ; preds = %entry + ret void + +bb104: ; preds = %entry + ret void + +return: ; preds = %entry + ret void +} diff --git a/test/CodeGen/ARM/bic.ll b/test/CodeGen/ARM/bic.ll index b16dcc6755b1..1dfd6278287d 100644 --- a/test/CodeGen/ARM/bic.ll +++ b/test/CodeGen/ARM/bic.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | grep {bic\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*} | count 2 +; RUN: llc < %s -march=arm | FileCheck %s define i32 @f1(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 @@ -6,8 +6,12 @@ define i32 @f1(i32 %a, i32 %b) { ret i32 %tmp1 } +; CHECK: bic r0, r0, r1 + define i32 @f2(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 %tmp1 = and i32 %tmp, %a ret i32 %tmp1 } + +; CHECK: bic r0, r0, r1 diff --git a/test/CodeGen/ARM/fabss.ll b/test/CodeGen/ARM/fabss.ll index 46f136ba1fef..e5b5791b3cda 100644 --- a/test/CodeGen/ARM/fabss.ll +++ b/test/CodeGen/ARM/fabss.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vabs.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vabs.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vabs.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vabs.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vabs.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: @@ -13,3 +13,16 @@ entry: } declare float @fabsf(float) + +; VFP2: test: +; VFP2: vabs.f32 s1, s1 + +; NFP1: test: +; NFP1: vabs.f32 d1, d1 +; NFP0: test: +; NFP0: vabs.f32 s1, s1 + +; CORTEXA8: test: +; CORTEXA8: vabs.f32 d1, d1 +; CORTEXA9: test: +; CORTEXA9: vabs.f32 s1, s1 diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll index 1426a2dc883a..db18a86eccd8 100644 --- a/test/CodeGen/ARM/fadds.ll +++ b/test/CodeGen/ARM/fadds.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vadd.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vadd.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vadd.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vadd.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vadd.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: @@ -10,3 +10,15 @@ entry: ret float %0 } +; VFP2: test: +; VFP2: vadd.f32 s0, s1, s0 + +; NFP1: test: +; NFP1: vadd.f32 d0, d1, d0 +; NFP0: test: +; NFP0: vadd.f32 s0, s1, s0 + +; CORTEXA8: test: +; CORTEXA8: vadd.f32 d0, d1, d0 +; CORTEXA9: test: +; CORTEXA9: vadd.f32 s0, s1, s0 diff --git a/test/CodeGen/ARM/fdivs.ll b/test/CodeGen/ARM/fdivs.ll index 45803f6d3c32..a5c86bf26343 100644 --- a/test/CodeGen/ARM/fdivs.ll +++ b/test/CodeGen/ARM/fdivs.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vdiv.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vdiv.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vdiv.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vdiv.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vdiv.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: @@ -10,3 +10,15 @@ entry: ret float %0 } +; VFP2: test: +; VFP2: vdiv.f32 s0, s1, s0 + +; NFP1: test: +; NFP1: vdiv.f32 s0, s1, s0 +; NFP0: test: +; NFP0: vdiv.f32 s0, s1, s0 + +; CORTEXA8: test: +; CORTEXA8: vdiv.f32 s0, s1, s0 +; CORTEXA9: test: +; CORTEXA9: vdiv.f32 s0, s1, s0 diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll index 57efa8264041..904a58739370 100644 --- a/test/CodeGen/ARM/fmacs.ll +++ b/test/CodeGen/ARM/fmacs.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vmla.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vmla.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vmla.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %acc, float %a, float %b) { entry: @@ -11,3 +11,15 @@ entry: ret float %1 } +; VFP2: test: +; VFP2: vmla.f32 s2, s1, s0 + +; NFP1: test: +; NFP1: vmul.f32 d0, d1, d0 +; NFP0: test: +; NFP0: vmla.f32 s2, s1, s0 + +; CORTEXA8: test: +; CORTEXA8: vmul.f32 d0, d1, d0 +; CORTEXA9: test: +; CORTEXA9: vmla.f32 s2, s1, s0 diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll index 31b5c52d38d8..7b9e029b676e 100644 --- a/test/CodeGen/ARM/fmscs.ll +++ b/test/CodeGen/ARM/fmscs.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vnmls.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vnmls.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vnmls.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vnmls.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vnmls.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %acc, float %a, float %b) { entry: @@ -11,3 +11,15 @@ entry: ret float %1 } +; VFP2: test: +; VFP2: vnmls.f32 s2, s1, s0 + +; NFP1: test: +; NFP1: vnmls.f32 s2, s1, s0 +; NFP0: test: +; NFP0: vnmls.f32 s2, s1, s0 + +; CORTEXA8: test: +; CORTEXA8: vnmls.f32 s2, s1, s0 +; CORTEXA9: test: +; CORTEXA9: vnmls.f32 s2, s1, s0 diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll index 735263c9a310..d3c9c82e9745 100644 --- a/test/CodeGen/ARM/fmuls.ll +++ b/test/CodeGen/ARM/fmuls.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vmul.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vmul.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vmul.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test(float %a, float %b) { entry: @@ -10,3 +10,15 @@ entry: ret float %0 } +; VFP2: test: +; VFP2: vmul.f32 s0, s1, s0 + +; NFP1: test: +; NFP1: vmul.f32 d0, d1, d0 +; NFP0: test: +; NFP0: vmul.f32 s0, s1, s0 + +; CORTEXA8: test: +; CORTEXA8: vmul.f32 d0, d1, d0 +; CORTEXA9: test: +; CORTEXA9: vmul.f32 s0, s1, s0 diff --git a/test/CodeGen/ARM/fnegs.ll b/test/CodeGen/ARM/fnegs.ll index bc3d42de75ca..d6c22f14a4ca 100644 --- a/test/CodeGen/ARM/fnegs.ll +++ b/test/CodeGen/ARM/fnegs.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vneg.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vneg.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 2 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vneg.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2 -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vneg.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 2 -; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {vneg.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 2 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9 define float @test1(float* %a) { entry: @@ -13,6 +13,20 @@ entry: %retval = select i1 %3, float %1, float %0 ; <float> [#uses=1] ret float %retval } +; VFP2: test1: +; VFP2: vneg.f32 s1, s0 + +; NFP1: test1: +; NFP1: vneg.f32 d1, d0 + +; NFP0: test1: +; NFP0: vneg.f32 s1, s0 + +; CORTEXA8: test1: +; CORTEXA8: vneg.f32 d1, d0 + +; CORTEXA9: test1: +; CORTEXA9: vneg.f32 s1, s0 define float @test2(float* %a) { entry: @@ -23,3 +37,18 @@ entry: %retval = select i1 %3, float %1, float %0 ; <float> [#uses=1] ret float %retval } +; VFP2: test2: +; VFP2: vneg.f32 s1, s0 + +; NFP1: test2: +; NFP1: vneg.f32 d1, d0 + +; NFP0: test2: +; NFP0: vneg.f32 s1, s0 + +; CORTEXA8: test2: +; CORTEXA8: vneg.f32 d1, d0 + +; CORTEXA9: test2: +; CORTEXA9: vneg.f32 s1, s0 + diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll index 4de18bc3b456..710994d8d736 100644 --- a/test/CodeGen/ARM/fpconsts.ll +++ b/test/CodeGen/ARM/fpconsts.ll @@ -3,7 +3,7 @@ define arm_apcscc float @t1(float %x) nounwind readnone optsize { entry: ; CHECK: t1: -; CHECK: fconsts s1, #16 +; CHECK: vmov.f32 s1, #4.000000e+00 %0 = fadd float %x, 4.000000e+00 ret float %0 } @@ -11,7 +11,7 @@ entry: define arm_apcscc double @t2(double %x) nounwind readnone optsize { entry: ; CHECK: t2: -; CHECK: fconstd d1, #8 +; CHECK: vmov.f64 d1, #3.000000e+00 %0 = fadd double %x, 3.000000e+00 ret double %0 } @@ -19,7 +19,7 @@ entry: define arm_apcscc double @t3(double %x) nounwind readnone optsize { entry: ; CHECK: t3: -; CHECK: fconstd d1, #170 +; CHECK: vmov.f64 d1, #-1.300000e+01 %0 = fmul double %x, -1.300000e+01 ret double %0 } @@ -27,7 +27,7 @@ entry: define arm_apcscc float @t4(float %x) nounwind readnone optsize { entry: ; CHECK: t4: -; CHECK: fconsts s1, #184 +; CHECK: vmov.f32 s1, #-2.400000e+01 %0 = fmul float %x, -2.400000e+01 ret float %0 } diff --git a/test/CodeGen/ARM/fptoint.ll b/test/CodeGen/ARM/fptoint.ll index 4cacc5de7eec..299cb8f81503 100644 --- a/test/CodeGen/ARM/fptoint.ll +++ b/test/CodeGen/ARM/fptoint.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep -E {vmov\\W*r\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | not grep fmrrd +; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s @i = weak global i32 0 ; <i32*> [#uses=2] @u = weak global i32 0 ; <i32*> [#uses=2] @@ -45,3 +44,6 @@ define void @foo9(double %x) { store i16 %tmp, i16* null ret void } +; CHECK: foo9: +; CHECK: vmov r0, s0 + diff --git a/test/CodeGen/ARM/fsubs.ll b/test/CodeGen/ARM/fsubs.ll index f84ccdd480b2..ae98be307892 100644 --- a/test/CodeGen/ARM/fsubs.ll +++ b/test/CodeGen/ARM/fsubs.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vsub.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vsub.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1 -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vsub.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1 +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1 +; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0 define float @test(float %a, float %b) { entry: @@ -8,3 +8,6 @@ entry: ret float %0 } +; VFP2: vsub.f32 s0, s1, s0 +; NFP1: vsub.f32 d0, d1, d0 +; NFP0: vsub.f32 s0, s1, s0 diff --git a/test/CodeGen/ARM/load-global.ll b/test/CodeGen/ARM/load-global.ll deleted file mode 100644 index 56a4a477f510..000000000000 --- a/test/CodeGen/ARM/load-global.ll +++ /dev/null @@ -1,15 +0,0 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | \ -; RUN: not grep {L_G\$non_lazy_ptr} -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | \ -; RUN: grep {L_G\$non_lazy_ptr} | count 2 -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | \ -; RUN: grep {ldr.*pc} | count 1 -; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | \ -; RUN: grep {GOT} | count 1 - -@G = external global i32 - -define i32 @test1() { - %tmp = load i32* @G - ret i32 %tmp -} diff --git a/test/CodeGen/ARM/mls.ll b/test/CodeGen/ARM/mls.ll index 85407fa254b0..a6cdba445451 100644 --- a/test/CodeGen/ARM/mls.ll +++ b/test/CodeGen/ARM/mls.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v6t2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 +; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s define i32 @f1(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b @@ -12,3 +12,5 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) { %tmp2 = sub i32 %tmp1, %c ret i32 %tmp2 } + +; CHECK: mls r0, r0, r1, r2 diff --git a/test/CodeGen/ARM/movt-movw-global.ll b/test/CodeGen/ARM/movt-movw-global.ll new file mode 100644 index 000000000000..886ff3fea7a8 --- /dev/null +++ b/test/CodeGen/ARM/movt-movw-global.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "armv7-eabi" + +@foo = common global i32 0 ; <i32*> [#uses=1] + +define arm_aapcs_vfpcc i32* @bar1() nounwind readnone { +entry: +; CHECK: movw r0, :lower16:foo +; CHECK-NEXT: movt r0, :upper16:foo + ret i32* @foo +} + +define arm_aapcs_vfpcc void @bar2(i32 %baz) nounwind { +entry: +; CHECK: movw r1, :lower16:foo +; CHECK-NEXT: movt r1, :upper16:foo + store i32 %baz, i32* @foo, align 4 + ret void +} diff --git a/test/CodeGen/ARM/remat-2.ll b/test/CodeGen/ARM/remat-2.ll new file mode 100644 index 000000000000..1a871d258e30 --- /dev/null +++ b/test/CodeGen/ARM/remat-2.ll @@ -0,0 +1,65 @@ +; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -stats -info-output-file - | grep "Number of re-materialization" + +define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +entry: + br i1 undef, label %smvp.exit, label %bb.i3 + +bb.i3: ; preds = %bb.i3, %bb134 + br i1 undef, label %smvp.exit, label %bb.i3 + +smvp.exit: ; preds = %bb.i3 + %0 = fmul double undef, 2.400000e-03 ; <double> [#uses=2] + br i1 undef, label %bb138.preheader, label %bb159 + +bb138.preheader: ; preds = %smvp.exit + br label %bb138 + +bb138: ; preds = %bb138, %bb138.preheader + br i1 undef, label %bb138, label %bb145.loopexit + +bb142: ; preds = %bb.nph218.bb.nph218.split_crit_edge, %phi0.exit + %1 = fmul double undef, -1.200000e-03 ; <double> [#uses=1] + %2 = fadd double undef, %1 ; <double> [#uses=1] + %3 = fmul double %2, undef ; <double> [#uses=1] + %4 = fsub double 0.000000e+00, %3 ; <double> [#uses=1] + br i1 %14, label %phi1.exit, label %bb.i35 + +bb.i35: ; preds = %bb142 + %5 = call arm_apcscc double @sin(double %15) nounwind readonly ; <double> [#uses=1] + %6 = fmul double %5, 0x4031740AFA84AD8A ; <double> [#uses=1] + %7 = fsub double 1.000000e+00, undef ; <double> [#uses=1] + %8 = fdiv double %7, 6.000000e-01 ; <double> [#uses=1] + br label %phi1.exit + +phi1.exit: ; preds = %bb.i35, %bb142 + %.pn = phi double [ %6, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; <double> [#uses=0] + %9 = phi double [ %8, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; <double> [#uses=1] + %10 = fmul double undef, %9 ; <double> [#uses=0] + br i1 %14, label %phi0.exit, label %bb.i + +bb.i: ; preds = %phi1.exit + unreachable + +phi0.exit: ; preds = %phi1.exit + %11 = fsub double %4, undef ; <double> [#uses=1] + %12 = fadd double 0.000000e+00, %11 ; <double> [#uses=1] + store double %12, double* undef, align 4 + br label %bb142 + +bb145.loopexit: ; preds = %bb138 + br i1 undef, label %bb.nph218.bb.nph218.split_crit_edge, label %bb159 + +bb.nph218.bb.nph218.split_crit_edge: ; preds = %bb145.loopexit + %13 = fmul double %0, 0x401921FB54442D18 ; <double> [#uses=1] + %14 = fcmp ugt double %0, 6.000000e-01 ; <i1> [#uses=2] + %15 = fdiv double %13, 6.000000e-01 ; <double> [#uses=1] + br label %bb142 + +bb159: ; preds = %bb145.loopexit, %smvp.exit, %bb134 + unreachable + +bb166: ; preds = %bb127 + unreachable +} + +declare arm_apcscc double @sin(double) nounwind readonly diff --git a/test/CodeGen/ARM/remat.ll b/test/CodeGen/ARM/remat.ll index 50da997ed468..9565c8bca6b0 100644 --- a/test/CodeGen/ARM/remat.ll +++ b/test/CodeGen/ARM/remat.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 5 +; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 3 %struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } %struct.LOCBOX = type { i32, i32, i32, i32 } diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll new file mode 100644 index 000000000000..07edc91519df --- /dev/null +++ b/test/CodeGen/ARM/select-imm.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2 + +define arm_apcscc i32 @t1(i32 %c) nounwind readnone { +entry: +; ARM: t1: +; ARM: mov r1, #101 +; ARM: orr r1, r1, #1, 24 +; ARM: movgt r0, #123 + +; T2: t1: +; T2: movw r0, #357 +; T2: movgt r0, #123 + + %0 = icmp sgt i32 %c, 1 + %1 = select i1 %0, i32 123, i32 357 + ret i32 %1 +} + +define arm_apcscc i32 @t2(i32 %c) nounwind readnone { +entry: +; ARM: t2: +; ARM: mov r1, #101 +; ARM: orr r1, r1, #1, 24 +; ARM: movle r0, #123 + +; T2: t2: +; T2: movw r0, #357 +; T2: movle r0, #123 + + %0 = icmp sgt i32 %c, 1 + %1 = select i1 %0, i32 357, i32 123 + ret i32 %1 +} + +define arm_apcscc i32 @t3(i32 %a) nounwind readnone { +entry: +; ARM: t3: +; ARM: mov r0, #0 +; ARM: moveq r0, #1 + +; T2: t3: +; T2: mov r0, #0 +; T2: moveq r0, #1 + %0 = icmp eq i32 %a, 160 + %1 = zext i1 %0 to i32 + ret i32 %1 +} diff --git a/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll b/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll index 33a36452b2e5..1519fe665cae 100644 --- a/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll +++ b/test/CodeGen/Generic/2007-06-06-CriticalEdgeLandingPad.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 -enable-eh -asm-verbose -o - | \ -; RUN: grep -A 3 {Llabel138.*Region start} | grep {3.*Action} +; RUN: llc < %s -march=x86 -enable-eh -asm-verbose -o - | FileCheck %s ; PR1422 ; PR1508 @@ -2864,3 +2863,8 @@ declare void @system__img_enum__image_enumeration_8(%struct.string___XUP* sret , declare i32 @memcmp(i8*, i8*, i32, ...) declare void @report__result() + +; CHECK: {{Llabel138.*Region start}} +; CHECK-NEXT: Region length +; CHECK-NEXT: Landing pad +; CHECK-NEXT: {{3.*Action}} diff --git a/test/CodeGen/MSP430/2009-11-20-NewNode.ll b/test/CodeGen/MSP430/2009-11-20-NewNode.ll new file mode 100644 index 000000000000..887c7d6fa24e --- /dev/null +++ b/test/CodeGen/MSP430/2009-11-20-NewNode.ll @@ -0,0 +1,36 @@ +; RUN: llc -march=msp430 < %s +; PR5558 + +define i64 @_strtoll_r(i16 %base) nounwind { +entry: + br i1 undef, label %if.then, label %if.end27 + +if.then: ; preds = %do.end + br label %if.end27 + +if.end27: ; preds = %if.then, %do.end + %cond66 = select i1 undef, i64 -9223372036854775808, i64 9223372036854775807 ; <i64> [#uses=3] + %conv69 = sext i16 %base to i64 ; <i64> [#uses=1] + %div = udiv i64 %cond66, %conv69 ; <i64> [#uses=1] + br label %for.cond + +for.cond: ; preds = %if.end116, %if.end27 + br i1 undef, label %if.then152, label %if.then93 + +if.then93: ; preds = %for.cond + br i1 undef, label %if.end116, label %if.then152 + +if.end116: ; preds = %if.then93 + %cmp123 = icmp ugt i64 undef, %div ; <i1> [#uses=1] + %or.cond = or i1 undef, %cmp123 ; <i1> [#uses=0] + br label %for.cond + +if.then152: ; preds = %if.then93, %for.cond + br i1 undef, label %if.end182, label %if.then172 + +if.then172: ; preds = %if.then152 + ret i64 %cond66 + +if.end182: ; preds = %if.then152 + ret i64 %cond66 +} diff --git a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll index f59639f66adf..636b318014a5 100644 --- a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll +++ b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll @@ -4,7 +4,7 @@ target triple = "mips-unknown-linux" define float @h() nounwind readnone { entry: -; CHECK: lui $2, %hi($CPI1_0) +; CHECK: lw $2, %got($CPI1_0)($gp) ; CHECK: lwc1 $f0, %lo($CPI1_0)($2) ret float 0x400B333340000000 } diff --git a/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll b/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll index d7072dd9b5d7..b508026c21f6 100644 --- a/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll +++ b/test/CodeGen/PIC16/2009-07-17-PR4566-pic16.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=pic16 | grep {movf \\+@i + 0, \\+W} +; RUN: llc < %s -march=pic16 | FileCheck %s target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-f32:32:32" target triple = "pic16-" @@ -27,3 +27,5 @@ entry: store i8 %conv8, i8* %tmp9 ret void } + +; CHECK: movf @i + 0, W diff --git a/test/CodeGen/PIC16/2009-11-20-NewNode.ll b/test/CodeGen/PIC16/2009-11-20-NewNode.ll new file mode 100644 index 000000000000..d68f0f41c4a5 --- /dev/null +++ b/test/CodeGen/PIC16/2009-11-20-NewNode.ll @@ -0,0 +1,36 @@ +; RUN: llc -march=pic16 < %s +; PR5558 + +define i64 @_strtoll_r(i16 %base) nounwind { +entry: + br i1 undef, label %if.then, label %if.end27 + +if.then: ; preds = %do.end + br label %if.end27 + +if.end27: ; preds = %if.then, %do.end + %cond66 = select i1 undef, i64 -9223372036854775808, i64 9223372036854775807 ; <i64> [#uses=3] + %conv69 = sext i16 %base to i64 ; <i64> [#uses=1] + %div = udiv i64 %cond66, %conv69 ; <i64> [#uses=1] + br label %for.cond + +for.cond: ; preds = %if.end116, %if.end27 + br i1 undef, label %if.then152, label %if.then93 + +if.then93: ; preds = %for.cond + br i1 undef, label %if.end116, label %if.then152 + +if.end116: ; preds = %if.then93 + %cmp123 = icmp ugt i64 undef, %div ; <i1> [#uses=1] + %or.cond = or i1 undef, %cmp123 ; <i1> [#uses=0] + br label %for.cond + +if.then152: ; preds = %if.then93, %for.cond + br i1 undef, label %if.end182, label %if.then172 + +if.then172: ; preds = %if.then152 + ret i64 %cond66 + +if.end182: ; preds = %if.then152 + ret i64 %cond66 +} diff --git a/test/CodeGen/PowerPC/2009-11-25-ImpDefBug.ll b/test/CodeGen/PowerPC/2009-11-25-ImpDefBug.ll new file mode 100644 index 000000000000..9a22a6f76c24 --- /dev/null +++ b/test/CodeGen/PowerPC/2009-11-25-ImpDefBug.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -mtriple=powerpc-apple-darwin9.5 -mcpu=g5 +; rdar://7422268 + +%struct..0EdgeT = type { i32, i32, float, float, i32, i32, i32, float, i32, i32 } + +define void @smooth_color_z_triangle(i32 %v0, i32 %v1, i32 %v2, i32 %pv) nounwind { +entry: + br i1 undef, label %return, label %bb14 + +bb14: ; preds = %entry + br i1 undef, label %bb15, label %return + +bb15: ; preds = %bb14 + br i1 undef, label %bb16, label %bb17 + +bb16: ; preds = %bb15 + br label %bb17 + +bb17: ; preds = %bb16, %bb15 + %0 = fcmp olt float undef, 0.000000e+00 ; <i1> [#uses=2] + %eTop.eMaj = select i1 %0, %struct..0EdgeT* undef, %struct..0EdgeT* null ; <%struct..0EdgeT*> [#uses=1] + br label %bb69 + +bb24: ; preds = %bb69 + br i1 undef, label %bb25, label %bb28 + +bb25: ; preds = %bb24 + br label %bb33 + +bb28: ; preds = %bb24 + br i1 undef, label %return, label %bb32 + +bb32: ; preds = %bb28 + br i1 %0, label %bb38, label %bb33 + +bb33: ; preds = %bb32, %bb25 + br i1 undef, label %bb34, label %bb38 + +bb34: ; preds = %bb33 + br label %bb38 + +bb38: ; preds = %bb34, %bb33, %bb32 + %eRight.08 = phi %struct..0EdgeT* [ %eTop.eMaj, %bb32 ], [ undef, %bb34 ], [ undef, %bb33 ] ; <%struct..0EdgeT*> [#uses=0] + %fdgOuter.0 = phi i32 [ %fdgOuter.1, %bb32 ], [ undef, %bb34 ], [ %fdgOuter.1, %bb33 ] ; <i32> [#uses=1] + %fz.3 = phi i32 [ %fz.2, %bb32 ], [ 2147483647, %bb34 ], [ %fz.2, %bb33 ] ; <i32> [#uses=1] + %1 = add i32 undef, 1 ; <i32> [#uses=0] + br label %bb69 + +bb69: ; preds = %bb38, %bb17 + %fdgOuter.1 = phi i32 [ undef, %bb17 ], [ %fdgOuter.0, %bb38 ] ; <i32> [#uses=2] + %fz.2 = phi i32 [ undef, %bb17 ], [ %fz.3, %bb38 ] ; <i32> [#uses=2] + br i1 undef, label %bb24, label %return + +return: ; preds = %bb69, %bb28, %bb14, %entry + ret void +} diff --git a/test/CodeGen/PowerPC/Frames-alloca.ll b/test/CodeGen/PowerPC/Frames-alloca.ll index 25fc626550d2..aed4fdbb2dcc 100644 --- a/test/CodeGen/PowerPC/Frames-alloca.ll +++ b/test/CodeGen/PowerPC/Frames-alloca.ll @@ -6,23 +6,23 @@ ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP -; CHECK-PPC32: stw r31, 20(r1) +; CHECK-PPC32: stw r31, -4(r1) ; CHECK-PPC32: lwz r1, 0(r1) -; CHECK-PPC32: lwz r31, 20(r1) -; CHECK-PPC32-NOFP: stw r31, 20(r1) +; CHECK-PPC32: lwz r31, -4(r1) +; CHECK-PPC32-NOFP: stw r31, -4(r1) ; CHECK-PPC32-NOFP: lwz r1, 0(r1) -; CHECK-PPC32-NOFP: lwz r31, 20(r1) +; CHECK-PPC32-NOFP: lwz r31, -4(r1) ; CHECK-PPC32-RS: stwu r1, -80(r1) ; CHECK-PPC32-RS-NOFP: stwu r1, -80(r1) -; CHECK-PPC64: std r31, 40(r1) -; CHECK-PPC64: stdu r1, -112(r1) +; CHECK-PPC64: std r31, -8(r1) +; CHECK-PPC64: stdu r1, -128(r1) ; CHECK-PPC64: ld r1, 0(r1) -; CHECK-PPC64: ld r31, 40(r1) -; CHECK-PPC64-NOFP: std r31, 40(r1) -; CHECK-PPC64-NOFP: stdu r1, -112(r1) +; CHECK-PPC64: ld r31, -8(r1) +; CHECK-PPC64-NOFP: std r31, -8(r1) +; CHECK-PPC64-NOFP: stdu r1, -128(r1) ; CHECK-PPC64-NOFP: ld r1, 0(r1) -; CHECK-PPC64-NOFP: ld r31, 40(r1) +; CHECK-PPC64-NOFP: ld r31, -8(r1) define i32* @f1(i32 %n) { %tmp = alloca i32, i32 %n ; <i32*> [#uses=1] diff --git a/test/CodeGen/PowerPC/Frames-large.ll b/test/CodeGen/PowerPC/Frames-large.ll index fda2e4ff9ce9..302d3df28436 100644 --- a/test/CodeGen/PowerPC/Frames-large.ll +++ b/test/CodeGen/PowerPC/Frames-large.ll @@ -22,13 +22,13 @@ define i32* @f1() nounwind { ; PPC32-NOFP: blr ; PPC32-FP: _f1: -; PPC32-FP: stw r31, 20(r1) +; PPC32-FP: stw r31, -4(r1) ; PPC32-FP: lis r0, -1 ; PPC32-FP: ori r0, r0, 32704 ; PPC32-FP: stwux r1, r1, r0 ; ... ; PPC32-FP: lwz r1, 0(r1) -; PPC32-FP: lwz r31, 20(r1) +; PPC32-FP: lwz r31, -4(r1) ; PPC32-FP: blr @@ -42,11 +42,11 @@ define i32* @f1() nounwind { ; PPC64-FP: _f1: -; PPC64-FP: std r31, 40(r1) +; PPC64-FP: std r31, -8(r1) ; PPC64-FP: lis r0, -1 -; PPC64-FP: ori r0, r0, 32656 +; PPC64-FP: ori r0, r0, 32640 ; PPC64-FP: stdux r1, r1, r0 ; ... ; PPC64-FP: ld r1, 0(r1) -; PPC64-FP: ld r31, 40(r1) +; PPC64-FP: ld r31, -8(r1) ; PPC64-FP: blr diff --git a/test/CodeGen/PowerPC/Frames-small.ll b/test/CodeGen/PowerPC/Frames-small.ll index 6875704cf30d..404fdd01966c 100644 --- a/test/CodeGen/PowerPC/Frames-small.ll +++ b/test/CodeGen/PowerPC/Frames-small.ll @@ -1,26 +1,26 @@ ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1 -; RUN not grep {stw r31, 20(r1)} %t1 +; RUN not grep {stw r31, -4(r1)} %t1 ; RUN: grep {stwu r1, -16448(r1)} %t1 ; RUN: grep {addi r1, r1, 16448} %t1 ; RUN: llc < %s -march=ppc32 | \ -; RUN: not grep {lwz r31, 20(r1)} +; RUN: not grep {lwz r31, -4(r1)} ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ ; RUN: -o %t2 -; RUN: grep {stw r31, 20(r1)} %t2 +; RUN: grep {stw r31, -4(r1)} %t2 ; RUN: grep {stwu r1, -16448(r1)} %t2 ; RUN: grep {addi r1, r1, 16448} %t2 -; RUN: grep {lwz r31, 20(r1)} %t2 +; RUN: grep {lwz r31, -4(r1)} %t2 ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3 -; RUN: not grep {std r31, 40(r1)} %t3 +; RUN: not grep {std r31, -8(r1)} %t3 ; RUN: grep {stdu r1, -16496(r1)} %t3 ; RUN: grep {addi r1, r1, 16496} %t3 -; RUN: not grep {ld r31, 40(r1)} %t3 +; RUN: not grep {ld r31, -8(r1)} %t3 ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ ; RUN: -o %t4 -; RUN: grep {std r31, 40(r1)} %t4 -; RUN: grep {stdu r1, -16496(r1)} %t4 -; RUN: grep {addi r1, r1, 16496} %t4 -; RUN: grep {ld r31, 40(r1)} %t4 +; RUN: grep {std r31, -8(r1)} %t4 +; RUN: grep {stdu r1, -16512(r1)} %t4 +; RUN: grep {addi r1, r1, 16512} %t4 +; RUN: grep {ld r31, -8(r1)} %t4 define i32* @f1() { %tmp = alloca i32, i32 4095 ; <i32*> [#uses=1] diff --git a/test/CodeGen/PowerPC/bswap-load-store.ll b/test/CodeGen/PowerPC/bswap-load-store.ll index 7eb3bbb8d308..4f6bfc729913 100644 --- a/test/CodeGen/PowerPC/bswap-load-store.ll +++ b/test/CodeGen/PowerPC/bswap-load-store.ll @@ -1,11 +1,6 @@ -; RUN: llc < %s -march=ppc32 | \ -; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4 -; RUN: llc < %s -march=ppc32 | not grep rlwinm -; RUN: llc < %s -march=ppc32 | not grep rlwimi -; RUN: llc < %s -march=ppc64 | \ -; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4 -; RUN: llc < %s -march=ppc64 | not grep rlwinm -; RUN: llc < %s -march=ppc64 | not grep rlwimi +; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=X64 + define void @STWBRX(i32 %i, i8* %ptr, i32 %off) { %tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1] @@ -43,3 +38,14 @@ declare i32 @llvm.bswap.i32(i32) declare i16 @llvm.bswap.i16(i16) + +; X32: stwbrx +; X32: lwbrx +; X32: sthbrx +; X32: lhbrx + +; X64: stwbrx +; X64: lwbrx +; X64: sthbrx +; X64: lhbrx + diff --git a/test/CodeGen/PowerPC/ppc-prologue.ll b/test/CodeGen/PowerPC/ppc-prologue.ll index 581d010a901e..e49dcb82c60d 100644 --- a/test/CodeGen/PowerPC/ppc-prologue.ll +++ b/test/CodeGen/PowerPC/ppc-prologue.ll @@ -2,7 +2,7 @@ define i32 @_Z4funci(i32 %a) ssp { ; CHECK: mflr r0 -; CHECK-NEXT: stw r31, 20(r1) +; CHECK-NEXT: stw r31, -4(r1) ; CHECK-NEXT: stw r0, 8(r1) ; CHECK-NEXT: stwu r1, -80(r1) ; CHECK-NEXT: Llabel1: diff --git a/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll b/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll new file mode 100644 index 000000000000..7bce01c00afa --- /dev/null +++ b/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s +; Formerly dropped the RHS of %tmp6 when constructing rlwimi. +; 7346117 + +@foo = external global i32 + +define void @xxx(i32 %a, i32 %b, i32 %c, i32 %d) nounwind optsize { +; CHECK: _xxx: +; CHECK: or +; CHECK: and +; CHECK: rlwimi +entry: + %tmp0 = ashr i32 %d, 31 + %tmp1 = and i32 %tmp0, 255 + %tmp2 = xor i32 %tmp1, 255 + %tmp3 = ashr i32 %b, 31 + %tmp4 = ashr i32 %a, 4 + %tmp5 = or i32 %tmp3, %tmp4 + %tmp6 = and i32 %tmp2, %tmp5 + %tmp7 = shl i32 %c, 8 + %tmp8 = or i32 %tmp6, %tmp7 + store i32 %tmp8, i32* @foo, align 4 + br label %return + +return: + ret void +; CHECK: blr +}
\ No newline at end of file diff --git a/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll new file mode 100644 index 000000000000..015c08605fea --- /dev/null +++ b/test/CodeGen/PowerPC/vec_buildvector_loadstore.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mattr=+altivec | FileCheck %s +; Formerly this did byte loads and word stores. +@a = external global <16 x i8> +@b = external global <16 x i8> +@c = external global <16 x i8> + +define void @foo() nounwind ssp { +; CHECK: _foo: +; CHECK-NOT: stw +entry: + %tmp0 = load <16 x i8>* @a, align 16 + %tmp180.i = extractelement <16 x i8> %tmp0, i32 0 ; <i8> [#uses=1] + %tmp181.i = insertelement <16 x i8> <i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp180.i, i32 2 ; <<16 x i8>> [#uses=1] + %tmp182.i = extractelement <16 x i8> %tmp0, i32 1 ; <i8> [#uses=1] + %tmp183.i = insertelement <16 x i8> %tmp181.i, i8 %tmp182.i, i32 3 ; <<16 x i8>> [#uses=1] + %tmp184.i = insertelement <16 x i8> %tmp183.i, i8 0, i32 4 ; <<16 x i8>> [#uses=1] + %tmp185.i = insertelement <16 x i8> %tmp184.i, i8 0, i32 5 ; <<16 x i8>> [#uses=1] + %tmp186.i = extractelement <16 x i8> %tmp0, i32 4 ; <i8> [#uses=1] + %tmp187.i = insertelement <16 x i8> %tmp185.i, i8 %tmp186.i, i32 6 ; <<16 x i8>> [#uses=1] + %tmp188.i = extractelement <16 x i8> %tmp0, i32 5 ; <i8> [#uses=1] + %tmp189.i = insertelement <16 x i8> %tmp187.i, i8 %tmp188.i, i32 7 ; <<16 x i8>> [#uses=1] + %tmp190.i = insertelement <16 x i8> %tmp189.i, i8 0, i32 8 ; <<16 x i8>> [#uses=1] + %tmp191.i = insertelement <16 x i8> %tmp190.i, i8 0, i32 9 ; <<16 x i8>> [#uses=1] + %tmp192.i = extractelement <16 x i8> %tmp0, i32 8 ; <i8> [#uses=1] + %tmp193.i = insertelement <16 x i8> %tmp191.i, i8 %tmp192.i, i32 10 ; <<16 x i8>> [#uses=1] + %tmp194.i = extractelement <16 x i8> %tmp0, i32 9 ; <i8> [#uses=1] + %tmp195.i = insertelement <16 x i8> %tmp193.i, i8 %tmp194.i, i32 11 ; <<16 x i8>> [#uses=1] + %tmp196.i = insertelement <16 x i8> %tmp195.i, i8 0, i32 12 ; <<16 x i8>> [#uses=1] + %tmp197.i = insertelement <16 x i8> %tmp196.i, i8 0, i32 13 ; <<16 x i8>> [#uses=1] +%tmp201 = shufflevector <16 x i8> %tmp197.i, <16 x i8> %tmp0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 28, i32 29>; ModuleID = 'try.c' + store <16 x i8> %tmp201, <16 x i8>* @c, align 16 + br label %return + +return: ; preds = %bb2 + ret void +; CHECK: blr +} diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll index eefbae53e720..8f6449e8ffd5 100644 --- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 4 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 7 define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind { entry: diff --git a/test/CodeGen/Thumb2/ifcvt-neon.ll b/test/CodeGen/Thumb2/ifcvt-neon.ll new file mode 100644 index 000000000000..c667909e3c11 --- /dev/null +++ b/test/CodeGen/Thumb2/ifcvt-neon.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s +; rdar://7368193 + +@a = common global float 0.000000e+00 ; <float*> [#uses=2] +@b = common global float 0.000000e+00 ; <float*> [#uses=1] + +define arm_apcscc float @t(i32 %c) nounwind { +entry: + %0 = icmp sgt i32 %c, 1 ; <i1> [#uses=1] + %1 = load float* @a, align 4 ; <float> [#uses=2] + %2 = load float* @b, align 4 ; <float> [#uses=2] + br i1 %0, label %bb, label %bb1 + +bb: ; preds = %entry +; CHECK: ite lt +; CHECK: vsublt.f32 +; CHECK-NEXT: vaddge.f32 + %3 = fadd float %1, %2 ; <float> [#uses=1] + br label %bb2 + +bb1: ; preds = %entry + %4 = fsub float %1, %2 ; <float> [#uses=1] + br label %bb2 + +bb2: ; preds = %bb1, %bb + %storemerge = phi float [ %4, %bb1 ], [ %3, %bb ] ; <float> [#uses=2] + store float %storemerge, float* @a + ret float %storemerge +} diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll index 7cbe26097b54..47d85b1aa0e5 100644 --- a/test/CodeGen/Thumb2/ldr-str-imm12.ll +++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll @@ -22,8 +22,7 @@ define arm_apcscc %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { entry: -; CHECK: ldr.w r9, [r7, #+32] -; CHECK-NEXT : str.w r9, [sp, #+28] +; CHECK: ldr.w r9, [r7, #+28] %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] br i1 false, label %bb, label %bb20 @@ -53,7 +52,6 @@ bb420: ; preds = %bb20, %bb20 ; CHECK: str r{{[0-7]}}, [sp] ; CHECK: str r{{[0-7]}}, [sp, #+4] ; CHECK: str r{{[0-7]}}, [sp, #+8] -; CHECK: ldr r{{[0-7]}}, [sp, #+28] ; CHECK: str r{{[0-7]}}, [sp, #+24] store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_res, align 4 diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index 912939bf24eb..9ab19e9d5a61 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC ; rdar://7353541 ; rdar://7354376 @@ -17,12 +18,24 @@ entry: bb.nph: ; preds = %entry ; CHECK: BB#1 ; CHECK: ldr.n r2, LCPI1_0 -; CHECK: add r2, pc -; CHECK: ldr r{{[0-9]+}}, [r2] +; CHECK: ldr r3, [r2] +; CHECK: ldr r3, [r3] +; CHECK: ldr r2, [r2] ; CHECK: LBB1_2 ; CHECK: LCPI1_0: ; CHECK-NOT: LCPI1_1: ; CHECK: .section + +; PIC: BB#1 +; PIC: ldr.n r2, LCPI1_0 +; PIC: add r2, pc +; PIC: ldr r3, [r2] +; PIC: ldr r3, [r3] +; PIC: ldr r2, [r2] +; PIC: LBB1_2 +; PIC: LCPI1_0: +; PIC-NOT: LCPI1_1: +; PIC: .section %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] br label %bb diff --git a/test/CodeGen/Thumb2/thumb2-add3.ll b/test/CodeGen/Thumb2/thumb2-add3.ll index 8d472cb110b8..58fc33372cf6 100644 --- a/test/CodeGen/Thumb2/thumb2-add3.ll +++ b/test/CodeGen/Thumb2/thumb2-add3.ll @@ -1,6 +1,9 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {addw\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#4095} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f1(i32 %a) { %tmp = add i32 %a, 4095 ret i32 %tmp } + +; CHECK: f1: +; CHECK: addw r0, r0, #4095 diff --git a/test/CodeGen/Thumb2/thumb2-and2.ll b/test/CodeGen/Thumb2/thumb2-and2.ll index 1e2666f40368..76c56d00473d 100644 --- a/test/CodeGen/Thumb2/thumb2-and2.ll +++ b/test/CodeGen/Thumb2/thumb2-and2.ll @@ -1,31 +1,41 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {and\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; 171 = 0x000000ab define i32 @f1(i32 %a) { %tmp = and i32 %a, 171 ret i32 %tmp } +; CHECK: f1: +; CHECK: and r0, r0, #171 ; 1179666 = 0x00120012 define i32 @f2(i32 %a) { %tmp = and i32 %a, 1179666 ret i32 %tmp } +; CHECK: f2: +; CHECK: and r0, r0, #1179666 ; 872428544 = 0x34003400 define i32 @f3(i32 %a) { %tmp = and i32 %a, 872428544 ret i32 %tmp } +; CHECK: f3: +; CHECK: and r0, r0, #872428544 ; 1448498774 = 0x56565656 define i32 @f4(i32 %a) { %tmp = and i32 %a, 1448498774 ret i32 %tmp } +; CHECK: f4: +; CHECK: and r0, r0, #1448498774 ; 66846720 = 0x03fc0000 define i32 @f5(i32 %a) { %tmp = and i32 %a, 66846720 ret i32 %tmp } +; CHECK: f5: +; CHECK: and r0, r0, #66846720 diff --git a/test/CodeGen/Thumb2/thumb2-cmn.ll b/test/CodeGen/Thumb2/thumb2-cmn.ll index 401c56a72139..eeaaa7fbdf91 100644 --- a/test/CodeGen/Thumb2/thumb2-cmn.ll +++ b/test/CodeGen/Thumb2/thumb2-cmn.ll @@ -1,32 +1,36 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\]$} | count 4 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {cmn\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i1 @f1(i32 %a, i32 %b) { %nb = sub i32 0, %b %tmp = icmp ne i32 %a, %nb ret i1 %tmp } +; CHECK: f1: +; CHECK: cmn.w r0, r1 define i1 @f2(i32 %a, i32 %b) { %nb = sub i32 0, %b %tmp = icmp ne i32 %nb, %a ret i1 %tmp } +; CHECK: f2: +; CHECK: cmn.w r0, r1 define i1 @f3(i32 %a, i32 %b) { %nb = sub i32 0, %b %tmp = icmp eq i32 %a, %nb ret i1 %tmp } +; CHECK: f3: +; CHECK: cmn.w r0, r1 define i1 @f4(i32 %a, i32 %b) { %nb = sub i32 0, %b %tmp = icmp eq i32 %nb, %a ret i1 %tmp } +; CHECK: f4: +; CHECK: cmn.w r0, r1 define i1 @f5(i32 %a, i32 %b) { %tmp = shl i32 %b, 5 @@ -34,6 +38,8 @@ define i1 @f5(i32 %a, i32 %b) { %tmp1 = icmp eq i32 %nb, %a ret i1 %tmp1 } +; CHECK: f5: +; CHECK: cmn.w r0, r1, lsl #5 define i1 @f6(i32 %a, i32 %b) { %tmp = lshr i32 %b, 6 @@ -41,6 +47,8 @@ define i1 @f6(i32 %a, i32 %b) { %tmp1 = icmp ne i32 %nb, %a ret i1 %tmp1 } +; CHECK: f6: +; CHECK: cmn.w r0, r1, lsr #6 define i1 @f7(i32 %a, i32 %b) { %tmp = ashr i32 %b, 7 @@ -48,6 +56,8 @@ define i1 @f7(i32 %a, i32 %b) { %tmp1 = icmp eq i32 %a, %nb ret i1 %tmp1 } +; CHECK: f7: +; CHECK: cmn.w r0, r1, asr #7 define i1 @f8(i32 %a, i32 %b) { %l8 = shl i32 %a, 24 @@ -57,3 +67,6 @@ define i1 @f8(i32 %a, i32 %b) { %tmp1 = icmp ne i32 %a, %nb ret i1 %tmp1 } +; CHECK: f8: +; CHECK: cmn.w r0, r0, ror #8 + diff --git a/test/CodeGen/Thumb2/thumb2-mla.ll b/test/CodeGen/Thumb2/thumb2-mla.ll index be66425d7e66..c4cc749ea5c7 100644 --- a/test/CodeGen/Thumb2/thumb2-mla.ll +++ b/test/CodeGen/Thumb2/thumb2-mla.ll @@ -1,13 +1,17 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {mla\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 2 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f1(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b %tmp2 = add i32 %c, %tmp1 ret i32 %tmp2 } +; CHECK: f1: +; CHECK: mla r0, r0, r1, r2 define i32 @f2(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b %tmp2 = add i32 %tmp1, %c ret i32 %tmp2 } +; CHECK: f2: +; CHECK: mla r0, r0, r1, r2 diff --git a/test/CodeGen/Thumb2/thumb2-mls.ll b/test/CodeGen/Thumb2/thumb2-mls.ll index 782def966615..fc9e6bab48cb 100644 --- a/test/CodeGen/Thumb2/thumb2-mls.ll +++ b/test/CodeGen/Thumb2/thumb2-mls.ll @@ -1,10 +1,12 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f1(i32 %a, i32 %b, i32 %c) { %tmp1 = mul i32 %a, %b %tmp2 = sub i32 %c, %tmp1 ret i32 %tmp2 } +; CHECK: f1: +; CHECK: mls r0, r0, r1, r2 ; sub doesn't commute, so no mls for this one define i32 @f2(i32 %a, i32 %b, i32 %c) { @@ -12,3 +14,6 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) { %tmp2 = sub i32 %tmp1, %c ret i32 %tmp2 } +; CHECK: f2: +; CHECK: muls r0, r1 + diff --git a/test/CodeGen/Thumb2/thumb2-mov2.ll b/test/CodeGen/Thumb2/thumb2-mov2.ll deleted file mode 100644 index 64e2ddcf3fe3..000000000000 --- a/test/CodeGen/Thumb2/thumb2-mov2.ll +++ /dev/null @@ -1,73 +0,0 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s - -define i32 @t2MOVTi16_ok_1(i32 %a) { -; CHECK: t2MOVTi16_ok_1: -; CHECK: movt r0, #1234 - %1 = and i32 %a, 65535 - %2 = shl i32 1234, 16 - %3 = or i32 %1, %2 - - ret i32 %3 -} - -define i32 @t2MOVTi16_test_1(i32 %a) { -; CHECK: t2MOVTi16_test_1: -; CHECK: movt r0, #1234 - %1 = shl i32 255, 8 - %2 = shl i32 1234, 8 - %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 - %4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4 - %5 = and i32 %a, %3 - %6 = or i32 %4, %5 - - ret i32 %6 -} - -define i32 @t2MOVTi16_test_2(i32 %a) { -; CHECK: t2MOVTi16_test_2: -; CHECK: movt r0, #1234 - %1 = shl i32 255, 8 - %2 = shl i32 1234, 8 - %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 - %4 = shl i32 %2, 6 - %5 = and i32 %a, %3 - %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 - %7 = or i32 %5, %6 - - ret i32 %7 -} - -define i32 @t2MOVTi16_test_3(i32 %a) { -; CHECK: t2MOVTi16_test_3: -; CHECK: movt r0, #1234 - %1 = shl i32 255, 8 - %2 = shl i32 1234, 8 - %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 - %4 = shl i32 %2, 6 - %5 = and i32 %a, %3 - %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 - %7 = lshr i32 %6, 6 - %8 = shl i32 %7, 6 - %9 = or i32 %5, %8 - - ret i32 %9 -} - -define i32 @t2MOVTi16_test_nomatch_1(i32 %a) { -; CHECK: t2MOVTi16_test_nomatch_1: -; CHECK: #8388608 -; CHECK: movw r1, #65535 -; CHECK-NEXT: movt r1, #154 -; CHECK: #1720320 - %1 = shl i32 255, 8 - %2 = shl i32 1234, 8 - %3 = or i32 %1, 255 ; This give us 0xFFFF in %3 - %4 = shl i32 %2, 6 - %5 = and i32 %a, %3 - %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6 - %7 = lshr i32 %6, 3 - %8 = or i32 %5, %7 - ret i32 %8 -} - - diff --git a/test/CodeGen/Thumb2/thumb2-mov3.ll b/test/CodeGen/Thumb2/thumb2-mov3.ll deleted file mode 100644 index 46af6fb16c49..000000000000 --- a/test/CodeGen/Thumb2/thumb2-mov3.ll +++ /dev/null @@ -1,41 +0,0 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s - -; 171 = 0x000000ab -define i32 @f1(i32 %a) { -; CHECK: f1: -; CHECK: movs r0, #171 - %tmp = add i32 0, 171 - ret i32 %tmp -} - -; 1179666 = 0x00120012 -define i32 @f2(i32 %a) { -; CHECK: f2: -; CHECK: mov.w r0, #1179666 - %tmp = add i32 0, 1179666 - ret i32 %tmp -} - -; 872428544 = 0x34003400 -define i32 @f3(i32 %a) { -; CHECK: f3: -; CHECK: mov.w r0, #872428544 - %tmp = add i32 0, 872428544 - ret i32 %tmp -} - -; 1448498774 = 0x56565656 -define i32 @f4(i32 %a) { -; CHECK: f4: -; CHECK: mov.w r0, #1448498774 - %tmp = add i32 0, 1448498774 - ret i32 %tmp -} - -; 66846720 = 0x03fc0000 -define i32 @f5(i32 %a) { -; CHECK: f5: -; CHECK: mov.w r0, #66846720 - %tmp = add i32 0, 66846720 - ret i32 %tmp -} diff --git a/test/CodeGen/Thumb2/thumb2-mov4.ll b/test/CodeGen/Thumb2/thumb2-mov4.ll deleted file mode 100644 index 06fa238263ab..000000000000 --- a/test/CodeGen/Thumb2/thumb2-mov4.ll +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {movw\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#65535} | count 1 - -define i32 @f6(i32 %a) { - %tmp = add i32 0, 65535 - ret i32 %tmp -} diff --git a/test/CodeGen/Thumb2/thumb2-orn.ll b/test/CodeGen/Thumb2/thumb2-orn.ll index d4222c2b2dac..97a3fd75f068 100644 --- a/test/CodeGen/Thumb2/thumb2-orn.ll +++ b/test/CodeGen/Thumb2/thumb2-orn.ll @@ -1,32 +1,37 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*r\[0-9\]*$} | count 4 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + define i32 @f1(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 %tmp1 = or i32 %a, %tmp ret i32 %tmp1 } +; CHECK: f1: +; CHECK: orn r0, r0, r1 define i32 @f2(i32 %a, i32 %b) { %tmp = xor i32 %b, 4294967295 %tmp1 = or i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f2: +; CHECK: orn r0, r0, r1 define i32 @f3(i32 %a, i32 %b) { %tmp = xor i32 4294967295, %b %tmp1 = or i32 %a, %tmp ret i32 %tmp1 } +; CHECK: f3: +; CHECK: orn r0, r0, r1 define i32 @f4(i32 %a, i32 %b) { %tmp = xor i32 4294967295, %b %tmp1 = or i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f4: +; CHECK: orn r0, r0, r1 define i32 @f5(i32 %a, i32 %b) { %tmp = shl i32 %b, 5 @@ -34,6 +39,8 @@ define i32 @f5(i32 %a, i32 %b) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f5: +; CHECK: orn r0, r0, r1, lsl #5 define i32 @f6(i32 %a, i32 %b) { %tmp = lshr i32 %b, 6 @@ -41,6 +48,8 @@ define i32 @f6(i32 %a, i32 %b) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f6: +; CHECK: orn r0, r0, r1, lsr #6 define i32 @f7(i32 %a, i32 %b) { %tmp = ashr i32 %b, 7 @@ -48,6 +57,8 @@ define i32 @f7(i32 %a, i32 %b) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f7: +; CHECK: orn r0, r0, r1, asr #7 define i32 @f8(i32 %a, i32 %b) { %l8 = shl i32 %a, 24 @@ -57,3 +68,5 @@ define i32 @f8(i32 %a, i32 %b) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f8: +; CHECK: orn r0, r0, r0, ror #8 diff --git a/test/CodeGen/Thumb2/thumb2-orn2.ll b/test/CodeGen/Thumb2/thumb2-orn2.ll index 7b018826a621..34ab3a56663c 100644 --- a/test/CodeGen/Thumb2/thumb2-orn2.ll +++ b/test/CodeGen/Thumb2/thumb2-orn2.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orn\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} |\ -; RUN: grep {#187\\|#11141290\\|#-872363008\\|#1114112} | count 4 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + ; 0x000000bb = 187 define i32 @f1(i32 %a) { @@ -7,6 +7,8 @@ define i32 @f1(i32 %a) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f1: +; CHECK: orn r0, r0, #187 ; 0x00aa00aa = 11141290 define i32 @f2(i32 %a) { @@ -14,6 +16,8 @@ define i32 @f2(i32 %a) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f2: +; CHECK: orn r0, r0, #11141290 ; 0xcc00cc00 = 3422604288 define i32 @f3(i32 %a) { @@ -21,6 +25,8 @@ define i32 @f3(i32 %a) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f3: +; CHECK: orn r0, r0, #-872363008 ; 0x00110000 = 1114112 define i32 @f5(i32 %a) { @@ -28,3 +34,5 @@ define i32 @f5(i32 %a) { %tmp2 = or i32 %a, %tmp1 ret i32 %tmp2 } +; CHECK: f5: +; CHECK: orn r0, r0, #1114112 diff --git a/test/CodeGen/Thumb2/thumb2-orr2.ll b/test/CodeGen/Thumb2/thumb2-orr2.ll index 759a5b8dd894..8f7a3c2a61a9 100644 --- a/test/CodeGen/Thumb2/thumb2-orr2.ll +++ b/test/CodeGen/Thumb2/thumb2-orr2.ll @@ -1,31 +1,42 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {orr\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} | grep {#187\\|#11141290\\|#-872363008\\|#1145324612\\|#1114112} | count 5 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + ; 0x000000bb = 187 define i32 @f1(i32 %a) { %tmp2 = or i32 %a, 187 ret i32 %tmp2 } +; CHECK: f1: +; CHECK: orr r0, r0, #187 ; 0x00aa00aa = 11141290 define i32 @f2(i32 %a) { %tmp2 = or i32 %a, 11141290 ret i32 %tmp2 } +; CHECK: f2: +; CHECK: orr r0, r0, #11141290 ; 0xcc00cc00 = 3422604288 define i32 @f3(i32 %a) { %tmp2 = or i32 %a, 3422604288 ret i32 %tmp2 } +; CHECK: f3: +; CHECK: orr r0, r0, #-872363008 ; 0x44444444 = 1145324612 define i32 @f4(i32 %a) { %tmp2 = or i32 %a, 1145324612 ret i32 %tmp2 } +; CHECK: f4: +; CHECK: orr r0, r0, #1145324612 ; 0x00110000 = 1114112 define i32 @f5(i32 %a) { %tmp2 = or i32 %a, 1114112 ret i32 %tmp2 } +; CHECK: f5: +; CHECK: orr r0, r0, #1114112 diff --git a/test/CodeGen/Thumb2/thumb2-ror.ll b/test/CodeGen/Thumb2/thumb2-ror.ll index 01adb528087b..0200116fc31a 100644 --- a/test/CodeGen/Thumb2/thumb2-ror.ll +++ b/test/CodeGen/Thumb2/thumb2-ror.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {ror\\.w\\W*r\[0-9\]*,\\W*r\[0-9\]*,\\W*#\[0-9\]*} | grep 22 | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + define i32 @f1(i32 %a) { %l8 = shl i32 %a, 10 @@ -6,3 +7,5 @@ define i32 @f1(i32 %a) { %tmp = or i32 %l8, %r8 ret i32 %tmp } +; CHECK: f1: +; CHECK: ror.w r0, r0, #22 diff --git a/test/CodeGen/Thumb2/thumb2-rsb.ll b/test/CodeGen/Thumb2/thumb2-rsb.ll index 4611e9435034..15185be94621 100644 --- a/test/CodeGen/Thumb2/thumb2-rsb.ll +++ b/test/CodeGen/Thumb2/thumb2-rsb.ll @@ -1,30 +1,35 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsl\\W*#5$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*lsr\\W*#6$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*asr\\W*#7$} | count 1 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*ror\\W*#8$} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s -define i32 @f2(i32 %a, i32 %b) { +define i32 @f1(i32 %a, i32 %b) { %tmp = shl i32 %b, 5 %tmp1 = sub i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f1: +; CHECK: rsb r0, r0, r1, lsl #5 -define i32 @f3(i32 %a, i32 %b) { +define i32 @f2(i32 %a, i32 %b) { %tmp = lshr i32 %b, 6 %tmp1 = sub i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f2: +; CHECK: rsb r0, r0, r1, lsr #6 -define i32 @f4(i32 %a, i32 %b) { +define i32 @f3(i32 %a, i32 %b) { %tmp = ashr i32 %b, 7 %tmp1 = sub i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f3: +; CHECK: rsb r0, r0, r1, asr #7 -define i32 @f5(i32 %a, i32 %b) { +define i32 @f4(i32 %a, i32 %b) { %l8 = shl i32 %a, 24 %r8 = lshr i32 %a, 8 %tmp = or i32 %l8, %r8 %tmp1 = sub i32 %tmp, %a ret i32 %tmp1 } +; CHECK: f4: +; CHECK: rsb r0, r0, r0, ror #8 diff --git a/test/CodeGen/Thumb2/thumb2-rsb2.ll b/test/CodeGen/Thumb2/thumb2-rsb2.ll index 84a379677ad4..61fb619c40e7 100644 --- a/test/CodeGen/Thumb2/thumb2-rsb2.ll +++ b/test/CodeGen/Thumb2/thumb2-rsb2.ll @@ -1,31 +1,41 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {rsb\\.w\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#171\\|#1179666\\|#872428544\\|#1448498774\\|#66846720} | count 5 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; 171 = 0x000000ab define i32 @f1(i32 %a) { %tmp = sub i32 171, %a ret i32 %tmp } +; CHECK: f1: +; CHECK: rsb.w r0, r0, #171 ; 1179666 = 0x00120012 define i32 @f2(i32 %a) { %tmp = sub i32 1179666, %a ret i32 %tmp } +; CHECK: f2: +; CHECK: rsb.w r0, r0, #1179666 ; 872428544 = 0x34003400 define i32 @f3(i32 %a) { %tmp = sub i32 872428544, %a ret i32 %tmp } +; CHECK: f3: +; CHECK: rsb.w r0, r0, #872428544 ; 1448498774 = 0x56565656 define i32 @f4(i32 %a) { %tmp = sub i32 1448498774, %a ret i32 %tmp } +; CHECK: f4: +; CHECK: rsb.w r0, r0, #1448498774 ; 66846720 = 0x03fc0000 define i32 @f5(i32 %a) { %tmp = sub i32 66846720, %a ret i32 %tmp } +; CHECK: f5: +; CHECK: rsb.w r0, r0, #66846720 diff --git a/test/CodeGen/Thumb2/thumb2-select_xform.ll b/test/CodeGen/Thumb2/thumb2-select_xform.ll index 44fa2458c1e4..7fc2e2a49bd8 100644 --- a/test/CodeGen/Thumb2/thumb2-select_xform.ll +++ b/test/CodeGen/Thumb2/thumb2-select_xform.ll @@ -2,9 +2,9 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { ; CHECK: t1 -; CHECK: mvn r0, #-2147483648 +; CHECK: sub.w r0, r1, #-2147483648 ; CHECK: cmp r2, #10 -; CHECK: add.w r0, r1, r0 +; CHECK: sub.w r0, r0, #1 ; CHECK: it gt ; CHECK: movgt r0, r1 %tmp1 = icmp sgt i32 %c, 10 diff --git a/test/CodeGen/Thumb2/thumb2-sub2.ll b/test/CodeGen/Thumb2/thumb2-sub2.ll index 6813f76d8932..bb99cbd67fcf 100644 --- a/test/CodeGen/Thumb2/thumb2-sub2.ll +++ b/test/CodeGen/Thumb2/thumb2-sub2.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {subw\\W*r\[0-9\],\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#4095} | count 1 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f1(i32 %a) { %tmp = sub i32 %a, 4095 ret i32 %tmp } +; CHECK: f1: +; CHECK: subw r0, r0, #4095 diff --git a/test/CodeGen/Thumb2/thumb2-teq.ll b/test/CodeGen/Thumb2/thumb2-teq.ll index 634d318c85c4..69f03837f4bf 100644 --- a/test/CodeGen/Thumb2/thumb2-teq.ll +++ b/test/CodeGen/Thumb2/thumb2-teq.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {teq\\.w\\W*r\[0-9\],\\W*#\[0-9\]*} | \ -; RUN: grep {#187\\|#11141290\\|#-872363008\\|#1114112\\|#-572662307} | count 10 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + ; 0x000000bb = 187 define i1 @f1(i32 %a) { @@ -7,6 +7,8 @@ define i1 @f1(i32 %a) { %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f1: +; CHECK: teq.w r0, #187 ; 0x000000bb = 187 define i1 @f2(i32 %a) { @@ -14,6 +16,8 @@ define i1 @f2(i32 %a) { %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f2: +; CHECK: teq.w r0, #187 ; 0x00aa00aa = 11141290 define i1 @f3(i32 %a) { @@ -21,6 +25,8 @@ define i1 @f3(i32 %a) { %tmp1 = icmp eq i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f3: +; CHECK: teq.w r0, #11141290 ; 0x00aa00aa = 11141290 define i1 @f4(i32 %a) { @@ -28,6 +34,8 @@ define i1 @f4(i32 %a) { %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } +; CHECK: f4: +; CHECK: teq.w r0, #11141290 ; 0xcc00cc00 = 3422604288 define i1 @f5(i32 %a) { @@ -35,6 +43,8 @@ define i1 @f5(i32 %a) { %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f5: +; CHECK: teq.w r0, #-872363008 ; 0xcc00cc00 = 3422604288 define i1 @f6(i32 %a) { @@ -42,6 +52,8 @@ define i1 @f6(i32 %a) { %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f6: +; CHECK: teq.w r0, #-872363008 ; 0xdddddddd = 3722304989 define i1 @f7(i32 %a) { @@ -49,6 +61,8 @@ define i1 @f7(i32 %a) { %tmp1 = icmp eq i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f7: +; CHECK: teq.w r0, #-572662307 ; 0xdddddddd = 3722304989 define i1 @f8(i32 %a) { @@ -56,6 +70,8 @@ define i1 @f8(i32 %a) { %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } +; CHECK: f8: +; CHECK: teq.w r0, #-572662307 ; 0x00110000 = 1114112 define i1 @f9(i32 %a) { @@ -63,6 +79,8 @@ define i1 @f9(i32 %a) { %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f9: +; CHECK: teq.w r0, #1114112 ; 0x00110000 = 1114112 define i1 @f10(i32 %a) { @@ -70,3 +88,6 @@ define i1 @f10(i32 %a) { %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f10: +; CHECK: teq.w r0, #1114112 + diff --git a/test/CodeGen/Thumb2/thumb2-tst.ll b/test/CodeGen/Thumb2/thumb2-tst.ll index 525a817fe37e..d905217189f4 100644 --- a/test/CodeGen/Thumb2/thumb2-tst.ll +++ b/test/CodeGen/Thumb2/thumb2-tst.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {tst\\.w\\W*r\[0-9\],\\W*#\[0-9\]*} | \ -; RUN: grep {#187\\|#11141290\\|#-872363008\\|#1114112\\|#-572662307} | count 10 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + ; 0x000000bb = 187 define i1 @f1(i32 %a) { @@ -7,6 +7,8 @@ define i1 @f1(i32 %a) { %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f1: +; CHECK: tst.w r0, #187 ; 0x000000bb = 187 define i1 @f2(i32 %a) { @@ -14,6 +16,8 @@ define i1 @f2(i32 %a) { %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f2: +; CHECK: tst.w r0, #187 ; 0x00aa00aa = 11141290 define i1 @f3(i32 %a) { @@ -21,6 +25,8 @@ define i1 @f3(i32 %a) { %tmp1 = icmp eq i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f3: +; CHECK: tst.w r0, #11141290 ; 0x00aa00aa = 11141290 define i1 @f4(i32 %a) { @@ -28,6 +34,8 @@ define i1 @f4(i32 %a) { %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } +; CHECK: f4: +; CHECK: tst.w r0, #11141290 ; 0xcc00cc00 = 3422604288 define i1 @f5(i32 %a) { @@ -35,6 +43,8 @@ define i1 @f5(i32 %a) { %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f5: +; CHECK: tst.w r0, #-872363008 ; 0xcc00cc00 = 3422604288 define i1 @f6(i32 %a) { @@ -42,6 +52,8 @@ define i1 @f6(i32 %a) { %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f6: +; CHECK: tst.w r0, #-872363008 ; 0xdddddddd = 3722304989 define i1 @f7(i32 %a) { @@ -49,6 +61,8 @@ define i1 @f7(i32 %a) { %tmp1 = icmp eq i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f7: +; CHECK: tst.w r0, #-572662307 ; 0xdddddddd = 3722304989 define i1 @f8(i32 %a) { @@ -56,6 +70,8 @@ define i1 @f8(i32 %a) { %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } +; CHECK: f8: +; CHECK: tst.w r0, #-572662307 ; 0x00110000 = 1114112 define i1 @f9(i32 %a) { @@ -63,6 +79,8 @@ define i1 @f9(i32 %a) { %tmp1 = icmp ne i32 %tmp, 0 ret i1 %tmp1 } +; CHECK: f9: +; CHECK: tst.w r0, #1114112 ; 0x00110000 = 1114112 define i1 @f10(i32 %a) { @@ -70,3 +88,5 @@ define i1 @f10(i32 %a) { %tmp1 = icmp eq i32 0, %tmp ret i1 %tmp1 } +; CHECK: f10: +; CHECK: tst.w r0, #1114112 diff --git a/test/CodeGen/X86/2008-08-05-SpillerBug.ll b/test/CodeGen/X86/2008-08-05-SpillerBug.ll index 1d166f488158..67e14ffae5e6 100644 --- a/test/CodeGen/X86/2008-08-05-SpillerBug.ll +++ b/test/CodeGen/X86/2008-08-05-SpillerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 59 +; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 58 ; PR2568 @g_3 = external global i16 ; <i16*> [#uses=1] diff --git a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll index 878fa51d5dc3..ad7f9f7d1c11 100644 --- a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll +++ b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep -A 2 {call.*f} | grep movl +; RUN: llc < %s -march=x86 | FileCheck %s ; Check the register copy comes after the call to f and before the call to g ; PR3784 @@ -26,3 +26,7 @@ lpad: ; preds = %cont, %entry %y = phi i32 [ %a, %entry ], [ %aa, %cont ] ; <i32> [#uses=1] ret i32 %y } + +; CHECK: call{{.*}}f +; CHECK-NEXT: Llabel1: +; CHECK-NEXT: movl %eax, %esi diff --git a/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll b/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll index adbd241cd98f..11c410173fcb 100644 --- a/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll +++ b/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -asm-verbose | grep -A 1 lpad | grep Llabel +; RUN: llc < %s -march=x86 -asm-verbose | FileCheck %s ; Check that register copies in the landing pad come after the EH_LABEL declare i32 @f() @@ -19,3 +19,6 @@ lpad: ; preds = %cont, %entry %v = phi i32 [ %x, %entry ], [ %a, %cont ] ; <i32> [#uses=1] ret i32 %v } + +; CHECK: lpad +; CHECK-NEXT: Llabel diff --git a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll index f3cf1d5e7019..d372da336769 100644 --- a/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll +++ b/test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll @@ -10,6 +10,7 @@ entry: bb: ; preds = %bb1, %entry ; CHECK: addl $1 +; CHECK-NEXT: movl %e ; CHECK-NEXT: adcl $0 %i.0 = phi i64 [ 0, %entry ], [ %0, %bb1 ] ; <i64> [#uses=1] %0 = add nsw i64 %i.0, 1 ; <i64> [#uses=2] diff --git a/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll b/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll index ef10ae59ab6b..91c5440b278f 100644 --- a/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll +++ b/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -stats |& grep {machine-licm} | grep 1 +; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -stats |& grep {machine-licm} | grep 2 ; rdar://7274692 %0 = type { [125 x i32] } diff --git a/test/CodeGen/X86/2009-11-25-ImpDefBug.ll b/test/CodeGen/X86/2009-11-25-ImpDefBug.ll new file mode 100644 index 000000000000..7606c0e1acc9 --- /dev/null +++ b/test/CodeGen/X86/2009-11-25-ImpDefBug.ll @@ -0,0 +1,116 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu +; pr5600 + +%struct..0__pthread_mutex_s = type { i32, i32, i32, i32, i32, i32, %struct.__pthread_list_t } +%struct.ASN1ObjHeader = type { i8, %"struct.__gmp_expr<__mpz_struct [1],__mpz_struct [1]>", i64, i32, i32, i32 } +%struct.ASN1Object = type { i32 (...)**, i32, i32, i64 } +%struct.ASN1Unit = type { [4 x i32 (%struct.ASN1ObjHeader*, %struct.ASN1Object**)*], %"struct.std::ASN1ObjList" } +%"struct.__gmp_expr<__mpz_struct [1],__mpz_struct [1]>" = type { [1 x %struct.__mpz_struct] } +%struct.__mpz_struct = type { i32, i32, i64* } +%struct.__pthread_list_t = type { %struct.__pthread_list_t*, %struct.__pthread_list_t* } +%struct.pthread_attr_t = type { i64, [48 x i8] } +%struct.pthread_mutex_t = type { %struct..0__pthread_mutex_s } +%struct.pthread_mutexattr_t = type { i32 } +%"struct.std::ASN1ObjList" = type { %"struct.std::_Vector_base<ASN1Object*,std::allocator<ASN1Object*> >" } +%"struct.std::_Vector_base<ASN1Object*,std::allocator<ASN1Object*> >" = type { %"struct.std::_Vector_base<ASN1Object*,std::allocator<ASN1Object*> >::_Vector_impl" } +%"struct.std::_Vector_base<ASN1Object*,std::allocator<ASN1Object*> >::_Vector_impl" = type { %struct.ASN1Object**, %struct.ASN1Object**, %struct.ASN1Object** } +%struct.xmstream = type { i8*, i64, i64, i64, i8 } + +declare void @_ZNSt6vectorIP10ASN1ObjectSaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%"struct.std::ASN1ObjList"* nocapture, i64, %struct.ASN1Object** nocapture) + +declare i32 @_Z17LoadObjectFromBERR8xmstreamPP10ASN1ObjectPPF10ASN1StatusP13ASN1ObjHeaderS3_E(%struct.xmstream*, %struct.ASN1Object**, i32 (%struct.ASN1ObjHeader*, %struct.ASN1Object**)**) + +define i32 @_ZN8ASN1Unit4loadER8xmstreamjm18ASN1LengthEncoding(%struct.ASN1Unit* %this, %struct.xmstream* nocapture %stream, i32 %numObjects, i64 %size, i32 %lEncoding) { +entry: + br label %meshBB85 + +bb5: ; preds = %bb13.fragment.cl135, %bb13.fragment.cl, %bb.i.i.bbcl.disp, %bb13.fragment + %0 = invoke i32 @_Z17LoadObjectFromBERR8xmstreamPP10ASN1ObjectPPF10ASN1StatusP13ASN1ObjHeaderS3_E(%struct.xmstream* undef, %struct.ASN1Object** undef, i32 (%struct.ASN1ObjHeader*, %struct.ASN1Object**)** undef) + to label %meshBB81.bbcl.disp unwind label %lpad ; <i32> [#uses=0] + +bb10.fragment: ; preds = %bb13.fragment.bbcl.disp + br i1 undef, label %bb1.i.fragment.bbcl.disp, label %bb.i.i.bbcl.disp + +bb1.i.fragment: ; preds = %bb1.i.fragment.bbcl.disp + invoke void @_ZNSt6vectorIP10ASN1ObjectSaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%"struct.std::ASN1ObjList"* undef, i64 undef, %struct.ASN1Object** undef) + to label %meshBB81.bbcl.disp unwind label %lpad + +bb13.fragment: ; preds = %bb13.fragment.bbcl.disp + br i1 undef, label %meshBB81.bbcl.disp, label %bb5 + +bb.i4: ; preds = %bb.i4.bbcl.disp, %bb1.i.fragment.bbcl.disp + ret i32 undef + +bb1.i5: ; preds = %bb.i1 + ret i32 undef + +lpad: ; preds = %bb1.i.fragment.cl, %bb1.i.fragment, %bb5 + %.SV10.phi807 = phi i8* [ undef, %bb1.i.fragment.cl ], [ undef, %bb1.i.fragment ], [ undef, %bb5 ] ; <i8*> [#uses=1] + %1 = load i8* %.SV10.phi807, align 8 ; <i8> [#uses=0] + br i1 undef, label %meshBB81.bbcl.disp, label %bb13.fragment.bbcl.disp + +bb.i1: ; preds = %bb.i.i.bbcl.disp + br i1 undef, label %meshBB81.bbcl.disp, label %bb1.i5 + +meshBB81: ; preds = %meshBB81.bbcl.disp, %bb.i.i.bbcl.disp + br i1 undef, label %meshBB81.bbcl.disp, label %bb.i4.bbcl.disp + +meshBB85: ; preds = %meshBB81.bbcl.disp, %bb.i4.bbcl.disp, %bb1.i.fragment.bbcl.disp, %bb.i.i.bbcl.disp, %entry + br i1 undef, label %meshBB81.bbcl.disp, label %bb13.fragment.bbcl.disp + +bb.i.i.bbcl.disp: ; preds = %bb10.fragment + switch i8 undef, label %meshBB85 [ + i8 123, label %bb.i1 + i8 97, label %bb5 + i8 44, label %meshBB81 + i8 1, label %meshBB81.cl + i8 51, label %meshBB81.cl141 + ] + +bb1.i.fragment.cl: ; preds = %bb1.i.fragment.bbcl.disp + invoke void @_ZNSt6vectorIP10ASN1ObjectSaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%"struct.std::ASN1ObjList"* undef, i64 undef, %struct.ASN1Object** undef) + to label %meshBB81.bbcl.disp unwind label %lpad + +bb1.i.fragment.bbcl.disp: ; preds = %bb10.fragment + switch i8 undef, label %bb.i4 [ + i8 97, label %bb1.i.fragment + i8 7, label %bb1.i.fragment.cl + i8 35, label %bb.i4.cl + i8 77, label %meshBB85 + ] + +bb13.fragment.cl: ; preds = %bb13.fragment.bbcl.disp + br i1 undef, label %meshBB81.bbcl.disp, label %bb5 + +bb13.fragment.cl135: ; preds = %bb13.fragment.bbcl.disp + br i1 undef, label %meshBB81.bbcl.disp, label %bb5 + +bb13.fragment.bbcl.disp: ; preds = %meshBB85, %lpad + switch i8 undef, label %bb10.fragment [ + i8 67, label %bb13.fragment.cl + i8 108, label %bb13.fragment + i8 58, label %bb13.fragment.cl135 + ] + +bb.i4.cl: ; preds = %bb.i4.bbcl.disp, %bb1.i.fragment.bbcl.disp + ret i32 undef + +bb.i4.bbcl.disp: ; preds = %meshBB81.cl141, %meshBB81.cl, %meshBB81 + switch i8 undef, label %bb.i4 [ + i8 35, label %bb.i4.cl + i8 77, label %meshBB85 + ] + +meshBB81.cl: ; preds = %meshBB81.bbcl.disp, %bb.i.i.bbcl.disp + br i1 undef, label %meshBB81.bbcl.disp, label %bb.i4.bbcl.disp + +meshBB81.cl141: ; preds = %meshBB81.bbcl.disp, %bb.i.i.bbcl.disp + br i1 undef, label %meshBB81.bbcl.disp, label %bb.i4.bbcl.disp + +meshBB81.bbcl.disp: ; preds = %meshBB81.cl141, %meshBB81.cl, %bb13.fragment.cl135, %bb13.fragment.cl, %bb1.i.fragment.cl, %meshBB85, %meshBB81, %bb.i1, %lpad, %bb13.fragment, %bb1.i.fragment, %bb5 + switch i8 undef, label %meshBB85 [ + i8 44, label %meshBB81 + i8 1, label %meshBB81.cl + i8 51, label %meshBB81.cl141 + ] +} diff --git a/test/CodeGen/X86/cmp1.ll b/test/CodeGen/X86/cmp1.ll deleted file mode 100644 index d4aa399ae95d..000000000000 --- a/test/CodeGen/X86/cmp1.ll +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: llc < %s -march=x86-64 | grep -v cmp - -define i64 @foo(i64 %x) { - %t = icmp slt i64 %x, 1 - %r = zext i1 %t to i64 - ret i64 %r -} diff --git a/test/CodeGen/X86/fp_constant_op.ll b/test/CodeGen/X86/fp_constant_op.ll index 8e823ede56a0..b3ec5388d704 100644 --- a/test/CodeGen/X86/fp_constant_op.ll +++ b/test/CodeGen/X86/fp_constant_op.ll @@ -1,6 +1,4 @@ -; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=i486 | \ -; RUN: grep {fadd\\|fsub\\|fdiv\\|fmul} | not grep -i ST - +; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=i486 | FileCheck %s ; Test that the load of the constant is folded into the operation. @@ -8,28 +6,41 @@ define double @foo_add(double %P) { %tmp.1 = fadd double %P, 1.230000e+02 ; <double> [#uses=1] ret double %tmp.1 } +; CHECK: foo_add: +; CHECK: fadd DWORD PTR define double @foo_mul(double %P) { %tmp.1 = fmul double %P, 1.230000e+02 ; <double> [#uses=1] ret double %tmp.1 } +; CHECK: foo_mul: +; CHECK: fmul DWORD PTR define double @foo_sub(double %P) { %tmp.1 = fsub double %P, 1.230000e+02 ; <double> [#uses=1] ret double %tmp.1 } +; CHECK: foo_sub: +; CHECK: fadd DWORD PTR define double @foo_subr(double %P) { %tmp.1 = fsub double 1.230000e+02, %P ; <double> [#uses=1] ret double %tmp.1 } +; CHECK: foo_subr: +; CHECK: fsub QWORD PTR define double @foo_div(double %P) { %tmp.1 = fdiv double %P, 1.230000e+02 ; <double> [#uses=1] ret double %tmp.1 } +; CHECK: foo_div: +; CHECK: fdiv DWORD PTR define double @foo_divr(double %P) { %tmp.1 = fdiv double 1.230000e+02, %P ; <double> [#uses=1] ret double %tmp.1 } +; CHECK: foo_divr: +; CHECK: fdiv QWORD PTR + diff --git a/test/CodeGen/X86/palignr-2.ll b/test/CodeGen/X86/palignr-2.ll index 2936641e95d9..116d4c71814a 100644 --- a/test/CodeGen/X86/palignr-2.ll +++ b/test/CodeGen/X86/palignr-2.ll @@ -9,12 +9,12 @@ define void @t1(<2 x i64> %a, <2 x i64> %b) nounwind ssp { entry: ; CHECK: t1: ; palignr $3, %xmm1, %xmm0 - %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i32 24) nounwind readnone + %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 ret void } -declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i32) nounwind readnone +declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone define void @t2() nounwind ssp { entry: @@ -22,7 +22,7 @@ entry: ; palignr $4, _b, %xmm0 %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1] - %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i32 32) nounwind readnone + %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) nounwind readnone store <2 x i64> %2, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16 ret void } diff --git a/test/CodeGen/X86/pic-load-remat.ll b/test/CodeGen/X86/pic-load-remat.ll index d930f76a7747..77297521cd0d 100644 --- a/test/CodeGen/X86/pic-load-remat.ll +++ b/test/CodeGen/X86/pic-load-remat.ll @@ -1,10 +1,4 @@ ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb -; XFAIL: * - -; This is XFAIL'd because MachineLICM is now hoisting all of the loads, and the pic -; base appears killed in the entry block when remat is making its decisions. Remat's -; simple heuristic decides against rematting because it doesn't want to extend the -; live-range of the pic base; this isn't necessarily optimal. define void @f() nounwind { entry: diff --git a/test/CodeGen/X86/scalar_widen_div.ll b/test/CodeGen/X86/scalar_widen_div.ll new file mode 100644 index 000000000000..fc67e4417c4a --- /dev/null +++ b/test/CodeGen/X86/scalar_widen_div.ll @@ -0,0 +1,154 @@ +; RUN: llc < %s -disable-mmx -march=x86-64 -mattr=+sse42 | FileCheck %s + +; Verify when widening a divide/remainder operation, we only generate a +; divide/rem per element since divide/remainder can trap. + +define void @vectorDiv (<2 x i32> addrspace(1)* %nsource, <2 x i32> addrspace(1)* %dsource, <2 x i32> addrspace(1)* %qdest) nounwind { +; CHECK: idivl +; CHECK: idivl +; CHECK-NOT: idivl +; CHECK: ret +entry: + %nsource.addr = alloca <2 x i32> addrspace(1)*, align 4 + %dsource.addr = alloca <2 x i32> addrspace(1)*, align 4 + %qdest.addr = alloca <2 x i32> addrspace(1)*, align 4 + %index = alloca i32, align 4 + store <2 x i32> addrspace(1)* %nsource, <2 x i32> addrspace(1)** %nsource.addr + store <2 x i32> addrspace(1)* %dsource, <2 x i32> addrspace(1)** %dsource.addr + store <2 x i32> addrspace(1)* %qdest, <2 x i32> addrspace(1)** %qdest.addr + %tmp = load <2 x i32> addrspace(1)** %qdest.addr + %tmp1 = load i32* %index + %arrayidx = getelementptr <2 x i32> addrspace(1)* %tmp, i32 %tmp1 + %tmp2 = load <2 x i32> addrspace(1)** %nsource.addr + %tmp3 = load i32* %index + %arrayidx4 = getelementptr <2 x i32> addrspace(1)* %tmp2, i32 %tmp3 + %tmp5 = load <2 x i32> addrspace(1)* %arrayidx4 + %tmp6 = load <2 x i32> addrspace(1)** %dsource.addr + %tmp7 = load i32* %index + %arrayidx8 = getelementptr <2 x i32> addrspace(1)* %tmp6, i32 %tmp7 + %tmp9 = load <2 x i32> addrspace(1)* %arrayidx8 + %tmp10 = sdiv <2 x i32> %tmp5, %tmp9 + store <2 x i32> %tmp10, <2 x i32> addrspace(1)* %arrayidx + ret void +} + +define <3 x i8> @test_char_div(<3 x i8> %num, <3 x i8> %div) { +; CHECK: idivb +; CHECK: idivb +; CHECK: idivb +; CHECK-NOT: idivb +; CHECK: ret + %div.r = sdiv <3 x i8> %num, %div + ret <3 x i8> %div.r +} + +define <3 x i8> @test_uchar_div(<3 x i8> %num, <3 x i8> %div) { +; CHECK: divb +; CHECK: divb +; CHECK: divb +; CHECK-NOT: divb +; CHECK: ret + %div.r = udiv <3 x i8> %num, %div + ret <3 x i8> %div.r +} + +define <5 x i16> @test_short_div(<5 x i16> %num, <5 x i16> %div) { +; CHECK: idivw +; CHECK: idivw +; CHECK: idivw +; CHECK: idivw +; CHECK: idivw +; CHECK-NOT: idivw +; CHECK: ret + %div.r = sdiv <5 x i16> %num, %div + ret <5 x i16> %div.r +} + +define <4 x i16> @test_ushort_div(<4 x i16> %num, <4 x i16> %div) { +; CHECK: divw +; CHECK: divw +; CHECK: divw +; CHECK: divw +; CHECK-NOT: divw +; CHECK: ret + %div.r = udiv <4 x i16> %num, %div + ret <4 x i16> %div.r +} + +define <3 x i32> @test_uint_div(<3 x i32> %num, <3 x i32> %div) { +; CHECK: divl +; CHECK: divl +; CHECK: divl +; CHECK-NOT: divl +; CHECK: ret + %div.r = udiv <3 x i32> %num, %div + ret <3 x i32> %div.r +} + +define <3 x i64> @test_long_div(<3 x i64> %num, <3 x i64> %div) { +; CHECK: idivq +; CHECK: idivq +; CHECK: idivq +; CHECK-NOT: idivq +; CHECK: ret + %div.r = sdiv <3 x i64> %num, %div + ret <3 x i64> %div.r +} + +define <3 x i64> @test_ulong_div(<3 x i64> %num, <3 x i64> %div) { +; CHECK: divq +; CHECK: divq +; CHECK: divq +; CHECK-NOT: divq +; CHECK: ret + %div.r = udiv <3 x i64> %num, %div + ret <3 x i64> %div.r +} + + +define <4 x i8> @test_char_rem(<4 x i8> %num, <4 x i8> %rem) { +; CHECK: idivb +; CHECK: idivb +; CHECK: idivb +; CHECK: idivb +; CHECK-NOT: idivb +; CHECK: ret + %rem.r = srem <4 x i8> %num, %rem + ret <4 x i8> %rem.r +} + +define <5 x i16> @test_short_rem(<5 x i16> %num, <5 x i16> %rem) { +; CHECK: idivw +; CHECK: idivw +; CHECK: idivw +; CHECK: idivw +; CHECK: idivw +; CHECK-NOT: idivw +; CHECK: ret + %rem.r = srem <5 x i16> %num, %rem + ret <5 x i16> %rem.r +} + +define <4 x i32> @test_uint_rem(<4 x i32> %num, <4 x i32> %rem) { +; CHECK: idivl +; CHECK: idivl +; CHECK: idivl +; CHECK: idivl +; CHECK-NOT: idivl +; CHECK: ret + %rem.r = srem <4 x i32> %num, %rem + ret <4 x i32> %rem.r +} + + +define <5 x i64> @test_ulong_rem(<5 x i64> %num, <5 x i64> %rem) { +; CHECK: divq +; CHECK: divq +; CHECK: divq +; CHECK: divq +; CHECK: divq +; CHECK-NOT: divq +; CHECK: ret + %rem.r = urem <5 x i64> %num, %rem + ret <5 x i64> %rem.r +} diff --git a/test/CodeGen/X86/tailcall-fastisel.ll b/test/CodeGen/X86/tailcall-fastisel.ll new file mode 100644 index 000000000000..d54fb4115b07 --- /dev/null +++ b/test/CodeGen/X86/tailcall-fastisel.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=x86-64 -tailcallopt -fast-isel | grep TAILCALL + +; Fast-isel shouldn't attempt to handle this tail call, and it should +; cleanly terminate instruction selection in the block after it's +; done to avoid emitting invalid MachineInstrs. + +%0 = type { i64, i32, i8* } + +define fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 %arg1) nounwind { +fail: ; preds = %entry + %tmp20 = tail call fastcc i8* @"visit_array_aux<`Reference>"(%0 %arg, i32 undef) ; <i8*> [#uses=1] + ret i8* %tmp20 +} diff --git a/test/CodeGen/X86/tailcall-stackalign.ll b/test/CodeGen/X86/tailcall-stackalign.ll index 110472c8b9f3..0233139e8082 100644 --- a/test/CodeGen/X86/tailcall-stackalign.ll +++ b/test/CodeGen/X86/tailcall-stackalign.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686-unknown-linux -tailcallopt | grep -A 1 call | grep -A 1 tailcaller | grep subl | grep 12 +; RUN: llc < %s -mtriple=i686-unknown-linux -tailcallopt | FileCheck %s ; Linux has 8 byte alignment so the params cause stack size 20 when tailcallopt ; is enabled, ensure that a normal fastcc call has matching stack size @@ -19,6 +19,5 @@ define i32 @main(i32 %argc, i8** %argv) { ret i32 0 } - - - +; CHECK: call tailcaller +; CHECK-NEXT: subl $12 diff --git a/test/CodeGen/X86/trunc-to-bool.ll b/test/CodeGen/X86/trunc-to-bool.ll index 374d404a968c..bfab1aef9014 100644 --- a/test/CodeGen/X86/trunc-to-bool.ll +++ b/test/CodeGen/X86/trunc-to-bool.ll @@ -1,13 +1,13 @@ ; An integer truncation to i1 should be done with an and instruction to make ; sure only the LSBit survives. Test that this is the case both for a returned ; value and as the operand of a branch. -; RUN: llc < %s -march=x86 | grep {\\(and\\)\\|\\(test.*\\\$1\\)} | \ -; RUN: count 5 +; RUN: llc < %s -march=x86 | FileCheck %s define i1 @test1(i32 %X) zeroext { %Y = trunc i32 %X to i1 ret i1 %Y } +; CHECK: andl $1, %eax define i1 @test2(i32 %val, i32 %mask) { entry: @@ -20,6 +20,7 @@ ret_true: ret_false: ret i1 false } +; CHECK: testb $1, %al define i32 @test3(i8* %ptr) { %val = load i8* %ptr @@ -30,6 +31,7 @@ cond_true: cond_false: ret i32 42 } +; CHECK: testb $1, %al define i32 @test4(i8* %ptr) { %tmp = ptrtoint i8* %ptr to i1 @@ -39,6 +41,7 @@ cond_true: cond_false: ret i32 42 } +; CHECK: testb $1, %al define i32 @test6(double %d) { %tmp = fptosi double %d to i1 @@ -48,4 +51,4 @@ cond_true: cond_false: ret i32 42 } - +; CHECK: testb $1 |