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author	Dimitry Andric <dim@FreeBSD.org>	2017-02-25 14:40:33 +0000
committer	Dimitry Andric <dim@FreeBSD.org>	2017-02-25 14:40:33 +0000
commit	9c618dddcd075579cf4f157ba4a03d088c166dab (patch)
tree	25c9f5ba1aa4fdc4e96faae87aec82f1ad0b0a30 /test
parent	5a813558fccf203e1f8733f4c8217a03fd87b430 (diff)
download	src-9c618dddcd075579cf4f157ba4a03d088c166dab.tar.gz src-9c618dddcd075579cf4f157ba4a03d088c166dab.zip

vendor/llvm/llvm-release_40-r296202

Notes

Diffstat (limited to 'test')

-rw-r--r--

test/CodeGen/AMDGPU/trunc.ll

-rw-r--r--

test/Transforms/CorrelatedValuePropagation/add.ll

-rw-r--r--

test/Transforms/Reassociate/basictest.ll

-rw-r--r--

test/Transforms/SLPVectorizer/X86/horizontal-list.ll

158

4 files changed, 166 insertions, 105 deletions

diff --git a/test/CodeGen/AMDGPU/trunc.ll b/test/CodeGen/AMDGPU/trunc.ll
index 63bb447df2fd..2c2ce4c5d351 100644
--- a/test/CodeGen/AMDGPU/trunc.ll
+++ b/test/CodeGen/AMDGPU/trunc.ll

@@ -1,13 +1,15 @@

-; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s

+; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=SI %s

+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=VI %s

; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s

declare i32 @llvm.r600.read.tidig.x() nounwind readnone

define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {

-; SI-LABEL: {{^}}trunc_i64_to_i32_store:

-; SI: s_load_dword [[SLOAD:s[0-9]+]], s[0:1], 0xb

-; SI: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]

+; GCN-LABEL: {{^}}trunc_i64_to_i32_store:

+; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[0:1],

+; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]

; SI: buffer_store_dword [[VLOAD]]

+; VI: flat_store_dword v[{{[0-9:]+}}], [[VLOAD]]

; EG-LABEL: {{^}}trunc_i64_to_i32_store:

; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1

@@ -18,12 +20,14 @@ define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {

ret void

}

-; SI-LABEL: {{^}}trunc_load_shl_i64:

-; SI-DAG: s_load_dwordx2

-; SI-DAG: s_load_dword [[SREG:s[0-9]+]],

-; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2

-; SI: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]

-; SI: buffer_store_dword [[VSHL]],

+; GCN-LABEL: {{^}}trunc_load_shl_i64:

+; GCN-DAG: s_load_dwordx2

+; GCN-DAG: s_load_dword [[SREG:s[0-9]+]],

+; GCN: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2

+; GCN: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]

+; SI: buffer_store_dword [[VSHL]]

+; VI: flat_store_dword v[{{[0-9:]+}}], [[VSHL]]

define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {

%b = shl i64 %a, 2

%result = trunc i64 %b to i32

@@ -31,15 +35,17 @@ define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {

ret void

}

-; SI-LABEL: {{^}}trunc_shl_i64:

+; GCN-LABEL: {{^}}trunc_shl_i64:

; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd

-; SI: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2

-; SI: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],

-; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]

-; SI: s_addc_u32

+; VI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34

+; GCN: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2

+; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],

+; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]

+; GCN: s_addc_u32

; SI: buffer_store_dword v[[LO_VREG]],

-; SI: v_mov_b32_e32

+; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]]

+; GCN: v_mov_b32_e32

define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {

%aa = add i64 %a, 234 ; Prevent shrinking store.

%b = shl i64 %aa, 2

@@ -49,9 +55,9 @@ define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64

ret void

}

-; SI-LABEL: {{^}}trunc_i32_to_i1:

-; SI: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}

-; SI: v_cmp_eq_u32

+; GCN-LABEL: {{^}}trunc_i32_to_i1:

+; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}

+; GCN: v_cmp_eq_u32

define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {

%a = load i32, i32 addrspace(1)* %ptr, align 4

%trunc = trunc i32 %a to i1

@@ -60,9 +66,30 @@ define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {

ret void

}

-; SI-LABEL: {{^}}sgpr_trunc_i32_to_i1:

-; SI: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}

-; SI: v_cmp_eq_u32

+; GCN-LABEL: {{^}}trunc_i8_to_i1:

+; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}

+; GCN: v_cmp_eq_u32

+define void @trunc_i8_to_i1(i8 addrspace(1)* %out, i8 addrspace(1)* %ptr) {

+ %a = load i8, i8 addrspace(1)* %ptr, align 4

+ %trunc = trunc i8 %a to i1

+ %result = select i1 %trunc, i8 1, i8 0

+ store i8 %result, i8 addrspace(1)* %out, align 4

+ ret void

+; GCN-LABEL: {{^}}sgpr_trunc_i16_to_i1:

+; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}

+; GCN: v_cmp_eq_u32

+define void @sgpr_trunc_i16_to_i1(i16 addrspace(1)* %out, i16 %a) {

+ %trunc = trunc i16 %a to i1

+ %result = select i1 %trunc, i16 1, i16 0

+ store i16 %result, i16 addrspace(1)* %out, align 4

+ ret void

+; GCN-LABEL: {{^}}sgpr_trunc_i32_to_i1:

+; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}

+; GCN: v_cmp_eq_u32

define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {

%trunc = trunc i32 %a to i1

%result = select i1 %trunc, i32 1, i32 0

@@ -70,11 +97,12 @@ define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {

ret void

}

-; SI-LABEL: {{^}}s_trunc_i64_to_i1:

+; GCN-LABEL: {{^}}s_trunc_i64_to_i1:

; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb

-; SI: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]

-; SI: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}

-; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]

+; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x2c

+; GCN: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]

+; GCN: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}

+; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]

define void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) {

%trunc = trunc i64 %x to i1

%sel = select i1 %trunc, i32 63, i32 -12

@@ -82,11 +110,12 @@ define void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) {

ret void

}

-; SI-LABEL: {{^}}v_trunc_i64_to_i1:

+; GCN-LABEL: {{^}}v_trunc_i64_to_i1:

; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}

-; SI: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]

-; SI: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]

-; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc

+; VI: flat_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}

+; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]

+; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]

+; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc

define void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {

%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone

%gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid

diff --git a/test/Transforms/CorrelatedValuePropagation/add.ll b/test/Transforms/CorrelatedValuePropagation/add.ll
index 4b436ff9a401..0ba521c894e2 100644
--- a/test/Transforms/CorrelatedValuePropagation/add.ll
+++ b/test/Transforms/CorrelatedValuePropagation/add.ll

@@ -1,4 +1,4 @@

-; RUN: opt < %s -correlated-propagation -S | FileCheck %s

+; RUN: opt < %s -correlated-propagation -cvp-dont-process-adds=false -S | FileCheck %s

; CHECK-LABEL: @test0(

define void @test0(i32 %a) {

diff --git a/test/Transforms/Reassociate/basictest.ll b/test/Transforms/Reassociate/basictest.ll
index 11c67bea2cb0..4703fd7621b6 100644
--- a/test/Transforms/Reassociate/basictest.ll
+++ b/test/Transforms/Reassociate/basictest.ll

@@ -222,3 +222,23 @@ define i32 @test15(i32 %X1, i32 %X2, i32 %X3) {

; CHECK-LABEL: @test15

; CHECK: and i1 %A, %B

}

+; PR30256 - previously this asserted.

+; CHECK-LABEL: @test16

+; CHECK: %[[FACTOR:.*]] = mul i64 %a, -4

+; CHECK-NEXT: %[[RES:.*]] = add i64 %[[FACTOR]], %b

+; CHECK-NEXT: ret i64 %[[RES]]

+define i64 @test16(i1 %cmp, i64 %a, i64 %b) {

+entry:

+ %shl = shl i64 %a, 1

+ %shl.neg = sub i64 0, %shl

+ br i1 %cmp, label %if.then, label %if.end

+if.then: ; preds = %entry

+ %add1 = add i64 %shl.neg, %shl.neg

+ %add2 = add i64 %add1, %b

+ ret i64 %add2

+if.end: ; preds = %entry

+ ret i64 0

diff --git a/test/Transforms/SLPVectorizer/X86/horizontal-list.ll b/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
index 07064304bf01..3f9fffb9b624 100644
--- a/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
+++ b/test/Transforms/SLPVectorizer/X86/horizontal-list.ll

@@ -12,25 +12,26 @@ define float @baz() {

; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @n, align 4

; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP0]], 3

; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[MUL]] to float

-; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, <2 x float>* bitcast ([20 x float]* @arr to <2 x float>*), align 16

-; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, <2 x float>* bitcast ([20 x float]* @arr1 to <2 x float>*), align 16

-; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <2 x float> [[TMP2]], [[TMP1]]

-; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x float> [[TMP3]], i32 0

-; CHECK-NEXT: [[ADD:%.*]] = fadd fast float [[TMP4]], [[CONV]]

-; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x float> [[TMP3]], i32 1

-; CHECK-NEXT: [[ADD_1:%.*]] = fadd fast float [[TMP5]], [[ADD]]

-; CHECK-NEXT: [[TMP6:%.*]] = load <2 x float>, <2 x float>* bitcast (float* getelementptr inbounds ([20 x float], [20 x float]* @arr, i64 0, i64 2) to <2 x float>*), align 8

-; CHECK-NEXT: [[TMP7:%.*]] = load <2 x float>, <2 x float>* bitcast (float* getelementptr inbounds ([20 x float], [20 x float]* @arr1, i64 0, i64 2) to <2 x float>*), align 8

-; CHECK-NEXT: [[TMP8:%.*]] = fmul fast <2 x float> [[TMP7]], [[TMP6]]

-; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP8]], i32 0

-; CHECK-NEXT: [[ADD_2:%.*]] = fadd fast float [[TMP9]], [[ADD_1]]

-; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x float> [[TMP8]], i32 1

-; CHECK-NEXT: [[ADD_3:%.*]] = fadd fast float [[TMP10]], [[ADD_2]]

+; CHECK-NEXT: [[TMP1:%.*]] = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr, i64 0, i64 0), align 16

+; CHECK-NEXT: [[TMP2:%.*]] = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr1, i64 0, i64 0), align 16

+; CHECK-NEXT: [[MUL4:%.*]] = fmul fast float [[TMP2]], [[TMP1]]

+; CHECK-NEXT: [[ADD:%.*]] = fadd fast float [[MUL4]], [[CONV]]

+; CHECK-NEXT: [[TMP3:%.*]] = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr, i64 0, i64 1), align 4

+; CHECK-NEXT: [[TMP4:%.*]] = load float, float* getelementptr inbounds ([20 x float], [20 x float]* @arr1, i64 0, i64 1), align 4

+; CHECK-NEXT: [[MUL4_1:%.*]] = fmul fast float [[TMP4]], [[TMP3]]

+; CHECK-NEXT: [[ADD_1:%.*]] = fadd fast float [[MUL4_1]], [[ADD]]

+; CHECK-NEXT: [[TMP5:%.*]] = load <2 x float>, <2 x float>* bitcast (float* getelementptr inbounds ([20 x float], [20 x float]* @arr, i64 0, i64 2) to <2 x float>*), align 8

+; CHECK-NEXT: [[TMP6:%.*]] = load <2 x float>, <2 x float>* bitcast (float* getelementptr inbounds ([20 x float], [20 x float]* @arr1, i64 0, i64 2) to <2 x float>*), align 8

+; CHECK-NEXT: [[TMP7:%.*]] = fmul fast <2 x float> [[TMP6]], [[TMP5]]

+; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x float> [[TMP7]], i32 0

+; CHECK-NEXT: [[ADD_2:%.*]] = fadd fast float [[TMP8]], [[ADD_1]]

+; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x float> [[TMP7]], i32 1

+; CHECK-NEXT: [[ADD_3:%.*]] = fadd fast float [[TMP9]], [[ADD_2]]

; CHECK-NEXT: [[ADD7:%.*]] = fadd fast float [[ADD_3]], [[CONV]]

-; CHECK-NEXT: [[ADD19:%.*]] = fadd fast float [[TMP4]], [[ADD7]]

-; CHECK-NEXT: [[ADD19_1:%.*]] = fadd fast float [[TMP5]], [[ADD19]]

-; CHECK-NEXT: [[ADD19_2:%.*]] = fadd fast float [[TMP9]], [[ADD19_1]]

-; CHECK-NEXT: [[ADD19_3:%.*]] = fadd fast float [[TMP10]], [[ADD19_2]]

+; CHECK-NEXT: [[ADD19:%.*]] = fadd fast float [[MUL4]], [[ADD7]]

+; CHECK-NEXT: [[ADD19_1:%.*]] = fadd fast float [[MUL4_1]], [[ADD19]]

+; CHECK-NEXT: [[ADD19_2:%.*]] = fadd fast float [[TMP8]], [[ADD19_1]]

+; CHECK-NEXT: [[ADD19_3:%.*]] = fadd fast float [[TMP9]], [[ADD19_2]]

; CHECK-NEXT: store float [[ADD19_3]], float* @res, align 4

; CHECK-NEXT: ret float [[ADD19_3]]

;

@@ -69,37 +70,40 @@ define float @bazz() {