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Diffstat (limited to 'Bindings/clock/xlnx,versal-clk.yaml')
| -rw-r--r-- | Bindings/clock/xlnx,versal-clk.yaml | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/Bindings/clock/xlnx,versal-clk.yaml b/Bindings/clock/xlnx,versal-clk.yaml index 229af98b1d30..5cbb34d0b61b 100644 --- a/Bindings/clock/xlnx,versal-clk.yaml +++ b/Bindings/clock/xlnx,versal-clk.yaml @@ -7,9 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx Versal clock controller maintainers: - - Michal Simek <michal.simek@xilinx.com> - - Jolly Shah <jolly.shah@xilinx.com> - - Rajan Vaja <rajan.vaja@xilinx.com> + - Michal Simek <michal.simek@amd.com> description: | The clock controller is a hardware block of Xilinx versal clock tree. It |