diff options
Diffstat (limited to 'contrib/llvm-project/clang/lib/Basic/Targets')
37 files changed, 1109 insertions, 480 deletions
diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.cpp index f5a5d689fa09..63fc15f916c5 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.cpp @@ -11,9 +11,11 @@ //===----------------------------------------------------------------------===// #include "AArch64.h" +#include "clang/Basic/Diagnostic.h" #include "clang/Basic/LangOptions.h" #include "clang/Basic/TargetBuiltins.h" #include "clang/Basic/TargetInfo.h" +#include "llvm/ADT/APSInt.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -152,6 +154,7 @@ AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple, else LongWidth = LongAlign = PointerWidth = PointerAlign = 32; + BitIntMaxAlign = 128; MaxVectorAlign = 128; MaxAtomicInlineWidth = 128; MaxAtomicPromoteWidth = 128; @@ -186,6 +189,8 @@ AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple, assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); UseZeroLengthBitfieldAlignment = true; + HasUnalignedAccess = true; + // AArch64 targets default to using the ARM C++ ABI. TheCXXABI.set(TargetCXXABI::GenericAArch64); @@ -199,18 +204,47 @@ AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple, StringRef AArch64TargetInfo::getABI() const { return ABI; } bool AArch64TargetInfo::setABI(const std::string &Name) { - if (Name != "aapcs" && Name != "darwinpcs") + if (Name != "aapcs" && Name != "aapcs-soft" && Name != "darwinpcs" && + Name != "pauthtest") return false; ABI = Name; return true; } +bool AArch64TargetInfo::validateTarget(DiagnosticsEngine &Diags) const { + if (hasFeature("fp") && ABI == "aapcs-soft") { + // aapcs-soft is not allowed for targets with an FPU, to avoid there being + // two incomatible ABIs. + Diags.Report(diag::err_target_unsupported_abi_with_fpu) << ABI; + return false; + } + if (getTriple().getEnvironment() == llvm::Triple::PAuthTest && + getTriple().getOS() != llvm::Triple::Linux) { + Diags.Report(diag::err_target_unsupported_abi_for_triple) + << getTriple().getEnvironmentName() << getTriple().getTriple(); + return false; + } + return true; +} + +bool AArch64TargetInfo::validateGlobalRegisterVariable( + StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const { + if ((RegName == "sp") || RegName.starts_with("x")) { + HasSizeMismatch = RegSize != 64; + return true; + } else if (RegName.starts_with("w")) { + HasSizeMismatch = RegSize != 32; + return true; + } + return false; +} + bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef, BranchProtectionInfo &BPI, StringRef &Err) const { llvm::ARM::ParsedBranchProtection PBP; - if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err)) + if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err, HasPAuthLR)) return false; BPI.SignReturnAddr = @@ -231,7 +265,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef, } bool AArch64TargetInfo::isValidCPUName(StringRef Name) const { - return Name == "generic" || llvm::AArch64::parseCpu(Name); + return llvm::AArch64::parseCpu(Name).has_value(); } bool AArch64TargetInfo::setCPU(const std::string &Name) { @@ -271,7 +305,6 @@ void AArch64TargetInfo::getTargetDefinesARMV84A(const LangOptions &Opts, void AArch64TargetInfo::getTargetDefinesARMV85A(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__ARM_FEATURE_FRINT", "1"); - Builder.defineMacro("__ARM_FEATURE_BTI", "1"); // Also include the Armv8.4 defines getTargetDefinesARMV84A(Opts, Builder); } @@ -423,6 +456,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, if (HasSVE2) Builder.defineMacro("__ARM_FEATURE_SVE2", "1"); + if (HasSVE2p1) + Builder.defineMacro("__ARM_FEATURE_SVE2p1", "1"); + if (HasSVE2 && HasSVE2AES) Builder.defineMacro("__ARM_FEATURE_SVE2_AES", "1"); @@ -435,16 +471,25 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, if (HasSVE2 && HasSVE2SM4) Builder.defineMacro("__ARM_FEATURE_SVE2_SM4", "1"); + if (HasSVEB16B16) + Builder.defineMacro("__ARM_FEATURE_SVE_B16B16", "1"); + if (HasSME) { Builder.defineMacro("__ARM_FEATURE_SME"); Builder.defineMacro("__ARM_FEATURE_LOCALLY_STREAMING", "1"); } - if (HasSME2) { - Builder.defineMacro("__ARM_FEATURE_SME"); - Builder.defineMacro("__ARM_FEATURE_SME2"); - Builder.defineMacro("__ARM_FEATURE_LOCALLY_STREAMING", "1"); - } + if (HasSME2) + Builder.defineMacro("__ARM_FEATURE_SME2", "1"); + + if (HasSME2p1) + Builder.defineMacro("__ARM_FEATURE_SME2p1", "1"); + + if (HasSMEF16F16) + Builder.defineMacro("__ARM_FEATURE_SME_F16F16", "1"); + + if (HasSMEB16B16) + Builder.defineMacro("__ARM_FEATURE_SME_B16B16", "1"); if (HasCRC) Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); @@ -481,7 +526,13 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, if (HasPAuth) Builder.defineMacro("__ARM_FEATURE_PAUTH", "1"); - if (HasUnaligned) + if (HasPAuthLR) + Builder.defineMacro("__ARM_FEATURE_PAUTH_LR", "1"); + + if (HasBTI) + Builder.defineMacro("__ARM_FEATURE_BTI", "1"); + + if (HasUnalignedAccess) Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); if ((FPU & NeonMode) && HasFullFP16) @@ -532,6 +583,7 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, // 0: Protection using the A key // 1: Protection using the B key // 2: Protection including leaf functions + // 3: Protection using PC as a diversifier unsigned Value = 0; if (Opts.isSignReturnAddressWithAKey()) @@ -542,6 +594,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, if (Opts.isSignReturnAddressScopeAll()) Value |= (1 << 2); + if (Opts.BranchProtectionPAuthLR) + Value |= (1 << 3); + Builder.defineMacro("__ARM_FEATURE_PAC_DEFAULT", std::to_string(Value)); } @@ -637,37 +692,40 @@ AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const { unsigned AArch64TargetInfo::multiVersionSortPriority(StringRef Name) const { if (Name == "default") return 0; - if (auto Ext = llvm::AArch64::parseArchExtension(Name)) - return Ext->FmvPriority; + if (auto Ext = llvm::AArch64::parseFMVExtension(Name)) + return Ext->Priority; return 0; } unsigned AArch64TargetInfo::multiVersionFeatureCost() const { // Take the maximum priority as per feature cost, so more features win. - return llvm::AArch64::ExtensionInfo::MaxFMVPriority; + constexpr unsigned MaxFMVPriority = 1000; + return MaxFMVPriority; } bool AArch64TargetInfo::doesFeatureAffectCodeGen(StringRef Name) const { - if (auto Ext = llvm::AArch64::parseArchExtension(Name)) - return !Ext->DependentFeatures.empty(); + // FMV extensions which imply no backend features do not affect codegen. + if (auto Ext = llvm::AArch64::parseFMVExtension(Name)) + return !Ext->Features.empty(); return false; } -StringRef AArch64TargetInfo::getFeatureDependencies(StringRef Name) const { - if (auto Ext = llvm::AArch64::parseArchExtension(Name)) - return Ext->DependentFeatures; - return StringRef(); -} - bool AArch64TargetInfo::validateCpuSupports(StringRef FeatureStr) const { - return llvm::AArch64::parseArchExtension(FeatureStr).has_value(); + // CPU features might be separated by '+', extract them and check + llvm::SmallVector<StringRef, 8> Features; + FeatureStr.split(Features, "+"); + for (auto &Feature : Features) + if (!llvm::AArch64::parseFMVExtension(Feature.trim()).has_value()) + return false; + return true; } bool AArch64TargetInfo::hasFeature(StringRef Feature) const { return llvm::StringSwitch<bool>(Feature) .Cases("aarch64", "arm64", "arm", true) .Case("fmv", HasFMV) - .Cases("neon", "fp", "simd", FPU & NeonMode) + .Case("fp", FPU & FPUMode) + .Cases("neon", "simd", FPU & NeonMode) .Case("jscvt", HasJSCVT) .Case("fcma", HasFCMA) .Case("rng", HasRandGen) @@ -693,6 +751,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const { .Case("sve", FPU & SveMode) .Case("sve-bf16", FPU & SveMode && HasBFloat16) .Case("sve-i8mm", FPU & SveMode && HasMatMul) + .Case("sve-b16b16", HasSVEB16B16) .Case("f32mm", FPU & SveMode && HasMatmulFP32) .Case("f64mm", FPU & SveMode && HasMatmulFP64) .Case("sve2", FPU & SveMode && HasSVE2) @@ -700,11 +759,15 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const { .Case("sve2-bitperm", FPU & SveMode && HasSVE2BitPerm) .Case("sve2-sha3", FPU & SveMode && HasSVE2SHA3) .Case("sve2-sm4", FPU & SveMode && HasSVE2SM4) + .Case("sve2p1", FPU & SveMode && HasSVE2p1) .Case("sme", HasSME) .Case("sme2", HasSME2) + .Case("sme2p1", HasSME2p1) .Case("sme-f64f64", HasSMEF64F64) .Case("sme-i16i64", HasSMEI16I64) .Case("sme-fa64", HasSMEFA64) + .Case("sme-f16f16", HasSMEF16F16) + .Case("sme-b16b16", HasSMEB16B16) .Cases("memtag", "memtag2", HasMTE) .Case("sb", HasSB) .Case("predres", HasPredRes) @@ -777,6 +840,13 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasFullFP16 = true; HasSVE2 = true; } + if (Feature == "+sve2p1") { + FPU |= NeonMode; + FPU |= SveMode; + HasFullFP16 = true; + HasSVE2 = true; + HasSVE2p1 = true; + } if (Feature == "+sve2-aes") { FPU |= NeonMode; FPU |= SveMode; @@ -798,6 +868,8 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasSVE2 = true; HasSVE2SM4 = true; } + if (Feature == "+sve-b16b16") + HasSVEB16B16 = true; if (Feature == "+sve2-bitperm") { FPU |= NeonMode; FPU |= SveMode; @@ -828,6 +900,13 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasBFloat16 = true; HasFullFP16 = true; } + if (Feature == "+sme2p1") { + HasSME = true; + HasSME2 = true; + HasSME2p1 = true; + HasBFloat16 = true; + HasFullFP16 = true; + } if (Feature == "+sme-f64f64") { HasSME = true; HasSMEF64F64 = true; @@ -847,6 +926,21 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasSVE2 = true; HasSMEFA64 = true; } + if (Feature == "+sme-f16f16") { + HasSME = true; + HasSME2 = true; + HasBFloat16 = true; + HasFullFP16 = true; + HasSMEF16F16 = true; + } + if (Feature == "+sme-b16b16") { + HasSME = true; + HasSME2 = true; + HasBFloat16 = true; + HasFullFP16 = true; + HasSVEB16B16 = true; + HasSMEB16B16 = true; + } if (Feature == "+sb") HasSB = true; if (Feature == "+predres") @@ -895,7 +989,8 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasSM4 = true; } if (Feature == "+strict-align") - HasUnaligned = false; + HasUnalignedAccess = false; + // All predecessor archs are added but select the latest one for ArchKind. if (Feature == "+v8a" && ArchInfo->Version < llvm::AArch64::ARMV8A.Version) ArchInfo = &llvm::AArch64::ARMV8A; @@ -988,6 +1083,10 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasGCS = true; if (Feature == "+rcpc3") HasRCPC3 = true; + if (Feature == "+pauth-lr") { + HasPAuthLR = true; + HasPAuth = true; + } } // Check features that are manually disabled by command line options. @@ -1016,57 +1115,17 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, return true; } -bool AArch64TargetInfo::initFeatureMap( - llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, - const std::vector<std::string> &FeaturesVec) const { - std::vector<std::string> UpdatedFeaturesVec; - // Parse the CPU and add any implied features. - std::optional<llvm::AArch64::CpuInfo> CpuInfo = llvm::AArch64::parseCpu(CPU); - if (CpuInfo) { - auto Exts = CpuInfo->getImpliedExtensions(); - std::vector<StringRef> CPUFeats; - llvm::AArch64::getExtensionFeatures(Exts, CPUFeats); - for (auto F : CPUFeats) { - assert((F[0] == '+' || F[0] == '-') && "Expected +/- in target feature!"); - UpdatedFeaturesVec.push_back(F.str()); - } - } - - // Process target and dependent features. This is done in two loops collecting - // them into UpdatedFeaturesVec: first to add dependent '+'features, second to - // add target '+/-'features that can later disable some of features added on - // the first loop. Function Multi Versioning features begin with '?'. - for (const auto &Feature : FeaturesVec) - if (((Feature[0] == '?' || Feature[0] == '+')) && - AArch64TargetInfo::doesFeatureAffectCodeGen(Feature.substr(1))) { - StringRef DepFeatures = - AArch64TargetInfo::getFeatureDependencies(Feature.substr(1)); - SmallVector<StringRef, 1> AttrFeatures; - DepFeatures.split(AttrFeatures, ","); - for (auto F : AttrFeatures) - UpdatedFeaturesVec.push_back(F.str()); - } - for (const auto &Feature : FeaturesVec) - if (Feature[0] != '?') { - std::string UpdatedFeature = Feature; - if (Feature[0] == '+') { - std::optional<llvm::AArch64::ExtensionInfo> Extension = - llvm::AArch64::parseArchExtension(Feature.substr(1)); - if (Extension) - UpdatedFeature = Extension->Feature.str(); - } - UpdatedFeaturesVec.push_back(UpdatedFeature); - } - - return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); -} - // Parse AArch64 Target attributes, which are a comma separated list of: // "arch=<arch>" - parsed to features as per -march=.. // "cpu=<cpu>" - parsed to features as per -mcpu=.., with CPU set to <cpu> // "tune=<cpu>" - TuneCPU set to <cpu> // "feature", "no-feature" - Add (or remove) feature. // "+feature", "+nofeature" - Add (or remove) feature. +// +// A feature may correspond to an Extension (anything with a corresponding +// AEK_), in which case an ExtensionSet is used to parse it and expand its +// dependencies. If the feature does not yield a successful parse then it +// is passed through. ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { ParsedTargetAttr Ret; if (Features == "default") @@ -1076,23 +1135,31 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { bool FoundArch = false; auto SplitAndAddFeatures = [](StringRef FeatString, - std::vector<std::string> &Features) { + std::vector<std::string> &Features, + llvm::AArch64::ExtensionSet &FeatureBits) { SmallVector<StringRef, 8> SplitFeatures; FeatString.split(SplitFeatures, StringRef("+"), -1, false); for (StringRef Feature : SplitFeatures) { - StringRef FeatureName = llvm::AArch64::getArchExtFeature(Feature); - if (!FeatureName.empty()) - Features.push_back(FeatureName.str()); + if (FeatureBits.parseModifier(Feature)) + continue; + // Pass through anything that failed to parse so that we can emit + // diagnostics, as well as valid internal feature names. + // + // FIXME: We should consider rejecting internal feature names like + // neon, v8a, etc. + // FIXME: We should consider emitting diagnostics here. + if (Feature.starts_with("no")) + Features.push_back("-" + Feature.drop_front(2).str()); else - // Pushing the original feature string to give a sema error later on - // when they get checked. - if (Feature.starts_with("no")) - Features.push_back("-" + Feature.drop_front(2).str()); - else - Features.push_back("+" + Feature.str()); + Features.push_back("+" + Feature.str()); } }; + llvm::AArch64::ExtensionSet FeatureBits; + // Reconstruct the bitset from the command line option features. + FeatureBits.reconstructFromParsedFeatures(getTargetOpts().FeaturesAsWritten, + Ret.Features); + for (auto &Feature : AttrFeatures) { Feature = Feature.trim(); if (Feature.starts_with("fpmath=")) @@ -1115,9 +1182,9 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { // Ret.Features. if (!AI) continue; - Ret.Features.push_back(AI->ArchFeature.str()); + FeatureBits.addArchDefaults(*AI); // Add any extra features, after the + - SplitAndAddFeatures(Split.second, Ret.Features); + SplitAndAddFeatures(Split.second, Ret.Features, FeatureBits); } else if (Feature.starts_with("cpu=")) { if (!Ret.CPU.empty()) Ret.Duplicate = "cpu="; @@ -1127,7 +1194,10 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { std::pair<StringRef, StringRef> Split = Feature.split("=").second.trim().split("+"); Ret.CPU = Split.first; - SplitAndAddFeatures(Split.second, Ret.Features); + if (auto CpuInfo = llvm::AArch64::parseCpu(Ret.CPU)) { + FeatureBits.addCPUDefaults(*CpuInfo); + SplitAndAddFeatures(Split.second, Ret.Features, FeatureBits); + } } } else if (Feature.starts_with("tune=")) { if (!Ret.Tune.empty()) @@ -1135,25 +1205,23 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { else Ret.Tune = Feature.split("=").second.trim(); } else if (Feature.starts_with("+")) { - SplitAndAddFeatures(Feature, Ret.Features); - } else if (Feature.starts_with("no-")) { - StringRef FeatureName = - llvm::AArch64::getArchExtFeature(Feature.split("-").second); - if (!FeatureName.empty()) - Ret.Features.push_back("-" + FeatureName.drop_front(1).str()); - else - Ret.Features.push_back("-" + Feature.split("-").second.str()); + SplitAndAddFeatures(Feature, Ret.Features, FeatureBits); } else { - // Try parsing the string to the internal target feature name. If it is - // invalid, add the original string (which could already be an internal - // name). These should be checked later by isValidFeatureName. - StringRef FeatureName = llvm::AArch64::getArchExtFeature(Feature); - if (!FeatureName.empty()) - Ret.Features.push_back(FeatureName.str()); + if (FeatureBits.parseModifier(Feature, /* AllowNoDashForm = */ true)) + continue; + // Pass through anything that failed to parse so that we can emit + // diagnostics, as well as valid internal feature names. + // + // FIXME: We should consider rejecting internal feature names like + // neon, v8a, etc. + // FIXME: We should consider emitting diagnostics here. + if (Feature.starts_with("no-")) + Ret.Features.push_back("-" + Feature.drop_front(3).str()); else Ret.Features.push_back("+" + Feature.str()); } } + FeatureBits.toLLVMFeatureList(Ret.Features); return Ret; } @@ -1169,6 +1237,7 @@ AArch64TargetInfo::checkCallingConvention(CallingConv CC) const { case CC_SwiftAsync: case CC_PreserveMost: case CC_PreserveAll: + case CC_PreserveNone: case CC_OpenCLKernel: case CC_AArch64VectorCall: case CC_AArch64SVEPCS: @@ -1433,6 +1502,11 @@ int AArch64TargetInfo::getEHDataRegisterNumber(unsigned RegNo) const { return -1; } +bool AArch64TargetInfo::validatePointerAuthKey( + const llvm::APSInt &value) const { + return 0 <= value && value <= 3; +} + bool AArch64TargetInfo::hasInt128Type() const { return true; } AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple, @@ -1442,11 +1516,11 @@ AArch64leTargetInfo::AArch64leTargetInfo(const llvm::Triple &Triple, void AArch64leTargetInfo::setDataLayout() { if (getTriple().isOSBinFormatMachO()) { if(getTriple().isArch32Bit()) - resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128", "_"); + resetDataLayout("e-m:o-p:32:32-i64:64-i128:128-n32:64-S128-Fn32", "_"); else - resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128", "_"); + resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128-Fn32", "_"); } else - resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); + resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"); } void AArch64leTargetInfo::getTargetDefines(const LangOptions &Opts, @@ -1469,7 +1543,7 @@ void AArch64beTargetInfo::getTargetDefines(const LangOptions &Opts, void AArch64beTargetInfo::setDataLayout() { assert(!getTriple().isOSBinFormatMachO()); - resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); + resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"); } WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple, @@ -1492,8 +1566,8 @@ WindowsARM64TargetInfo::WindowsARM64TargetInfo(const llvm::Triple &Triple, void WindowsARM64TargetInfo::setDataLayout() { resetDataLayout(Triple.isOSBinFormatMachO() - ? "e-m:o-i64:64-i128:128-n32:64-S128" - : "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128", + ? "e-m:o-i64:64-i128:128-n32:64-S128-Fn32" + : "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128-Fn32", Triple.isOSBinFormatMachO() ? "_" : ""); } @@ -1505,15 +1579,19 @@ WindowsARM64TargetInfo::getBuiltinVaListKind() const { TargetInfo::CallingConvCheckResult WindowsARM64TargetInfo::checkCallingConvention(CallingConv CC) const { switch (CC) { + case CC_X86VectorCall: + if (getTriple().isWindowsArm64EC()) + return CCCR_OK; + return CCCR_Ignore; case CC_X86StdCall: case CC_X86ThisCall: case CC_X86FastCall: - case CC_X86VectorCall: return CCCR_Ignore; case CC_C: case CC_OpenCLKernel: case CC_PreserveMost: case CC_PreserveAll: + case CC_PreserveNone: case CC_Swift: case CC_SwiftAsync: case CC_Win64: @@ -1546,8 +1624,10 @@ MicrosoftARM64TargetInfo::getCallingConvKind(bool ClangABICompat4) const { return CCK_MicrosoftWin64; } -unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize) const { - unsigned Align = WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize); +unsigned MicrosoftARM64TargetInfo::getMinGlobalAlign(uint64_t TypeSize, + bool HasNonWeakDef) const { + unsigned Align = + WindowsARM64TargetInfo::getMinGlobalAlign(TypeSize, HasNonWeakDef); // MSVC does size based alignment for arm64 based on alignment section in // below document, replicate that to keep alignment consistent with object diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.h b/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.h index 9699222b0bf7..526f7f30a386 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/AArch64.h @@ -38,7 +38,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo { bool HasSHA2 = false; bool HasSHA3 = false; bool HasSM4 = false; - bool HasUnaligned = true; bool HasFullFP16 = false; bool HasDotProd = false; bool HasFP16FML = false; @@ -50,9 +49,11 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo { bool HasMatMul = false; bool HasBFloat16 = false; bool HasSVE2 = false; + bool HasSVE2p1 = false; bool HasSVE2AES = false; bool HasSVE2SHA3 = false; bool HasSVE2SM4 = false; + bool HasSVEB16B16 = false; bool HasSVE2BitPerm = false; bool HasMatmulFP64 = false; bool HasMatmulFP32 = false; @@ -71,6 +72,9 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo { bool HasSME2 = false; bool HasSMEF64F64 = false; bool HasSMEI16I64 = false; + bool HasSMEF16F16 = false; + bool HasSMEB16B16 = false; + bool HasSME2p1 = false; bool HasSB = false; bool HasPredRes = false; bool HasSSBS = false; @@ -85,6 +89,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo { bool HasGCS = false; bool HasRCPC3 = false; bool HasSMEFA64 = false; + bool HasPAuthLR = false; const llvm::AArch64::ArchInfo *ArchInfo = &llvm::AArch64::ARMV8A; @@ -107,10 +112,6 @@ public: unsigned multiVersionSortPriority(StringRef Name) const override; unsigned multiVersionFeatureCost() const override; - bool - initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, - StringRef CPU, - const std::vector<std::string> &FeaturesVec) const override; bool useFP16ConversionIntrinsics() const override { return false; } @@ -155,7 +156,6 @@ public: std::optional<std::pair<unsigned, unsigned>> getVScaleRange(const LangOptions &LangOpts) const override; bool doesFeatureAffectCodeGen(StringRef Name) const override; - StringRef getFeatureDependencies(StringRef Name) const override; bool validateCpuSupports(StringRef FeatureStr) const override; bool hasFeature(StringRef Feature) const override; void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, @@ -164,7 +164,7 @@ public: DiagnosticsEngine &Diags) override; ParsedTargetAttr parseTargetAttr(StringRef Str) const override; bool supportsTargetAttributeTune() const override { return true; } - + bool supportsCpuSupports() const override { return true; } bool checkArithmeticFenceSupported() const override { return true; } bool hasBFloat16Type() const override; @@ -194,10 +194,17 @@ public: int getEHDataRegisterNumber(unsigned RegNo) const override; + bool validatePointerAuthKey(const llvm::APSInt &value) const override; + const char *getBFloat16Mangling() const override { return "u6__bf16"; }; bool hasInt128Type() const override; bool hasBitIntType() const override { return true; } + + bool validateTarget(DiagnosticsEngine &Diags) const override; + + bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize, + bool &HasSizeMismatch) const override; }; class LLVM_LIBRARY_VISIBILITY AArch64leTargetInfo : public AArch64TargetInfo { @@ -237,7 +244,8 @@ public: TargetInfo::CallingConvKind getCallingConvKind(bool ClangABICompat4) const override; - unsigned getMinGlobalAlign(uint64_t TypeSize) const override; + unsigned getMinGlobalAlign(uint64_t TypeSize, + bool HasNonWeakDef) const override; }; // ARM64 MinGW target diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/AMDGPU.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/AMDGPU.cpp index 6f3a4908623d..3b748d0249d5 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/AMDGPU.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/AMDGPU.cpp @@ -17,6 +17,7 @@ #include "clang/Basic/LangOptions.h" #include "clang/Basic/MacroBuilder.h" #include "clang/Basic/TargetBuiltins.h" +#include "llvm/ADT/SmallString.h" using namespace clang; using namespace clang::targets; @@ -186,9 +187,15 @@ bool AMDGPUTargetInfo::initFeatureMap( return false; // TODO: Should move this logic into TargetParser - std::string ErrorMsg; - if (!insertWaveSizeFeature(CPU, getTriple(), Features, ErrorMsg)) { - Diags.Report(diag::err_invalid_feature_combination) << ErrorMsg; + auto HasError = insertWaveSizeFeature(CPU, getTriple(), Features); + switch (HasError.first) { + default: + break; + case llvm::AMDGPU::INVALID_FEATURE_COMBINATION: + Diags.Report(diag::err_invalid_feature_combination) << HasError.second; + return false; + case llvm::AMDGPU::UNSUPPORTED_TARGET_FEATURE: + Diags.Report(diag::err_opt_not_valid_on_target) << HasError.second; return false; } @@ -231,7 +238,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple, HasLegalHalfType = true; HasFloat16 = true; - WavefrontSize = GPUFeatures & llvm::AMDGPU::FEATURE_WAVE32 ? 32 : 64; + WavefrontSize = (GPUFeatures & llvm::AMDGPU::FEATURE_WAVE32) ? 32 : 64; AllowAMDGPUUnsafeFPAtomics = Opts.AllowAMDGPUUnsafeFPAtomics; // Set pointer width and alignment for the generic address space. @@ -274,30 +281,42 @@ void AMDGPUTargetInfo::getTargetDefines(const LangOptions &Opts, else Builder.defineMacro("__R600__"); - if (GPUKind != llvm::AMDGPU::GK_NONE) { - StringRef CanonName = isAMDGCN(getTriple()) ? - getArchNameAMDGCN(GPUKind) : getArchNameR600(GPUKind); - Builder.defineMacro(Twine("__") + Twine(CanonName) + Twine("__")); - // Emit macros for gfx family e.g. gfx906 -> __GFX9__, gfx1030 -> __GFX10___ - if (isAMDGCN(getTriple())) { - assert(CanonName.starts_with("gfx") && "Invalid amdgcn canonical name"); - Builder.defineMacro(Twine("__") + Twine(CanonName.drop_back(2).upper()) + - Twine("__")); - } - if (isAMDGCN(getTriple())) { - Builder.defineMacro("__amdgcn_processor__", - Twine("\"") + Twine(CanonName) + Twine("\"")); - Builder.defineMacro("__amdgcn_target_id__", - Twine("\"") + Twine(*getTargetID()) + Twine("\"")); - for (auto F : getAllPossibleTargetIDFeatures(getTriple(), CanonName)) { - auto Loc = OffloadArchFeatures.find(F); - if (Loc != OffloadArchFeatures.end()) { - std::string NewF = F.str(); - std::replace(NewF.begin(), NewF.end(), '-', '_'); - Builder.defineMacro(Twine("__amdgcn_feature_") + Twine(NewF) + - Twine("__"), - Loc->second ? "1" : "0"); - } + // Legacy HIP host code relies on these default attributes to be defined. + bool IsHIPHost = Opts.HIP && !Opts.CUDAIsDevice; + if (GPUKind == llvm::AMDGPU::GK_NONE && !IsHIPHost) + return; + + llvm::SmallString<16> CanonName = + (isAMDGCN(getTriple()) ? getArchNameAMDGCN(GPUKind) + : getArchNameR600(GPUKind)); + + // Sanitize the name of generic targets. + // e.g. gfx10-1-generic -> gfx10_1_generic + if (GPUKind >= llvm::AMDGPU::GK_AMDGCN_GENERIC_FIRST && + GPUKind <= llvm::AMDGPU::GK_AMDGCN_GENERIC_LAST) { + std::replace(CanonName.begin(), CanonName.end(), '-', '_'); + } + + Builder.defineMacro(Twine("__") + Twine(CanonName) + Twine("__")); + // Emit macros for gfx family e.g. gfx906 -> __GFX9__, gfx1030 -> __GFX10___ + if (isAMDGCN(getTriple()) && !IsHIPHost) { + assert(StringRef(CanonName).starts_with("gfx") && + "Invalid amdgcn canonical name"); + StringRef CanonFamilyName = getArchFamilyNameAMDGCN(GPUKind); + Builder.defineMacro(Twine("__") + Twine(CanonFamilyName.upper()) + + Twine("__")); + Builder.defineMacro("__amdgcn_processor__", + Twine("\"") + Twine(CanonName) + Twine("\"")); + Builder.defineMacro("__amdgcn_target_id__", + Twine("\"") + Twine(*getTargetID()) + Twine("\"")); + for (auto F : getAllPossibleTargetIDFeatures(getTriple(), CanonName)) { + auto Loc = OffloadArchFeatures.find(F); + if (Loc != OffloadArchFeatures.end()) { + std::string NewF = F.str(); + std::replace(NewF.begin(), NewF.end(), '-', '_'); + Builder.defineMacro(Twine("__amdgcn_feature_") + Twine(NewF) + + Twine("__"), + Loc->second ? "1" : "0"); } } } diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/AMDGPU.h b/contrib/llvm-project/clang/lib/Basic/Targets/AMDGPU.h index 90a1516ecdd2..94d9ba93ed22 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/AMDGPU.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/AMDGPU.h @@ -168,9 +168,7 @@ public: return true; } - bool HasLeftParen = false; - if (S.consume_front("{")) - HasLeftParen = true; + bool HasLeftParen = S.consume_front("{"); if (S.empty()) return false; if (S.front() != 'v' && S.front() != 's' && S.front() != 'a') { @@ -196,9 +194,7 @@ public: Name = S.data() - 1; return true; } - bool HasLeftBracket = false; - if (S.consume_front("[")) - HasLeftBracket = true; + bool HasLeftBracket = S.consume_front("["); unsigned long long N; if (S.empty() || consumeUnsignedInteger(S, 10, N)) return false; @@ -418,8 +414,10 @@ public: // value ~0. uint64_t getNullPointerValue(LangAS AS) const override { // FIXME: Also should handle region. - return (AS == LangAS::opencl_local || AS == LangAS::opencl_private) - ? ~0 : 0; + return (AS == LangAS::opencl_local || AS == LangAS::opencl_private || + AS == LangAS::sycl_local || AS == LangAS::sycl_private) + ? ~0 + : 0; } void setAuxTarget(const TargetInfo *Aux) override; diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/ARM.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/ARM.cpp index 55b71557452f..e55feedbd5c6 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/ARM.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/ARM.cpp @@ -173,8 +173,7 @@ bool ARMTargetInfo::supportsThumb() const { } bool ARMTargetInfo::supportsThumb2() const { - return CPUAttr.equals("6T2") || - (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); + return CPUAttr == "6T2" || (ArchVersion >= 7 && CPUAttr != "8M_BASE"); } StringRef ARMTargetInfo::getCPUAttr() const { @@ -312,7 +311,9 @@ ARMTargetInfo::ARMTargetInfo(const llvm::Triple &Triple, switch (Triple.getEnvironment()) { case llvm::Triple::Android: case llvm::Triple::GNUEABI: + case llvm::Triple::GNUEABIT64: case llvm::Triple::GNUEABIHF: + case llvm::Triple::GNUEABIHFT64: case llvm::Triple::MuslEABI: case llvm::Triple::MuslEABIHF: case llvm::Triple::OpenHOS: @@ -509,7 +510,7 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, SHA2 = 0; AES = 0; DSP = 0; - Unaligned = 1; + HasUnalignedAccess = true; SoftFloat = false; // Note that SoftFloatABI is initialized in our constructor. HWDiv = 0; @@ -576,7 +577,7 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, return false; } } else if (Feature == "+strict-align") { - Unaligned = 0; + HasUnalignedAccess = false; } else if (Feature == "+fp16") { HW_FP |= HW_FP_HP; } else if (Feature == "+fullfp16") { @@ -785,7 +786,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); // ACLE 6.4.3 Unaligned access supported in hardware - if (Unaligned) + if (HasUnalignedAccess) Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); // ACLE 6.4.4 LDREX/STREX @@ -1162,7 +1163,7 @@ bool ARMTargetInfo::validateAsmConstraint( return true; case 'j': // An immediate integer between 0 and 65535 (valid for MOVW) // only available in ARMv6T2 and above - if (CPUAttr.equals("6T2") || ArchVersion >= 7) { + if (CPUAttr == "6T2" || ArchVersion >= 7) { Info.setRequiresImmediate(0, 65535); return true; } diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/ARM.h b/contrib/llvm-project/clang/lib/Basic/Targets/ARM.h index 9802eb01abf3..df9855a52e61 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/ARM.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/ARM.h @@ -61,26 +61,41 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public TargetInfo { llvm::ARM::ProfileKind ArchProfile; unsigned ArchVersion; + LLVM_PREFERRED_TYPE(FPUMode) unsigned FPU : 5; + LLVM_PREFERRED_TYPE(MVEMode) unsigned MVE : 2; + LLVM_PREFERRED_TYPE(bool) unsigned IsAAPCS : 1; + LLVM_PREFERRED_TYPE(HWDivMode) unsigned HWDiv : 2; // Initialized via features. + LLVM_PREFERRED_TYPE(bool) unsigned SoftFloat : 1; + LLVM_PREFERRED_TYPE(bool) unsigned SoftFloatABI : 1; + LLVM_PREFERRED_TYPE(bool) unsigned CRC : 1; + LLVM_PREFERRED_TYPE(bool) unsigned Crypto : 1; + LLVM_PREFERRED_TYPE(bool) unsigned SHA2 : 1; + LLVM_PREFERRED_TYPE(bool) unsigned AES : 1; + LLVM_PREFERRED_TYPE(bool) unsigned DSP : 1; - unsigned Unaligned : 1; + LLVM_PREFERRED_TYPE(bool) unsigned DotProd : 1; + LLVM_PREFERRED_TYPE(bool) unsigned HasMatMul : 1; + LLVM_PREFERRED_TYPE(bool) unsigned FPRegsDisabled : 1; + LLVM_PREFERRED_TYPE(bool) unsigned HasPAC : 1; + LLVM_PREFERRED_TYPE(bool) unsigned HasBTI : 1; enum { @@ -210,6 +225,10 @@ public: bool hasBitIntType() const override { return true; } const char *getBFloat16Mangling() const override { return "u6__bf16"; }; + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(getTriple().isArch64Bit() ? 256 : 64, 64); + } }; class LLVM_LIBRARY_VISIBILITY ARMleTargetInfo : public ARMTargetInfo { diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/AVR.h b/contrib/llvm-project/clang/lib/Basic/Targets/AVR.h index 9376c46cd98c..feeb04f37eeb 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/AVR.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/AVR.h @@ -175,6 +175,10 @@ public: std::optional<std::string> handleAsmEscapedChar(char EscChar) const override; StringRef getABI() const override { return ABI; } + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } + protected: std::string CPU; StringRef ABI; diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/BPF.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/BPF.cpp index e713e0847922..b5ba11a3bdca 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/BPF.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/BPF.cpp @@ -22,7 +22,7 @@ using namespace clang::targets; static constexpr Builtin::Info BuiltinInfo[] = { #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, -#include "clang/Basic/BuiltinsBPF.def" +#include "clang/Basic/BuiltinsBPF.inc" }; void BPFTargetInfo::getTargetDefines(const LangOptions &Opts, @@ -35,6 +35,9 @@ void BPFTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__BPF_CPU_VERSION__", "0"); return; } + + Builder.defineMacro("__BPF_FEATURE_ADDR_SPACE_CAST"); + if (CPU.empty() || CPU == "generic" || CPU == "v1") { Builder.defineMacro("__BPF_CPU_VERSION__", "1"); return; @@ -42,6 +45,7 @@ void BPFTargetInfo::getTargetDefines(const LangOptions &Opts, std::string CpuVerNumStr = CPU.substr(1); Builder.defineMacro("__BPF_CPU_VERSION__", CpuVerNumStr); + Builder.defineMacro("__BPF_FEATURE_MAY_GOTO"); int CpuVerNum = std::stoi(CpuVerNumStr); if (CpuVerNum >= 2) diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/BPF.h b/contrib/llvm-project/clang/lib/Basic/Targets/BPF.h index 489f29fc4fea..d19b37dd4df7 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/BPF.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/BPF.h @@ -113,6 +113,10 @@ public: StringRef CPUName(Name); return isValidCPUName(CPUName); } + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; } // namespace targets } // namespace clang diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/CSKY.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/CSKY.cpp index 851f27dbb1e5..c8bf8b9234d2 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/CSKY.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/CSKY.cpp @@ -308,7 +308,8 @@ bool CSKYTargetInfo::validateAsmConstraint( } } -unsigned CSKYTargetInfo::getMinGlobalAlign(uint64_t Size) const { +unsigned CSKYTargetInfo::getMinGlobalAlign(uint64_t Size, + bool HasNonWeakDef) const { if (Size >= 32) return 32; return 0; diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/CSKY.h b/contrib/llvm-project/clang/lib/Basic/Targets/CSKY.h index 11404e37db36..94d4eeb9a1ff 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/CSKY.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/CSKY.h @@ -71,7 +71,7 @@ public: bool isValidCPUName(StringRef Name) const override; - unsigned getMinGlobalAlign(uint64_t) const override; + unsigned getMinGlobalAlign(uint64_t, bool HasNonWeakDef) const override; ArrayRef<Builtin::Info> getTargetBuiltins() const override; diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/DirectX.h b/contrib/llvm-project/clang/lib/Basic/Targets/DirectX.h index acfcc8c47ba9..a084e2823453 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/DirectX.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/DirectX.h @@ -53,7 +53,6 @@ public: : TargetInfo(Triple) { TLSSupported = false; VLASupported = false; - LongWidth = LongAlign = 64; AddrSpaceMap = &DirectXAddrSpaceMap; UseAddrSpaceMapMangling = true; HasLegalHalfType = true; diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/Hexagon.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/Hexagon.cpp index ac747e371fb4..0282ac812c30 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/Hexagon.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/Hexagon.cpp @@ -238,6 +238,18 @@ static constexpr CPUSuffix Suffixes[] = { {{"hexagonv73"}, {"73"}}, }; +std::optional<unsigned> HexagonTargetInfo::getHexagonCPURev(StringRef Name) { + StringRef Arch = Name; + Arch.consume_front("hexagonv"); + Arch.consume_back("t"); + + unsigned Val; + if (!Arch.getAsInteger(0, Val)) + return Val; + + return std::nullopt; +} + const char *HexagonTargetInfo::getHexagonCPUSuffix(StringRef Name) { const CPUSuffix *Item = llvm::find_if( Suffixes, [Name](const CPUSuffix &S) { return S.Name == Name; }); diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/Hexagon.h b/contrib/llvm-project/clang/lib/Basic/Targets/Hexagon.h index cdb47dbae799..7f053ab7e488 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/Hexagon.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/Hexagon.h @@ -17,6 +17,7 @@ #include "clang/Basic/TargetOptions.h" #include "llvm/Support/Compiler.h" #include "llvm/TargetParser/Triple.h" +#include <optional> namespace clang { namespace targets { @@ -115,6 +116,7 @@ public: std::string_view getClobbers() const override { return ""; } static const char *getHexagonCPUSuffix(StringRef Name); + static std::optional<unsigned> getHexagonCPURev(StringRef Name); bool isValidCPUName(StringRef Name) const override { return getHexagonCPUSuffix(Name); @@ -139,6 +141,14 @@ public: } bool hasBitIntType() const override { return true; } + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + std::optional<unsigned> Rev = getHexagonCPURev(CPU); + + // V73 and later have 64-byte cache lines. + unsigned CacheLineSizeBytes = Rev >= 73U ? 64 : 32; + return std::make_pair(CacheLineSizeBytes, CacheLineSizeBytes); + } }; } // namespace targets } // namespace clang diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/LoongArch.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/LoongArch.cpp index 88537989a051..cb3fd12c48dd 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/LoongArch.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/LoongArch.cpp @@ -200,7 +200,24 @@ void LoongArchTargetInfo::getTargetDefines(const LangOptions &Opts, // Define __loongarch_arch. StringRef ArchName = getCPU(); - Builder.defineMacro("__loongarch_arch", Twine('"') + ArchName + Twine('"')); + if (ArchName == "loongarch64") { + if (HasFeatureLSX) { + // TODO: As more features of the V1.1 ISA are supported, a unified "v1.1" + // arch feature set will be used to include all sub-features belonging to + // the V1.1 ISA version. + if (HasFeatureFrecipe) + Builder.defineMacro("__loongarch_arch", + Twine('"') + "la64v1.1" + Twine('"')); + else + Builder.defineMacro("__loongarch_arch", + Twine('"') + "la64v1.0" + Twine('"')); + } else { + Builder.defineMacro("__loongarch_arch", + Twine('"') + ArchName + Twine('"')); + } + } else { + Builder.defineMacro("__loongarch_arch", Twine('"') + ArchName + Twine('"')); + } // Define __loongarch_tune. StringRef TuneCPU = getTargetOpts().TuneCPU; @@ -208,10 +225,16 @@ void LoongArchTargetInfo::getTargetDefines(const LangOptions &Opts, TuneCPU = ArchName; Builder.defineMacro("__loongarch_tune", Twine('"') + TuneCPU + Twine('"')); - if (HasFeatureLSX) + if (HasFeatureLASX) { + Builder.defineMacro("__loongarch_simd_width", "256"); Builder.defineMacro("__loongarch_sx", Twine(1)); - if (HasFeatureLASX) Builder.defineMacro("__loongarch_asx", Twine(1)); + } else if (HasFeatureLSX) { + Builder.defineMacro("__loongarch_simd_width", "128"); + Builder.defineMacro("__loongarch_sx", Twine(1)); + } + if (HasFeatureFrecipe) + Builder.defineMacro("__loongarch_frecipe", Twine(1)); StringRef ABI = getABI(); if (ABI == "lp64d" || ABI == "lp64f" || ABI == "lp64s") @@ -285,6 +308,10 @@ bool LoongArchTargetInfo::handleTargetFeatures( HasFeatureLSX = true; else if (Feature == "+lasx") HasFeatureLASX = true; + else if (Feature == "-ual") + HasUnalignedAccess = false; + else if (Feature == "+frecipe") + HasFeatureFrecipe = true; } return true; } diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/LoongArch.h b/contrib/llvm-project/clang/lib/Basic/Targets/LoongArch.h index 3313102492cb..c668ca7eca04 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/LoongArch.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/LoongArch.h @@ -29,6 +29,7 @@ protected: bool HasFeatureF; bool HasFeatureLSX; bool HasFeatureLASX; + bool HasFeatureFrecipe; public: LoongArchTargetInfo(const llvm::Triple &Triple, const TargetOptions &) @@ -37,6 +38,7 @@ public: HasFeatureF = false; HasFeatureLSX = false; HasFeatureLASX = false; + HasFeatureFrecipe = false; LongDoubleWidth = 128; LongDoubleAlign = 128; LongDoubleFormat = &llvm::APFloat::IEEEquad(); @@ -132,7 +134,8 @@ public: : LoongArchTargetInfo(Triple, Opts) { LongWidth = LongAlign = PointerWidth = PointerAlign = 64; IntMaxType = Int64Type = SignedLong; - resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n64-S128"); + HasUnalignedAccess = true; + resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"); // TODO: select appropriate ABI. setABI("lp64d"); } diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/M68k.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/M68k.cpp index 1b7e0a7f32c9..8b8bf97d6f99 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/M68k.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/M68k.cpp @@ -127,16 +127,21 @@ bool M68kTargetInfo::hasFeature(StringRef Feature) const { const char *const M68kTargetInfo::GCCRegNames[] = { "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", - "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", + "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", "pc"}; ArrayRef<const char *> M68kTargetInfo::getGCCRegNames() const { return llvm::ArrayRef(GCCRegNames); } +const TargetInfo::GCCRegAlias M68kTargetInfo::GCCRegAliases[] = { + {{"bp"}, "a5"}, + {{"fp"}, "a6"}, + {{"usp", "ssp", "isp", "a7"}, "sp"}, +}; + ArrayRef<TargetInfo::GCCRegAlias> M68kTargetInfo::getGCCRegAliases() const { - // No aliases. - return std::nullopt; + return llvm::ArrayRef(GCCRegAliases); } bool M68kTargetInfo::validateAsmConstraint( diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/M68k.h b/contrib/llvm-project/clang/lib/Basic/Targets/M68k.h index a9c262e62fba..b732add77e03 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/M68k.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/M68k.h @@ -25,6 +25,7 @@ namespace targets { class LLVM_LIBRARY_VISIBILITY M68kTargetInfo : public TargetInfo { static const char *const GCCRegNames[]; + static const TargetInfo::GCCRegAlias GCCRegAliases[]; enum CPUKind { CK_Unknown, @@ -55,6 +56,10 @@ public: BuiltinVaListKind getBuiltinVaListKind() const override; bool setCPU(const std::string &Name) override; CallingConvCheckResult checkCallingConvention(CallingConv CC) const override; + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; } // namespace targets diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/Mips.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/Mips.cpp index 3a65f53c5248..174bc9d2ab99 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/Mips.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/Mips.cpp @@ -273,6 +273,34 @@ bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const { Diags.Report(diag::err_mips_fp64_req) << "-mfp64"; return false; } + // FPXX requires mips2+ + if (FPMode == FPXX && CPU == "mips1") { + Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU; + return false; + } + // -mmsa with -msoft-float makes nonsense + if (FloatABI == SoftFloat && HasMSA) { + Diags.Report(diag::err_opt_not_valid_with_opt) << "-msoft-float" + << "-mmsa"; + return false; + } + // Option -mmsa permitted on Mips32 iff revision 2 or higher is present + if (HasMSA && (CPU == "mips1" || CPU == "mips2" || getISARev() < 2) && + ABI == "o32") { + Diags.Report(diag::err_mips_fp64_req) << "-mmsa"; + return false; + } + // MSA requires FP64 + if (FPMode == FPXX && HasMSA) { + Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" + << "-mmsa"; + return false; + } + if (FPMode == FP32 && HasMSA) { + Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" + << "-mmsa"; + return false; + } return true; } diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/Mips.h b/contrib/llvm-project/clang/lib/Basic/Targets/Mips.h index 23d4e1b598fa..b6f110249fa7 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/Mips.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/Mips.h @@ -85,8 +85,13 @@ public: return CPU == "mips32r6" || CPU == "mips64r6"; } - bool isFP64Default() const { - return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; + enum FPModeEnum getDefaultFPMode() const { + if (CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64") + return FP64; + else if (CPU == "mips1") + return FP32; + else + return FPXX; } bool isNan2008() const override { return IsNan2008; } @@ -315,9 +320,11 @@ public: IsSingleFloat = false; FloatABI = HardFloat; DspRev = NoDSP; - FPMode = isFP64Default() ? FP64 : FPXX; NoOddSpreg = false; + FPMode = getDefaultFPMode(); bool OddSpregGiven = false; + bool StrictAlign = false; + bool FpGiven = false; for (const auto &Feature : Features) { if (Feature == "+single-float") @@ -328,6 +335,12 @@ public: IsMips16 = true; else if (Feature == "+micromips") IsMicromips = true; + else if (Feature == "+mips32r6" || Feature == "+mips64r6") + HasUnalignedAccess = true; + // We cannot be sure that the order of strict-align vs mips32r6. + // Thus we need an extra variable here. + else if (Feature == "+strict-align") + StrictAlign = true; else if (Feature == "+dsp") DspRev = std::max(DspRev, DSP1); else if (Feature == "+dspr2") @@ -336,13 +349,16 @@ public: HasMSA = true; else if (Feature == "+nomadd4") DisableMadd4 = true; - else if (Feature == "+fp64") + else if (Feature == "+fp64") { FPMode = FP64; - else if (Feature == "-fp64") + FpGiven = true; + } else if (Feature == "-fp64") { FPMode = FP32; - else if (Feature == "+fpxx") + FpGiven = true; + } else if (Feature == "+fpxx") { FPMode = FPXX; - else if (Feature == "+nan2008") + FpGiven = true; + } else if (Feature == "+nan2008") IsNan2008 = true; else if (Feature == "-nan2008") IsNan2008 = false; @@ -366,6 +382,14 @@ public: if (FPMode == FPXX && !OddSpregGiven) NoOddSpreg = true; + if (StrictAlign) + HasUnalignedAccess = false; + + if (HasMSA && !FpGiven) { + FPMode = FP64; + Features.push_back("+fp64"); + } + setDataLayout(); return true; @@ -421,6 +445,10 @@ public: bool validateTarget(DiagnosticsEngine &Diags) const override; bool hasBitIntType() const override { return true; } + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; } // namespace targets } // namespace clang diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/NVPTX.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/NVPTX.cpp index c0b5db795e27..43b653dc52ce 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/NVPTX.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/NVPTX.cpp @@ -59,7 +59,11 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple, // Define available target features // These must be defined in sorted order! NoAsmVariants = true; - GPU = CudaArch::SM_20; + GPU = OffloadArch::UNUSED; + + // PTX supports f16 as a fundamental type. + HasLegalHalfType = true; + HasFloat16 = true; if (TargetPointerWidth == 32) resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"); @@ -115,7 +119,8 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple, LongAlign = HostTarget->getLongAlign(); LongLongWidth = HostTarget->getLongLongWidth(); LongLongAlign = HostTarget->getLongLongAlign(); - MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0); + MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0, + /* HasNonWeakDef = */ true); NewAlign = HostTarget->getNewAlign(); DefaultAlignForAttributeAligned = HostTarget->getDefaultAlignForAttributeAligned(); @@ -168,107 +173,119 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__PTX__"); Builder.defineMacro("__NVPTX__"); + + // Skip setting architecture dependent macros if undefined. + if (GPU == OffloadArch::UNUSED && !HostTarget) + return; + if (Opts.CUDAIsDevice || Opts.OpenMPIsTargetDevice || !HostTarget) { // Set __CUDA_ARCH__ for the GPU specified. std::string CUDAArchCode = [this] { switch (GPU) { - case CudaArch::GFX600: - case CudaArch::GFX601: - case CudaArch::GFX602: - case CudaArch::GFX700: - case CudaArch::GFX701: - case CudaArch::GFX702: - case CudaArch::GFX703: - case CudaArch::GFX704: - case CudaArch::GFX705: - case CudaArch::GFX801: - case CudaArch::GFX802: - case CudaArch::GFX803: - case CudaArch::GFX805: - case CudaArch::GFX810: - case CudaArch::GFX900: - case CudaArch::GFX902: - case CudaArch::GFX904: - case CudaArch::GFX906: - case CudaArch::GFX908: - case CudaArch::GFX909: - case CudaArch::GFX90a: - case CudaArch::GFX90c: - case CudaArch::GFX940: - case CudaArch::GFX941: - case CudaArch::GFX942: - case CudaArch::GFX1010: - case CudaArch::GFX1011: - case CudaArch::GFX1012: - case CudaArch::GFX1013: - case CudaArch::GFX1030: - case CudaArch::GFX1031: - case CudaArch::GFX1032: - case CudaArch::GFX1033: - case CudaArch::GFX1034: - case CudaArch::GFX1035: - case CudaArch::GFX1036: - case CudaArch::GFX1100: - case CudaArch::GFX1101: - case CudaArch::GFX1102: - case CudaArch::GFX1103: - case CudaArch::GFX1150: - case CudaArch::GFX1151: - case CudaArch::GFX1200: - case CudaArch::GFX1201: - case CudaArch::Generic: - case CudaArch::LAST: + case OffloadArch::GFX600: + case OffloadArch::GFX601: + case OffloadArch::GFX602: + case OffloadArch::GFX700: + case OffloadArch::GFX701: + case OffloadArch::GFX702: + case OffloadArch::GFX703: + case OffloadArch::GFX704: + case OffloadArch::GFX705: + case OffloadArch::GFX801: + case OffloadArch::GFX802: + case OffloadArch::GFX803: + case OffloadArch::GFX805: + case OffloadArch::GFX810: + case OffloadArch::GFX9_GENERIC: + case OffloadArch::GFX900: + case OffloadArch::GFX902: + case OffloadArch::GFX904: + case OffloadArch::GFX906: + case OffloadArch::GFX908: + case OffloadArch::GFX909: + case OffloadArch::GFX90a: + case OffloadArch::GFX90c: + case OffloadArch::GFX940: + case OffloadArch::GFX941: + case OffloadArch::GFX942: + case OffloadArch::GFX10_1_GENERIC: + case OffloadArch::GFX1010: + case OffloadArch::GFX1011: + case OffloadArch::GFX1012: + case OffloadArch::GFX1013: + case OffloadArch::GFX10_3_GENERIC: + case OffloadArch::GFX1030: + case OffloadArch::GFX1031: + case OffloadArch::GFX1032: + case OffloadArch::GFX1033: + case OffloadArch::GFX1034: + case OffloadArch::GFX1035: + case OffloadArch::GFX1036: + case OffloadArch::GFX11_GENERIC: + case OffloadArch::GFX1100: + case OffloadArch::GFX1101: + case OffloadArch::GFX1102: + case OffloadArch::GFX1103: + case OffloadArch::GFX1150: + case OffloadArch::GFX1151: + case OffloadArch::GFX1152: + case OffloadArch::GFX12_GENERIC: + case OffloadArch::GFX1200: + case OffloadArch::GFX1201: + case OffloadArch::AMDGCNSPIRV: + case OffloadArch::Generic: + case OffloadArch::LAST: break; - case CudaArch::UNUSED: - case CudaArch::UNKNOWN: + case OffloadArch::UNKNOWN: assert(false && "No GPU arch when compiling CUDA device code."); return ""; - case CudaArch::SM_20: + case OffloadArch::UNUSED: + case OffloadArch::SM_20: return "200"; - case CudaArch::SM_21: + case OffloadArch::SM_21: return "210"; - case CudaArch::SM_30: + case OffloadArch::SM_30: return "300"; - case CudaArch::SM_32: + case OffloadArch::SM_32_: return "320"; - case CudaArch::SM_35: + case OffloadArch::SM_35: return "350"; - case CudaArch::SM_37: + case OffloadArch::SM_37: return "370"; - case CudaArch::SM_50: + case OffloadArch::SM_50: return "500"; - case CudaArch::SM_52: + case OffloadArch::SM_52: return "520"; - case CudaArch::SM_53: + case OffloadArch::SM_53: return "530"; - case CudaArch::SM_60: + case OffloadArch::SM_60: return "600"; - case CudaArch::SM_61: + case OffloadArch::SM_61: return "610"; - case CudaArch::SM_62: + case OffloadArch::SM_62: return "620"; - case CudaArch::SM_70: + case OffloadArch::SM_70: return "700"; - case CudaArch::SM_72: + case OffloadArch::SM_72: return "720"; - case CudaArch::SM_75: + case OffloadArch::SM_75: return "750"; - case CudaArch::SM_80: + case OffloadArch::SM_80: return "800"; - case CudaArch::SM_86: + case OffloadArch::SM_86: return "860"; - case CudaArch::SM_87: + case OffloadArch::SM_87: return "870"; - case CudaArch::SM_89: + case OffloadArch::SM_89: return "890"; - case CudaArch::SM_90: - case CudaArch::SM_90a: + case OffloadArch::SM_90: + case OffloadArch::SM_90a: return "900"; } - llvm_unreachable("unhandled CudaArch"); + llvm_unreachable("unhandled OffloadArch"); }(); Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); - if (GPU == CudaArch::SM_90a) + if (GPU == OffloadArch::SM_90a) Builder.defineMacro("__CUDA_ARCH_FEAT_SM90_ALL", "1"); } } diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/NVPTX.h b/contrib/llvm-project/clang/lib/Basic/Targets/NVPTX.h index 20d76b702a94..25dc979d882f 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/NVPTX.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/NVPTX.h @@ -62,7 +62,7 @@ static const int NVPTXDWARFAddrSpaceMap[] = { class LLVM_LIBRARY_VISIBILITY NVPTXTargetInfo : public TargetInfo { static const char *const GCCRegNames[]; - CudaArch GPU; + OffloadArch GPU; uint32_t PTXVersion; std::unique_ptr<TargetInfo> HostTarget; @@ -75,11 +75,14 @@ public: ArrayRef<Builtin::Info> getTargetBuiltins() const override; + bool useFP16ConversionIntrinsics() const override { return false; } + bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector<std::string> &FeaturesVec) const override { - Features[CudaArchToString(GPU)] = true; + if (GPU != OffloadArch::UNUSED) + Features[OffloadArchToString(GPU)] = true; Features["ptx" + std::to_string(PTXVersion)] = true; return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); } @@ -104,6 +107,7 @@ public: case 'l': case 'f': case 'd': + case 'q': Info.setAllowsRegister(); return true; } @@ -115,23 +119,22 @@ public: } BuiltinVaListKind getBuiltinVaListKind() const override { - // FIXME: implement - return TargetInfo::CharPtrBuiltinVaList; + return TargetInfo::VoidPtrBuiltinVaList; } bool isValidCPUName(StringRef Name) const override { - return StringToCudaArch(Name) != CudaArch::UNKNOWN; + return StringToOffloadArch(Name) != OffloadArch::UNKNOWN; } void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override { - for (int i = static_cast<int>(CudaArch::SM_20); - i < static_cast<int>(CudaArch::Generic); ++i) - Values.emplace_back(CudaArchToString(static_cast<CudaArch>(i))); + for (int i = static_cast<int>(OffloadArch::SM_20); + i < static_cast<int>(OffloadArch::Generic); ++i) + Values.emplace_back(OffloadArchToString(static_cast<OffloadArch>(i))); } bool setCPU(const std::string &Name) override { - GPU = StringToCudaArch(Name); - return GPU != CudaArch::UNKNOWN; + GPU = StringToOffloadArch(Name); + return GPU != OffloadArch::UNKNOWN; } void setSupportedOpenCLOpts() override { @@ -182,7 +185,7 @@ public: bool hasBitIntType() const override { return true; } bool hasBFloat16Type() const override { return true; } - CudaArch getGPU() const { return GPU; } + OffloadArch getGPU() const { return GPU; } }; } // namespace targets } // namespace clang diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/OSTargets.h b/contrib/llvm-project/clang/lib/Basic/Targets/OSTargets.h index 4366c1149e40..357c1965057c 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/OSTargets.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/OSTargets.h @@ -337,6 +337,10 @@ protected: Builder.defineMacro("_GNU_SOURCE"); if (this->HasFloat128) Builder.defineMacro("__FLOAT128__"); + if (Triple.isTime64ABI()) { + Builder.defineMacro("_FILE_OFFSET_BITS", "64"); + Builder.defineMacro("_TIME_BITS", "64"); + } } public: @@ -868,6 +872,7 @@ protected: public: FuchsiaTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : OSTargetInfo<Target>(Triple, Opts) { + this->WIntType = TargetInfo::UnsignedInt; this->MCountName = "__mcount"; this->TheCXXABI.set(TargetCXXABI::Fuchsia); } diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/PPC.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/PPC.cpp index 41935abfb65d..9ff54083c923 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/PPC.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/PPC.cpp @@ -79,6 +79,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasPrivileged = true; } else if (Feature == "+aix-small-local-exec-tls") { HasAIXSmallLocalExecTLS = true; + } else if (Feature == "+aix-small-local-dynamic-tls") { + HasAIXSmallLocalDynamicTLS = true; } else if (Feature == "+isa-v206-instructions") { IsISA2_06 = true; } else if (Feature == "+isa-v207-instructions") { @@ -89,6 +91,10 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, IsISA3_1 = true; } else if (Feature == "+quadword-atomics") { HasQuadwordAtomics = true; + } else if (Feature == "+aix-shared-lib-tls-model-opt") { + HasAIXShLibTLSModelOpt = true; + } else if (Feature == "+longcall") { + UseLongCalls = true; } // TODO: Finish this list and add an assert that we've handled them // all. @@ -379,6 +385,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("_ARCH_PWR9"); if (ArchDefs & ArchDefinePwr10) Builder.defineMacro("_ARCH_PWR10"); + if (ArchDefs & ArchDefinePwr11) + Builder.defineMacro("_ARCH_PWR11"); if (ArchDefs & ArchDefineA2) Builder.defineMacro("_ARCH_A2"); if (ArchDefs & ArchDefineE500) @@ -442,19 +450,44 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, // _CALL_DARWIN } -// Handle explicit options being passed to the compiler here: if we've -// explicitly turned off vsx and turned on any of: -// - power8-vector -// - direct-move -// - float128 -// - power9-vector -// - paired-vector-memops -// - mma -// - power10-vector +// Handle explicit options being passed to the compiler here: +// - if we've explicitly turned off vsx and turned on any of: +// - power8-vector +// - direct-move +// - float128 +// - power9-vector +// - paired-vector-memops +// - mma +// - power10-vector +// - if we've explicitly turned on vsx and turned off altivec. +// - if we've explicitly turned off hard-float and turned on altivec. // then go ahead and error since the customer has expressed an incompatible // set of options. static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, const std::vector<std::string> &FeaturesVec) { + // Cannot allow soft-float with Altivec. + if (llvm::is_contained(FeaturesVec, "-hard-float") && + llvm::is_contained(FeaturesVec, "+altivec")) { + Diags.Report(diag::err_opt_not_valid_with_opt) << "-msoft-float" + << "-maltivec"; + return false; + } + + // Cannot allow soft-float with VSX. + if (llvm::is_contained(FeaturesVec, "-hard-float") && + llvm::is_contained(FeaturesVec, "+vsx")) { + Diags.Report(diag::err_opt_not_valid_with_opt) << "-msoft-float" + << "-mvsx"; + return false; + } + + // Cannot allow VSX with no Altivec. + if (llvm::is_contained(FeaturesVec, "+vsx") && + llvm::is_contained(FeaturesVec, "-altivec")) { + Diags.Report(diag::err_opt_not_valid_with_opt) << "-mvsx" + << "-mno-altivec"; + return false; + } // vsx was not explicitly turned off. if (!llvm::is_contained(FeaturesVec, "-vsx")) @@ -548,9 +581,13 @@ bool PPCTargetInfo::initFeatureMap( // Privileged instructions are off by default. Features["privileged"] = false; - // The code generated by the -maix-small-local-exec-tls option is turned - // off by default. + // The code generated by the -maix-small-local-[exec|dynamic]-tls option is + // turned off by default. Features["aix-small-local-exec-tls"] = false; + Features["aix-small-local-dynamic-tls"] = false; + + // Turn off TLS model opt by default. + Features["aix-shared-lib-tls-model-opt"] = false; Features["spe"] = llvm::StringSwitch<bool>(CPU) .Case("8548", true) @@ -587,10 +624,17 @@ bool PPCTargetInfo::initFeatureMap( addP10SpecificFeatures(Features); } - // Future CPU should include all of the features of Power 10 as well as any + // Power11 includes all the same features as Power10 plus any features + // specific to the Power11 core. + if (CPU == "pwr11" || CPU == "power11") { + initFeatureMap(Features, Diags, "pwr10", FeaturesVec); + addP11SpecificFeatures(Features); + } + + // Future CPU should include all of the features of Power 11 as well as any // additional features (yet to be determined) specific to it. if (CPU == "future") { - initFeatureMap(Features, Diags, "pwr10", FeaturesVec); + initFeatureMap(Features, Diags, "pwr11", FeaturesVec); addFutureSpecificFeatures(Features); } @@ -646,14 +690,6 @@ bool PPCTargetInfo::initFeatureMap( return false; } - if (llvm::is_contained(FeaturesVec, "+aix-small-local-exec-tls")) { - if (!getTriple().isOSAIX() || !getTriple().isArch64Bit()) { - Diags.Report(diag::err_opt_not_valid_on_target) - << "-maix-small-local-exec-tls"; - return false; - } - } - return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); } @@ -669,6 +705,10 @@ void PPCTargetInfo::addP10SpecificFeatures( Features["isa-v31-instructions"] = true; } +// Add any Power11 specific features. +void PPCTargetInfo::addP11SpecificFeatures( + llvm::StringMap<bool> &Features) const {} + // Add features specific to the "Future" CPU. void PPCTargetInfo::addFutureSpecificFeatures( llvm::StringMap<bool> &Features) const {} @@ -696,11 +736,14 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const { .Case("rop-protect", HasROPProtect) .Case("privileged", HasPrivileged) .Case("aix-small-local-exec-tls", HasAIXSmallLocalExecTLS) + .Case("aix-small-local-dynamic-tls", HasAIXSmallLocalDynamicTLS) .Case("isa-v206-instructions", IsISA2_06) .Case("isa-v207-instructions", IsISA2_07) .Case("isa-v30-instructions", IsISA3_0) .Case("isa-v31-instructions", IsISA3_1) .Case("quadword-atomics", HasQuadwordAtomics) + .Case("aix-shared-lib-tls-model-opt", HasAIXShLibTLSModelOpt) + .Case("longcall", UseLongCalls) .Default(false); } @@ -840,17 +883,17 @@ ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const { } static constexpr llvm::StringLiteral ValidCPUNames[] = { - {"generic"}, {"440"}, {"450"}, {"601"}, {"602"}, - {"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"}, - {"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"}, - {"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"}, - {"g5"}, {"a2"}, {"e500"}, {"e500mc"}, {"e5500"}, - {"power3"}, {"pwr3"}, {"power4"}, {"pwr4"}, {"power5"}, - {"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"}, {"pwr6"}, - {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"}, - {"pwr8"}, {"power9"}, {"pwr9"}, {"power10"}, {"pwr10"}, - {"powerpc"}, {"ppc"}, {"ppc32"}, {"powerpc64"}, {"ppc64"}, - {"powerpc64le"}, {"ppc64le"}, {"future"}}; + {"generic"}, {"440"}, {"450"}, {"601"}, {"602"}, + {"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"}, + {"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"}, + {"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"}, + {"g5"}, {"a2"}, {"e500"}, {"e500mc"}, {"e5500"}, + {"power3"}, {"pwr3"}, {"power4"}, {"pwr4"}, {"power5"}, + {"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"}, {"pwr6"}, + {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"}, + {"pwr8"}, {"power9"}, {"pwr9"}, {"power10"}, {"pwr10"}, + {"power11"}, {"pwr11"}, {"powerpc"}, {"ppc"}, {"ppc32"}, + {"powerpc64"}, {"ppc64"}, {"powerpc64le"}, {"ppc64le"}, {"future"}}; bool PPCTargetInfo::isValidCPUName(StringRef Name) const { return llvm::is_contained(ValidCPUNames, Name); @@ -878,3 +921,41 @@ ArrayRef<Builtin::Info> PPCTargetInfo::getTargetBuiltins() const { return llvm::ArrayRef(BuiltinInfo, clang::PPC::LastTSBuiltin - Builtin::FirstTSBuiltin); } + +bool PPCTargetInfo::validateCpuSupports(StringRef FeatureStr) const { + llvm::Triple Triple = getTriple(); + if (Triple.isOSAIX()) { +#define PPC_AIX_FEATURE(NAME, DESC, SUPPORT_METHOD, INDEX, MASK, COMP_OP, \ + VALUE) \ + .Case(NAME, true) + return llvm::StringSwitch<bool>(FeatureStr) +#include "llvm/TargetParser/PPCTargetParser.def" + .Default(false); + } + + assert(Triple.isOSLinux() && + "__builtin_cpu_supports() is only supported for AIX and Linux."); + +#define PPC_LNX_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) .Case(NAME, true) + return llvm::StringSwitch<bool>(FeatureStr) +#include "llvm/TargetParser/PPCTargetParser.def" + .Default(false); +} + +bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const { + llvm::Triple Triple = getTriple(); + assert((Triple.isOSAIX() || Triple.isOSLinux()) && + "__builtin_cpu_is() is only supported for AIX and Linux."); + +#define PPC_CPU(NAME, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD, \ + AIXID) \ + .Case(NAME, {Linux_SUPPORT_METHOD, AIX_SUPPORT_METHOD}) + + std::pair<unsigned, unsigned> SuppportMethod = + llvm::StringSwitch<std::pair<unsigned, unsigned>>(CPUName) +#include "llvm/TargetParser/PPCTargetParser.def" + .Default({BUILTIN_PPC_UNSUPPORTED, BUILTIN_PPC_UNSUPPORTED}); + return Triple.isOSLinux() + ? (SuppportMethod.first != BUILTIN_PPC_UNSUPPORTED) + : (SuppportMethod.second != BUILTIN_PPC_UNSUPPORTED); +} diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/PPC.h b/contrib/llvm-project/clang/lib/Basic/Targets/PPC.h index 4d62673ba7fb..6d5d8dd54d01 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/PPC.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/PPC.h @@ -44,8 +44,9 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { ArchDefinePwr8 = 1 << 12, ArchDefinePwr9 = 1 << 13, ArchDefinePwr10 = 1 << 14, - ArchDefineFuture = 1 << 15, - ArchDefineA2 = 1 << 16, + ArchDefinePwr11 = 1 << 15, + ArchDefineFuture = 1 << 16, + ArchDefineA2 = 1 << 17, ArchDefineE500 = 1 << 18 } ArchDefineTypes; @@ -61,6 +62,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool HasROPProtect = false; bool HasPrivileged = false; bool HasAIXSmallLocalExecTLS = false; + bool HasAIXSmallLocalDynamicTLS = false; bool HasVSX = false; bool UseCRBits = false; bool HasP8Vector = false; @@ -80,6 +82,8 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool IsISA3_0 = false; bool IsISA3_1 = false; bool HasQuadwordAtomics = false; + bool HasAIXShLibTLSModelOpt = false; + bool UseLongCalls = false; protected: std::string ABI; @@ -92,6 +96,7 @@ public: LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); HasStrictFP = true; HasIbm128 = true; + HasUnalignedAccess = true; } // Set the language option for altivec based on our value. @@ -162,11 +167,16 @@ public: ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) + .Cases("power11", "pwr11", + ArchDefinePwr11 | ArchDefinePwr10 | ArchDefinePwr9 | + ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | + ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | + ArchDefinePpcgr | ArchDefinePpcsq) .Case("future", - ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 | - ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 | - ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | - ArchDefinePpcgr | ArchDefinePpcsq) + ArchDefineFuture | ArchDefinePwr11 | ArchDefinePwr10 | + ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | + ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | + ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) .Cases("8548", "e500", ArchDefineE500) .Default(ArchDefineNone); } @@ -188,6 +198,7 @@ public: const std::vector<std::string> &FeaturesVec) const override; void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const; + void addP11SpecificFeatures(llvm::StringMap<bool> &Features) const; void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const; bool handleTargetFeatures(std::vector<std::string> &Features, @@ -302,9 +313,11 @@ public: // asm statements) Info.setAllowsMemory(); break; - case 'R': // AIX TOC entry case 'a': // Address operand that is an indexed or indirect from a // register (`p' is preferable for asm statements) + // TODO: Add full support for this constraint + return false; + case 'R': // AIX TOC entry case 'S': // Constant suitable as a 64-bit mask operand case 'T': // Constant suitable as a 32-bit mask operand case 'U': // System V Release 4 small data area reference @@ -357,8 +370,30 @@ public: bool hasBitIntType() const override { return true; } bool isSPRegName(StringRef RegName) const override { - return RegName.equals("r1") || RegName.equals("x1"); + return RegName == "r1" || RegName == "x1"; + } + + // We support __builtin_cpu_supports/__builtin_cpu_is on targets that + // have Glibc since it is Glibc that provides the HWCAP[2] in the auxv. + static constexpr int MINIMUM_AIX_OS_MAJOR = 7; + static constexpr int MINIMUM_AIX_OS_MINOR = 2; + bool supportsCpuSupports() const override { + llvm::Triple Triple = getTriple(); + // AIX 7.2 is the minimum requirement to support __builtin_cpu_supports(). + return Triple.isOSGlibc() || + (Triple.isOSAIX() && + !Triple.isOSVersionLT(MINIMUM_AIX_OS_MAJOR, MINIMUM_AIX_OS_MINOR)); } + + bool supportsCpuIs() const override { + llvm::Triple Triple = getTriple(); + // AIX 7.2 is the minimum requirement to support __builtin_cpu_is(). + return Triple.isOSGlibc() || + (Triple.isOSAIX() && + !Triple.isOSVersionLT(MINIMUM_AIX_OS_MAJOR, MINIMUM_AIX_OS_MINOR)); + } + bool validateCpuSupports(StringRef Feature) const override; + bool validateCpuIs(StringRef Name) const override; }; class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo { @@ -406,6 +441,10 @@ public: // This is the ELF definition return TargetInfo::PowerABIBuiltinVaList; } + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; // Note: ABI differences may eventually require us to have a separate @@ -486,6 +525,10 @@ public: return CCCR_Warning; } } + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(128, 128); + } }; class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp index c71b2e9eeb6c..9159162f01d1 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp @@ -96,7 +96,8 @@ bool RISCVTargetInfo::validateAsmConstraint( // An address that is held in a general-purpose register. Info.setAllowsMemory(); return true; - case 'S': // A symbolic address + case 's': + case 'S': // A symbol or label reference with a constant offset Info.setAllowsRegister(); return true; case 'v': @@ -167,7 +168,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, Twine(getVersionValue(ExtInfo.Major, ExtInfo.Minor))); } - if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul")) + if (ISAInfo->hasExtension("zmmul")) Builder.defineMacro("__riscv_mul"); if (ISAInfo->hasExtension("m")) { @@ -210,7 +211,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__riscv_v_fixed_vlen", Twine(VScale->first * llvm::RISCV::RVVBitsPerBlock)); - if (FastUnalignedAccess) + if (FastScalarUnalignedAccess) Builder.defineMacro("__riscv_misaligned_fast"); else Builder.defineMacro("__riscv_misaligned_avoid"); @@ -233,7 +234,7 @@ static constexpr Builtin::Info BuiltinInfo[] = { {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, -#include "clang/Basic/BuiltinsRISCV.def" +#include "clang/Basic/BuiltinsRISCV.inc" }; ArrayRef<Builtin::Info> RISCVTargetInfo::getTargetBuiltins() const { @@ -352,7 +353,8 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx")) HasLegalHalfType = true; - FastUnalignedAccess = llvm::is_contained(Features, "+fast-unaligned-access"); + FastScalarUnalignedAccess = + llvm::is_contained(Features, "+unaligned-scalar-mem"); if (llvm::is_contained(Features, "+experimental")) HasExperimental = true; @@ -466,3 +468,14 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { } return Ret; } + +TargetInfo::CallingConvCheckResult +RISCVTargetInfo::checkCallingConvention(CallingConv CC) const { + switch (CC) { + default: + return CCCR_Warning; + case CC_C: + case CC_RISCVVectorCall: + return CCCR_OK; + } +} diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.h b/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.h index bfbdafb682c8..d5df6344bedc 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.h @@ -16,7 +16,7 @@ #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" #include "llvm/Support/Compiler.h" -#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/Triple.h" #include <optional> @@ -30,7 +30,7 @@ protected: std::unique_ptr<llvm::RISCVISAInfo> ISAInfo; private: - bool FastUnalignedAccess; + bool FastScalarUnalignedAccess; bool HasExperimental = false; public: @@ -110,6 +110,8 @@ public: bool hasBFloat16Type() const override { return true; } + CallingConvCheckResult checkCallingConvention(CallingConv CC) const override; + bool useFP16ConversionIntrinsics() const override { return false; } @@ -120,6 +122,10 @@ public: void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override; bool supportsTargetAttributeTune() const override { return true; } ParsedTargetAttr parseTargetAttr(StringRef Str) const override; + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo { public: diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/SPIR.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/SPIR.cpp index dc920177d3a9..040303983594 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/SPIR.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/SPIR.cpp @@ -11,7 +11,9 @@ //===----------------------------------------------------------------------===// #include "SPIR.h" +#include "AMDGPU.h" #include "Targets.h" +#include "llvm/TargetParser/TargetParser.h" using namespace clang; using namespace clang::targets; @@ -54,3 +56,76 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions &Opts, BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder); DefineStd(Builder, "SPIRV64", Opts); } + +static const AMDGPUTargetInfo AMDGPUTI(llvm::Triple("amdgcn-amd-amdhsa"), {}); + +ArrayRef<const char *> SPIRV64AMDGCNTargetInfo::getGCCRegNames() const { + return AMDGPUTI.getGCCRegNames(); +} + +bool SPIRV64AMDGCNTargetInfo::initFeatureMap( + llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef, + const std::vector<std::string> &FeatureVec) const { + llvm::AMDGPU::fillAMDGPUFeatureMap({}, getTriple(), Features); + + return TargetInfo::initFeatureMap(Features, Diags, {}, FeatureVec); +} + +bool SPIRV64AMDGCNTargetInfo::validateAsmConstraint( + const char *&Name, TargetInfo::ConstraintInfo &Info) const { + return AMDGPUTI.validateAsmConstraint(Name, Info); +} + +std::string +SPIRV64AMDGCNTargetInfo::convertConstraint(const char *&Constraint) const { + return AMDGPUTI.convertConstraint(Constraint); +} + +ArrayRef<Builtin::Info> SPIRV64AMDGCNTargetInfo::getTargetBuiltins() const { + return AMDGPUTI.getTargetBuiltins(); +} + +void SPIRV64AMDGCNTargetInfo::getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const { + BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder); + DefineStd(Builder, "SPIRV64", Opts); + + Builder.defineMacro("__AMD__"); + Builder.defineMacro("__AMDGPU__"); + Builder.defineMacro("__AMDGCN__"); +} + +void SPIRV64AMDGCNTargetInfo::setAuxTarget(const TargetInfo *Aux) { + assert(Aux && "Cannot invoke setAuxTarget without a valid auxiliary target!"); + + // This is a 1:1 copy of AMDGPUTargetInfo::setAuxTarget() + assert(HalfFormat == Aux->HalfFormat); + assert(FloatFormat == Aux->FloatFormat); + assert(DoubleFormat == Aux->DoubleFormat); + + // On x86_64 long double is 80-bit extended precision format, which is + // not supported by AMDGPU. 128-bit floating point format is also not + // supported by AMDGPU. Therefore keep its own format for these two types. + auto SaveLongDoubleFormat = LongDoubleFormat; + auto SaveFloat128Format = Float128Format; + auto SaveLongDoubleWidth = LongDoubleWidth; + auto SaveLongDoubleAlign = LongDoubleAlign; + copyAuxTarget(Aux); + LongDoubleFormat = SaveLongDoubleFormat; + Float128Format = SaveFloat128Format; + LongDoubleWidth = SaveLongDoubleWidth; + LongDoubleAlign = SaveLongDoubleAlign; + // For certain builtin types support on the host target, claim they are + // supported to pass the compilation of the host code during the device-side + // compilation. + // FIXME: As the side effect, we also accept `__float128` uses in the device + // code. To reject these builtin types supported in the host target but not in + // the device target, one approach would support `device_builtin` attribute + // so that we could tell the device builtin types from the host ones. This + // also solves the different representations of the same builtin type, such + // as `size_t` in the MSVC environment. + if (Aux->hasFloat128Type()) { + HasFloat128 = true; + Float128Format = DoubleFormat; + } +} diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/SPIR.h b/contrib/llvm-project/clang/lib/Basic/Targets/SPIR.h index fa4a3bb1c82e..37cf9d7921ba 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/SPIR.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/SPIR.h @@ -125,7 +125,9 @@ protected: LongAlign = HostTarget->getLongAlign(); LongLongWidth = HostTarget->getLongLongWidth(); LongLongAlign = HostTarget->getLongLongAlign(); - MinGlobalAlign = HostTarget->getMinGlobalAlign(/* TypeSize = */ 0); + MinGlobalAlign = + HostTarget->getMinGlobalAlign(/* TypeSize = */ 0, + /* HasNonWeakDef = */ true); NewAlign = HostTarget->getNewAlign(); DefaultAlignForAttributeAligned = HostTarget->getDefaultAlignForAttributeAligned(); @@ -257,7 +259,7 @@ public: SizeType = TargetInfo::UnsignedInt; PtrDiffType = IntPtrType = TargetInfo::SignedInt; resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" - "v96:128-v192:256-v256:256-v512:512-v1024:1024"); + "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"); } void getTargetDefines(const LangOptions &Opts, @@ -274,7 +276,7 @@ public: SizeType = TargetInfo::UnsignedLong; PtrDiffType = IntPtrType = TargetInfo::SignedLong; resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" - "v96:128-v192:256-v256:256-v512:512-v1024:1024"); + "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"); } void getTargetDefines(const LangOptions &Opts, @@ -308,11 +310,12 @@ public: assert(Triple.getEnvironment() >= llvm::Triple::Pixel && Triple.getEnvironment() <= llvm::Triple::Amplification && "Logical SPIR-V environment must be a valid shader stage."); + PointerWidth = PointerAlign = 64; // SPIR-V IDs are represented with a single 32-bit word. SizeType = TargetInfo::UnsignedInt; resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" - "v96:128-v192:256-v256:256-v512:512-v1024:1024"); + "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"); } void getTargetDefines(const LangOptions &Opts, @@ -333,7 +336,7 @@ public: SizeType = TargetInfo::UnsignedInt; PtrDiffType = IntPtrType = TargetInfo::SignedInt; resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" - "v96:128-v192:256-v256:256-v512:512-v1024:1024"); + "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"); } void getTargetDefines(const LangOptions &Opts, @@ -354,11 +357,62 @@ public: SizeType = TargetInfo::UnsignedLong; PtrDiffType = IntPtrType = TargetInfo::SignedLong; resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" - "v96:128-v192:256-v256:256-v512:512-v1024:1024"); + "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"); + } + + void getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const override; +}; + +class LLVM_LIBRARY_VISIBILITY SPIRV64AMDGCNTargetInfo final + : public BaseSPIRVTargetInfo { +public: + SPIRV64AMDGCNTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) + : BaseSPIRVTargetInfo(Triple, Opts) { + assert(Triple.getArch() == llvm::Triple::spirv64 && + "Invalid architecture for 64-bit AMDGCN SPIR-V."); + assert(Triple.getVendor() == llvm::Triple::VendorType::AMD && + "64-bit AMDGCN SPIR-V target must use AMD vendor"); + assert(getTriple().getOS() == llvm::Triple::OSType::AMDHSA && + "64-bit AMDGCN SPIR-V target must use AMDHSA OS"); + assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && + "64-bit SPIR-V target must use unknown environment type"); + PointerWidth = PointerAlign = 64; + SizeType = TargetInfo::UnsignedLong; + PtrDiffType = IntPtrType = TargetInfo::SignedLong; + + resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" + "v96:128-v192:256-v256:256-v512:512-v1024:1024-G1-P4-A0"); + + BFloat16Width = BFloat16Align = 16; + BFloat16Format = &llvm::APFloat::BFloat(); + + HasLegalHalfType = true; + HasFloat16 = true; + HalfArgsAndReturns = true; } + bool hasBFloat16Type() const override { return true; } + + ArrayRef<const char *> getGCCRegNames() const override; + + bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, + StringRef, + const std::vector<std::string> &) const override; + + bool validateAsmConstraint(const char *&Name, + TargetInfo::ConstraintInfo &Info) const override; + + std::string convertConstraint(const char *&Constraint) const override; + + ArrayRef<Builtin::Info> getTargetBuiltins() const override; + void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override; + + void setAuxTarget(const TargetInfo *Aux) override; + + bool hasInt128Type() const override { return TargetInfo::hasInt128Type(); } }; } // namespace targets diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/Sparc.h b/contrib/llvm-project/clang/lib/Basic/Targets/Sparc.h index 214fef88e1dc..3357bee33e1a 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/Sparc.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/Sparc.h @@ -140,6 +140,10 @@ public: CPU = getCPUKind(Name); return CPU != CK_GENERIC; } + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; // SPARC v8 is the 32-bit mode selected by Triple::sparc. diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/SystemZ.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/SystemZ.cpp index a9b5ca483861..06f08db2eadd 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/SystemZ.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/SystemZ.cpp @@ -138,6 +138,16 @@ bool SystemZTargetInfo::hasFeature(StringRef Feature) const { .Default(false); } +unsigned SystemZTargetInfo::getMinGlobalAlign(uint64_t Size, + bool HasNonWeakDef) const { + // Don't enforce the minimum alignment on an external or weak symbol if + // -munaligned-symbols is passed. + if (UnalignedSymbols && !HasNonWeakDef) + return 0; + + return MinGlobalAlign; +} + void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__s390__"); diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/SystemZ.h b/contrib/llvm-project/clang/lib/Basic/Targets/SystemZ.h index e4ec338880f2..3bc6f2c1d308 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/SystemZ.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/SystemZ.h @@ -29,11 +29,13 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public TargetInfo { bool HasTransactionalExecution; bool HasVector; bool SoftFloat; + bool UnalignedSymbols; public: SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) : TargetInfo(Triple), CPU("z10"), ISARevision(8), - HasTransactionalExecution(false), HasVector(false), SoftFloat(false) { + HasTransactionalExecution(false), HasVector(false), SoftFloat(false), + UnalignedSymbols(false) { IntMaxType = SignedLong; Int64Type = SignedLong; IntWidth = IntAlign = 32; @@ -45,6 +47,7 @@ public: LongDoubleFormat = &llvm::APFloat::IEEEquad(); DefaultAlignForAttributeAligned = 64; MinGlobalAlign = 16; + HasUnalignedAccess = true; if (Triple.isOSzOS()) { TLSSupported = false; // All vector types are default aligned on an 8-byte boundary, even if the @@ -64,6 +67,8 @@ public: HasStrictFP = true; } + unsigned getMinGlobalAlign(uint64_t Size, bool HasNonWeakDef) const override; + void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override; @@ -79,7 +84,7 @@ public: ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; bool isSPRegName(StringRef RegName) const override { - return RegName.equals("r15"); + return RegName == "r15"; } bool validateAsmConstraint(const char *&Name, @@ -163,6 +168,7 @@ public: HasTransactionalExecution = false; HasVector = false; SoftFloat = false; + UnalignedSymbols = false; for (const auto &Feature : Features) { if (Feature == "+transactional-execution") HasTransactionalExecution = true; @@ -170,6 +176,8 @@ public: HasVector = true; else if (Feature == "+soft-float") SoftFloat = true; + else if (Feature == "+unaligned-symbols") + UnalignedSymbols = true; } HasVector &= !SoftFloat; @@ -212,6 +220,10 @@ public: int getEHDataRegisterNumber(unsigned RegNo) const override { return RegNo < 4 ? 6 + RegNo : -1; } + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(256, 256); + } }; } // namespace targets } // namespace clang diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/VE.h b/contrib/llvm-project/clang/lib/Basic/Targets/VE.h index ea9a092cad80..7e8fdf6096ef 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/VE.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/VE.h @@ -40,6 +40,7 @@ public: Int64Type = SignedLong; RegParmMax = 8; MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; + HasUnalignedAccess = true; WCharType = UnsignedInt; WIntType = UnsignedInt; diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/WebAssembly.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/WebAssembly.cpp index f1c925d90cb6..1e565f0a5319 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/WebAssembly.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/WebAssembly.cpp @@ -45,19 +45,20 @@ bool WebAssemblyTargetInfo::setABI(const std::string &Name) { bool WebAssemblyTargetInfo::hasFeature(StringRef Feature) const { return llvm::StringSwitch<bool>(Feature) - .Case("simd128", SIMDLevel >= SIMD128) - .Case("relaxed-simd", SIMDLevel >= RelaxedSIMD) - .Case("nontrapping-fptoint", HasNontrappingFPToInt) - .Case("sign-ext", HasSignExt) - .Case("exception-handling", HasExceptionHandling) - .Case("bulk-memory", HasBulkMemory) .Case("atomics", HasAtomics) - .Case("mutable-globals", HasMutableGlobals) - .Case("multivalue", HasMultivalue) - .Case("tail-call", HasTailCall) - .Case("reference-types", HasReferenceTypes) + .Case("bulk-memory", HasBulkMemory) + .Case("exception-handling", HasExceptionHandling) .Case("extended-const", HasExtendedConst) + .Case("half-precision", HasHalfPrecision) .Case("multimemory", HasMultiMemory) + .Case("multivalue", HasMultivalue) + .Case("mutable-globals", HasMutableGlobals) + .Case("nontrapping-fptoint", HasNontrappingFPToInt) + .Case("reference-types", HasReferenceTypes) + .Case("relaxed-simd", SIMDLevel >= RelaxedSIMD) + .Case("sign-ext", HasSignExt) + .Case("simd128", SIMDLevel >= SIMD128) + .Case("tail-call", HasTailCall) .Default(false); } @@ -73,32 +74,34 @@ void WebAssemblyTargetInfo::fillValidCPUList( void WebAssemblyTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { defineCPUMacros(Builder, "wasm", /*Tuning=*/false); - if (SIMDLevel >= SIMD128) - Builder.defineMacro("__wasm_simd128__"); - if (SIMDLevel >= RelaxedSIMD) - Builder.defineMacro("__wasm_relaxed_simd__"); - if (HasNontrappingFPToInt) - Builder.defineMacro("__wasm_nontrapping_fptoint__"); - if (HasSignExt) - Builder.defineMacro("__wasm_sign_ext__"); - if (HasExceptionHandling) - Builder.defineMacro("__wasm_exception_handling__"); - if (HasBulkMemory) - Builder.defineMacro("__wasm_bulk_memory__"); if (HasAtomics) Builder.defineMacro("__wasm_atomics__"); - if (HasMutableGlobals) - Builder.defineMacro("__wasm_mutable_globals__"); - if (HasMultivalue) - Builder.defineMacro("__wasm_multivalue__"); - if (HasTailCall) - Builder.defineMacro("__wasm_tail_call__"); - if (HasReferenceTypes) - Builder.defineMacro("__wasm_reference_types__"); + if (HasBulkMemory) + Builder.defineMacro("__wasm_bulk_memory__"); + if (HasExceptionHandling) + Builder.defineMacro("__wasm_exception_handling__"); if (HasExtendedConst) Builder.defineMacro("__wasm_extended_const__"); if (HasMultiMemory) Builder.defineMacro("__wasm_multimemory__"); + if (HasHalfPrecision) + Builder.defineMacro("__wasm_half_precision__"); + if (HasMultivalue) + Builder.defineMacro("__wasm_multivalue__"); + if (HasMutableGlobals) + Builder.defineMacro("__wasm_mutable_globals__"); + if (HasNontrappingFPToInt) + Builder.defineMacro("__wasm_nontrapping_fptoint__"); + if (HasReferenceTypes) + Builder.defineMacro("__wasm_reference_types__"); + if (SIMDLevel >= RelaxedSIMD) + Builder.defineMacro("__wasm_relaxed_simd__"); + if (HasSignExt) + Builder.defineMacro("__wasm_sign_ext__"); + if (SIMDLevel >= SIMD128) + Builder.defineMacro("__wasm_simd128__"); + if (HasTailCall) + Builder.defineMacro("__wasm_tail_call__"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); @@ -147,19 +150,28 @@ void WebAssemblyTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, bool WebAssemblyTargetInfo::initFeatureMap( llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector<std::string> &FeaturesVec) const { - if (CPU == "bleeding-edge") { - Features["nontrapping-fptoint"] = true; - Features["sign-ext"] = true; - Features["bulk-memory"] = true; - Features["atomics"] = true; + auto addGenericFeatures = [&]() { + Features["multivalue"] = true; Features["mutable-globals"] = true; - Features["tail-call"] = true; Features["reference-types"] = true; - Features["multimemory"] = true; - setSIMDLevel(Features, SIMD128, true); - } else if (CPU == "generic") { Features["sign-ext"] = true; - Features["mutable-globals"] = true; + }; + auto addBleedingEdgeFeatures = [&]() { + addGenericFeatures(); + Features["atomics"] = true; + Features["bulk-memory"] = true; + Features["exception-handling"] = true; + Features["extended-const"] = true; + Features["half-precision"] = true; + Features["multimemory"] = true; + Features["nontrapping-fptoint"] = true; + Features["tail-call"] = true; + setSIMDLevel(Features, RelaxedSIMD, true); + }; + if (CPU == "generic") { + addGenericFeatures(); + } else if (CPU == "bleeding-edge") { + addBleedingEdgeFeatures(); } return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); @@ -168,36 +180,20 @@ bool WebAssemblyTargetInfo::initFeatureMap( bool WebAssemblyTargetInfo::handleTargetFeatures( std::vector<std::string> &Features, DiagnosticsEngine &Diags) { for (const auto &Feature : Features) { - if (Feature == "+simd128") { - SIMDLevel = std::max(SIMDLevel, SIMD128); - continue; - } - if (Feature == "-simd128") { - SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); - continue; - } - if (Feature == "+relaxed-simd") { - SIMDLevel = std::max(SIMDLevel, RelaxedSIMD); - continue; - } - if (Feature == "-relaxed-simd") { - SIMDLevel = std::min(SIMDLevel, SIMDEnum(RelaxedSIMD - 1)); - continue; - } - if (Feature == "+nontrapping-fptoint") { - HasNontrappingFPToInt = true; + if (Feature == "+atomics") { + HasAtomics = true; continue; } - if (Feature == "-nontrapping-fptoint") { - HasNontrappingFPToInt = false; + if (Feature == "-atomics") { + HasAtomics = false; continue; } - if (Feature == "+sign-ext") { - HasSignExt = true; + if (Feature == "+bulk-memory") { + HasBulkMemory = true; continue; } - if (Feature == "-sign-ext") { - HasSignExt = false; + if (Feature == "-bulk-memory") { + HasBulkMemory = false; continue; } if (Feature == "+exception-handling") { @@ -208,28 +204,29 @@ bool WebAssemblyTargetInfo::handleTargetFeatures( HasExceptionHandling = false; continue; } - if (Feature == "+bulk-memory") { - HasBulkMemory = true; + if (Feature == "+extended-const") { + HasExtendedConst = true; continue; } - if (Feature == "-bulk-memory") { - HasBulkMemory = false; + if (Feature == "-extended-const") { + HasExtendedConst = false; continue; } - if (Feature == "+atomics") { - HasAtomics = true; + if (Feature == "+half-precision") { + SIMDLevel = std::max(SIMDLevel, SIMD128); + HasHalfPrecision = true; continue; } - if (Feature == "-atomics") { - HasAtomics = false; + if (Feature == "-half-precision") { + HasHalfPrecision = false; continue; } - if (Feature == "+mutable-globals") { - HasMutableGlobals = true; + if (Feature == "+multimemory") { + HasMultiMemory = true; continue; } - if (Feature == "-mutable-globals") { - HasMutableGlobals = false; + if (Feature == "-multimemory") { + HasMultiMemory = false; continue; } if (Feature == "+multivalue") { @@ -240,12 +237,20 @@ bool WebAssemblyTargetInfo::handleTargetFeatures( HasMultivalue = false; continue; } - if (Feature == "+tail-call") { - HasTailCall = true; + if (Feature == "+mutable-globals") { + HasMutableGlobals = true; continue; } - if (Feature == "-tail-call") { - HasTailCall = false; + if (Feature == "-mutable-globals") { + HasMutableGlobals = false; + continue; + } + if (Feature == "+nontrapping-fptoint") { + HasNontrappingFPToInt = true; + continue; + } + if (Feature == "-nontrapping-fptoint") { + HasNontrappingFPToInt = false; continue; } if (Feature == "+reference-types") { @@ -256,20 +261,36 @@ bool WebAssemblyTargetInfo::handleTargetFeatures( HasReferenceTypes = false; continue; } - if (Feature == "+extended-const") { - HasExtendedConst = true; + if (Feature == "+relaxed-simd") { + SIMDLevel = std::max(SIMDLevel, RelaxedSIMD); continue; } - if (Feature == "-extended-const") { - HasExtendedConst = false; + if (Feature == "-relaxed-simd") { + SIMDLevel = std::min(SIMDLevel, SIMDEnum(RelaxedSIMD - 1)); continue; } - if (Feature == "+multimemory") { - HasMultiMemory = true; + if (Feature == "+sign-ext") { + HasSignExt = true; continue; } - if (Feature == "-multimemory") { - HasMultiMemory = false; + if (Feature == "-sign-ext") { + HasSignExt = false; + continue; + } + if (Feature == "+simd128") { + SIMDLevel = std::max(SIMDLevel, SIMD128); + continue; + } + if (Feature == "-simd128") { + SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); + continue; + } + if (Feature == "+tail-call") { + HasTailCall = true; + continue; + } + if (Feature == "-tail-call") { + HasTailCall = false; continue; } diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/WebAssembly.h b/contrib/llvm-project/clang/lib/Basic/Targets/WebAssembly.h index 83b1711f9fdf..e4a449d1ff30 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/WebAssembly.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/WebAssembly.h @@ -53,17 +53,18 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyTargetInfo : public TargetInfo { RelaxedSIMD, } SIMDLevel = NoSIMD; - bool HasNontrappingFPToInt = false; - bool HasSignExt = false; - bool HasExceptionHandling = false; - bool HasBulkMemory = false; bool HasAtomics = false; - bool HasMutableGlobals = false; - bool HasMultivalue = false; - bool HasTailCall = false; - bool HasReferenceTypes = false; + bool HasBulkMemory = false; + bool HasExceptionHandling = false; bool HasExtendedConst = false; + bool HasHalfPrecision = false; bool HasMultiMemory = false; + bool HasMultivalue = false; + bool HasMutableGlobals = false; + bool HasNontrappingFPToInt = false; + bool HasReferenceTypes = false; + bool HasSignExt = false; + bool HasTailCall = false; std::string ABI; @@ -84,10 +85,14 @@ public: SizeType = UnsignedLong; PtrDiffType = SignedLong; IntPtrType = SignedLong; + HasUnalignedAccess = true; } StringRef getABI() const override; bool setABI(const std::string &Name) override; + bool useFP16ConversionIntrinsics() const override { + return !HasHalfPrecision; + } protected: void getTargetDefines(const LangOptions &Opts, diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp b/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp index a68b662d9401..072c97e6c8c6 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp +++ b/contrib/llvm-project/clang/lib/Basic/Targets/X86.cpp @@ -64,6 +64,8 @@ static const char *const GCCRegNames[] = { "dr0", "dr1", "dr2", "dr3", "dr6", "dr7", "bnd0", "bnd1", "bnd2", "bnd3", "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", }; const TargetInfo::AddlRegName AddlRegNames[] = { @@ -83,8 +85,23 @@ const TargetInfo::AddlRegName AddlRegNames[] = { {{"r13d", "r13w", "r13b"}, 43}, {{"r14d", "r14w", "r14b"}, 44}, {{"r15d", "r15w", "r15b"}, 45}, + {{"r16d", "r16w", "r16b"}, 165}, + {{"r17d", "r17w", "r17b"}, 166}, + {{"r18d", "r18w", "r18b"}, 167}, + {{"r19d", "r19w", "r19b"}, 168}, + {{"r20d", "r20w", "r20b"}, 169}, + {{"r21d", "r21w", "r21b"}, 170}, + {{"r22d", "r22w", "r22b"}, 171}, + {{"r23d", "r23w", "r23b"}, 172}, + {{"r24d", "r24w", "r24b"}, 173}, + {{"r25d", "r25w", "r25b"}, 174}, + {{"r26d", "r26w", "r26b"}, 175}, + {{"r27d", "r27w", "r27b"}, 176}, + {{"r28d", "r28w", "r28b"}, 177}, + {{"r29d", "r29w", "r29b"}, 178}, + {{"r30d", "r30w", "r30b"}, 179}, + {{"r31d", "r31w", "r31b"}, 180}, }; - } // namespace targets } // namespace clang @@ -139,7 +156,7 @@ bool X86TargetInfo::initFeatureMap( if (Feature.substr(1, 6) == "avx10.") { if (Feature[0] == '+') { HasAVX10 = true; - if (Feature.substr(Feature.size() - 3, 3) == "512") + if (StringRef(Feature).ends_with("512")) HasAVX10_512 = true; LastAVX10 = Feature; } else if (HasAVX10 && Feature == "-avx10.1-256") { @@ -151,7 +168,7 @@ bool X86TargetInfo::initFeatureMap( // Postpone AVX10 features handling after AVX512 settled. UpdatedAVX10FeaturesVec.push_back(Feature); continue; - } else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") { + } else if (!HasAVX512F && StringRef(Feature).starts_with("+avx512")) { HasAVX512F = true; LastAVX512 = Feature; } else if (HasAVX512F && Feature == "-avx512f") { @@ -241,7 +258,9 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, if (Feature[0] != '+') continue; - if (Feature == "+aes") { + if (Feature == "+mmx") { + HasMMX = true; + } else if (Feature == "+aes") { HasAES = true; } else if (Feature == "+vaes") { HasVAES = true; @@ -293,15 +312,9 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasAVX512VNNI = true; } else if (Feature == "+avx512bf16") { HasAVX512BF16 = true; - } else if (Feature == "+avx512er") { - HasAVX512ER = true; - Diags.Report(diag::warn_knl_knm_isa_support_removed); } else if (Feature == "+avx512fp16") { HasAVX512FP16 = true; HasLegalHalfType = true; - } else if (Feature == "+avx512pf") { - HasAVX512PF = true; - Diags.Report(diag::warn_knl_knm_isa_support_removed); } else if (Feature == "+avx512dq") { HasAVX512DQ = true; } else if (Feature == "+avx512bitalg") { @@ -358,9 +371,6 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasWBNOINVD = true; } else if (Feature == "+prefetchi") { HasPREFETCHI = true; - } else if (Feature == "+prefetchwt1") { - HasPREFETCHWT1 = true; - Diags.Report(diag::warn_knl_knm_isa_support_removed); } else if (Feature == "+clzero") { HasCLZERO = true; } else if (Feature == "+cldemote") { @@ -433,6 +443,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasFullBFloat16 = true; } else if (Feature == "+egpr") { HasEGPR = true; + } else if (Feature == "+inline-asm-use-gpr32") { + HasInlineAsmUseGPR32 = true; } else if (Feature == "+push2pop2") { HasPush2Pop2 = true; } else if (Feature == "+ppx") { @@ -441,8 +453,14 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasNDD = true; } else if (Feature == "+ccmp") { HasCCMP = true; + } else if (Feature == "+nf") { + HasNF = true; } else if (Feature == "+cf") { HasCF = true; + } else if (Feature == "+zu") { + HasZU = true; + } else if (Feature == "+branch-hint") { + HasBranchHint = true; } X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) @@ -471,13 +489,6 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, // for bfloat16 arithmetic operations in the front-end. HasBFloat16 = SSELevel >= SSE2; - MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) - .Case("+3dnowa", AMD3DNowAthlon) - .Case("+3dnow", AMD3DNow) - .Case("+mmx", MMX) - .Default(NoMMX3DNow); - MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); - XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) .Case("+xop", XOP) .Case("+fma4", FMA4) @@ -712,6 +723,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, case CK_ZNVER4: defineCPUMacros(Builder, "znver4"); break; + case CK_ZNVER5: + defineCPUMacros(Builder, "znver5"); + break; case CK_Geode: defineCPUMacros(Builder, "geode"); break; @@ -821,12 +835,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__AVX512VNNI__"); if (HasAVX512BF16) Builder.defineMacro("__AVX512BF16__"); - if (HasAVX512ER) - Builder.defineMacro("__AVX512ER__"); if (HasAVX512FP16) Builder.defineMacro("__AVX512FP16__"); - if (HasAVX512PF) - Builder.defineMacro("__AVX512PF__"); if (HasAVX512DQ) Builder.defineMacro("__AVX512DQ__"); if (HasAVX512BITALG) @@ -878,8 +888,6 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__SM4__"); if (HasPREFETCHI) Builder.defineMacro("__PREFETCHI__"); - if (HasPREFETCHWT1) - Builder.defineMacro("__PREFETCHWT1__"); if (HasCLZERO) Builder.defineMacro("__CLZERO__"); if (HasKL) @@ -952,8 +960,17 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__NDD__"); if (HasCCMP) Builder.defineMacro("__CCMP__"); + if (HasNF) + Builder.defineMacro("__NF__"); if (HasCF) Builder.defineMacro("__CF__"); + if (HasZU) + Builder.defineMacro("__ZU__"); + if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD && HasCCMP && HasNF && + HasCF && HasZU) + Builder.defineMacro("__APX_F__"); + if (HasEGPR && HasInlineAsmUseGPR32) + Builder.defineMacro("__APX_INLINE_ASM_USE_GPR32__"); // Each case falls through to the previous one here. switch (SSELevel) { @@ -1012,18 +1029,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, } // Each case falls through to the previous one here. - switch (MMX3DNowLevel) { - case AMD3DNowAthlon: - Builder.defineMacro("__3dNOW_A__"); - [[fallthrough]]; - case AMD3DNow: - Builder.defineMacro("__3dNOW__"); - [[fallthrough]]; - case MMX: + if (HasMMX) { Builder.defineMacro("__MMX__"); - [[fallthrough]]; - case NoMMX3DNow: - break; } if (CPU >= CK_i486 || CPU == CK_None) { @@ -1042,8 +1049,6 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, bool X86TargetInfo::isValidFeatureName(StringRef Name) const { return llvm::StringSwitch<bool>(Name) - .Case("3dnow", true) - .Case("3dnowa", true) .Case("adx", true) .Case("aes", true) .Case("amx-bf16", true) @@ -1060,9 +1065,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { .Case("avx512vpopcntdq", true) .Case("avx512vnni", true) .Case("avx512bf16", true) - .Case("avx512er", true) .Case("avx512fp16", true) - .Case("avx512pf", true) .Case("avx512dq", true) .Case("avx512bitalg", true) .Case("avx512bw", true) @@ -1110,7 +1113,6 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { .Case("pku", true) .Case("popcnt", true) .Case("prefetchi", true) - .Case("prefetchwt1", true) .Case("prfchw", true) .Case("ptwrite", true) .Case("raoint", true) @@ -1154,7 +1156,9 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { .Case("ppx", true) .Case("ndd", true) .Case("ccmp", true) + .Case("nf", true) .Case("cf", true) + .Case("zu", true) .Default(false); } @@ -1176,9 +1180,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) .Case("avx512vnni", HasAVX512VNNI) .Case("avx512bf16", HasAVX512BF16) - .Case("avx512er", HasAVX512ER) .Case("avx512fp16", HasAVX512FP16) - .Case("avx512pf", HasAVX512PF) .Case("avx512dq", HasAVX512DQ) .Case("avx512bitalg", HasAVX512BITALG) .Case("avx512bw", HasAVX512BW) @@ -1216,9 +1218,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("widekl", HasWIDEKL) .Case("lwp", HasLWP) .Case("lzcnt", HasLZCNT) - .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) - .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) - .Case("mmx", MMX3DNowLevel >= MMX) + .Case("mmx", HasMMX) .Case("movbe", HasMOVBE) .Case("movdiri", HasMOVDIRI) .Case("movdir64b", HasMOVDIR64B) @@ -1228,7 +1228,6 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("pku", HasPKU) .Case("popcnt", HasPOPCNT) .Case("prefetchi", HasPREFETCHI) - .Case("prefetchwt1", HasPREFETCHWT1) .Case("prfchw", HasPRFCHW) .Case("ptwrite", HasPTWRITE) .Case("raoint", HasRAOINT) @@ -1276,7 +1275,10 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("ppx", HasPPX) .Case("ndd", HasNDD) .Case("ccmp", HasCCMP) + .Case("nf", HasNF) .Case("cf", HasCF) + .Case("zu", HasZU) + .Case("branch-hint", HasBranchHint) .Default(false); } @@ -1473,6 +1475,18 @@ bool X86TargetInfo::validateAsmConstraint( case 'C': // SSE floating point constant. case 'G': // x87 floating point constant. return true; + case 'j': + Name++; + switch (*Name) { + default: + return false; + case 'r': + Info.setAllowsRegister(); + return true; + case 'R': + Info.setAllowsRegister(); + return true; + } case '@': // CC condition changes. if (auto Len = matchAsmCCConstraint(Name)) { @@ -1602,6 +1616,7 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const { case CK_ZNVER2: case CK_ZNVER3: case CK_ZNVER4: + case CK_ZNVER5: // Deprecated case CK_x86_64: case CK_x86_64_v2: @@ -1745,6 +1760,21 @@ std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { return std::string("^") + std::string(Constraint++, 2); } [[fallthrough]]; + case 'j': + switch (Constraint[1]) { + default: + // Break from inner switch and fall through (copy single char), + // continue parsing after copying the current constraint into + // the return string. + break; + case 'r': + case 'R': + // "^" hints llvm that this is a 2 letter constraint. + // "Constraint++" is used to promote the string iterator + // to the next constraint. + return std::string("^") + std::string(Constraint++, 2); + } + [[fallthrough]]; default: return std::string(1, *Constraint); } diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/X86.h b/contrib/llvm-project/clang/lib/Basic/Targets/X86.h index 0ab1c10833db..ba34ab2c7f33 100644 --- a/contrib/llvm-project/clang/lib/Basic/Targets/X86.h +++ b/contrib/llvm-project/clang/lib/Basic/Targets/X86.h @@ -67,12 +67,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { AVX2, AVX512F } SSELevel = NoSSE; - enum MMX3DNowEnum { - NoMMX3DNow, - MMX, - AMD3DNow, - AMD3DNowAthlon - } MMX3DNowLevel = NoMMX3DNow; + bool HasMMX = false; enum XOPEnum { NoXOP, SSE4A, FMA4, XOP } XOPLevel = NoXOP; enum AddrSpace { ptr32_sptr = 270, ptr32_uptr = 271, ptr64 = 272 }; @@ -103,8 +98,6 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { bool HasAVX512VNNI = false; bool HasAVX512FP16 = false; bool HasAVX512BF16 = false; - bool HasAVX512ER = false; - bool HasAVX512PF = false; bool HasAVX512DQ = false; bool HasAVX512BITALG = false; bool HasAVX512BW = false; @@ -136,7 +129,6 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { bool HasCLWB = false; bool HasMOVBE = false; bool HasPREFETCHI = false; - bool HasPREFETCHWT1 = false; bool HasRDPID = false; bool HasRDPRU = false; bool HasRetpolineExternalThunk = false; @@ -173,7 +165,11 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { bool HasPPX = false; bool HasNDD = false; bool HasCCMP = false; + bool HasNF = false; bool HasCF = false; + bool HasZU = false; + bool HasInlineAsmUseGPR32 = false; + bool HasBranchHint = false; protected: llvm::X86::CPUKind CPU = llvm::X86::CK_None; @@ -188,6 +184,7 @@ public: LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); AddrSpaceMap = &X86AddrSpaceMap; HasStrictFP = true; + HasUnalignedAccess = true; bool IsWinCOFF = getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); @@ -217,9 +214,13 @@ public: ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override; bool isSPRegName(StringRef RegName) const override { - return RegName.equals("esp") || RegName.equals("rsp"); + return RegName == "esp" || RegName == "rsp"; } + bool supportsCpuSupports() const override { return true; } + bool supportsCpuIs() const override { return true; } + bool supportsCpuInit() const override { return true; } + bool validateCpuSupports(StringRef FeatureStr) const override; bool validateCpuIs(StringRef FeatureStr) const override; @@ -241,7 +242,7 @@ public: bool &HasSizeMismatch) const override { // esp and ebp are the only 32-bit registers the x86 backend can currently // handle. - if (RegName.equals("esp") || RegName.equals("ebp")) { + if (RegName == "esp" || RegName == "ebp") { // Check that the register size is 32-bit. HasSizeMismatch = RegSize != 32; return true; @@ -342,8 +343,7 @@ public: return "avx512"; if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) return "avx"; - if (getTriple().getArch() == llvm::Triple::x86 && - MMX3DNowLevel == NoMMX3DNow) + if (getTriple().getArch() == llvm::Triple::x86 && !HasMMX) return "no-mmx"; return ""; } @@ -513,15 +513,6 @@ class LLVM_LIBRARY_VISIBILITY NetBSDI386TargetInfo public: NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} - - LangOptions::FPEvalMethodKind getFPEvalMethod() const override { - VersionTuple OsVersion = getTriple().getOSVersion(); - // New NetBSD uses the default rounding mode. - if (OsVersion >= VersionTuple(6, 99, 26) || OsVersion.getMajor() == 0) - return X86_32TargetInfo::getFPEvalMethod(); - // NetBSD before 6.99.26 defaults to "double" rounding. - return LangOptions::FPEvalMethodKind::FEM_Double; - } }; class LLVM_LIBRARY_VISIBILITY OpenBSDI386TargetInfo @@ -668,6 +659,7 @@ public: MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : X86_32TargetInfo(Triple, Opts) { LongDoubleWidth = 64; + DefaultAlignForAttributeAligned = 32; LongDoubleFormat = &llvm::APFloat::IEEEdouble(); resetDataLayout("e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:32-" "f64:32-f128:32-n8:16:32-a:0:32-S32"); @@ -772,6 +764,7 @@ public: case CC_Win64: case CC_PreserveMost: case CC_PreserveAll: + case CC_PreserveNone: case CC_X86RegCall: case CC_OpenCLKernel: return CCCR_OK; @@ -795,7 +788,7 @@ public: bool &HasSizeMismatch) const override { // rsp and rbp are the only 64-bit registers the x86 backend can currently // handle. - if (RegName.equals("rsp") || RegName.equals("rbp")) { + if (RegName == "rsp" || RegName == "rbp") { // Check that the register size is 64-bit. HasSizeMismatch = RegSize != 64; return true; @@ -849,6 +842,7 @@ public: case CC_IntelOclBicc: case CC_PreserveMost: case CC_PreserveAll: + case CC_PreserveNone: case CC_X86_64SysV: case CC_Swift: case CC_SwiftAsync: |