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Diffstat (limited to 'contrib/llvm-project/llvm/lib/CodeGen/MachineInstr.cpp')
-rw-r--r--contrib/llvm-project/llvm/lib/CodeGen/MachineInstr.cpp139
1 files changed, 61 insertions, 78 deletions
diff --git a/contrib/llvm-project/llvm/lib/CodeGen/MachineInstr.cpp b/contrib/llvm-project/llvm/lib/CodeGen/MachineInstr.cpp
index 08d786f8f12c..d81f5bbf78c5 100644
--- a/contrib/llvm-project/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/contrib/llvm-project/llvm/lib/CodeGen/MachineInstr.cpp
@@ -187,8 +187,8 @@ static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
unsigned NumOps, MachineRegisterInfo *MRI) {
if (MRI)
return MRI->moveOperands(Dst, Src, NumOps);
+
// MachineOperand is a trivially copyable type so we can just use memmove.
- assert(Dst && Src && "Unknown operands");
std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
}
@@ -338,7 +338,7 @@ void MachineInstr::setExtraInfo(MachineFunction &MF,
// 32-bit pointers.
// FIXME: Maybe we should make the symbols in the extra info mutable?
else if (NumPointers > 1 || HasHeapAllocMarker) {
- Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
+ Info.set<EIIK_OutOfLine>(MF.createMIExtraInfoWithMarker(
MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
return;
}
@@ -627,8 +627,8 @@ bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
if (Check == IgnoreDefs)
continue;
else if (Check == IgnoreVRegDefs) {
- if (!Register::isVirtualRegister(MO.getReg()) ||
- !Register::isVirtualRegister(OMO.getReg()))
+ if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()) ||
+ !TargetRegisterInfo::isVirtualRegister(OMO.getReg()))
if (!MO.isIdenticalTo(OMO))
return false;
} else {
@@ -683,8 +683,8 @@ void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
for (const MachineOperand &MO : MI->operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
- Register Reg = MO.getReg();
- if (!Reg.isVirtual())
+ unsigned Reg = MO.getReg();
+ if (!TargetRegisterInfo::isVirtualRegister(Reg))
continue;
MRI.markUsesInDebugValueAsUndef(Reg);
}
@@ -823,10 +823,6 @@ const DIExpression *MachineInstr::getDebugExpression() const {
return cast<DIExpression>(getOperand(3).getMetadata());
}
-bool MachineInstr::isDebugEntryValue() const {
- return isDebugValue() && getDebugExpression()->isEntryValue();
-}
-
const TargetRegisterClass*
MachineInstr::getRegClassConstraint(unsigned OpIdx,
const TargetInstrInfo *TII,
@@ -868,7 +864,7 @@ MachineInstr::getRegClassConstraint(unsigned OpIdx,
}
const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
- Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
+ unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI, bool ExploreBundle) const {
// Check every operands inside the bundle if we have
// been asked to.
@@ -885,7 +881,7 @@ const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
}
const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
- unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
+ unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
assert(CurRC && "Invalid initial register class");
// Check if Reg is constrained by some of its use/def from MI.
@@ -928,7 +924,7 @@ unsigned MachineInstr::getBundleSize() const {
/// Returns true if the MachineInstr has an implicit-use operand of exactly
/// the given register (not considering sub/super-registers).
-bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
+bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
@@ -941,12 +937,12 @@ bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
/// the specific register or -1 if it is not found. It further tightens
/// the search criteria to a use that kills the register if isKill is true.
int MachineInstr::findRegisterUseOperandIdx(
- Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
+ unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
- Register MOReg = MO.getReg();
+ unsigned MOReg = MO.getReg();
if (!MOReg)
continue;
if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
@@ -960,7 +956,7 @@ int MachineInstr::findRegisterUseOperandIdx(
/// indicating if this instruction reads or writes Reg. This also considers
/// partial defines.
std::pair<bool,bool>
-MachineInstr::readsWritesVirtualRegister(Register Reg,
+MachineInstr::readsWritesVirtualRegister(unsigned Reg,
SmallVectorImpl<unsigned> *Ops) const {
bool PartDef = false; // Partial redefine.
bool FullDef = false; // Full define.
@@ -989,9 +985,9 @@ MachineInstr::readsWritesVirtualRegister(Register Reg,
/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
/// also checks if there is a def of a super-register.
int
-MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
+MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
const TargetRegisterInfo *TRI) const {
- bool isPhys = Register::isPhysicalRegister(Reg);
+ bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO = getOperand(i);
// Accept regmask operands when Overlap is set.
@@ -1000,9 +996,10 @@ MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
return i;
if (!MO.isReg() || !MO.isDef())
continue;
- Register MOReg = MO.getReg();
+ unsigned MOReg = MO.getReg();
bool Found = (MOReg == Reg);
- if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
+ if (!Found && TRI && isPhys &&
+ TargetRegisterInfo::isPhysicalRegister(MOReg)) {
if (Overlap)
Found = TRI->regsOverlap(MOReg, Reg);
else
@@ -1136,10 +1133,10 @@ void MachineInstr::clearKillInfo() {
}
}
-void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
+void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
unsigned SubIdx,
const TargetRegisterInfo &RegInfo) {
- if (Register::isPhysicalRegister(ToReg)) {
+ if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
if (SubIdx)
ToReg = RegInfo.getSubReg(ToReg, SubIdx);
for (MachineOperand &MO : operands()) {
@@ -1159,7 +1156,7 @@ void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
/// isSafeToMove - Return true if it is safe to move this instruction. If
/// SawStore is set to true, it means that there is a store (or call) between
/// the instruction's location and its intended destination.
-bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
+bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
// Ignore stuff that we obviously can't move.
//
// Treat volatile loads as stores. This is not strictly necessary for
@@ -1188,7 +1185,7 @@ bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
return true;
}
-bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
+bool MachineInstr::mayAlias(AliasAnalysis *AA, const MachineInstr &Other,
bool UseTBAA) const {
const MachineFunction *MF = getMF();
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
@@ -1200,7 +1197,7 @@ bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
return false;
// Let the target decide if memory accesses cannot possibly overlap.
- if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
+ if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
return false;
// FIXME: Need to handle multiple memory operands to support all targets.
@@ -1306,7 +1303,7 @@ bool MachineInstr::hasOrderedMemoryRef() const {
/// isDereferenceableInvariantLoad - Return true if this instruction will never
/// trap and is loading from a location whose value is invariant across a run of
/// this function.
-bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
+bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
// If the instruction doesn't load at all, it isn't an invariant load.
if (!mayLoad())
return false;
@@ -1358,7 +1355,7 @@ unsigned MachineInstr::isConstantValuePHI() const {
assert(getNumOperands() >= 3 &&
"It's illegal to have a PHI without source operands");
- Register Reg = getOperand(1).getReg();
+ unsigned Reg = getOperand(1).getReg();
for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
if (getOperand(i).getReg() != Reg)
return 0;
@@ -1506,7 +1503,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
- MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
+ MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
++StartOp;
}
@@ -1538,8 +1535,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << "nsw ";
if (getFlag(MachineInstr::IsExact))
OS << "exact ";
- if (getFlag(MachineInstr::NoFPExcept))
- OS << "nofpexcept ";
+ if (getFlag(MachineInstr::FPExcept))
+ OS << "fpexcept ";
// Print the opcode name.
if (TII)
@@ -1561,7 +1558,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
const unsigned OpIdx = InlineAsm::MIOp_AsmString;
LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
- getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
+ getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
ShouldPrintRegisterTies, TiedOperandIdx, TRI,
IntrinsicInfo);
@@ -1600,7 +1597,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
else {
LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
unsigned TiedOperandIdx = getTiedOperandIdx(i);
- MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
+ MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
}
} else if (isDebugLabel() && MO.isMetadata()) {
@@ -1611,7 +1608,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
else {
LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
unsigned TiedOperandIdx = getTiedOperandIdx(i);
- MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
+ MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
}
} else if (i == AsmDescOp && MO.isImm()) {
@@ -1678,7 +1675,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (MO.isImm() && isOperandSubregIdx(i))
MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
else
- MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
+ MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
}
}
@@ -1706,8 +1703,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
FirstOp = false;
OS << ',';
}
- OS << " heap-alloc-marker ";
- HeapAllocMarker->printAsOperand(OS, MST);
+ OS << " heap-alloc-marker";
}
if (!SkipDebugLoc) {
@@ -1728,7 +1724,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
MFI = &MF->getFrameInfo();
Context = &MF->getFunction().getContext();
} else {
- CtxPtr = std::make_unique<LLVMContext>();
+ CtxPtr = llvm::make_unique<LLVMContext>();
Context = CtxPtr.get();
}
@@ -1782,10 +1778,10 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
OS << '\n';
}
-bool MachineInstr::addRegisterKilled(Register IncomingReg,
+bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) {
- bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
+ bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
bool hasAliases = isPhysReg &&
MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
bool Found = false;
@@ -1801,7 +1797,7 @@ bool MachineInstr::addRegisterKilled(Register IncomingReg,
if (MO.isDebug())
continue;
- Register Reg = MO.getReg();
+ unsigned Reg = MO.getReg();
if (!Reg)
continue;
@@ -1816,7 +1812,8 @@ bool MachineInstr::addRegisterKilled(Register IncomingReg,
MO.setIsKill();
Found = true;
}
- } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
+ } else if (hasAliases && MO.isKill() &&
+ TargetRegisterInfo::isPhysicalRegister(Reg)) {
// A super-register kill already exists.
if (RegInfo->isSuperRegister(IncomingReg, Reg))
return true;
@@ -1848,23 +1845,23 @@ bool MachineInstr::addRegisterKilled(Register IncomingReg,
return Found;
}
-void MachineInstr::clearRegisterKills(Register Reg,
+void MachineInstr::clearRegisterKills(unsigned Reg,
const TargetRegisterInfo *RegInfo) {
- if (!Register::isPhysicalRegister(Reg))
+ if (!TargetRegisterInfo::isPhysicalRegister(Reg))
RegInfo = nullptr;
for (MachineOperand &MO : operands()) {
if (!MO.isReg() || !MO.isUse() || !MO.isKill())
continue;
- Register OpReg = MO.getReg();
+ unsigned OpReg = MO.getReg();
if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
MO.setIsKill(false);
}
}
-bool MachineInstr::addRegisterDead(Register Reg,
+bool MachineInstr::addRegisterDead(unsigned Reg,
const TargetRegisterInfo *RegInfo,
bool AddIfNotFound) {
- bool isPhysReg = Register::isPhysicalRegister(Reg);
+ bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
bool hasAliases = isPhysReg &&
MCRegAliasIterator(Reg, RegInfo, false).isValid();
bool Found = false;
@@ -1873,7 +1870,7 @@ bool MachineInstr::addRegisterDead(Register Reg,
MachineOperand &MO = getOperand(i);
if (!MO.isReg() || !MO.isDef())
continue;
- Register MOReg = MO.getReg();
+ unsigned MOReg = MO.getReg();
if (!MOReg)
continue;
@@ -1881,7 +1878,7 @@ bool MachineInstr::addRegisterDead(Register Reg,
MO.setIsDead();
Found = true;
} else if (hasAliases && MO.isDead() &&
- Register::isPhysicalRegister(MOReg)) {
+ TargetRegisterInfo::isPhysicalRegister(MOReg)) {
// There exists a super-register that's marked dead.
if (RegInfo->isSuperRegister(Reg, MOReg))
return true;
@@ -1914,7 +1911,7 @@ bool MachineInstr::addRegisterDead(Register Reg,
return true;
}
-void MachineInstr::clearRegisterDeads(Register Reg) {
+void MachineInstr::clearRegisterDeads(unsigned Reg) {
for (MachineOperand &MO : operands()) {
if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
continue;
@@ -1922,7 +1919,7 @@ void MachineInstr::clearRegisterDeads(Register Reg) {
}
}
-void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
+void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
for (MachineOperand &MO : operands()) {
if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
continue;
@@ -1930,9 +1927,9 @@ void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
}
}
-void MachineInstr::addRegisterDefined(Register Reg,
+void MachineInstr::addRegisterDefined(unsigned Reg,
const TargetRegisterInfo *RegInfo) {
- if (Register::isPhysicalRegister(Reg)) {
+ if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
if (MO)
return;
@@ -1948,7 +1945,7 @@ void MachineInstr::addRegisterDefined(Register Reg,
true /*IsImp*/));
}
-void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
+void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
const TargetRegisterInfo &TRI) {
bool HasRegMask = false;
for (MachineOperand &MO : operands()) {
@@ -1957,19 +1954,18 @@ void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
continue;
}
if (!MO.isReg() || !MO.isDef()) continue;
- Register Reg = MO.getReg();
- if (!Reg.isPhysical())
- continue;
+ unsigned Reg = MO.getReg();
+ if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
// If there are no uses, including partial uses, the def is dead.
if (llvm::none_of(UsedRegs,
- [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
+ [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
MO.setIsDead();
}
// This is a call with a register mask operand.
// Mask clobbers are always dead, so add defs for the non-dead defines.
if (HasRegMask)
- for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
+ for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
I != E; ++I)
addRegisterDefined(*I, &TRI);
}
@@ -1977,11 +1973,12 @@ void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
unsigned
MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
// Build up a buffer of hash code components.
- SmallVector<size_t, 16> HashComponents;
+ SmallVector<size_t, 8> HashComponents;
HashComponents.reserve(MI->getNumOperands() + 1);
HashComponents.push_back(MI->getOpcode());
for (const MachineOperand &MO : MI->operands()) {
- if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
+ if (MO.isReg() && MO.isDef() &&
+ TargetRegisterInfo::isVirtualRegister(MO.getReg()))
continue; // Skip virtual register defs.
HashComponents.push_back(hash_value(MO));
@@ -2013,7 +2010,7 @@ void MachineInstr::emitError(StringRef Msg) const {
MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
const MCInstrDesc &MCID, bool IsIndirect,
- Register Reg, const MDNode *Variable,
+ unsigned Reg, const MDNode *Variable,
const MDNode *Expr) {
assert(isa<DILocalVariable>(Variable) && "not a variable");
assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
@@ -2049,7 +2046,7 @@ MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, const MCInstrDesc &MCID,
- bool IsIndirect, Register Reg,
+ bool IsIndirect, unsigned Reg,
const MDNode *Variable, const MDNode *Expr) {
MachineFunction &MF = *BB.getParent();
MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
@@ -2119,24 +2116,10 @@ void MachineInstr::collectDebugValues(
}
}
-void MachineInstr::changeDebugValuesDefReg(Register Reg) {
+void MachineInstr::changeDebugValuesDefReg(unsigned Reg) {
// Collect matching debug values.
SmallVector<MachineInstr *, 2> DbgValues;
-
- if (!getOperand(0).isReg())
- return;
-
- unsigned DefReg = getOperand(0).getReg();
- auto *MRI = getRegInfo();
- for (auto &MO : MRI->use_operands(DefReg)) {
- auto *DI = MO.getParent();
- if (!DI->isDebugValue())
- continue;
- if (DI->getOperand(0).isReg() &&
- DI->getOperand(0).getReg() == DefReg){
- DbgValues.push_back(DI);
- }
- }
+ collectDebugValues(DbgValues);
// Propagate Reg to debug value instructions.
for (auto *DBI : DbgValues)
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-20 00:51:30 +0000