diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp index fc7105bc15a7..9f98f9ada802 100644 --- a/contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp +++ b/contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp @@ -190,6 +190,14 @@ GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const { if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg()) return NSA_Status::FIXED; + // InlineSpiller does not call LRM::assign() after an LI split leaving + // it in an inconsistent state, so we cannot call LRM::unassign(). + // See llvm bug #48911. + // Skip reassign if a register has originated from such split. + // FIXME: Remove the workaround when bug #48911 is fixed. + if (VRM->getPreSplitReg(Reg)) + return NSA_Status::FIXED; + const MachineInstr *Def = MRI->getUniqueVRegDef(Reg); if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg) |