diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index ebe23a5eac57..396d22c7ec18 100644 --- a/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -273,8 +273,8 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, // subtract the index by one. Offset0Idx -= get(Opc0).NumDefs; Offset1Idx -= get(Opc1).NumDefs; - Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue(); - Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue(); + Offset0 = Load0->getConstantOperandVal(Offset0Idx); + Offset1 = Load1->getConstantOperandVal(Offset1Idx); return true; } @@ -955,12 +955,8 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, bool IsSGPRSrc = AMDGPU::SReg_LO16RegClass.contains(SrcReg); bool IsAGPRDst = AMDGPU::AGPR_LO16RegClass.contains(DestReg); bool IsAGPRSrc = AMDGPU::AGPR_LO16RegClass.contains(SrcReg); - bool DstLow = AMDGPU::VGPR_LO16RegClass.contains(DestReg) || - AMDGPU::SReg_LO16RegClass.contains(DestReg) || - AMDGPU::AGPR_LO16RegClass.contains(DestReg); - bool SrcLow = AMDGPU::VGPR_LO16RegClass.contains(SrcReg) || - AMDGPU::SReg_LO16RegClass.contains(SrcReg) || - AMDGPU::AGPR_LO16RegClass.contains(SrcReg); + bool DstLow = !AMDGPU::isHi(DestReg, RI); + bool SrcLow = !AMDGPU::isHi(SrcReg, RI); MCRegister NewDestReg = RI.get32BitRegister(DestReg); MCRegister NewSrcReg = RI.get32BitRegister(SrcReg); @@ -7202,6 +7198,18 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist, Register DstReg = Inst.getOperand(0).getReg(); const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(Inst); + // If it's a copy of a VGPR to a physical SGPR, insert a V_READFIRSTLANE and + // hope for the best. + if (Inst.isCopy() && DstReg.isPhysical() && + RI.isVGPR(MRI, Inst.getOperand(1).getReg())) { + // TODO: Only works for 32 bit registers. + BuildMI(*Inst.getParent(), &Inst, Inst.getDebugLoc(), + get(AMDGPU::V_READFIRSTLANE_B32), Inst.getOperand(0).getReg()) + .add(Inst.getOperand(1)); + Inst.eraseFromParent(); + return; + } + if (Inst.isCopy() && Inst.getOperand(1).getReg().isVirtual() && NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) { // Instead of creating a copy where src and dst are the same register |