diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/Mips/MipsFastISel.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/Mips/MipsFastISel.cpp | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsFastISel.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsFastISel.cpp index 8a847eaf6618..e963185eaeaa 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -228,14 +228,13 @@ private: unsigned fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, bool Op0IsKill, - unsigned Op1, bool Op1IsKill); + unsigned Op0, unsigned Op1); // for some reason, this default is not generated by tablegen // so we explicitly generate it here. unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, - unsigned Op0, bool Op0IsKill, uint64_t imm1, - uint64_t imm2, unsigned Op3, bool Op3IsKill) { + unsigned Op0, uint64_t imm1, uint64_t imm2, + unsigned Op3) { return 0; } @@ -2122,8 +2121,7 @@ void MipsFastISel::simplifyAddress(Address &Addr) { unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, bool Op0IsKill, - unsigned Op1, bool Op1IsKill) { + unsigned Op0, unsigned Op1) { // We treat the MUL instruction in a special way because it clobbers // the HI0 & LO0 registers. The TableGen definition of this instruction can // mark these registers only as implicitly defined. As a result, the @@ -2136,15 +2134,14 @@ unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode, Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) - .addReg(Op0, getKillRegState(Op0IsKill)) - .addReg(Op1, getKillRegState(Op1IsKill)) + .addReg(Op0) + .addReg(Op1) .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); return ResultReg; } - return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1, - Op1IsKill); + return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op1); } namespace llvm { |