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-rw-r--r--contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 561b04cc0b44..ce36331e044d 100644
--- a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -62,6 +62,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool EnableSaveRestore = false;
unsigned XLen = 32;
MVT XLenVT = MVT::i32;
+ uint8_t MaxInterleaveFactor = 2;
RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
BitVector UserReservedRegister;
RISCVFrameLowering FrameLowering;
@@ -134,6 +135,9 @@ public:
assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
return UserReservedRegister[i];
}
+ unsigned getMaxInterleaveFactor() const {
+ return hasStdExtV() ? MaxInterleaveFactor : 1;
+ }
protected:
// GlobalISel related APIs.
@@ -147,6 +151,14 @@ public:
InstructionSelector *getInstructionSelector() const override;
const LegalizerInfo *getLegalizerInfo() const override;
const RegisterBankInfo *getRegBankInfo() const override;
+
+ // Return the known range for the bit length of RVV data registers. A value
+ // of 0 means nothing is known about that particular limit beyond what's
+ // implied by the architecture.
+ unsigned getMaxRVVVectorSizeInBits() const;
+ unsigned getMinRVVVectorSizeInBits() const;
+ unsigned getMaxLMULForFixedLengthVectors() const;
+ bool useRVVForFixedLengthVectors() const;
};
} // End llvm namespace