diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h | 92 |
1 files changed, 55 insertions, 37 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h index c8237e60b4e4..831f7fadaa62 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -20,7 +20,7 @@ #include "llvm/CodeGen/GlobalISel/CallLowering.h" #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" -#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" +#include "llvm/CodeGen/RegisterBankInfo.h" #include "llvm/CodeGen/SelectionDAGTargetInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/DataLayout.h" @@ -34,22 +34,6 @@ class StringRef; class RISCVSubtarget : public RISCVGenSubtargetInfo { public: - enum ExtZvl : unsigned { - NotSet = 0, - Zvl32b = 32, - Zvl64b = 64, - Zvl128b = 128, - Zvl256b = 256, - Zvl512b = 512, - Zvl1024b = 1024, - Zvl2048b = 2048, - Zvl4096b = 4096, - Zvl8192b = 8192, - Zvl16384b = 16384, - Zvl32768b = 32768, - Zvl65536b = 65536 - }; - enum RISCVProcFamilyEnum : uint8_t { Others, SiFive7, @@ -65,6 +49,7 @@ private: bool HasStdExtF = false; bool HasStdExtD = false; bool HasStdExtC = false; + bool HasStdExtZihintpause = false; bool HasStdExtZba = false; bool HasStdExtZbb = false; bool HasStdExtZbc = false; @@ -81,6 +66,7 @@ private: bool HasStdExtZve64x = false; bool HasStdExtZve64f = false; bool HasStdExtZve64d = false; + bool HasStdExtZvfh = false; bool HasStdExtZfhmin = false; bool HasStdExtZfh = false; bool HasStdExtZfinx = false; @@ -100,13 +86,19 @@ private: bool HasStdExtZks = false; bool HasStdExtZkt = false; bool HasStdExtZk = false; + bool HasStdExtZicbom = false; + bool HasStdExtZicboz = false; + bool HasStdExtZicbop = false; bool HasRV64 = false; bool IsRV32E = false; bool EnableLinkerRelax = false; bool EnableRVCHintInstrs = true; + bool EnableDefaultUnroll = true; bool EnableSaveRestore = false; + bool EnableUnalignedScalarMem = false; + bool HasLUIADDIFusion = false; unsigned XLen = 32; - ExtZvl ZvlLen = ExtZvl::NotSet; + unsigned ZvlLen = 0; MVT XLenVT = MVT::i32; uint8_t MaxInterleaveFactor = 2; RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown; @@ -161,6 +153,7 @@ public: bool hasStdExtD() const { return HasStdExtD; } bool hasStdExtC() const { return HasStdExtC; } bool hasStdExtV() const { return HasStdExtV; } + bool hasStdExtZihintpause() const { return HasStdExtZihintpause; } bool hasStdExtZba() const { return HasStdExtZba; } bool hasStdExtZbb() const { return HasStdExtZbb; } bool hasStdExtZbc() const { return HasStdExtZbc; } @@ -171,7 +164,8 @@ public: bool hasStdExtZbr() const { return HasStdExtZbr; } bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZbt() const { return HasStdExtZbt; } - bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; } + bool hasStdExtZvl() const { return ZvlLen != 0; } + bool hasStdExtZvfh() const { return HasStdExtZvfh; } bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } bool hasStdExtZfh() const { return HasStdExtZfh; } bool hasStdExtZfinx() const { return HasStdExtZfinx; } @@ -187,11 +181,17 @@ public: bool hasStdExtZksed() const { return HasStdExtZksed; } bool hasStdExtZksh() const { return HasStdExtZksh; } bool hasStdExtZkr() const { return HasStdExtZkr; } + bool hasStdExtZicbom() const { return HasStdExtZicbom; } + bool hasStdExtZicboz() const { return HasStdExtZicboz; } + bool hasStdExtZicbop() const { return HasStdExtZicbop; } bool is64Bit() const { return HasRV64; } bool isRV32E() const { return IsRV32E; } bool enableLinkerRelax() const { return EnableLinkerRelax; } bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; } + bool enableDefaultUnroll() const { return EnableDefaultUnroll; } bool enableSaveRestore() const { return EnableSaveRestore; } + bool enableUnalignedScalarMem() const { return EnableUnalignedScalarMem; } + bool hasLUIADDIFusion() const { return HasLUIADDIFusion; } MVT getXLenVT() const { return XLenVT; } unsigned getXLen() const { return XLen; } unsigned getFLen() const { @@ -203,27 +203,34 @@ public: return 0; } - unsigned getMinVLen() const { return ZvlLen; } + unsigned getELEN() const { + assert(hasVInstructions() && "Expected V extension"); + return hasVInstructionsI64() ? 64 : 32; + } + unsigned getRealMinVLen() const { + unsigned VLen = getMinRVVVectorSizeInBits(); + return VLen == 0 ? getArchMinVLen() : VLen; + } + unsigned getRealMaxVLen() const { + unsigned VLen = getMaxRVVVectorSizeInBits(); + return VLen == 0 ? getArchMaxVLen() : VLen; + } RISCVABI::ABI getTargetABI() const { return TargetABI; } bool isRegisterReservedByUser(Register i) const { assert(i < RISCV::NUM_TARGET_REGS && "Register out of range"); return UserReservedRegister[i]; } + bool hasMacroFusion() const { return hasLUIADDIFusion(); } + // Vector codegen related methods. - bool hasVInstructions() const { return HasStdExtV || HasStdExtZve32x; } - bool hasVInstructionsI64() const { return HasStdExtV || HasStdExtZve64x; } - bool hasVInstructionsF16() const { - return (HasStdExtV || HasStdExtZve32f) && HasStdExtZfh; - } + bool hasVInstructions() const { return HasStdExtZve32x; } + bool hasVInstructionsI64() const { return HasStdExtZve64x; } + bool hasVInstructionsF16() const { return HasStdExtZvfh && HasStdExtZfh; } // FIXME: Consider Zfinx in the future - bool hasVInstructionsF32() const { - return HasStdExtV || (HasStdExtZve32f && HasStdExtF); - } + bool hasVInstructionsF32() const { return HasStdExtZve32f && HasStdExtF; } // FIXME: Consider Zdinx in the future - bool hasVInstructionsF64() const { - return HasStdExtV || (HasStdExtZve64d && HasStdExtD); - } + bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; } // F16 and F64 both require F32. bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); } unsigned getMaxInterleaveFactor() const { @@ -237,6 +244,18 @@ protected: std::unique_ptr<LegalizerInfo> Legalizer; std::unique_ptr<RegisterBankInfo> RegBankInfo; + // Return the known range for the bit length of RVV data registers as set + // at the command line. A value of 0 means nothing is known about that particular + // limit beyond what's implied by the architecture. + // NOTE: Please use getRealMinVLen and getRealMaxVLen instead! + unsigned getMaxRVVVectorSizeInBits() const; + unsigned getMinRVVVectorSizeInBits() const; + + // Return the known range for the bit length of RVV data registers as indicated + // by -march and -mattr. + unsigned getArchMinVLen() const { return ZvlLen; } + unsigned getArchMaxVLen() const { return 65536; } + public: const CallLowering *getCallLowering() const override; InstructionSelector *getInstructionSelector() const override; @@ -249,14 +268,13 @@ public: // pool if exceeded. unsigned getMaxBuildIntsCost() const; - // Return the known range for the bit length of RVV data registers. A value - // of 0 means nothing is known about that particular limit beyond what's - // implied by the architecture. - unsigned getMaxRVVVectorSizeInBits() const; - unsigned getMinRVVVectorSizeInBits() const; unsigned getMaxLMULForFixedLengthVectors() const; - unsigned getMaxELENForFixedLengthVectors() const; bool useRVVForFixedLengthVectors() const; + + bool enableSubRegLiveness() const override; + + void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>> + &Mutations) const override; }; } // End llvm namespace |