diff options
Diffstat (limited to 'cvmx-gpio.h')
| -rw-r--r-- | cvmx-gpio.h | 71 |
1 files changed, 66 insertions, 5 deletions
diff --git a/cvmx-gpio.h b/cvmx-gpio.h index f728933861b2..c10c70247195 100644 --- a/cvmx-gpio.h +++ b/cvmx-gpio.h @@ -1,5 +1,5 @@ /***********************license start*************** - * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights + * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights * reserved. * * @@ -15,7 +15,7 @@ * disclaimer in the documentation and/or other materials provided * with the distribution. - * * Neither the name of Cavium Networks nor the names of + * * Neither the name of Cavium Inc. nor the names of * its contributors may be used to endorse or promote products * derived from this software without specific prior written * permission. @@ -26,7 +26,7 @@ * countries. * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" - * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR + * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM @@ -48,7 +48,7 @@ * * General Purpose IO interface. * - * <hr>$Revision: 49448 $<hr> + * <hr>$Revision: 70030 $<hr> */ #ifndef __CVMX_GPIO_H__ @@ -64,17 +64,78 @@ extern "C" { * Clear the interrupt rising edge detector for the supplied * pins in the mask. Chips which have more than 16 GPIO pins * can't use them for interrupts. - * + e * @param clear_mask Mask of pins to clear */ static inline void cvmx_gpio_interrupt_clear(uint16_t clear_mask) { + if (OCTEON_IS_MODEL(OCTEON_CN61XX)) + { + cvmx_gpio_multi_cast_t multi_cast; + cvmx_gpio_bit_cfgx_t gpio_bit; + int core = cvmx_get_core_num(); + + multi_cast.u64 = cvmx_read_csr(CVMX_GPIO_MULTI_CAST); + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(core)); + + /* If Multicast mode is enabled, and GPIO interrupt is enabled for + edge detection, then GPIO<4..7> interrupts are per core */ + if (multi_cast.s.en && gpio_bit.s.int_en && gpio_bit.s.int_type) + { + /* Clear GPIO<4..7> per core */ + cvmx_ciu_intx_sum0_t ciu_sum0; + ciu_sum0.u64 = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core * 2)); + ciu_sum0.s.gpio = clear_mask & 0xf0; + cvmx_write_csr(CVMX_CIU_INTX_SUM0(core * 2), ciu_sum0.u64); + + /* Clear other GPIO pins for all cores. */ + cvmx_write_csr(CVMX_GPIO_INT_CLR, (clear_mask & ~0xf0)); + return; + } + } + /* Clear GPIO pins state across all cores and common interrupt states. */ cvmx_gpio_int_clr_t gpio_int_clr; gpio_int_clr.u64 = 0; gpio_int_clr.s.type = clear_mask; cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64); } +/** + * GPIO Output Pin + * + * @param bit The GPIO to use + * @param mode Drive GPIO as output pin or not. + * + */ +static inline void cvmx_gpio_cfg(int bit, int mode) +{ + if (bit > 15 && bit < 20) + { + /* CN61XX/CN66XX has 20 GPIO pins and only 16 are interruptable. */ + if (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)) + { + cvmx_gpio_xbit_cfgx_t gpio_xbit; + gpio_xbit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(bit)); + if (mode) + gpio_xbit.s.tx_oe = 1; + else + gpio_xbit.s.tx_oe = 0; + cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(bit), gpio_xbit.u64); + } + else + cvmx_dprintf("cvmx_gpio_cfg: Invalid GPIO bit(%d)\n", bit); + } + else + { + cvmx_gpio_bit_cfgx_t gpio_bit; + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(bit)); + if (mode) + gpio_bit.s.tx_oe = 1; + else + gpio_bit.s.tx_oe = 0; + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), gpio_bit.u64); + } +} /** * GPIO Read Data |