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Diffstat (limited to 'docs/AMDGPUUsage.rst')
| -rw-r--r-- | docs/AMDGPUUsage.rst | 75 |
1 files changed, 64 insertions, 11 deletions
diff --git a/docs/AMDGPUUsage.rst b/docs/AMDGPUUsage.rst index 0824eb86650a..5ff0f207f227 100644 --- a/docs/AMDGPUUsage.rst +++ b/docs/AMDGPUUsage.rst @@ -19,20 +19,73 @@ Address Spaces The AMDGPU back-end uses the following address space mapping: - ============= ============================================ - Address Space Memory Space - ============= ============================================ - 0 Private - 1 Global - 2 Constant - 3 Local - 4 Generic (Flat) - 5 Region - ============= ============================================ + ================== =================== ============== + LLVM Address Space DWARF Address Space Memory Space + ================== =================== ============== + 0 1 Private + 1 N/A Global + 2 N/A Constant + 3 2 Local + 4 N/A Generic (Flat) + 5 N/A Region + ================== =================== ============== The terminology in the table, aside from the region memory space, is from the OpenCL standard. +LLVM Address Space is used throughout LLVM (for example, in LLVM IR). DWARF +Address Space is emitted in DWARF, and is used by tools, such as debugger, +profiler and others. + +Trap Handler ABI +---------------- +The OS element of the target triple controls the trap handler behavior. + +HSA OS +^^^^^^ +For code objects generated by AMDGPU back-end for the HSA OS, the runtime +installs a trap handler that supports the s_trap instruction with the following +usage: + + +--------------+-------------+-------------------+----------------------------+ + |Usage |Code Sequence|Trap Handler Inputs|Description | + +==============+=============+===================+============================+ + |reserved |s_trap 0x00 | |Reserved by hardware. | + +--------------+-------------+-------------------+----------------------------+ + |HSA debugtrap |s_trap 0x01 |SGPR0-1: queue_ptr |Reserved for HSA debugtrap | + |(arg) | |VGPR0: arg |intrinsic (not implemented).| + +--------------+-------------+-------------------+----------------------------+ + |llvm.trap |s_trap 0x02 |SGPR0-1: queue_ptr |Causes dispatch to be | + | | | |terminated and its | + | | | |associated queue put into | + | | | |the error state. | + +--------------+-------------+-------------------+----------------------------+ + |llvm.debugtrap| s_trap 0x03 |SGPR0-1: queue_ptr |If debugger not installed | + | | | |handled same as llvm.trap. | + +--------------+-------------+-------------------+----------------------------+ + |debugger |s_trap 0x07 | |Reserved for debugger | + |breakpoint | | |breakpoints. | + +--------------+-------------+-------------------+----------------------------+ + |debugger |s_trap 0x08 | |Reserved for debugger. | + +--------------+-------------+-------------------+----------------------------+ + |debugger |s_trap 0xfe | |Reserved for debugger. | + +--------------+-------------+-------------------+----------------------------+ + |debugger |s_trap 0xff | |Reserved for debugger. | + +--------------+-------------+-------------------+----------------------------+ + +Non-HSA OS +^^^^^^^^^^ +For code objects generated by AMDGPU back-end for non-HSA OS, the runtime does +not install a trap handler. The llvm.trap and llvm.debugtrap instructions are +handler as follows: + + =============== ============= =============================================== + Usage Code Sequence Description + =============== ============= =============================================== + llvm.trap s_endpgm Causes wavefront to be terminated. + llvm.debugtrap s_nop No operation. Compiler warning generated that + there is no trap handler installed. + =============== ============= =============================================== Assembler ========= @@ -204,7 +257,7 @@ SOPP Instruction Examples For full list of supported instructions, refer to "SOPP Instructions" in ISA Manual. Unless otherwise mentioned, little verification is performed on the operands -of SOPP Instrucitons, so it is up to the programmer to be familiar with the +of SOPP Instructions, so it is up to the programmer to be familiar with the range or acceptable values. Vector ALU Instruction Examples |