diff options
Diffstat (limited to 'include/clang/AST/X86Builtins.def')
| -rw-r--r-- | include/clang/AST/X86Builtins.def | 427 |
1 files changed, 427 insertions, 0 deletions
diff --git a/include/clang/AST/X86Builtins.def b/include/clang/AST/X86Builtins.def new file mode 100644 index 000000000000..710efa8cee4b --- /dev/null +++ b/include/clang/AST/X86Builtins.def @@ -0,0 +1,427 @@ +//===--- X86Builtins.def - X86 Builtin function database --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the X86-specific builtin function database. Users of +// this file must define the BUILTIN macro to make use of this information. +// +//===----------------------------------------------------------------------===// + +// FIXME: this needs to be the full list supported by GCC. Right now, I'm just +// adding stuff on demand. + +// The format of this database matches clang/AST/Builtins.def. + +// FIXME: In GCC, these builtins are defined depending on whether support for +// MMX/SSE/etc is turned on. We should do this too. + +// FIXME: Ideally we would be able to pull this information from what +// LLVM already knows about X86 builtins. We need to match the LLVM +// definition anyway, since code generation will lower to the +// intrinsic if one exists. + +BUILTIN(__builtin_ia32_emms , "v", "") + +// FIXME: Are these nothrow/const? + +// SSE intrinsics. +BUILTIN(__builtin_ia32_comieq, "iV4fV4f", "") +BUILTIN(__builtin_ia32_comilt, "iV4fV4f", "") +BUILTIN(__builtin_ia32_comile, "iV4fV4f", "") +BUILTIN(__builtin_ia32_comigt, "iV4fV4f", "") +BUILTIN(__builtin_ia32_comige, "iV4fV4f", "") +BUILTIN(__builtin_ia32_comineq, "iV4fV4f", "") +BUILTIN(__builtin_ia32_ucomieq, "iV4fV4f", "") +BUILTIN(__builtin_ia32_ucomilt, "iV4fV4f", "") +BUILTIN(__builtin_ia32_ucomile, "iV4fV4f", "") +BUILTIN(__builtin_ia32_ucomigt, "iV4fV4f", "") +BUILTIN(__builtin_ia32_ucomige, "iV4fV4f", "") +BUILTIN(__builtin_ia32_ucomineq, "iV4fV4f", "") +BUILTIN(__builtin_ia32_comisdeq, "iV2dV2d", "") +BUILTIN(__builtin_ia32_comisdlt, "iV2dV2d", "") +BUILTIN(__builtin_ia32_comisdle, "iV2dV2d", "") +BUILTIN(__builtin_ia32_comisdgt, "iV2dV2d", "") +BUILTIN(__builtin_ia32_comisdge, "iV2dV2d", "") +BUILTIN(__builtin_ia32_comisdneq, "iV2dV2d", "") +BUILTIN(__builtin_ia32_ucomisdeq, "iV2dV2d", "") +BUILTIN(__builtin_ia32_ucomisdlt, "iV2dV2d", "") +BUILTIN(__builtin_ia32_ucomisdle, "iV2dV2d", "") +BUILTIN(__builtin_ia32_ucomisdgt, "iV2dV2d", "") +BUILTIN(__builtin_ia32_ucomisdge, "iV2dV2d", "") +BUILTIN(__builtin_ia32_ucomisdneq, "iV2dV2d", "") +BUILTIN(__builtin_ia32_addps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_subps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_mulps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_divps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_addss, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_subss, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_mulss, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_divss, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fc", "") +BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fc", "") +BUILTIN(__builtin_ia32_minps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_maxps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_minss, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_maxss, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_andps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_andnps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_orps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_xorps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_movss, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_movhlps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_movlhps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_unpckhps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_unpcklps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_paddb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_paddw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_paddd, "V2iV2iV2i", "") +BUILTIN(__builtin_ia32_paddq, "V1LLiV1LLiV1LLi", "") +BUILTIN(__builtin_ia32_psubb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_psubw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_psubd, "V2iV2iV2i", "") +BUILTIN(__builtin_ia32_psubq, "V1LLiV1LLiV1LLi", "") +BUILTIN(__builtin_ia32_paddsb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_paddsw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_psubsb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_psubsw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_paddusb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_paddusw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_psubusb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_psubusw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pmullw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pmulhw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pmulhuw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pand, "V1LLiV1LLiV1LLi", "") +BUILTIN(__builtin_ia32_pandn, "V1LLiV1LLiV1LLi", "") +BUILTIN(__builtin_ia32_por, "V1LLiV1LLiV1LLi", "") +BUILTIN(__builtin_ia32_pxor, "V1LLiV1LLiV1LLi", "") +BUILTIN(__builtin_ia32_pavgb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_pavgw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pcmpeqb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_pcmpeqw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pcmpeqd, "V2iV2iV2i", "") +BUILTIN(__builtin_ia32_pcmpgtb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_pcmpgtw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pcmpgtd, "V2iV2iV2i", "") +BUILTIN(__builtin_ia32_pmaxub, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_pmaxsw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pminub, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_pminsw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_punpckhbw, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_punpckhwd, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_punpckhdq, "V2iV2iV2i", "") +BUILTIN(__builtin_ia32_punpcklbw, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_punpcklwd, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_punpckldq, "V2iV2iV2i", "") +BUILTIN(__builtin_ia32_addpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_subpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_mulpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_divpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_addsd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_subsd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_mulsd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_divsd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dc", "") +BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dc", "") +BUILTIN(__builtin_ia32_minpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_maxpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_minsd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_maxsd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_andpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_andnpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_orpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_xorpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_movsd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_unpckhpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_unpcklpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_paddb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_paddw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_paddd128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_paddq128, "V2LLiV2LLiV2LLi", "") +BUILTIN(__builtin_ia32_psubb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_psubw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_psubd128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_psubq128, "V2LLiV2LLiV2LLi", "") +BUILTIN(__builtin_ia32_paddsb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_paddsw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_psubsb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_psubsw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_paddusb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_paddusw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_psubusb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_psubusw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pmullw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pmulhw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pand128, "V2LLiV2LLiV2LLi", "") +BUILTIN(__builtin_ia32_pandn128, "V2LLiV2LLiV2LLi", "") +BUILTIN(__builtin_ia32_por128, "V2LLiV2LLiV2LLi", "") +BUILTIN(__builtin_ia32_pxor128, "V2LLiV2LLiV2LLi", "") +BUILTIN(__builtin_ia32_pavgb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_pavgw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pcmpeqb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_pcmpeqw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pcmpeqd128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_pcmpgtb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_pcmpgtw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pcmpgtd128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_pmaxub128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_pmaxsw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pminub128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_pminsw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_punpckhbw128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_punpckhwd128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_punpckhdq128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_punpckhqdq128, "V2LLiV2LLiV2LLi", "") +BUILTIN(__builtin_ia32_punpcklbw128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_punpcklwd128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_punpckldq128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_punpcklqdq128, "V2LLiV2LLiV2LLi", "") +BUILTIN(__builtin_ia32_packsswb128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_packssdw128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_packuswb128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pmulhuw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_addsubps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_addsubpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_haddps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_haddpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_hsubps, "V4fV4fV4f", "") +BUILTIN(__builtin_ia32_hsubpd, "V2dV2dV2d", "") +BUILTIN(__builtin_ia32_phaddw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_phaddw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_phaddd128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_phaddd, "V2iV2iV2i", "") +BUILTIN(__builtin_ia32_phaddsw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_phaddsw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_phsubw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_phsubw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_phsubd128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_phsubd, "V2iV2iV2i", "") +BUILTIN(__builtin_ia32_phsubsw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_phsubsw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pmaddubsw128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_pmaddubsw, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_pmulhrsw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pmulhrsw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pshufb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_pshufb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_psignb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_psignb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_psignw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_psignw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_psignd128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_psignd, "V2iV2iV2i", "") +BUILTIN(__builtin_ia32_pabsb128, "V16cV16c", "") +BUILTIN(__builtin_ia32_pabsb, "V8cV8c", "") +BUILTIN(__builtin_ia32_pabsw128, "V8sV8s", "") +BUILTIN(__builtin_ia32_pabsw, "V4sV4s", "") +BUILTIN(__builtin_ia32_pabsd128, "V4iV4i", "") +BUILTIN(__builtin_ia32_pabsd, "V2iV2i", "") +BUILTIN(__builtin_ia32_psllw, "V4sV4sV1LLi", "") +BUILTIN(__builtin_ia32_pslld, "V2iV2iV1LLi", "") +BUILTIN(__builtin_ia32_psllq, "V1LLiV1LLiV1LLi", "") +BUILTIN(__builtin_ia32_psrlw, "V4sV4sV1LLi", "") +BUILTIN(__builtin_ia32_psrld, "V2iV2iV1LLi", "") +BUILTIN(__builtin_ia32_psrlq, "V1LLiV1LLiV1LLi", "") +BUILTIN(__builtin_ia32_psraw, "V4sV4sV1LLi", "") +BUILTIN(__builtin_ia32_psrad, "V2iV2iV1LLi", "") +BUILTIN(__builtin_ia32_pshufw, "V4sV4si", "") +BUILTIN(__builtin_ia32_pmaddwd, "V2iV4sV4s", "") +BUILTIN(__builtin_ia32_packsswb, "V8cV4sV4s", "") +BUILTIN(__builtin_ia32_packssdw, "V4sV2iV2i", "") +BUILTIN(__builtin_ia32_packuswb, "V8cV4sV4s", "") +BUILTIN(__builtin_ia32_ldmxcsr, "vUi", "") +BUILTIN(__builtin_ia32_stmxcsr, "Ui", "") +BUILTIN(__builtin_ia32_cvtpi2ps, "V4fV4fV2i", "") +BUILTIN(__builtin_ia32_cvtps2pi, "V2iV4f", "") +BUILTIN(__builtin_ia32_cvtsi2ss, "V4fV4fi", "") +BUILTIN(__builtin_ia32_cvtsi642ss, "V4fV4fLLi", "") +BUILTIN(__builtin_ia32_cvtss2si, "iV4f", "") +BUILTIN(__builtin_ia32_cvtss2si64, "LLiV4f", "") +BUILTIN(__builtin_ia32_cvttps2pi, "V2iV4f", "") +BUILTIN(__builtin_ia32_cvttss2si, "iV4f", "") +BUILTIN(__builtin_ia32_cvttss2si64, "LLiV4f", "") +BUILTIN(__builtin_ia32_maskmovq, "vV8cV8cc*", "") +BUILTIN(__builtin_ia32_loadups, "V4ffC*", "") +BUILTIN(__builtin_ia32_storeups, "vf*V4f", "") +BUILTIN(__builtin_ia32_loadhps, "V4fV4fV2i*", "") +BUILTIN(__builtin_ia32_loadlps, "V4fV4fV2i*", "") +BUILTIN(__builtin_ia32_storehps, "vV2i*V4f", "") +BUILTIN(__builtin_ia32_storelps, "vV2i*V4f", "") +BUILTIN(__builtin_ia32_movmskps, "iV4f", "") +BUILTIN(__builtin_ia32_pmovmskb, "iV8c", "") +BUILTIN(__builtin_ia32_movntps, "vf*V4f", "") +BUILTIN(__builtin_ia32_movntq, "vV1LLi*V1LLi", "") +BUILTIN(__builtin_ia32_sfence, "v", "") +BUILTIN(__builtin_ia32_psadbw, "V4sV8cV8c", "") +BUILTIN(__builtin_ia32_rcpps, "V4fV4f", "") +BUILTIN(__builtin_ia32_rcpss, "V4fV4f", "") +BUILTIN(__builtin_ia32_rsqrtps, "V4fV4f", "") +BUILTIN(__builtin_ia32_rsqrtss, "V4fV4f", "") +BUILTIN(__builtin_ia32_sqrtps, "V4fV4f", "") +BUILTIN(__builtin_ia32_sqrtss, "V4fV4f", "") +BUILTIN(__builtin_ia32_shufps, "V4fV4fV4fi", "") +BUILTIN(__builtin_ia32_femms, "v", "") +BUILTIN(__builtin_ia32_pavgusb, "V8cV8cV8c", "") +BUILTIN(__builtin_ia32_pf2id, "V2iV2f", "") +BUILTIN(__builtin_ia32_pfacc, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pfadd, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pfcmpeq, "V2iV2fV2f", "") +BUILTIN(__builtin_ia32_pfcmpge, "V2iV2fV2f", "") +BUILTIN(__builtin_ia32_pfcmpgt, "V2iV2fV2f", "") +BUILTIN(__builtin_ia32_pfmax, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pfmin, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pfmul, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pfrcp, "V2fV2f", "") +BUILTIN(__builtin_ia32_pfrcpit1, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pfrcpit2, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pfrsqrt, "V2fV2f", "") +BUILTIN(__builtin_ia32_pfrsqit1, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pfsub, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pfsubr, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pi2fd, "V2fV2i", "") +BUILTIN(__builtin_ia32_pmulhrw, "V4sV4sV4s", "") +BUILTIN(__builtin_ia32_pf2iw, "V2iV2f", "") +BUILTIN(__builtin_ia32_pfnacc, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pfpnacc, "V2fV2fV2f", "") +BUILTIN(__builtin_ia32_pi2fw, "V2fV2i", "") +BUILTIN(__builtin_ia32_pswapdsf, "V2fV2f", "") +BUILTIN(__builtin_ia32_pswapdsi, "V2iV2i", "") +BUILTIN(__builtin_ia32_maskmovdqu, "vV16cV16cc*", "") +BUILTIN(__builtin_ia32_loadupd, "V2ddC*", "") +BUILTIN(__builtin_ia32_storeupd, "vd*V2d", "") +BUILTIN(__builtin_ia32_loadhpd, "V2dV2ddC*", "") +BUILTIN(__builtin_ia32_loadlpd, "V2dV2ddC*", "") +BUILTIN(__builtin_ia32_movmskpd, "iV2d", "") +BUILTIN(__builtin_ia32_pmovmskb128, "iV16c", "") +BUILTIN(__builtin_ia32_movnti, "vi*i", "") +BUILTIN(__builtin_ia32_movntpd, "vd*V2d", "") +BUILTIN(__builtin_ia32_movntdq, "vV2LLi*V2LLi", "") +BUILTIN(__builtin_ia32_pshufd, "V4iV4ii", "") +BUILTIN(__builtin_ia32_pshuflw, "V8sV8si", "") +BUILTIN(__builtin_ia32_pshufhw, "V8sV8si", "") +BUILTIN(__builtin_ia32_psadbw128, "V2LLiV16cV16c", "") +BUILTIN(__builtin_ia32_sqrtpd, "V2dV2d", "") +BUILTIN(__builtin_ia32_sqrtsd, "V2dV2d", "") +BUILTIN(__builtin_ia32_shufpd, "V2dV2dV2di", "") +BUILTIN(__builtin_ia32_cvtdq2pd, "V2dV4i", "") +BUILTIN(__builtin_ia32_cvtdq2ps, "V4fV4i", "") +BUILTIN(__builtin_ia32_cvtpd2dq, "V2LLiV2d", "") +BUILTIN(__builtin_ia32_cvtpd2pi, "V2iV2d", "") +BUILTIN(__builtin_ia32_cvtpd2ps, "V4fV2d", "") +BUILTIN(__builtin_ia32_cvttpd2dq, "V4iV2d", "") +BUILTIN(__builtin_ia32_cvttpd2pi, "V2iV2d", "") +BUILTIN(__builtin_ia32_cvtpi2pd, "V2dV2i", "") +BUILTIN(__builtin_ia32_cvtsd2si, "iV2d", "") +BUILTIN(__builtin_ia32_cvttsd2si, "iV2d", "") +BUILTIN(__builtin_ia32_cvtsd2si64, "LLiV2d", "") +BUILTIN(__builtin_ia32_cvttsd2si64, "LLiV2d", "") +BUILTIN(__builtin_ia32_cvtps2dq, "V4iV4f", "") +BUILTIN(__builtin_ia32_cvtps2pd, "V2dV4f", "") +BUILTIN(__builtin_ia32_cvttps2dq, "V4iV4f", "") +BUILTIN(__builtin_ia32_cvtsi2sd, "V2dV2di", "") +BUILTIN(__builtin_ia32_cvtsi642sd, "V2dV2dLLi", "") +BUILTIN(__builtin_ia32_cvtsd2ss, "V4fV4fV2d", "") +BUILTIN(__builtin_ia32_cvtss2sd, "V2dV2dV4f", "") +BUILTIN(__builtin_ia32_clflush, "vvC*", "") +BUILTIN(__builtin_ia32_lfence, "v", "") +BUILTIN(__builtin_ia32_mfence, "v", "") +BUILTIN(__builtin_ia32_loaddqu, "V16ccC*", "") +BUILTIN(__builtin_ia32_storedqu, "vc*V16c", "") +BUILTIN(__builtin_ia32_psllwi, "V4sV4si", "") +BUILTIN(__builtin_ia32_pslldi, "V2iV2ii", "") +BUILTIN(__builtin_ia32_psllqi, "V1LLiV1LLii", "") +BUILTIN(__builtin_ia32_psrawi, "V4sV4si", "") +BUILTIN(__builtin_ia32_psradi, "V2iV2ii", "") +BUILTIN(__builtin_ia32_psrlwi, "V4sV4si", "") +BUILTIN(__builtin_ia32_psrldi, "V2iV2ii", "") +BUILTIN(__builtin_ia32_psrlqi, "V1LLiV1LLii", "") +BUILTIN(__builtin_ia32_pmuludq, "V1LLiV2iV2i", "") +BUILTIN(__builtin_ia32_pmuludq128, "V2LLiV4iV4i", "") +BUILTIN(__builtin_ia32_psraw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_psrad128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_psrlw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_psrld128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_pslldqi128, "V2LLiV2LLii", "") +BUILTIN(__builtin_ia32_psrldqi128, "V2LLiV2LLii", "") +BUILTIN(__builtin_ia32_psrlq128, "V2LLiV2LLiV2LLi", "") +BUILTIN(__builtin_ia32_psllw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pslld128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_psllq128, "V2LLiV2LLiV2LLi", "") +BUILTIN(__builtin_ia32_psllwi128, "V8sV8si", "") +BUILTIN(__builtin_ia32_pslldi128, "V4iV4ii", "") +BUILTIN(__builtin_ia32_psllqi128, "V2LLiV2LLii", "") +BUILTIN(__builtin_ia32_psrlwi128, "V8sV8si", "") +BUILTIN(__builtin_ia32_psrldi128, "V4iV4ii", "") +BUILTIN(__builtin_ia32_psrlqi128, "V2LLiV2LLii", "") +BUILTIN(__builtin_ia32_psrawi128, "V8sV8si", "") +BUILTIN(__builtin_ia32_psradi128, "V4iV4ii", "") +BUILTIN(__builtin_ia32_pmaddwd128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_monitor, "vv*UiUi", "") +BUILTIN(__builtin_ia32_mwait, "vUiUi", "") +BUILTIN(__builtin_ia32_movshdup, "V4fV4f", "") +BUILTIN(__builtin_ia32_movsldup, "V4fV4f", "") +BUILTIN(__builtin_ia32_lddqu, "V16ccC*", "") +BUILTIN(__builtin_ia32_palignr128, "V2LLiV2LLiV2LLii", "") +BUILTIN(__builtin_ia32_palignr, "V1LLiV1LLiV1LLis", "") +BUILTIN(__builtin_ia32_vec_init_v2si, "V2iii", "") +BUILTIN(__builtin_ia32_vec_init_v4hi, "V4sssss", "") +BUILTIN(__builtin_ia32_vec_init_v8qi, "V8ccccccccc", "") +BUILTIN(__builtin_ia32_vec_ext_v2df, "dV2di", "") +BUILTIN(__builtin_ia32_vec_ext_v2di, "LLiV2LLii", "") +BUILTIN(__builtin_ia32_vec_ext_v4sf, "fV4fi", "") +BUILTIN(__builtin_ia32_vec_ext_v4si, "iV4ii", "") +BUILTIN(__builtin_ia32_vec_ext_v8hi, "UsV8si", "") +BUILTIN(__builtin_ia32_vec_ext_v4hi, "sV4si", "") +BUILTIN(__builtin_ia32_vec_ext_v2si, "iV2ii", "") +BUILTIN(__builtin_ia32_vec_set_v8hi, "V8sV8ssi", "") +BUILTIN(__builtin_ia32_vec_set_v4hi, "V4sV4ssi", "") +BUILTIN(__builtin_ia32_vec_set_v16qi, "V16cV16cii", "") +BUILTIN(__builtin_ia32_vec_set_v4si, "V4iV4iii", "") +BUILTIN(__builtin_ia32_vec_set_v2di, "V2LLiV2LLiLLii", "") +BUILTIN(__builtin_ia32_insertps128, "V4fV4fV4fi", "") + +BUILTIN(__builtin_ia32_loadlv4si, "V4iV2i*", "") +BUILTIN(__builtin_ia32_storelv4si, "vV2i*V2LLi", "") + +BUILTIN(__builtin_ia32_pblendvb128, "V16cV16cV16cV16c", "") +BUILTIN(__builtin_ia32_pblendw128, "V8sV8sV8si", "") +BUILTIN(__builtin_ia32_blendpd, "V2dV2dV2di", "") +BUILTIN(__builtin_ia32_blendps, "V4fV4fV4fi", "") +BUILTIN(__builtin_ia32_blendvpd, "V2dV2dV2dV2d", "") +BUILTIN(__builtin_ia32_blendvps, "V4fV4fV4fV4f", "") + +BUILTIN(__builtin_ia32_packusdw128, "V8sV4iV4i", "") +BUILTIN(__builtin_ia32_pmaxsb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_pmaxsd128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_pmaxud128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_pmaxuw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pminsb128, "V16cV16cV16c", "") +BUILTIN(__builtin_ia32_pminsd128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_pminud128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_pminuw128, "V8sV8sV8s", "") +BUILTIN(__builtin_ia32_pmovsxbd128, "V4iV16c", "") +BUILTIN(__builtin_ia32_pmovsxbq128, "V2LLiV16c", "") +BUILTIN(__builtin_ia32_pmovsxbw128, "V8sV16c", "") +BUILTIN(__builtin_ia32_pmovsxdq128, "V2LLiV4i", "") +BUILTIN(__builtin_ia32_pmovsxwd128, "V4iV8s", "") +BUILTIN(__builtin_ia32_pmovsxwq128, "V2LLiV8s", "") +BUILTIN(__builtin_ia32_pmovzxbd128, "V4iV16c", "") +BUILTIN(__builtin_ia32_pmovzxbq128, "V2LLiV16c", "") +BUILTIN(__builtin_ia32_pmovzxbw128, "V8sV16c", "") +BUILTIN(__builtin_ia32_pmovzxdq128, "V2LLiV4i", "") +BUILTIN(__builtin_ia32_pmovzxwd128, "V4iV8s", "") +BUILTIN(__builtin_ia32_pmovzxwq128, "V2LLiV8s", "") +BUILTIN(__builtin_ia32_pmuldq128, "V2LLiV4iV4i", "") +BUILTIN(__builtin_ia32_pmulld128, "V4iV4iV4i", "") +BUILTIN(__builtin_ia32_roundps, "V4fV4fi", "") +BUILTIN(__builtin_ia32_roundss, "V4fV4fi", "") +BUILTIN(__builtin_ia32_roundsd, "V2dV2di", "") +BUILTIN(__builtin_ia32_roundpd, "V2dV2di", "") + + +#undef BUILTIN |