diff options
Diffstat (limited to 'include/llvm/DebugInfo/CodeView/CodeViewRegisters.def')
| -rw-r--r-- | include/llvm/DebugInfo/CodeView/CodeViewRegisters.def | 210 |
1 files changed, 205 insertions, 5 deletions
diff --git a/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def b/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def index fdfcf4d53a23..9767e49c44f5 100644 --- a/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def +++ b/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def @@ -1,9 +1,8 @@ //===-- CodeViewRegisters.def - CodeView registers --------------*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -15,8 +14,15 @@ #define CV_REGISTER(name, value) #endif +#if !defined(CV_REGISTERS_ALL) && !defined(CV_REGISTERS_X86) && \ + !defined(CV_REGISTERS_ARM64) +#error Need include at least one register set. +#endif + // This currently only contains the "register subset shared by all processor -// types" (ERR etc.) and the x86 registers. +// types" (ERR etc.) and the x86/arm64 registers. + +#if defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_X86) // Some system headers define macros that conflict with our enums. Every // compiler supported by LLVM has the push_macro and pop_macro pragmas, so use @@ -357,3 +363,197 @@ CV_REGISTER(AMD64_K7, 765) #pragma pop_macro("CR2") #pragma pop_macro("CR3") #pragma pop_macro("CR4") + +#endif // defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_X86) + +#if defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_ARM64) + +// ARM64 registers + +CV_REGISTER(ARM64_NOREG, 0) + +// General purpose 32-bit integer registers + +CV_REGISTER(ARM64_W0, 10) +CV_REGISTER(ARM64_W1, 11) +CV_REGISTER(ARM64_W2, 12) +CV_REGISTER(ARM64_W3, 13) +CV_REGISTER(ARM64_W4, 14) +CV_REGISTER(ARM64_W5, 15) +CV_REGISTER(ARM64_W6, 16) +CV_REGISTER(ARM64_W7, 17) +CV_REGISTER(ARM64_W8, 18) +CV_REGISTER(ARM64_W9, 19) +CV_REGISTER(ARM64_W10, 20) +CV_REGISTER(ARM64_W11, 21) +CV_REGISTER(ARM64_W12, 22) +CV_REGISTER(ARM64_W13, 23) +CV_REGISTER(ARM64_W14, 24) +CV_REGISTER(ARM64_W15, 25) +CV_REGISTER(ARM64_W16, 26) +CV_REGISTER(ARM64_W17, 27) +CV_REGISTER(ARM64_W18, 28) +CV_REGISTER(ARM64_W19, 29) +CV_REGISTER(ARM64_W20, 30) +CV_REGISTER(ARM64_W21, 31) +CV_REGISTER(ARM64_W22, 32) +CV_REGISTER(ARM64_W23, 33) +CV_REGISTER(ARM64_W24, 34) +CV_REGISTER(ARM64_W25, 35) +CV_REGISTER(ARM64_W26, 36) +CV_REGISTER(ARM64_W27, 37) +CV_REGISTER(ARM64_W28, 38) +CV_REGISTER(ARM64_W29, 39) +CV_REGISTER(ARM64_W30, 40) +CV_REGISTER(ARM64_WZR, 41) + +// General purpose 64-bit integer registers + +CV_REGISTER(ARM64_X0, 50) +CV_REGISTER(ARM64_X1, 51) +CV_REGISTER(ARM64_X2, 52) +CV_REGISTER(ARM64_X3, 53) +CV_REGISTER(ARM64_X4, 54) +CV_REGISTER(ARM64_X5, 55) +CV_REGISTER(ARM64_X6, 56) +CV_REGISTER(ARM64_X7, 57) +CV_REGISTER(ARM64_X8, 58) +CV_REGISTER(ARM64_X9, 59) +CV_REGISTER(ARM64_X10, 60) +CV_REGISTER(ARM64_X11, 61) +CV_REGISTER(ARM64_X12, 62) +CV_REGISTER(ARM64_X13, 63) +CV_REGISTER(ARM64_X14, 64) +CV_REGISTER(ARM64_X15, 65) +CV_REGISTER(ARM64_X16, 66) +CV_REGISTER(ARM64_X17, 67) +CV_REGISTER(ARM64_X18, 68) +CV_REGISTER(ARM64_X19, 69) +CV_REGISTER(ARM64_X20, 70) +CV_REGISTER(ARM64_X21, 71) +CV_REGISTER(ARM64_X22, 72) +CV_REGISTER(ARM64_X23, 73) +CV_REGISTER(ARM64_X24, 74) +CV_REGISTER(ARM64_X25, 75) +CV_REGISTER(ARM64_X26, 76) +CV_REGISTER(ARM64_X27, 77) +CV_REGISTER(ARM64_X28, 78) +CV_REGISTER(ARM64_FP, 79) +CV_REGISTER(ARM64_LR, 80) +CV_REGISTER(ARM64_SP, 81) +CV_REGISTER(ARM64_ZR, 82) + +// status register + +CV_REGISTER(ARM64_NZCV, 90) + +// 32-bit floating point registers + +CV_REGISTER(ARM64_S0, 100) +CV_REGISTER(ARM64_S1, 101) +CV_REGISTER(ARM64_S2, 102) +CV_REGISTER(ARM64_S3, 103) +CV_REGISTER(ARM64_S4, 104) +CV_REGISTER(ARM64_S5, 105) +CV_REGISTER(ARM64_S6, 106) +CV_REGISTER(ARM64_S7, 107) +CV_REGISTER(ARM64_S8, 108) +CV_REGISTER(ARM64_S9, 109) +CV_REGISTER(ARM64_S10, 110) +CV_REGISTER(ARM64_S11, 111) +CV_REGISTER(ARM64_S12, 112) +CV_REGISTER(ARM64_S13, 113) +CV_REGISTER(ARM64_S14, 114) +CV_REGISTER(ARM64_S15, 115) +CV_REGISTER(ARM64_S16, 116) +CV_REGISTER(ARM64_S17, 117) +CV_REGISTER(ARM64_S18, 118) +CV_REGISTER(ARM64_S19, 119) +CV_REGISTER(ARM64_S20, 120) +CV_REGISTER(ARM64_S21, 121) +CV_REGISTER(ARM64_S22, 122) +CV_REGISTER(ARM64_S23, 123) +CV_REGISTER(ARM64_S24, 124) +CV_REGISTER(ARM64_S25, 125) +CV_REGISTER(ARM64_S26, 126) +CV_REGISTER(ARM64_S27, 127) +CV_REGISTER(ARM64_S28, 128) +CV_REGISTER(ARM64_S29, 129) +CV_REGISTER(ARM64_S30, 130) +CV_REGISTER(ARM64_S31, 131) + +// 64-bit floating point registers + +CV_REGISTER(ARM64_D0, 140) +CV_REGISTER(ARM64_D1, 141) +CV_REGISTER(ARM64_D2, 142) +CV_REGISTER(ARM64_D3, 143) +CV_REGISTER(ARM64_D4, 144) +CV_REGISTER(ARM64_D5, 145) +CV_REGISTER(ARM64_D6, 146) +CV_REGISTER(ARM64_D7, 147) +CV_REGISTER(ARM64_D8, 148) +CV_REGISTER(ARM64_D9, 149) +CV_REGISTER(ARM64_D10, 150) +CV_REGISTER(ARM64_D11, 151) +CV_REGISTER(ARM64_D12, 152) +CV_REGISTER(ARM64_D13, 153) +CV_REGISTER(ARM64_D14, 154) +CV_REGISTER(ARM64_D15, 155) +CV_REGISTER(ARM64_D16, 156) +CV_REGISTER(ARM64_D17, 157) +CV_REGISTER(ARM64_D18, 158) +CV_REGISTER(ARM64_D19, 159) +CV_REGISTER(ARM64_D20, 160) +CV_REGISTER(ARM64_D21, 161) +CV_REGISTER(ARM64_D22, 162) +CV_REGISTER(ARM64_D23, 163) +CV_REGISTER(ARM64_D24, 164) +CV_REGISTER(ARM64_D25, 165) +CV_REGISTER(ARM64_D26, 166) +CV_REGISTER(ARM64_D27, 167) +CV_REGISTER(ARM64_D28, 168) +CV_REGISTER(ARM64_D29, 169) +CV_REGISTER(ARM64_D30, 170) +CV_REGISTER(ARM64_D31, 171) + +// 128-bit SIMD registers + +CV_REGISTER(ARM64_Q0, 180) +CV_REGISTER(ARM64_Q1, 181) +CV_REGISTER(ARM64_Q2, 182) +CV_REGISTER(ARM64_Q3, 183) +CV_REGISTER(ARM64_Q4, 184) +CV_REGISTER(ARM64_Q5, 185) +CV_REGISTER(ARM64_Q6, 186) +CV_REGISTER(ARM64_Q7, 187) +CV_REGISTER(ARM64_Q8, 188) +CV_REGISTER(ARM64_Q9, 189) +CV_REGISTER(ARM64_Q10, 190) +CV_REGISTER(ARM64_Q11, 191) +CV_REGISTER(ARM64_Q12, 192) +CV_REGISTER(ARM64_Q13, 193) +CV_REGISTER(ARM64_Q14, 194) +CV_REGISTER(ARM64_Q15, 195) +CV_REGISTER(ARM64_Q16, 196) +CV_REGISTER(ARM64_Q17, 197) +CV_REGISTER(ARM64_Q18, 198) +CV_REGISTER(ARM64_Q19, 199) +CV_REGISTER(ARM64_Q20, 200) +CV_REGISTER(ARM64_Q21, 201) +CV_REGISTER(ARM64_Q22, 202) +CV_REGISTER(ARM64_Q23, 203) +CV_REGISTER(ARM64_Q24, 204) +CV_REGISTER(ARM64_Q25, 205) +CV_REGISTER(ARM64_Q26, 206) +CV_REGISTER(ARM64_Q27, 207) +CV_REGISTER(ARM64_Q28, 208) +CV_REGISTER(ARM64_Q29, 209) +CV_REGISTER(ARM64_Q30, 210) +CV_REGISTER(ARM64_Q31, 211) + +// Floating point status register + +CV_REGISTER(ARM64_FPSR, 220) + +#endif // defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_ARM64) |