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-rw-r--r--include/llvm/Target/TargetELFWriterInfo.h39
-rw-r--r--include/llvm/Target/TargetLowering.h43
-rw-r--r--include/llvm/Target/TargetMachine.h10
-rw-r--r--include/llvm/Target/TargetOptions.h8
-rw-r--r--include/llvm/Target/TargetSelectionDAG.td1
5 files changed, 76 insertions, 25 deletions
diff --git a/include/llvm/Target/TargetELFWriterInfo.h b/include/llvm/Target/TargetELFWriterInfo.h
index e266a71f8c85..f7e3392577d9 100644
--- a/include/llvm/Target/TargetELFWriterInfo.h
+++ b/include/llvm/Target/TargetELFWriterInfo.h
@@ -15,15 +15,21 @@
#define LLVM_TARGET_TARGETELFWRITERINFO_H
namespace llvm {
+ class Function;
+ class TargetData;
+ class TargetMachine;
//===--------------------------------------------------------------------===//
// TargetELFWriterInfo
//===--------------------------------------------------------------------===//
class TargetELFWriterInfo {
+ protected:
// EMachine - This field is the target specific value to emit as the
// e_machine member of the ELF header.
unsigned short EMachine;
+ TargetMachine &TM;
+ bool is64Bit, isLittleEndian;
public:
// Machine architectures
@@ -44,10 +50,39 @@ namespace llvm {
EM_X86_64 = 62 // AMD64
};
- explicit TargetELFWriterInfo(MachineType machine) : EMachine(machine) {}
- virtual ~TargetELFWriterInfo() {}
+ // ELF File classes
+ enum {
+ ELFCLASS32 = 1, // 32-bit object file
+ ELFCLASS64 = 2 // 64-bit object file
+ };
+
+ // ELF Endianess
+ enum {
+ ELFDATA2LSB = 1, // Little-endian object file
+ ELFDATA2MSB = 2 // Big-endian object file
+ };
+
+ explicit TargetELFWriterInfo(TargetMachine &tm);
+ virtual ~TargetELFWriterInfo();
unsigned short getEMachine() const { return EMachine; }
+ unsigned getEFlags() const { return 0; }
+ unsigned getEIClass() const { return is64Bit ? ELFCLASS64 : ELFCLASS32; }
+ unsigned getEIData() const {
+ return isLittleEndian ? ELFDATA2LSB : ELFDATA2MSB;
+ }
+
+ /// ELF Header and ELF Section Header Info
+ unsigned getHdrSize() const { return is64Bit ? 64 : 52; }
+ unsigned getSHdrSize() const { return is64Bit ? 64 : 40; }
+
+ /// Symbol Table Info
+ unsigned getSymTabEntrySize() const { return is64Bit ? 24 : 16; }
+ unsigned getSymTabAlignment() const { return is64Bit ? 8 : 4; }
+
+ /// getFunctionAlignment - Returns the alignment for function 'F', targets
+ /// with different alignment constraints should overload this method
+ virtual unsigned getFunctionAlignment(const Function *F) const;
};
} // end llvm namespace
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 327af275114c..47dcc6c8e48f 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -350,7 +350,7 @@ public:
LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
if (VT.isExtended()) return Expand;
assert(Op < array_lengthof(OpActions) &&
- (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
+ (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*8 &&
"Table isn't big enough!");
return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
}
@@ -417,11 +417,10 @@ public:
/// for it.
LegalizeAction
getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
- assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
- (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 &&
+ assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
+ ((unsigned)VT.getSimpleVT()) < MVT::LAST_VALUETYPE &&
"Table isn't big enough!");
- return (LegalizeAction)((IndexedModeActions[0][IdxMode] >>
- (2*VT.getSimpleVT())) & 3);
+ return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode]));
}
/// isIndexedLoadLegal - Return true if the specified indexed load is legal
@@ -438,11 +437,10 @@ public:
/// for it.
LegalizeAction
getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
- assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
- (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
+ assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
+ (unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
"Table isn't big enough!");
- return (LegalizeAction)((IndexedModeActions[1][IdxMode] >>
- (2*VT.getSimpleVT())) & 3);
+ return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode]));
}
/// isIndexedStoreLegal - Return true if the specified indexed load is legal
@@ -942,7 +940,7 @@ protected:
/// with the specified type and indicate what to do about it.
void setOperationAction(unsigned Op, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
+ assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*8 &&
Op < array_lengthof(OpActions) && "Table isn't big enough!");
OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2;
@@ -978,11 +976,10 @@ protected:
/// TargetLowering.cpp
void setIndexedLoadAction(unsigned IdxMode, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 &&
- IdxMode < array_lengthof(IndexedModeActions[0]) &&
+ assert((unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
+ IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
"Table isn't big enough!");
- IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
- IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
+ IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode] = (uint8_t)Action;
}
/// setIndexedStoreAction - Indicate that the specified indexed store does or
@@ -991,11 +988,10 @@ protected:
/// TargetLowering.cpp
void setIndexedStoreAction(unsigned IdxMode, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
- IdxMode < array_lengthof(IndexedModeActions[1]) &&
+ assert((unsigned)VT.getSimpleVT() < MVT::LAST_VALUETYPE &&
+ IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
"Table isn't big enough!");
- IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
- IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
+ IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode] = (uint8_t)Action;
}
/// setConvertAction - Indicate that the specified conversion does or does
@@ -1581,10 +1577,13 @@ private:
/// indicates how instruction selection should deal with the store.
uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
- /// IndexedModeActions - For each indexed mode and each value type, keep a
- /// pair of LegalizeAction that indicates how instruction selection should
- /// deal with the load / store.
- uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
+ /// IndexedModeActions - For each indexed mode and each value type,
+ /// keep a pair of LegalizeAction that indicates how instruction
+ /// selection should deal with the load / store. The first
+ /// dimension is now the value_type for the reference. The second
+ /// dimension is the load [0] vs. store[1]. The third dimension
+ /// represents the various modes for load store.
+ uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
/// ConvertActions - For each conversion from source type to destination type,
/// keep a LegalizeAction that indicates how instruction selection should
diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index bdcc4eff675f..a8db68c59789 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -78,6 +78,14 @@ namespace CodeGenOpt {
};
}
+namespace FloatABI {
+ enum ABIType {
+ Default,
+ Soft,
+ Hard
+ };
+}
+
//===----------------------------------------------------------------------===//
///
/// TargetMachine - Primary interface to the complete machine description for
@@ -88,7 +96,7 @@ class TargetMachine {
TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
void operator=(const TargetMachine &); // DO NOT IMPLEMENT
protected: // Can only create subclasses.
- TargetMachine() : AsmInfo(0) { }
+ TargetMachine();
/// getSubtargetImpl - virtual method implemented by subclasses that returns
/// a reference to that target's TargetSubtarget-derived member variable.
diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h
index 0c74fa1f2c1e..377e03f95c47 100644
--- a/include/llvm/Target/TargetOptions.h
+++ b/include/llvm/Target/TargetOptions.h
@@ -73,6 +73,14 @@ namespace llvm {
/// target FP instructions.
extern bool UseSoftFloat;
+ /// FloatABIType - This setting is set by -float-abi=xxx option is specfied
+ /// on the command line. This setting may either be Default, Soft, or Hard.
+ /// Default selects the target's default behavior. Soft selects the ABI for
+ /// UseSoftFloat, but does not inidcate that FP hardware may not be used.
+ /// Such a combination is unfortunately popular (e.g. arm-apple-darwin).
+ /// Hard presumes that the normal FP ABI is used.
+ extern FloatABI::ABIType FloatABIType;
+
/// NoZerosInBSS - By default some codegens place zero-initialized data to
/// .bss section. This flag disables such behaviour (necessary, e.g. for
/// crt*.o compiling).
diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td
index 2cd29676dbfd..364d4d0d3cc0 100644
--- a/include/llvm/Target/TargetSelectionDAG.td
+++ b/include/llvm/Target/TargetSelectionDAG.td
@@ -228,6 +228,7 @@ class SDNode<string opcode, SDTypeProfile typeprof,
SDTypeProfile TypeProfile = typeprof;
}
+// Special TableGen-recognized dag nodes
def set;
def implicit;
def parallel;
generated by cgit v1.3 (git 2.53.0) at 2026-08-06 03:38:51 +0000