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Diffstat (limited to 'include')
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diff --git a/include/COPYING b/include/COPYING new file mode 100644 index 000000000000..d60c31a97a54 --- /dev/null +++ b/include/COPYING @@ -0,0 +1,340 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Library General Public License instead.) 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + <one line to give the program's name and a brief idea of what it does.> + Copyright (C) <year> <name of author> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + <signature of Ty Coon>, 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. diff --git a/include/ChangeLog-9103 b/include/ChangeLog-9103 new file mode 100644 index 000000000000..670fe38b3125 --- /dev/null +++ b/include/ChangeLog-9103 @@ -0,0 +1,2737 @@ +2003-12-19 Andreas Tobler <a.tobler@schweiz.ch> + + * include/fibheap.h (fibnode): Use __extension__ for + bit-fields mark and degree if __GNUC__. + +2003-12-18 Kazu Hirata <kazu@cs.umass.edu> + + * include/fibheap.h (fibnode): Use unsigned long int for + bit-fields if __GNUC__ is defined. + +2003-12-04 H.J. Lu <hongjiu.lu@intel.com> + + * bfdlink.h (bfd_link_info): Change relax_finalizing to + need_relax_finalize. + +2003-12-03 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_hash_entry): Rename "next" to "und_next". + +2003-12-02 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_info): Remove mpc860c0 field. + +2003-11-18 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * opcode/mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB. + +2003-11-14 Nick Clifton <nickc@redhat.com> + + * dis-asm.h (struct disassemble_info): Add new field + 'symbol_is_valid' which is a function which can tell the + disassembler to skip certain symbols as they should not be + displayed to the user. + (arm_symbol_is_valid): New prototype. This is the ARM + specific function for the symbol_is_valid field. + (generic_symbol_is_valid): New prototype. This is the default + function pointed to by the symbol_is_valid field. + +2003-11-06 Bruno Rohee <bruno@rohee.com> + + * hp-symtab.h: Fix "the the" typo. + +2003-10-24 H.J. Lu <hongjiu.lu@intel.com> + + * bfdlink.h (bfd_elf_version_expr): Add "symbol" and remove + "wildcard". + +2003-10-22 Joseph S. Myers <jsm@polyomino.org.uk> + + * obstack.h: Merge the following change from gnulib: + 2003-10-21 Paul Eggert <eggert@twinsun.com> + * obstack.h (obstack_1grow_fast): Properly parenthesize arg. + (obstack_ptr_grow_fast, obstack_int_grow_fast): + Don't use lvalue casts, as GCC plans to remove support for them + in GCC 3.5. Reported by Joseph S. Myers. This bug + was also present in the non-GCC version, indicating that this + code had always been buggy and had never been widely used. + (obstack_1grow, obstack_ptr_grow, obstack_int_grow, obstack_blank): + Use the fast variant of each macro, rather than copying the + definiens of the fast variant; that way, we'll be more likely to + catch future bugs in the fast variants. + +2003-10-22 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_elf_version_expr): Remove match field. + Add wildcard and mask fields. + (BFD_ELF_VERSION_C_TYPE): Define. + (BFD_ELF_VERSION_CXX_TYPE): Likewise. + (BFD_ELF_VERSION_JAVA_TYPE): Likewise. + (struct bfd_elf_version_expr_head): New. + (struct bfd_elf_version_tree): Add match field. + Change type of globals and locals fields + to struct bfd_elf_version_expr_head. + +2003-10-14 Bob Wilson <bob.wilson@acm.org> + + * elf/xtensa.h: Formatting. Fix comments about property section + names for linkonce sections. + +2003-09-22 Andrew Cagney <cagney@redhat.com> + + * floatformat.h (struct floatformat): Add field "is_valid". + +2003-09-15 Andrew Cagney <cagney@redhat.com> + + * floatformat.h (floatformat_to_double): Make input buffer constant. + (floatformat_from_double, floatformat_is_valid): Ditto. + +2003-09-15 Andrew Cagney <cagney@redhat.com> + + * floatformat.h (struct floatformat): Make "exp_bias" signed. + +2003-09-15 Daniel Jacobowitz <drow@mvista.com> + + * floatformat.h (floatformat_is_valid): Add prototype. + +2003-08-27 Andrew Cagney <cagney@redhat.com> + + * dis-asm.h (init_disassemble_info): Declare. + (INIT_DISASSEMBLE_INFO): Redefine as a call to + init_disassemble_info. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Ditto. + +2003-08-20 Nick Clifton <nickc@redhat.com> + + * bfdlink.h (enum report_method): New enum. Describes how to + report something. + (struct bfd_link_info): Delete fields 'no_undefined' and + 'allow_shlib_undefined'. Replace with + 'unresolved_symbols_in_objects' and + 'unresolved_symbols_in_shared_libs'. + +2003-08-07 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h: Remove PARAMS macro. Replace PTR with void *. + * dis-asm.h: Likewise. + +2003-07-09 Bob Wilson <bob.wilson@acm.org> + + * xtensa-config.h: Undef all macros before defining them. + +2003-07-06 H.J. Lu <hongjiu.lu@intel.com> + + * demangle.h: Support C++. + +2003-07-01 Zack Weinberg <zack@codesourcery.com> + + * filenames.h: New file imported from binutils. + +2003-06-30 Bob Wilson <bob.wilson@acm.org> + + * xtensa-config.h: New file imported from binutils. + +2003-06-30 Bob Wilson <bob.wilson@acm.org> + + * xtensa-config.h (XCHAL_HAVE_CONST16, XCHAL_HAVE_ABS, + XCHAL_HAVE_ADDX, XCHAL_HAVE_L32R): Define. + +2003-06-25 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h: Correct spelling of "relocatable". + +2003-06-22 Zack Weinberg <zack@codesourcery.com> + + * safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC): Rename to + HOST_CHARSET_UNKNOWN, HOST_CHARSET_ASCII, HOST_CHARSET_EBCDIC + respectively. + +2003-06-21 Zack Weinberg <zack@codesourcery.com> + + * safe-ctype.h (HC_UNKNOWN, HC_ASCII, HC_EBCDIC, HOST_CHARSET): + New #defines. + +2003-06-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h: Delete HAVE_LONG_DOUBLE GCC bootstrap support. + +2003-05-23 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add execstack and noexecstack. + * elf/common.h (PT_GNU_STACK): Define. + +2003-06-03 H.J. Lu <hongjiu.lu@intel.com> + + * bfdlink.h (LD_DEFINITION_IN_DISCARDED_SECTION): New. + +2003-05-30 Ulrich Drepper <drepper@redhat.com> + Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add pie and executable + bits. + +2003-05-21 Nick Clifton <nickc@redhat.com> + + * bfdlink.h (struct bfd_link_hash_table): Fix typo in comment. + +2003-05-15 Jim Blandy <jimb@redhat.com> + + * libiberty.h (hex_value): Make the value an unsigned int, to + avoid unexpected sign-extension when cast to unsigned types larger + than int --- like bfd_vma, on some platforms. + (_hex_value): Update declaration. + +2003-05-09 Alan Modra <amodra@bigpond.net.au> + + * xtensa-isa-internal.h (xtensa_isa_module_struct): Remove const on + gen_num_opcodes_fn return type. + +2003-05-07 Jason Merrill <jason@redhat.com> + + * hashtab.h (iterative_hash): Prototype. + (iterative_hash_object): New macro. + +2003-04-28 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_info): Add relax_finalizing. + +2003-04-23 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_callbacks): Add error_handler. + +2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com> + + * coff/tic4x.h: Namespace cleanup. Replace s/c4x/tic4x + and s/c3x/tic3x/ + * coff/tc-tic4x.h: Ditto + * opcode/tic4x.h: Ditto + +2003-04-02 Bob Wilson <bob.wilson@acm.org> + + * xtensa-config.h: Remove comment indicating that this is a + generated file. + +2003-04-01 Bob Wilson <bob.wilson@acm.org> + + * dis-asm.h (print_insn_xtensa): Declare. + * xtensa-config.h: New file. + * xtensa-isa-internal.h: Likewise. + * xtensa-isa.h: Likewise. + +2003-03-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (ATTRIBUTE_NONNULL, ATTRIBUTE_NULL_PRINTF, + ATTRIBUTE_NULL_PRINTF_1, ATTRIBUTE_NULL_PRINTF_2, + ATTRIBUTE_NULL_PRINTF_3, ATTRIBUTE_NULL_PRINTF_4, + ATTRIBUTE_NULL_PRINTF_5): New. + (ATTRIBUTE_PRINTF): Add ATTRIBUTE_NONNULL. + +2003-03-17 Jan Hubicka <jh@suse.cz> + + * hashtab.h (htab_traverse_noresize): Declare. + +2003-02-27 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h: Document return value of physmem routines. + +2003-02-20 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (physmem_total, physmem_available): Prototype. + +2003-02-20 Daniel Jacobowitz <drow@mvista.com> + + * libiberty.h (lrealpath): Add declaration. + +2003-01-31 Grant Grundler <grundler@dsl2.external.hp.com> + + * hppa.h (ldwa, ldda): Add ordered opcodes. + +2003-01-26 Daniel Jacobowitz <drow@mvista.com> + + * hashtab.h (htab_alloc_with_arg, htab_free_with_arg): Add new types. + (struct htab): Add alloc_arg, alloc_with_arg_f, free_with_arg_f. + (htab_create_alloc_ex): New prototype. + (htab_set_functions_ex): New prototype. + +2003-01-25 Jakub Jelinek <jakub@redhat.com> + + * elf/sparc.h: Add TLS relocs. Move R_SPARC_REV32 to 252. + +2003-01-20 Svein E. Seldal <Svein.Seldal@solidas.com> + + * coff/tic4x.h (TICOFF_TARGET_MACHINE_GET): Fixed define bug + * coff/ti.h (TICOFF_TARGET_MACHINE_GET): Added macros + +2002-07-17 Geoffrey Keating <geoffk@redhat.com> + + * splay-tree.h (GTY): Define if undefined. + (splay_tree_allocate_fn): Return PTR for compatibility, not void *. + (struct splay_tree_node_s): Support gengtype. + (struct splay_tree_s): Likewise. Make allocate_data a PTR, + not a void *. + +2002-01-02 Ben Elliston <bje@redhat.com> + + * dis-asm.h (print_insn_iq2000): Declare. + +2002-12-24 Dmitry Diky <diwil@mail.ru> + + * dis-asm.h: Add msp430 disassembler prototype. + +2002-12-27 Chris Demetriou <cgd@broadcom.com> + + * dis-asm.h (print_mips_disassembler_options): Prototype. + +2002-12-23 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_info): Add "strip_discarded". + +2002-12-20 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_info): Replace bfd_boolean fields with + bit-fields. Rearrange to put all like types together. + +2002-11-30 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h: Replace boolean with bfd_boolean. Formatting. + +2002-11-23 Simon Burge <simonb@wasabisystems.com> + + * libiberty.h (basename): Add NetBSD to the list. + +2002-11-22 Daniel Jacobowitz <drow@mvista.com> + + * libiberty.h (make_relative_prefix): Add prototype. + +2002-11-16 Klee Dienes <kdienes@apple.com> + + * opcode/m88k.h (INSTAB): Remove 'next' field. + (instruction): Remove definition; replace with extern declaration + and mark as const. + +2002-11-14 Egor Duda <deo@logos-m.ru> + + * bfdlink.h (struct bfd_link_info): Add new boolean + field pei386_runtime_pseudo_reloc. + +2002-10-26 Roger Sayle <roger@eyesopen.com> + + * partition.h: Close the extern "C" scope when compiling with C++. + +2002-10-26 Roger Sayle <roger@eyesopen.com> + DJ Delorie <dj@redhat.com> + + PR bootstrap/8351 + * getopt.h: Avoid prototyping getopt with no arguments in C++. + +2002-10-24 Nathan Tallent <eraxxon@alumni.rice.edu> + + * ansidecl.h (__STDC__): Add (__alpha && __cplusplus) to the + list of platform compilers that may look, smell and act + like __STDC__ but that may not define it. + +2002-10-11 David O'Brien <obrien@FreeBSD.org> + + * getopt.h: getopt is in unistd.h (based on SUSv2). + +2002-09-26 Jakub Jelinek <jakub@redhat.com> + + * elf/x86-64.h: Add TLS relocs. + +2002-09-26 Andrew Cagney <ac131313@redhat.com> + + * regs/: Delete directory. + +2002-09-19 Alexandre Oliva <aoliva@redhat.com> + + * libiberty.h (asprintf, vasprintf): Don't declare them if the + corresponding HAVE_DECL_ macro is 1. + +2002-09-19 Jakub Jelinek <jakub@redhat.com> + + * elf/i386.h (R_386_TLS_TPOFF, R_386_TLS_IE, R_386_TLS_GOTIE): + Define. + +2002-09-19 Nathan Tallent <eraxxon@alumni.rice.edu> + + * dis-asm.h: Remove (errant) trailing semicolon (;) from the + extern "C" { } declaration. + +2002-09-04 Nick Clifton <nickc@redhat.com> + + * dis-asm.h (print_ppc_disassembler_options): Prototype. + +2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz> + + * coff/internal.h: Add new relocation types. + * coff/ti.h: Add file-header flags for tic4x code. + * dis-asm.h: Add standard disassembler for tic4x. + * opcode/tic4x.h: New file. + * coff/tic4x.h: New file + +2002-08-07 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_info): Add allow_undefined_version. + (bfd_elf_version_expr): Add symver and script. + +2002-07-31 Ian Dall <ian@sibyl.beware.dropbear.id.au> + + * bfdlink.h (bfd_link_common_skip_ar_symbols): New enum. + (struct bfd_link_info): Add new field 'common_skip_ar_symbols'. + +2002-07-25 Richard Sandiford <rsandifo@redhat.com> + + * opcode/mips.h (CPU_R2000): Remove. + +2002-07-19 Denis Chertykov <denisc@overta.ru> + Matthew Green <mrg@redhat.com> + + * dis-asm.h (print_insn_ip2k): Declare. + +2002-07-10 Jakub Jelinek <jakub@redhat.com> + + * elf/common.h (SHT_GNU_LIBLIST, DT_GNU_PRELINKED, + DT_GNU_CONFLICT*, DT_GNU_LIBLIST*): Define. + +2002-07-01 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_sym_chain): Declare. + (struct bfd_link_info): Add gc_sym_list. Formatting fixes. + +2002-06-25 Alan Modra <amodra@bigpond.net.au> + + * demangle.h: #include "ansidecl.h" rather than #include <ansidecl.h>. + * fibheap.h: Likewise. + * hashtab.h: Likewise. + * partition.h: Likewise. + * sort.h: Likewise. + * splay-tree.h: Likewise. + +2002-06-24 Alan Modra <amodra@bigpond.net.au> + + * libiberty.h (basename): Don't declare if HAVE_DECL_BASENAME. + * getopt.h (getopt): Don't declare if HAVE_DECL_GETOPT. + +2002-06-18 Dave Brolley <brolley@redhat.com> + + From Catherine Moore: + * dis-asm.h (print_insn_frv): New prototype. + +2002-06-09 Andrew Cagney <cagney@redhat.com> + + * remote-sim.h: Move to directory gdb/. + * callback.h: Move to directory gdb/. + +2002-06-07 Charles Wilson <cwilson@ece.gatech.edu> + + * bfdlink.h (struct bfd_link_info): Change type of + pei386_auto_import field to int so that -1 can mean enabled by + default and 1 can mean enabled by command line switch. + +2002-06-06 DJ Delorie <dj@redhat.com> + + * hashtab.h (htab): Rearrange new members for backward + compatibility. + (htab_create): Don't use a macro that requires other headers. + +2002-06-05 Geoffrey Keating <geoffk@redhat.com> + + * hashtab.h (htab_create): Restore prototype for backward + compatibility. + (htab_try_create): Likewise. + +2002-05-22 Geoffrey Keating <geoffk@redhat.com> + + * hashtab.h (struct htab): Update for change to length specifier. + +2002-05-10 Geoffrey Keating <geoffk@redhat.com> + + * hashtab.h (GTY): Define if undefined. + (htab_alloc): New typedef. + (htab_free): New typedef. + (struct htab): Support gengtype; allow user-specified memory + allocation. + (htab_create_alloc): New. + (htab_create): Replace with #define. + (htab_try_create): Delete. + +2002-05-31 Michal Ludvig <mludvig@suse.cz> + + * elf/dwarf2.h (DW_CFA_low_user, DW_CFA_high_user): Renamed + to DW_CFA_lo_user, DW_CFA_hi_user respectively. + +2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> + + * dis-asm.h: Prototype print_insn_dlx. + +2002-05-23 Andrew Cagney <ac131313@redhat.com> + + * sim-d10v.h: Delete file. Moved to include/gdb/. + +2002-05-23 Jakub Jelinek <jakub@redhat.com> + + * elf/common.h (PT_TLS, SHF_TLS, STT_TLS, DF_STATIC_TLS): Define. + * elf/ia64.h (R_IA64_LTOFF_TPREL22): Renamed from R_IA64_LTOFF_TP22. + * elf/i386.h: Add TLS relocs. + +2002-05-21 H.J. Lu (hjl@gnu.org) + + * bfdlink.h (bfd_link_info): Add allow_multiple_definition. + +2002-05-17 J"orn Rennecke <joern.rennecke@superh.com> + + * dis-asm.h (print_insn_shl, print_insn_sh64l): Remove prototype. + +2002-04-16 David S. Miller <davem@redhat.com> + + * xregex2.h (__restrict_arr): Define to __restrict on GCC + 3.1 and later. Do not redefine. + +2002-04-01 Phil Edwards <pme@gcc.gnu.org> + + * dyn-string.h: Also allow IN_GLIBCPP_V3 to redefine names. + +2002-03-10 Daniel Jacobowitz <drow@mvista.com> + + * gdb: New directory. + +2002-03-06 Andrew Cagney <ac131313@redhat.com> + + * floatformat.h (floatformat_arm_ext): Delete declaration. + +2002-02-21 Jim Blandy <jimb@redhat.com> + + Allow the user to specify functions for allocating memory for + splay tree roots and nodes. + * splay-tree.h (splay_tree_allocate_fn, splay_tree_deallocate_fn): + New types. + (splay_tree): New fields: `allocate', `deallocate', and + `allocate_data'. + (splay_tree_new_with_allocator): New function declaration. + +2002-02-15 Alan Modra <amodra@bigpond.net.au> + + Support arbitrary length fill patterns. + * bfdlink.h (enum bfd_link_order_type): Remove bfd_fill_link_order. + (struct bfd_link_order): Remove fill. Add data.size. + +2002-02-08 Alexandre Oliva <aoliva@redhat.com> + + Contribute sh64-elf. + 2000-11-25 Hans-Peter Nilsson <hpn@cygnus.com> + * dis-asm.h (print_insn_sh64): New prototype. + (print_insn_sh64l): New prototype. + (print_insn_sh64x_media): New prototype. + +2002-02-05 Frank Ch. Eigler <fche@redhat.com> + + * dis-asm.h (disassemble_info): New field `insn_sets'. + (INIT_DISASSEMBLE_INFO): Clear it. + +2002-02-05 Jason Merrill <jason@redhat.com> + + * demangle.h (cplus_demangle_v3): Add "options" parm. + (cplus_demangle_v3_type): Remove prototype. + (DMGL_VERBOSE): New macro. + (DMGL_TYPES): New macro. + +2002-02-02 H.J. Lu (hjl@gnu.org) + + * demangle.h (cplus_demangle_v3_type): New prototype. + +2002-01-31 Ivan Guzvinec <ivang@opencores.org> + + * dis-asm.h : Add support for or32 targets + +2002-01-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (C_alloca): Add ATTRIBUTE_MALLOC. + +2002-01-27 David O'Brien <obrien@FreeBSD.org> + + * cgen.h (BFD_VERSION): Use BFD_VERSION_DATE instead. + +2001-12-14 Nick Clifton <nickc@cambridge.redhat.com> + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise the + disassembler_options field (to NULL). + +2001-12-13 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add eh_frame_hdr field. + +2001-12-07 Geoffrey Keating <geoffk@redhat.com> + + * dis-asm.h (print_insn_xstormy16): Declare. + +2001-12-06 Richard Henderson <rth@redhat.com> + + * demangle.h (no_demangling): New. + (NO_DEMANGLING_STYLE_STRING): New. + +2001-11-14 Alan Modra <amodra@bigpond.net.au> + + * dis-asm.h (print_insn_i386): Declare. + +2001-11-11 Timothy Wall <twall@alum.mit.edu> + + * dis-asm.h: Fix comment to refer to octets rather than bytes. + +2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> + + * dis-asm.h (print_insn_mmix): Add prototype. + +2001-10-24 Neil Booth <neil@daikokuya.demon.co.uk> + + * safe-ctype.h (_sch_isbasic, IS_ISOBASIC): New. + +2001-10-22 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (hex_init): Revert delete. + + * libiberty.h (_hex_value): Const-ify. + (hex_init): Delete. + +2001-10-16 Christopher Faylor <cgf@redhat.com> + + * filenames.h: Add cygwin to the list of dosish style path systems. + +2001-10-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h (demangler_engine): Const-ify. + * libiberty.h (buildargv): Likewise. + +2001-10-03 Vassili Karpov <malc@pulsesoft.com> + + * bfdlink.h (struct bfd_link_info): Add nocopyreloc field. + +2001-09-24 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (reconcat): New function. + +2001-09-18 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (concat, concat_length, concat_copy, concat_copy2, + ACONCAT): Improve comments. + +2001-09-18 Alan Modra <amodra@bigpond.net.au> + + * objalloc.h (OBJALLOC_ALIGN): Define using offsetof. + +2001-09-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (concat_length, concat_copy, concat_copy2, + libiberty_concat_ptr, ACONCAT): New. + + * libiberty.h (ASTRDUP): New macro. + libiberty_optr, libiberty_nptr, libiberty_len): Declare. + +2001-08-29 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h: Update comments reflecting previous change. + +2001-08-27 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (VA_OPEN, VA_CLOSE): Allow multiple uses. + +2001-08-25 Nick Clifton <nickc@cambridge.redhat.com> + + * bfdlink.h (struct bfd_link_info): Change 'spare_dynamic_tags' to + unsigned to remove a compile time warning message. + +2001-08-24 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_hash_table_type): New. The linker hash + table type, bfd_link_generic_hash_table and + bfd_link_elf_hash_table. + (bfd_link_hash_table): Add a new field, type, for the linker + hash table type. + +2001-08-23 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add combreloc and + spare_dynamic_tags fields. + +2001-08-23 Lars Brinkhoff <lars@nocrew.org> + + * dyn-string.h, fibheap.h, partition.h, sort.h, splay-tree.h: + replace "GNU CC" with "GCC". + +2001-08-21 Richard Henderson <rth@redhat.com> + + * fibheap.h: Tidy formatting. + (fibnode_t): Limit degree to 31 bits to avoid warning. + +2001-08-20 Daniel Berlin <dan@cgsoftware.com> + + * fibheap.h: New file. Fibonacci heap. + +2001-08-20 Andrew Cagney <ac131313@redhat.com> + + * floatformat.h (floatformat_arm_ext): Document as deprecated. + (floatformat_arm_ext_big, floatformat_arm_ext_littlebyte_bigword) + (floatformat_ia64_spill_little, floatformat_ia64_quad_little) + (floatformat_ia64_spill_big, floatformat_ia64_quad_big) + (floatformat_m88110_harris_ext): Declare. + +2001-08-18 Zack Weinberg <zackw@panix.com> + + * ansidecl.h: Reorganize for readability, remove documentation + of obsolete macros, document PARAMS and VPARAMS. Add new + macros VA_OPEN, VA_CLOSE, and VA_FIXEDARG for nicer variadic + function implementation. + +2001-08-16 Richard Henderson <rth@redhat.com> + + * hashtab.h (htab_hash_string): Declare. + +2001-08-10 Andrew Cagney <ac131313@redhat.com> + + * libiberty.h (lbasename): Change function declaration to return a + const char pointer. + +2001-08-02 Mark Kettenis <kettenis@gnu.org> + + * xregex.h (_REGEX_RE_COMP): Define. + (re_comp): Define to xre_comp. + (re_exec): Define to xre_exec. + +2001-08-02 Charles Wilson <cwilson@ece.gatech.edu> + + * bfdlink.h (struct bfd_link_info): add new boolean + field pei386_auto_import. + +2001-07-18 Andreas Jaeger <aj@suse.de> + + * xregex2.h: Place under LGPL version 2.1. + +2001-07-10 Jeff Johnston <jjohnstn@redhat.com> + + * xregex.h: New file to support libiberty regex. + * xregex2.h: Ditto. + +2001-06-15 Hans-Peter Nilsson <hp@axis.com> + + * bfdlink.h (struct bfd_link_info): New member export_dynamic. + +2001-05-16 Matt Kraai <kraai@alumni.carnegiemellon.edu> + + * partition.h: Fix misspelling of `implementation'. + +2001-05-10 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (NULL_PTR): Delete. + +2001-05-07 Zack Weinberg <zackw@stanford.edu> + + * demangle.h: Use PARAMS for all prototypes. + * ternary.h: Use PARAMS for all prototypes. Use PTR, not void *. + Make arguments constant where possible. + +2001-05-07 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_max): New function. + (splay_tree_min): Likewise. + +2001-04-27 Johan Rydberg <jrydberg@opencores.org> + + * dis-asm.h (print_insn_openrisc): Add prototype. + +2001-04-15 Daniel Berlin <dan@cgsoftware.com> + + * ternary.h: New file - Ternary search tree header. + +2001-04-13 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (bfd_link_discard): Add discard_sec_merge. + +2001-04-03 Zack Weinberg <zackw@stanford.edu> + + * ansidecl.h: All logic from gcc/gansidecl.h moved here. + +2001-03-31 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (alloca): Handle setting C_ALLOCA. + +2001-03-20 Jim Blandy <jimb@redhat.com> + + * demangle.h (enum gnu_v3_constructor_kinds, + is_gnu_v3_mangled_ctor, enum gnu_v3_destructor_kinds, + is_gnu_v3_mangled_dtor): New declarations. + +2001-03-14 Nick Clifton <nickc@redhat.com> + + * ansidecl.h: Fix copyright dates. + * demangle.h: Fix copyright dates. + * floatformat.h: Fix copyright dates. + * fnmatch.h: Fix copyright dates. + * getopt.h: Fix copyright dates. + * libiberty.h: Add FSF copyright notice. + * md5.h: Fix copyright dates. + * obstack.h: Fix copyright dates. + * splay-tree.h: Fix copyright dates. + +2001-03-10 Neil Booth <neil@daikokuya.demon.co.uk> + John David Anglin <dave@hiauly1.hia.nrc.ca> + + * libiberty.h: Add lbasename. + +2001-03-06 Zack Weinberg <zackw@stanford.edu> + + * libiberty.h: Prototype C_alloca; define alloca to either + __builtin_alloca or C_alloca as appropriate. + +2001-03-01 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * safe-ctype.h (_sch_test): Cast enum bit to unsigned short int for pcc + compatibility. + +2001-02-18 lars brinkhoff <lars@nocrew.org> + + * dis-asm.h: Add PDP-11 target. + +2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * dis-asm.h: Add linux target for S/390. + +2001-01-11 Peter Targett <peter.targett@arccores.com> + + * dis-asm.h (arc_get_disassembler): Correct declaration. + +2001-01-09 Philip Blundell <philb@gnu.org> + + * bin-bugs.h (REPORT_BUGS_TO): Set to `bug-binutils@gnu.org'. + +2000-12-18 Joseph S. Myers <jsm28@cam.ac.uk> + + * COPYING: Update to current + ftp://ftp.gnu.org/pub/gnu/Licenses/COPYING-2.0 (fixes references + to 19yy as example year in copyright notice). + +2000-12-19 Hans-Peter Nilsson <hp@bitrange.com> + + * dis-asm.h (struct disassemble_info): New member "section". + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize private_data member. + Initialize section member. + +2000-12-16 Herman A.J. ten Brugge <Haj.Ten.Brugge@net.HCC.nl> + + * safe-ctype.h: Make code work on all targets and not just on + targets where a char is 8 bits. + +2000-12-10 Fred Fish <fnf@be.com> + + * bfdlink.h (struct bfd_link_info): Add new allow_shlib_undefined + member to struct for systems where it is normal to have undefined + symbols in shared libraries at runtime and the runtime linker + takes care of redirecting them. + +2000-12-07 Zack Weinberg <zack@wolery.stanford.edu> + + * safe-ctype.h: New file. + +2000-12-06 Rodney Brown <RodneyBrown@mynd.com> + + * getopt.h obstack.h: Standarize copyright statement. + +2000-12-04 Richard Henderson <rth@redhat.com> + + * demangle.h: Change "new_abi" to "v3" everywhere. + +2000-11-22 Zack Weinberg <zack@wolery.stanford.edu> + + * libiberty.h: Move #includes to top. Prototype xmalloc_failed. + +2000-11-15 Kenneth Block <kenneth.block@compaq.com> + + * demangle.h: Add gnat and java demangle styles. + +2000-11-04 Hans-Peter Nilsson <hp@bitrange.com> + + * hashtab.h (struct htab): Add member return_allocation_failure. + (htab_try_create): New prototype. Mention which functions may + return NULL when this is used. + +2000-11-03 Hans-Peter Nilsson <hp@bitrange.com> + + * hashtab.h: Change void * to PTR where necessary. + +2000-10-11 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_predecessor): Declare. + +2000-09-29 Hans-Peter Nilsson <hp@axis.com> + + * dis-asm.h: Declare cris_get_disassembler, not print_insn_cris. + Fix typo in comment. + +2000-09-28 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * alloca-conf.h: New file (copied from libiberty). + +2000-09-05 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * md5.h (md5_uint32): Choose via INT_MAX instead of UINT_MAX. + +2000-09-04 Alex Samuel <samuel@codesourcery.com> + + * dyn-string.h: Adjust formatting. + (dyn_string_insert_char): New macro. New declaration. + +2000-08-28 Jason Merrill <jason@redhat.com> + + * md5.h: New file. + +2000-08-24 Greg McGary <greg@mcgary.org> + + * libiberty.h (ARRAY_SIZE): New macro. + +2000-07-29 Nick Clifton <nickc@cygnus.com> + + * os9k.h: Add copyright notice. + Fix formatting. + +2000-07-22 Jason Eckhardt <jle@cygnus.com> + + * dis-asm.h (print_insn_i860): Add prototype. + +2000-07-20 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_info): Add new_dtags. + +2000-07-20 Hans-Peter Nilsson <hp@axis.com> + + * dis-asm.h (print_insn_cris): Declare. + +2000-07-19 H.J. Lu (hjl@gnu.org) + + * bfdlink.h (bfd_link_info): Add flags and flags_1. + +2000-06-05 DJ Delorie <dj@redhat.com> + + * MAINTAINERS: new + +2000-06-21 Alex Samuel <samuel@codesourcery.com> + + * dyn-string.h (dyn_string_init, dyn_string_new, + dyn_string_delete, dyn_string_release, dyn_string_resize, + dyn_string_clear, dyn_string_copy, dyn_string_copy_cstr, + dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert, + dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr, + dyn_string_append_char, dyn_string_substring_dyn_string_eq): + Define as same name with __cxa_ prepended, if IN_LIBGCC2. + (dyn_string_init, dyn_string_copy, dyn_string_copy_cstr, + dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert, + dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr, + dyn_string_append_char, dyn_string_substring): Change return type + to int. + +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * dis-asm.h (print_insn_m68hc12): Define. + (print_insn_m68hc11): Likewise. + +2000-06-18 Nick Clifton <nickc@redhat.com> + + * os9k.h: Change values of MODSYNC and CRCCON due to bug report + from Russ Magee <rmagee@home.com>. + +2000-06-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h (demangling_styles): Remove trailing comma in enum. + + * dyn-string.h (dyn_string_append_char): Change parameter from + char to int. + +2000-06-04 Alex Samuel <samuel@codesourcery.com> + + * dyn-string.h: Move here from gcc/dyn-string.h. Add new functions. + + * demangle.h (DMGL_GNU_NEW_ABI): New macro. + (DMGL_STYLE_MASK): Or in DMGL_GNU_NEW_ABI. + (current_demangling_style): Add gnu_new_abi_demangling. + (GNU_NEW_ABI_DEMANGLING_STYLE_STRING): New macro. + (GNU_NEW_ABI_DEMANGLING): Likewise. + (cplus_demangle_new_abi): New declaration. + +Tue May 30 16:53:34 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * floatformat.h (struct floatformat): Add field name. + +2000-05-26 Eli Zaretskii <eliz@is.elta.co.il> + + * filenames.h: New file. + (HAVE_DOS_BASED_FILE_SYSTEM, IS_DIR_SEPARATOR) + (IS_ABSOLUTE_PATH, FILENAME_CMP): New macros. + +2000-05-23 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * getopt.h (getopt): Also check HAVE_DECL_* when prototyping. + + * libiberty.h (basename): Likewise. + +2000-05-17 S. Bharadwaj Yadavalli <sby@scrugs.lkg.dec.com> + Rick Gorton <gorton@scrugs.lkg.dec.com> + + * bfdlink.h (struct bfd_link_info): Add emitrelocations flag. + +2000-05-08 Alan Modra <alan@linuxcare.com.au> + + * dis-asm.h (print_insn_tic54x): Declare. + +2000-05-06 Zack Weinberg <zack@wolery.cumb.org> + + * ansidecl.h: #define __extension__ to nothing if + GCC_VERSION < 2008. + +2000-05-04 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h (demangler_engine): Constify. + +Thu May 4 17:15:26 2000 Philippe De Muyter <phdm@macqel.be> + + * sort.h (sys/types.h): File included unconditionnaly. + (stddef.h): File include only #ifdef __STDC__. + +2000-05-03 Zack Weinberg <zack@wolery.cumb.org> + + * symcat.h: Remove #endif label. + +2000-04-28 Kenneth Block <block@zk3.dec.com> + Jason Merrill <jason@casey.cygnus.com> + + * demangle.h (libiberty_demanglers): new table for different styles. + (cplus_demangle_set_style): New function for setting style. + (cplus_demangle_name_to_style): New function to translate name. + +2000-04-24 Mark Mitchell <mark@codesourcery.com> + + * hashtab.h (hash_pointer): Declare. + (eq_pointer): Likewise. + +2000-04-23 Mark Mitchell <mark@codesourcery.com> + + * sort.h: New file. + +Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> + David Mosberger <davidm@hpl.hp.com> + + * dis-asm.h (print_insn_ia64): Declare. + +Tue Apr 18 16:22:30 2000 Richard Kenner <kenner@vlsi1.ultra.nyu.edu> + + * hashtab.h (enum insert_option): New type. + (htab_find_slot, htab_find_slot_with_hash): Use it. + +2000-04-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * symcat.h: Honor autoconf macro HAVE_STRINGIZE. Add + comments/caveats with regard to traditional C behavior. + +2000-04-05 Richard Henderson <rth@cygnus.com> + + * splay-tree.h (splay_tree_remove): Declare. + +2000-04-04 Alan Modra <alan@linuxcare.com.au> + + * bin-bugs.h (REPORT_BUGS_TO): Remove translated part. + +2000-04-03 Alan Modra <alan@linuxcare.com.au> + + * bin-bugs.h: New file. + +2000-03-30 Mark Mitchell <mark@codesourcery.com> + + * hashtab.h (hashval_t): New type. + (htab_find_with_hash): Use it as an argument. + (htab_find_slot_with_hash): Likewise. + +2000-03-27 Denis Chertykov <denisc@overta.ru> + + * dis-asm.h (print_insn_avr): Declare. + +2000-03-14 Bernd Schmidt <bernds@cygnus.co.uk> + + * hashtab.h (htab_trav): Modify type so that first arg is of type + void **. + (htab_find_with_hash, htab_find_slot_with_hash): Declare new + functions. + +2000-03-09 Alex Samuel <samuel@codesourcery.com> + + * partition.h: New file. + +2000-03-09 Zack Weinberg <zack@wolery.cumb.org> + + * hashtab.h (struct htab): Add del_f. + (htab_del): New type. + (htab_create): Add fourth argument. + +2000-03-08 Zack Weinberg <zack@wolery.cumb.org> + + * hashtab.h (hash_table_t): Rename to htab_t. + (struct hash_table): Rename to struct htab. Shorten element + names. Reorder elements by size. + (htab_hash, htab_eq, htab_trav): New typedefs for the callback + function pointers. + (hash_table_entry_t): Discard; just use void * for element + type. + +2000-03-01 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_callbacks): Add a boolean arg to + the undefined_symbol callback. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * dis-asm.h (print_insn_i370): Declare. + +Tue Feb 22 15:19:54 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_trace): Document return values. + (sim_set_trace): Declare. Deprecate. + +2000-02-21 Alan Modra <alan@spri.levels.unisa.edu.au> + + * dis-asm.h (struct disassemble_info): Change `length' param of + read_memory_func to unsigned. Change type of `buffer_length' and + `octets_per_byte' to unsigned. + (buffer_read_memory): Change `length' param to unsigned. + +2000-02-16 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h: Add prototypes for ARM register name functions. + +Wed Feb 9 18:45:49 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * wait.h: Delete. No longer used by GDB. + +Tue Feb 8 17:01:13 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_resume): Clarify use of SIGGNAL. + (sim_stop_reason): Clarify meaning of sim_signalled. + +2000-02-03 Timothy Wall <twall@redhat.com> + + * dis-asm.h (struct disassemble_info): Added octets_per_byte + field and initialize it to one (1). + +2000-01-27 Nick Clifton <nickc@redhat.com> + + * dis-asm.h: Add prototype for disassembler_usage(). + Add prototype for arm_disassembler_options(). + Remove prototype for arm_toggle_regnames(). + Add prototype for parse_arm_disassembler_option(). + +Sat Jan 1 19:06:52 2000 Hans-Peter Nilsson <hp@bitrange.com> + + * symcat.h (STRINGX) [!__STDC__ || ALMOST_STDC]: Change "?" to "s" + to stringify argument s. + +Wed Dec 15 11:22:56 1999 Jeffrey A Law (law@cygnus.com) + + * hp-symtab.h (HP_LANGUAGE_FORTRAN): New enumeration constant. + (HP_LANGUAGE_F77): Define using HP_LANGUAGE_FORTRAN. + +1999-12-15 Doug Evans <dje@transmeta.com> + + * dis-asm.h: Enclose in extern "C" ifdef __cplusplus. + +1999-12-05 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (struct splay_tree_node): Rename to ... + (struct splay_tree_node_s): ... this. + (struct splay_tree): Rename to ... + (struct splay_tree_s): ... this. + +1999-11-30 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (ATTRIBUTE_MALLOC): New macro. + + * libiberty.h (buildargv, dupargv, concat, choose_temp_base, + make_temp_file, xmalloc, xcalloc, xstrdup, xmemdup): Add + ATTRIBUTE_MALLOC. + (xatexit): Remove __GNUC__ check, add ATTRIBUTE_NORETURN. + +1999-11-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h: Include stdarg.h when ANSI_PROTOTYPES is defined. + (asprintf, vasprintf): Provide declarations. + +Wed Nov 10 12:43:21 1999 Philippe De Muyter <phdm@macqel.be> + Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h: Define and test `GCC_VERSION', not `HAVE_GCC_VERSION'. + +1999-11-04 Jimmy Guo <guo@cup.hp.com> + + * hp-symtab.h (dntt_type_fparam): Add doc_ranges, misc_kind + fields, change location type to CORE_ADDR from int. + (dntt_type_const): Name the 5th field location_type. + +Sun Oct 24 19:11:32 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-d10v.h (SIM_D10V_TS2_DMAP_REGNUM): Define. + +1999-10-23 08:51 -0700 Zack Weinberg <zack@bitmover.com> + + * hashtab.h: Give hash_table_t a struct tag. Add prototypes + for clear_hash_table_slot and traverse_hash_table. Correct + prototype of all_hash_table_collisions. + +Sat Oct 23 19:00:13 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-d10v.h: New file. + +Fri Oct 15 01:47:51 1999 Vladimir Makarov <vmakarov@loony.cygnus.com> + + * hashtab.h: New file. + +1999-10-10 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (HAVE_GCC_VERSION): New macro. Use it instead of + explicitly testing __GNUC__ and __GNUC_MINOR__. + + (ATTRIBUTE_PRINTF): Use `__format__', not `format'. + +1999-09-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (make_temp_file): Add a prototype. + +Tue Sep 14 00:35:02 1999 Marc Espie <espie@cvs.openbsd.org> + + * libiberty.h (basename): OpenBSD has a correct prototype. + (xrealloc): Remove outdated comment. + +1999-09-07 Jeff Garzik <jgarzik@pobox.com> + + * libiberty.h (xmemdup): Add prototype for new function. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * dis-asm.h (print_insn_pj): Declare. + +1999-09-01 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * obstack.h (obstack_grow, obstack_grow0): Move (char*) casts + in calls to `_obstack_memcpy' from here ... + + (_obstack_memcpy): ... to here, except in the __STDC__ case which + doesn't need it. + +1999-08-30 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (getpwd): Prototype. + +1999-08-01 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_insert): Return the new node. + +1999-07-11 Ian Lance Taylor <ian@zembu.com> + + * ansidecl.h: Copy attribute support macros from egcs. + +1999-06-22 Mark Mitchell <mark@codesourcery.com> + + * bfdlink.h (struct bfd_link_hash_entry): Add init_function and + fini_function. + +1999-06-20 Mark Mitchell <mark@codesourcery.com> + + * mips.h (Elf32_Internal_Msym): New structure. + (Elf32_External_Msym): Likewise. + (ELF32_MS_REL_INDEX): New macro. + (ELF32_MS_FLAGS): Likewise. + (ELF32_MS_INFO): Likewise. + +1999-06-14 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h (arm_toggle_regnames): New prototype. + (struct diassemble_info): New field: disassembler_options. + +1999-04-11 Richard Henderson <rth@cygnus.com> + + * bfdlink.h (bfd_elf_version_expr): Rename `match' to `pattern'. + Add `match' callback function. + +1999-04-10 Richard Henderson <rth@cygnus.com> + + * bfdlink.h (bfd_link_info): Add no_undefined. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h: Add prototype for print_insn_mcore. + +1999-04-02 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_compare_pointers): Declare. + +1999-03-30 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_compare_ints): Declare. + +Wed Mar 24 12:46:29 1999 Andrew Cagney <cagney@amy.cygnus.com> + + * libiberty.h (basename): Cygwin{,32} should have the prototype. + +1999-02-22 Jim Lemke <jlemke@cygnus.com> + + * bfdlink.h (bfd_link_info): add field "mpc860c0". + +Mon Feb 1 21:05:46 1999 Catherine Moore <clm@cygnus.com> + + * dis-asm.h (print_insn_i386_att): Declare. + (print_insn_i386_intel): Declare. + +1998-12-30 Michael Meissner <meissner@cygnus.com> + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Cast STREAM and + FPRINTF_FUNC to avoid compiler warnings. + +Wed Dec 30 16:07:14 1998 David Taylor <taylor@texas.cygnus.com> + + * dis-asm.h: change void * to PTR (two places). + +Mon Dec 14 09:53:31 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h: Don't check IN_GCC anymore. + * splay-tree.h: Likewise. + +Tue Dec 8 00:30:31 1998 Elena Zannoni <ezannoni@kwikemart.cygnus.com> + + The following changes were made by Elena Zannoni + <ezannoni@kwikemart.cygnus.com> and Edith Epstein + <eepstein@sophia.cygnus.com> as part of a project to merge in + changes made by HP; HP did not create ChangeLog entries. + + * dis-asm.h (struct disassemble_info): change the type of stream + from FILE* to void*, for use with gdb's new type GDB_FILE. + (fprintf_ftype): change FILE* parameter type to void*. + + * demangle.h: (DMGL_EDG): new macro for Kuck and Associates + (DMGL_STYLE_MASK): modify to include Kuck and Assoc style + (demangling_styles): add new edg_demangling style + (EDG_DEMANGLING_STYLE_STRING): new macro + (EDG_DEMANGLING): new macro + (DMGL_HP): new macro, for HP/aCC compiler. + (DMGL_STYLE_MASK): modify to include new HP's style. + (demangling_styles): add new hp_demangling value. + (HP_DEMANGLING_STYLE_STRING): new macro. + (ARM_DEMANGLING): coerce to int. + (HP_DEMANGLING): new macro. + + * hp-symtab.h: rewritten, from HP. + (quick_procedure): change type of language field to unsigned int + (quick_module): change type of language field to unsigned int + (struct dntt_type_svar): add field thread_specific. + (hp_language): add languages modcal and dmpascal. + +Fri Nov 20 13:14:00 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * libiberty.h (basename): Add prototype for FreeBSD. + +Fri Nov 13 19:19:11 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h: Prototype xcalloc. + +Sun Nov 8 17:42:25 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h: Wrap problematic macros with !IN_GCC. + + * demangle.h: Never define PARAMS(). + * splay-tree.h: Likewise. + +Sat Nov 7 18:30:20 1998 Peter Schauer <peter.schauer@regent.e-technik.tu-muenchen.de> + + * dis-asm.h (print_insn_vax): Declare. + +Sat Nov 7 16:04:03 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h: Don't include gansidecl.h. + * splay-tree.h: Likewise. + +1998-10-26 16:03 Ulrich Drepper <drepper@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add new field optimize. + +Thu Oct 22 19:58:00 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * splay-tree.h: Wrap function pointer parameter declarations in + PARAMS() macro. + +1998-10-21 Mark Mitchell <mark@markmitchell.com> + + * splay-tree.h: New file. + +Fri Oct 9 00:02:03 1998 Jeffrey A Law (law@cygnus.com) + + * Merge devo and egcs include directories. + +Sat Sep 5 12:16:33 1998 Jeffrey A Law (law@cygnus.com) + + * getopt.h, obstack.h: Updated from gcc. + +1998-08-03 Jason Molenda (jsm@bugshack.cygnus.com) + + * libiberty.h (xexit): Change decl to use modern GCC attribute + to indicate exit does not return. + +Mon Jun 1 13:48:32 1998 Jason Molenda (crash@bugshack.cygnus.com) + + * obstack.h: Update to latest FSF version. + +Tue Feb 24 13:05:02 1998 Doug Evans <devans@canuck.cygnus.com> + + * dis-asm.h (disassemble_info): Member `symbol' renamed to `symbols' + and made an "asymbol **". New member num_symbols. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Update. + +Tue Feb 17 12:32:18 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_fetch_register, sim_store_register): Add + register length parameter. Functions return actual length of + register. + +Thu Feb 12 16:29:01 1998 Ian Lance Taylor <ian@cygnus.com> + + * getopt.h: Update to latest FSF version. + +Wed Feb 11 16:56:06 1998 Doug Evans <devans@canuck.cygnus.com> + + * symcat.h: New file. + +Mon Feb 2 17:13:31 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> + + * dis-asm.h (print_insn_tic30): Declare. + +Thu Jan 22 16:23:59 1998 Fred Fish <fnf@cygnus.com> + + * dis-asm.h: Add flag INSN_HAS_RELOC to tell disassembly + function there is a reloc on this line. + +Mon Dec 8 11:22:23 1997 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h: Remove prototype of disasm_symaddr() as this function + no longer exists. + +Tue Dec 2 10:20:53 1997 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h (disasm_symaddr): New prototype. + +Mon Dec 1 11:29:35 1997 Doug Evans <devans@canuck.cygnus.com> + + * callback.h (CB_SYSCALL): Comment out arg names in prototypes. + +Wed Nov 26 16:47:58 1997 Michael Meissner <meissner@cygnus.com> + + * callback.h (CB_SYSCALL): Consistantly use names for prototype + arguments. + +Wed Nov 26 11:39:30 1997 Doug Evans <devans@canuck.cygnus.com> + + * callback.h (CB_SYSCALL): Change byte count arguments to + {read,write}_mem to `int'. New member `magic'. + (CB_SYSCALL_MAGIC,CB_SYSCALL_INIT): New macros. + +Tue Nov 25 01:35:52 1997 Doug Evans <devans@seba.cygnus.com> + + * callback.h (struct stat): Move forward decl up. + (host_callback): Pass stat struct pointer to stat,fstat. + (CB_SYS_nnn): Reorganize. + (CB_SYSCALL): New members p1,p2. + (cb_host_to_target_stat): Delete fourth arg. + +Sat Nov 22 23:34:15 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_stop_reason): Clarify sim_signalled SIGRC + argument. + +Mon Nov 17 14:00:51 1997 Doug Evans <devans@seba.cygnus.com> + + * callback.h (CB_TARGET_DEFS_MAP): Renamed from target_defs_map. + (host_callback): Add stat, fstat, syscall_map, errno_map, open_map, + signal_map, stat_map. + (errn_map,open_map): Renamed to cb_init_foo_map. + (cb_host_to_target_errno,cb_target_to_host_open): Renamed from + host_to_target_errno,target_to_host_open. + (cb_read_target_syscall_maps): Add prototype. + (cb_target_to_host_syscall): Likewise. + (cb_host_to_target_stat): Likewise. + (cb_syscall): Likewise. + (CB_SYS_{exit,open,close,read,write,lseek,unlink,getpid,kill,fstat, + argvlen,argv,chdir,stat,chmod,utime,time}): Define. + (CB_SYSCALL): New type. + (CB_RC): New enum. + +Fri Nov 7 10:34:09 1997 Rob Savoye <rob@darkstar.cygnus.com> + + * libiberty.h: Add extern "C" { so it can be used with C++ + programs. + * remote-sim.h: Add extern "C" { so it can be used with C++ + programs. + +Tue Oct 14 16:07:51 1997 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h (struct disassemble_info): New field + 'symbol_at_address_func'. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise new field with + generic_symbol_at_address. + +Mon Oct 13 10:17:15 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h: Clarify sim_read, sim_write MEM argument. + +Wed Sep 24 18:03:10 1997 Stu Grossman <grossman@babylon-5.cygnus.com> + + * remote-sim.h (SIM_RC): Add a bunch of new return codes for + breakpoint stuff. + * Add functions to tell the simulator to set/clear/enable/disable + intrinsic breakpoints. + +Thu Aug 28 19:41:42 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * libiberty.h (dupargv): Add prototype. + +Tue Aug 26 12:25:49 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_create_inferior): Add ABFD arg. Document. + +Mon Aug 25 10:50:51 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_open): Add ABFD arg. Document. + +Fri Aug 8 16:43:56 1997 Doug Evans <dje@canuck.cygnus.com> + + * dis-asm.h (arc_get_disassembler): Declare. + +Wed Jul 30 11:39:50 1997 Per Bothner <bothner@deneb.cygnus.com> + + * demangle.h (DMGL_JAVA): New option to request Java demangling. + +Tue Jul 22 17:59:54 1997 Ian Lance Taylor <ian@cygnus.com> + + * libiberty.h (PEXECUTE_*): Define. + (pexecute, pwait): Declare. + +Fri Jun 6 13:02:33 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_kill): Mark as depreciated. + +Fri May 23 13:43:41 1997 Fred Fish <fnf@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add task_link member. + +Thu May 22 11:32:49 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h: Review documentation. Clarify restrictions on + when functions can be called. + +Wed May 21 16:47:53 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_set_profile_size): Add prototype, document as + depreciated. + +Tue May 20 09:32:22 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_open): Add callback struct. + (sim_set_callbacks): Drop SIM_DESC argument. Document. + (sim_size): Remove recently added SIM_DESC argument. Document. + +Mon May 19 19:14:44 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h: Pass SD into sim_size. + +Thu May 15 01:24:16 1997 Mark Alexander <marka@cygnus.com> + + * obstack.h (obstack_specify_allocation_with_arg, obstack_chunkfun, + obstack_freefun): Eliminate compile warnings in gdb. + +Tue Apr 22 10:24:34 1997 Fred Fish <fnf@cygnus.com> + + * floatformat.h (floatformat_byteorders): Add comments for previous + formats and add floatformat_littlebyte_bigword, primarily for ARM. + Add declaration for floatformat_ieee_double_littlebyte_bigword. + +Fri Apr 18 13:04:49 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_stop): New interface - asynchronous + notification of a request to stop / suspend the running + simulation. + + * remote-sim.h (enum sim_stop): Add sim_running and sim_polling as + states for use internal to simulators. + + * callback.h (struct host_callback_strut): Put a magic number at + the end of the struct to allow basic checking. + (struct host_callback_struct ): Add poll_quit - so + that the console etc can be polled at regular intervals. + +Thu Apr 17 02:17:12 1997 Doug Evans <dje@canuck.cygnus.com> + + * remote-sim.h (struct _bfd): Declare. + (sim_load): Return SIM_RC. New arg `abfd'. + (sim_create_inferior): Return SIM_RC. Delete arg `start_address'. + +Wed Apr 2 17:09:12 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * remote-sim.h (sim_trace, sim_size): Make these global. They + will go away shortly. + +Wed Apr 2 15:23:49 1997 Doug Evans <dje@canuck.cygnus.com> + + * remote-sim.h (SIM_OPEN_KIND, SIM_RC): New enums. + (sim_open): New argument `kind'. + +Wed Apr 2 14:45:51 1997 Ian Lance Taylor <ian@cygnus.com> + + * COPYING: Update FSF address. + +Fri Mar 28 15:29:54 1997 Mike Meissner <meissner@cygnus.com> + + * callback.h (top level): Include stdarg.h or varargs.h if + va_start is not defined. + (host_callback_struct): Make {,e}vprintf_filtered take a va_list + instead of void *, since va_list might be an array or structure + type. + +Fri Mar 28 15:44:41 1997 H.J. Lu <hjl@gnu.ai.mit.edu> + + * libiberty.h (basename): Add prototype for glibc and linux. + +Mon Mar 17 19:22:12 1997 Ian Lance Taylor <ian@cygnus.com> + + * objalloc.h: New file. + +Mon Mar 17 14:57:55 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * remote-sim.h: New file, copied in from gdb/remote-sim.h. One + day this will be placed in a directory of its own. + +Sat Mar 15 19:00:14 1997 Ian Lance Taylor <ian@cygnus.com> + + * obstack.h: Update to current FSF version. + +Thu Mar 6 15:46:59 1997 Andrew Cagney <cagney@kremvax.cygnus.com> + + * callback.h (struct host_callback_struct): Add callbacks - + flush_stdout, write_stderr, flush_stderr, vprintf_filtered, + evprintf_filtered. Delete redundant callbacks - printf_filtered. + +Thu Feb 27 23:18:27 1997 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Remove lprefix and lprefix_len + fields. + +Tue Feb 25 00:10:49 1997 Ian Lance Taylor <ian@cygnus.com> + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize + bytes_per_chunk and display_endian. + +Mon Feb 24 17:47:02 1997 Ian Lance Taylor <ian@cygnus.com> + + From Eric Youngdale <eric@andante.jic.com>: + * bfdlink.h (struct bfd_elf_version_expr): Define. + (struct bfd_elf_version_deps): Define. + (struct bfd_elf_version_tree): Define. + +Thu Feb 6 14:20:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * dis-asm.h: (disassemble_info): Add new fields + bytes_per_chunk and display_endian to control the + display of raw instructions. + +Fri Dec 27 22:17:37 1996 Fred Fish <fnf@cygnus.com> + + * dis-asm.h (print_insn_tic80): Declare. + +Sun Dec 8 17:11:12 1996 Doug Evans <dje@canuck.cygnus.com> + + * callback.h (host_callback): New member `error'. + +Wed Nov 20 00:40:23 1996 Doug Evans <dje@canuck.cygnus.com> + + * callback.h: New file, moved here from gdb. + +Mon Nov 18 16:34:00 1996 Dawn Perchik <dawn@critters.cygnus.com> + + * libiberty.h: Checkin again; last checkin failed due to sticky tag. + +Wed Nov 13 08:22:00 1996 Dawn Perchik <dawn@critters.cygnus.com> + + * libiberty.h: Revert last commit due to conflicts with hpux + system headers. + +Tue Nov 12 16:31:00 1996 Dawn Perchik <dawn@critters.cygnus.com> + + * libiberty.h: Move prototypes from argv.c here. + +Thu Oct 31 14:56:18 1996 Doug Evans <dje@canuck.cygnus.com> + + * ansidecl.h (VPARAMS,VA_START): Define. + +Fri Oct 25 12:08:04 1996 Ian Lance Taylor <ian@cygnus.com> + + * dis-asm.h (disassemble_info): Add bytes_per_line field. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize bytes_per_line field. + +Thu Oct 24 17:10:01 1996 Ian Lance Taylor <ian@cygnus.com> + + * dis-asm.h (disassemble_info): Add symbol field. + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize symbol field. + +Thu Oct 17 11:17:40 1996 Doug Evans <dje@canuck.cygnus.com> + + * dis-asm.h (print_insn_m32r): Declare. + +Mon Oct 14 23:56:52 1996 Ian Lance Taylor <ian@cygnus.com> + + * libiberty.h: Declare parameter types for xmalloc and xrealloc. + +Thu Oct 3 13:45:27 1996 Ian Lance Taylor <ian@cygnus.com> + + * fnmatch.h: New file. + +Thu Oct 3 10:33:14 1996 Jeffrey A Law (law@cygnus.com) + + * dis-asm.h (print_insn_mn10x00): Delete declaration. + (print_insn_mn10200, print_insn_mn10300): Declare. + +Wed Oct 2 21:24:43 1996 Jeffrey A Law (law@cygnus.com) + + * dis-asm.h (print_insn_mn10x00): Declare. + +Mon Sep 30 13:56:11 1996 Fred Fish <fnf@cygnus.com> + + * libiberty.h: Remove #ifndef PRIVATE_XMALLOC. + +Sat Aug 31 13:27:06 1996 Jeffrey A Law (law@cygnus.com) + + * dis-asm.h (print_insn_v850): Declare. + +Tue Aug 13 16:10:30 1996 Stu Grossman (grossman@critters.cygnus.com) + + * obstack.h: Change bcopy to memcpy. Works better on Posix + systems, which generally lack bcopy. + +Mon Aug 12 17:03:18 1996 Stu Grossman (grossman@critters.cygnus.com) + + * ansidecl.h: Change WIN32 to _WIN32. + +Fri Jul 26 13:58:18 1996 Ian Lance Taylor <ian@cygnus.com> + + * dis-asm.h: Add flavour field. + (print_insn_alpha): Declare. + (print_insn_alpha_osf, print_insn_alpha_vms): Don't declare. + (INIT_DISASSEMBLE_INFO): Initialize flavour field. + +Tue Jul 23 17:37:58 1996 Fred Fish <fnf@cygnus.com> + + * libiberty.h (PRIVATE_XMALLOC): Enclose xmalloc/xrealloc + definitions inside #ifndef so that programs that want to + can define PRIVATE_XMALLOC and then define xmalloc and + xrealloc anyway they want. + (basename): Document in source that we can't declare the + parameter type because it is declared inconsistently across + different systems. + +Mon Jul 22 13:16:13 1996 Richard Henderson <rth@tamu.edu> + + * dis-asm.h (print_insn_alpha): Don't declare. + (print_insn_alpha_osf, print_insn_alpha_vms): Declare. + +Wed Jul 17 14:45:12 1996 Martin M. Hunt <hunt@pizza.cygnus.com> + + * dis-asm.h: (print_insn_d10v): Declare. + +Mon Jul 15 16:55:38 1996 Stu Grossman (grossman@critters.cygnus.com) + + * dis-asm.h: Get rid of decls for print_insn_i8086, + print_insn_sparc64 and print_insn_sparclite. + * (INIT_DISASSEMBLE_INFO): Split into two pieces. One, + INIT_DISASSEMBLE_INFO_NO_ARCH inits everything except for endian, + mach, and arch. + +Fri Jul 12 10:19:27 1996 Stu Grossman (grossman@critters.cygnus.com) + + * dis-asm.h (print_insn_i8086): Declare. + +Wed Jul 3 16:02:39 1996 Stu Grossman (grossman@critters.cygnus.com) + + * dis-asm.h (print_insn_sparclite): Declare. + +Tue Jun 18 16:02:46 1996 Jeffrey A. Law <law@rtl.cygnus.com> + + * dis-asm.h (print_insn_h8300s): Declare. + +Tue Jun 18 15:11:33 1996 Klaus Kaempf <kkaempf@progis.de> + + * fopen-vms.h: New file. + +Tue Jun 4 18:58:16 1996 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add notice_all field. + +Fri Apr 26 10:33:12 1996 Doug Evans <dje@canuck.cygnus.com> + + * demangle.h (#ifdef IN_GCC): #include "gansidecl.h". + (PROTO,PTR,const): Delete. + +Mon Apr 22 17:27:42 1996 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add traditional_format field. + +Mon Apr 15 15:16:56 1996 Doug Evans <dje@canuck.cygnus.com> + + * libiberty.h (choose_temp_base): Add prototype. + +Tue Mar 12 17:29:46 1996 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (bfd_wrapped_link_hash_lookup): Declare. + (struct bfd_link_info): Add wrap_hash field. + +Wed Feb 14 16:49:17 1996 Martin Anantharaman <martin@mail.imech.uni-duisburg.de> + + * ieee.h (ieee_record_enum_type): Define + ieee_external_reference_info_enum. + +Fri Feb 2 17:09:25 1996 Doug Evans <dje@charmed.cygnus.com> + + * dis-asm.h (DISASM_RAW_INSN): Delete. + +Tue Jan 23 09:21:47 1996 Doug Evans <dje@charmed.cygnus.com> + + * dis-asm.h (INIT_DISASSEMBLE_INFO): Set endian to BFD_ENDIAN_UNKNOWN. + New argument FPRINTF_FUNC. + +Mon Jan 22 16:37:59 1996 Doug Evans <dje@charmed.cygnus.com> + + * dis-asm.h (disassemble_info): New members arch, mach, endian. + (INIT_DISASSEMBLE_INFO): Initialize them. + (DISASM_RAW_INSN{,FLAG}): Define. + +Thu Jan 18 11:32:38 1996 Ian Lance Taylor <ian@cygnus.com> + + * demangle.h (cplus_demangle_opname): Change opname parameter to + const char *. + (cplus_mangle_opname): Change return type and opname parameter to + const char *. + +Fri Jan 5 00:01:22 1996 Ian Lance Taylor <ian@cygnus.com> + + * ieee.h (enum ieee_record): Add ieee_asn_record_enum, + ieee_at_record_enum, ieee_ty_record_enum, ieee_atn_record_enum, + ieee_bb_record_enum, and ieee_be_record_enum. + +Wed Jan 3 13:12:09 1996 Fred Fish <fnf@cygnus.com> + + * obstack.h: Update copyright to 1996. + (_obstack_memory_used): Declare. + (obstack_memory_used): Define macro. + +Thu Dec 28 11:42:12 1995 Ian Lance Taylor <ian@cygnus.com> + + * libiberty.h (xstrdup): Declare. + +Thu Dec 21 14:47:17 1995 Michael Meissner <meissner@tiktok.cygnus.com> + + * wait.h: Protect all macros with #ifndef. + +Tue Oct 24 21:45:40 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add static_link field. + +Tue Sep 12 16:28:04 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_callbacks): Add symbol parameter to + warning callback. + +Fri Sep 1 13:11:51 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_callbacks): Change warning callback + to take BFD, section, and address arguments. + +Thu Aug 31 16:45:12 1995 steve chamberlain <sac@slash.cygnus.com> + + * bfdlink.h (struct bfd_link_info): Remove PE stuff. + +Tue Aug 22 03:18:23 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com> + + * libiberty.h: Declare xstrerror. From Pat Rankin. + +Mon Aug 21 18:11:36 1995 steve chamberlain <sac@slash.cygnus.com> + + * bfdlink.h (struct bfd_link_info): Remove PE stuff. + +Wed Aug 2 08:14:12 1995 Doug Evans <dje@canuck.cygnus.com> + + * dis-asm.h (print_insn_sparc64): Declare. + +Mon Jul 10 13:26:49 1995 Eric Youngdale <eric@aib.com> + + * bfdlink.h (struct bfd_link_info): Add new field symbolic. + +Sun Jul 2 17:48:40 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Change type of base_file to + PTR. + +Thu Jun 29 00:02:45 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * bfdlink.h (struct bfd_link_info): Added base_file member. + +Tue Jun 20 16:40:04 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * ansidecl.h: win32s is ANSI enough. + +Thu May 18 04:25:50 1995 Ken Raeburn <raeburn@kr-laptop.cygnus.com> + + Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk) + + * dis-asm.h (print_insn_arm): Delete declaration. + (print_insn_{little,big}_arm): New declarations. + + * floatformat.h (floatformat_arm_ext): Declare. + +Sat May 13 10:14:08 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * bfdlink.h (subsytem, stack_heap_parameters): New. + +Thu May 4 14:36:42 1995 Jason Merrill <jason@phydeaux.cygnus.com> + + * demangle.h: Don't include ansidecl.h if IN_GCC. + +Tue Feb 21 00:37:28 1995 Jeff Law (law@snake.cs.utah.edu) + + * hp-symtab.h: Don't use bitfield enumerations, the HP C compiler + does not handle them correctly. + +Thu Feb 9 14:20:27 1995 Ian Lance Taylor <ian@cygnus.com> + + * libiberty.h (basename): Don't declare parameter type; some + systems have this in their header files. + +Wed Feb 8 17:35:38 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (struct bfd_link_hash_entry): Change format of common + symbol information, to remove restrictions on maximum size and + alignment power, by using a pointer to a structure instead. + +Mon Feb 6 14:55:32 1995 Ian Lance Taylor <ian@cygnus.com> + + * bfdlink.h (enum bfd_link_hash_type): Rename bfd_link_hash_weak + to bfd_link_hash_undefweak. Add bfd_link_hash_defweak. + +Mon Jan 16 21:00:23 1995 Stan Shebs <shebs@andros.cygnus.com> + + * dis-asm.h (GDB_INIT_DISASSEMBLE_INFO, etc): Remove all + GDB-specific definitions. + +Sun Jan 15 18:39:35 1995 Steve Chamberlain <sac@splat> + + * dis-asm.h (print_insn_w65): Declare. + +Thu Jan 12 17:51:17 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * libiberty.h (hex_p): Fix sense of test. + +Wed Jan 11 22:36:40 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * libiberty.h (_hex_array_size, _hex_bad, _hex_value, hex_init, + hex_p, hex_value): New macros and declarations, for hex.c. + +Fri Jan 6 17:44:14 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * dis-asm.h: Make idempotent. + +Wed Dec 14 13:08:43 1994 Stan Shebs <shebs@andros.cygnus.com> + + * progress.h: New file, empty definitions for progress macros. + +Fri Nov 25 00:14:05 1994 Jeff Law (law@snake.cs.utah.edu) + + * hp-symtab.h: New file describing the debug symbols emitted + by the HP C compilers. + +Fri Nov 11 15:48:37 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * bfdlink.h (struct bfd_link_hash_entry): Change u.c.size from 24 + to 26 bits, and change u.c.alignment_power from 8 to 6 bits. 6 + bit in the alignment power is enough for a 64 bit address space. + +Mon Oct 31 13:02:51 1994 Stan Shebs (shebs@andros.cygnus.com) + + * demangle.h (cplus_mangle_opname): Declare. + +Tue Oct 25 11:38:02 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> + + * bfdlink.h (struct bfd_link_callbacks): Fix comments for + multiple_common field. + +Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org) + + * dis-asm.h: Add support for the ARM. + +Wed Aug 10 12:51:41 1994 Doug Evans (dje@canuck.cygnus.com) + + * libiberty.h (strsignal): Document its existence even if we + can't declare it. + +Tue Aug 2 14:40:03 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * os9k.h: Remove u_int16, u_int32, and owner_id typedefs and + expand their uses. Those names conflict with Mach headers. + +Fri Jul 22 14:17:12 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * bfdlink.h (struct bfd_link_hash_entry): Change u.c.size into a + bitfield. Add field u.c.alignment_power. + +Sun Jul 10 00:26:39 1994 Ian Dall (dall@hfrd.dsto.gov.au) + + * dis-asm.h: Add print_insn_ns32k declaration. + +Mon Jun 20 17:13:29 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * bfdlink.h (bfd_link_hash_table): Make creator a const pointer. + +Sat Jun 18 16:09:32 1994 Stan Shebs (shebs@andros.cygnus.com) + + * demangle.h (cplus_demangle_opname): Declare. + +Thu Jun 16 15:19:03 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_info): Add new field shared. + +Mon Jun 6 14:39:44 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_hash_entry): Remove written field: + not needed for all backends. + +Thu Apr 28 19:06:50 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * dis-asm.h (disassembler): Declare. + +Fri Apr 1 00:38:17 1994 Jim Wilson (wilson@mole.gnu.ai.mit.edu) + + * obstack.h: Delete use of IN_GCC to control whether + stddef.h or gstddef.h is included. + +Tue Mar 22 13:06:02 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (enum bfd_link_order_type): Add bfd_data_link_order. + (struct bfd_link_order): Add data field to union. + +Mon Mar 21 18:45:26 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_callbacks): Change bitsize argument + to add_to_set to reloc. Remove bitsize argument from constructor. + Comment that reloc_overflow, reloc_dangerous and unattached_reloc + must handle NULL pointers for reloc location. + (enum bfd_link_order_type): Add bfd_section_reloc_link_order and + bfd_symbol_reloc_link_order. + (struct bfd_link_order): Add reloc field to union. + (struct bfd_link_order_reloc): Define. + +Mon Mar 14 12:27:50 1994 Ian Lance Taylor (ian@cygnus.com) + + * ieee-float.h: Removed; no longer used. + +Tue Mar 1 18:10:49 1994 Kung Hsu (kung@mexican.cygnus.com) + + * os9k.h: os9000 target specific header file, the header of the + object file is used now. + +Sun Feb 27 21:52:26 1994 Jim Kingdon (kingdon@deneb.cygnus.com) + + * floatformat.h: New file, intended to replace ieee-float.h. + +Sun Feb 20 17:15:42 1994 Ian Lance Taylor (ian@lisa.cygnus.com) + + * ansidecl.h (ANSI_PROTOTYPES): Define if using ANSI prototypes. + +Wed Feb 16 01:07:12 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * libiberty.h: Don't declare strsignal, to avoid conflicts with + Solaris system header files. + +Sat Feb 12 22:11:32 1994 Jeffrey A. Law (law@snake.cs.utah.edu) + + * libiberty.h (xexit): Use __volatile__ to avoid losing if + compiling with gcc -traditional. + +Thu Feb 10 14:05:41 1994 Ian Lance Taylor (ian@cygnus.com) + + * libiberty.h: New file. Declares functions provided by + libiberty. + +Tue Feb 8 05:19:52 1994 David J. Mackenzie (djm@thepub.cygnus.com) + + Handle obstack_chunk_alloc returning NULL. This allows + obstacks to be used by libraries, without forcing them + to call exit or longjmp. + * obstack.h (struct obstack): Add alloc_failed flag. + _obstack_begin, _obstack_begin_1): Declare to return int, not void. + (obstack_finish): If alloc_failed, return NULL. + (obstack_base, obstack_next_free, objstack_object_size): + If alloc_failed, return 0. + (obstack_grow, obstack_grow0, obstack_1grow, obstack_ptr_grow, + obstack_int_grow, obstack_blank): If alloc_failed, do nothing that + could corrupt the obstack. + +Mon Jan 24 15:06:05 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_callbacks): Add name, reloc_name and + addend argments to reloc_overflow callback. + +Fri Jan 21 19:13:12 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * dis-asm.h (print_insn_big_powerpc, print_insn_little_powerpc, + print_insn_rs6000): Declare. + +Thu Jan 6 14:15:55 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfdlink.h (struct bfd_link_callbacks): Add bitsize argument to + add_to_set field. Add new callback named constructor. + +Thu Dec 30 10:44:06 1993 Ian Lance Taylor (ian@rtl.cygnus.com) + + * bfdlink.h: New file for new BFD linker backend routines. + +Mon Nov 29 10:43:57 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * dis-asm.h (enum dis_insn_tyupe): Remove non-ANSI trailing comma. + +Sat Oct 2 20:42:26 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-asm.h: Move comment to right place. + +Mon Aug 9 19:03:35 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * obstack.h (obstack_chunkfun, obstack_freefun): Add defns from + previous version. Are these Cygnus local changes? + +Fri Aug 6 17:05:47 1993 David J. Mackenzie (djm@thepub.cygnus.com) + + * getopt.h, obstack.h: Update to latest FSF version. + +Mon Aug 2 14:45:29 1993 John Gilmore (gnu@cygnus.com) + + * dis-asm.h: Move enum outside of struct defn to avoid warnings. + +Mon Aug 2 08:49:30 1993 Stu Grossman (grossman at cygnus.com) + + * wait.h (WEXITSTATUS, WSTOPSIG): Mask down to 8 bits. This is + for systems that store stuff into the high 16 bits of a wait + status. + +Fri Jul 30 18:38:02 1993 John Gilmore (gnu@cygnus.com) + + * dis-asm.h: Add new fields insn_info_valid, branch_delay_insns, + data_size, insn_type, target, target2. These are used to return + information from the instruction decoders back to the calling + program. Add comments, make more readable. + +Mon Jul 19 22:14:14 1993 Fred Fish (fnf@deneb.cygnus.com) + + * nlm: New directory containing NLM/NetWare includes. + +Thu Jul 15 12:10:04 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * dis-asm.h (struct disassemble_info): New field application_data. + +Thu Jul 15 12:41:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * dis-asm.h: Added declaration of print_insn_m88k. + +Fri Jul 2 10:31:59 1993 Ian Lance Taylor (ian@cygnus.com) + + * ansidecl.h: Use ANSI macros if __mips and _SYSTYPE_SVR4 are + defined, since RISC/OS cc handles ANSI declarations in SVR4 mode + but does not define __STDC__. + +Sun Jun 20 18:27:52 1993 Ken Raeburn (raeburn@poseidon.cygnus.com) + + * dis-asm.h: Don't need to include ansidecl.h any more. + +Fri Jun 18 03:22:10 1993 John Gilmore (gnu@cygnus.com) + + * oasys.h: Eliminate "int8_type", "int16_type", "int32_type", and + their variants. These changes are coordinated with corresponding + changes in ../bfd/oasys.c. + +Wed Jun 16 10:43:08 1993 Fred Fish (fnf@cygnus.com) + + * bfd.h: Note that it has been removed. + +Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + Support for H8/300-H + * dis-asm.h (print_insn_h8300, print_insn_h8300h): Declare it. + +Tue Jun 1 07:35:03 1993 Ken Raeburn (raeburn@kr-pc.cygnus.com) + + * ansidecl.h (const): Don't define it if it's already defined. + +Thu May 27 18:19:51 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) + + * dis-asm.h (print_insn_hppa): Declare it. + + * bfd.h: Moved to bfd directory. Small stub here includes it + without requiring "-I../bfd". + +Thu Apr 29 12:06:13 1993 Ken Raeburn (raeburn@deneb.cygnus.com) + + * bfd.h: Updated with BSF_FUNCTION. + +Mon Apr 26 18:15:50 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h, dis-asm.h: Updated with Hitachi SH. + +Fri Apr 23 18:41:38 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: Updated with alpha changes. + * dis-asm.h: Added alpha. + +Fri Apr 16 17:35:30 1993 Jim Kingdon (kingdon@cygnus.com) + + * bfd.h: Update for signed bfd_*get_*. + +Thu Apr 15 09:24:21 1993 Jim Kingdon (kingdon@cygnus.com) + + * bfd.h: Updated for file_truncated error. + +Thu Apr 8 10:53:47 1993 Ian Lance Taylor (ian@cygnus.com) + + * ansidecl.h: If no ANSI, define const to be empty. + +Thu Apr 1 09:00:10 1993 Jim Kingdon (kingdon@cygnus.com) + + * dis-asm.h: Declare a29k and i960 print_insn_*. + + * dis-asm.h: Add print_address_func and related stuff. + + * dis-asm.h (dis_asm_read_memory): Fix prototype. + +Wed Mar 31 17:40:16 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-asm.h: Add print_insn_sparc. + +Wed Mar 31 17:51:42 1993 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Updated for BFD_RELOC_MIPS_GPREL and bfd_[gs]et_gp_size + prototypes. + +Wed Mar 31 16:35:12 1993 Stu Grossman (grossman@cygnus.com) + + * dis-asm.h: (disassemble_info): Fix typo in prototype of + dis_asm_memory_error(). + +Tue Mar 30 19:09:23 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * dis-asm.h (disassembler_info): Add read_memory_func, + memory_error_func, buffer, and length. + ({GDB_,}INIT_DISASSEMBLE_INFO): Set them. + print_insn_*: Remove second argument. + +Tue Mar 30 14:48:55 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: Update for lma field of section. + +Tue Mar 30 12:22:55 1993 Jim Kingdon (kingdon@cygnus.com) + + * ansidecl.h: Use ANSI versions on AIX regardless of __STDC__. + +Fri Mar 19 14:49:49 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * dis-asm.h: Add h8500. + +Thu Mar 18 13:49:09 1993 Per Bothner (bothner@rtl.cygnus.com) + + * ieee-float.h: Moved from ../gdb. + * dis-asm.h: New file. Interface to dis-assembler. + +Thu Mar 11 10:52:57 1993 Fred Fish (fnf@cygnus.com) + + * demangle.h (DMGL_NO_OPTS): Add define (set to 0) to use + in place of bare 0, for readability reasons. + +Tue Mar 2 17:50:11 1993 Fred Fish (fnf@cygnus.com) + + * demangle.h: Replace all references to cfront with ARM. + +Tue Feb 23 12:21:14 1993 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Update for new elements in JUMP_TABLE. + +Tue Feb 16 00:51:30 1993 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update for BFD_VERSION 2.1. + +Tue Jan 26 11:49:20 1993 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Update for SEC_IS_COMMON flag. + +Tue Jan 19 12:25:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfd.h: Update for bfd_asymbol_value bug fix. + +Fri Jan 8 16:37:18 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * bfd.h: Update to include ECOFF tdata and target_flavour. + +Sun Dec 27 17:52:30 1992 Fred Fish (fnf@cygnus.com) + + * bfd.h: Add declaration for bfd_get_size(). + +Tue Dec 22 22:42:46 1992 Fred Fish (fnf@cygnus.com) + + * demangle.h: Protect file from multiple inclusions with + #if !defined(DEMANGLE_H)...#define DEMANGLE_H...#endif. + +Mon Dec 21 21:25:50 1992 Stu Grossman (grossman at cygnus.com) + + * bfd.h: Update to get hppa_core_struct from bfd.c. + +Thu Dec 17 00:42:35 1992 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update to get tekhex tdata name change from bfd. + +Mon Nov 9 23:55:42 1992 John Gilmore (gnu@cygnus.com) + + * ansidecl.h: Update comments to discourage use of EXFUN. + +Thu Nov 5 16:35:44 1992 Ian Lance Taylor (ian@cygnus.com) + + * bfd.h: Update to bring in SEC_SHARED_LIBRARY. + +Thu Nov 5 03:21:32 1992 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update to match EXFUN, bfd_seclet_struct, and SDEF + cleanups in bfd. + +Wed Nov 4 07:28:05 1992 Ken Raeburn (raeburn@cygnus.com) + + * bout.h (N_CALLNAME, N_BALNAME): Define as char-type values, so + widening works consistently. + +Fri Oct 16 03:17:08 1992 John Gilmore (gnu@cygnus.com) + + * getopt.h: Update to Revised Standard FSF Version. + +Thu Oct 15 21:43:22 1992 K. Richard Pixley (rich@sendai.cygnus.com) + + * getopt.h (struct option): use the provided enum for has_arg. + + * demangle.h (AUTO_DEMANGLING, GNU_DEMANGLING, + LUCID_DEMANGLING): ultrix compilers require enums to be + enums and ints to be ints and casts where they meet. cast some + enums into ints. + +Thu Oct 15 04:35:51 1992 John Gilmore (gnu@cygnus.com) + + * bfd.h: Update after comment changes. + +Thu Oct 8 09:03:02 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h (bfd_get_symbol_leading_char): new macro for getting in xvec + +Thu Sep 3 09:10:50 1992 Stu Grossman (grossman at cygnus.com) + + * bfd.h (struct reloc_howto_struct): size needs to be signed if + it's going to hold negative values. + +Sun Aug 30 17:50:27 1992 Per Bothner (bothner@rtl.cygnus.com) + + * demangle.h: New file, moved from ../gdb. Made independent + of gdb. Allow demangling style option to be passed as a + parameter to cplus_demangle(), but using the + current_demangling_style global as the default. + +Sat Aug 29 10:07:55 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h: Merge comment change from current FSF version. + +Thu Aug 27 12:59:29 1992 Brendan Kehoe (brendan@cygnus.com) + + * bfd.h: add we32k + +Tue Aug 25 15:07:47 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: new after Z8000 stuff + +Mon Aug 17 09:01:23 1992 Ken Raeburn (raeburn@cygnus.com) + + * bfd.h: Regenerated after page/segment size changes. + +Sat Aug 1 13:46:31 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h: Merge changes from current FSF version. + +Mon Jul 20 21:06:23 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h (area_id, flags): Remove, replace with extra_arg, + use_extra_arg, and maybe_empty_object. + * obstack.h (OBSTACK_MAYBE_EMPTY_OBJECT, OBSTACK_MMALLOC_LIKE): + Remove, replaced by maybe_empty_object and use_extra_arg bitfields. + * obstack.h (obstack_full_begin, _obstack_begin): Remove area_id + and flags arguments. + * obstack.h (obstack_alloc_arg): New macro to set extra_arg. + +Thu Jul 16 08:12:44 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * bfd.h: new after adding BFD_IS_RELAXABLE + +Sat Jul 4 03:22:23 1992 John Gilmore (gnu at cygnus.com) + + * bfd.h: Regen after adding BSF_FILE. + +Mon Jun 29 14:18:36 1992 Fred Fish (fnf at sunfish) + + * obstack.h: Convert bcopy() use to memcpy(), which is more + portable, more standard, and can take advantage of gcc's builtin + functions for increased performance. + +Thu Jun 25 04:46:08 1992 John Gilmore (gnu at cygnus.com) + + * ansidecl.h (PARAMS): Incorporate this macro from gdb's defs.h. + It's a cleaner way to forward-declare function prototypes. + +Fri Jun 19 15:46:32 1992 Stu Grossman (grossman at cygnus.com) + + * bfd.h: HPPA merge. + +Tue Jun 16 21:30:56 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.h: gratuitous white space changes merged from other prep + releases. + +Thu Jun 11 01:10:55 1992 John Gilmore (gnu at cygnus.com) + + * bfd.h: Regen'd from bfd.c after removing elf_core_tdata_struct. + +Mon May 18 17:29:03 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.h: merged changes from make-3.62.11. + + * getopt.h: merged changes from grep-1.6 (alpha). + +Fri May 8 14:53:32 1992 K. Richard Pixley (rich@cygnus.com) + + * getopt.h: merged changes from bison-1.18. + +Sat Mar 14 17:25:20 1992 Fred Fish (fnf@cygnus.com) + + * obstack.h: Add "area_id" and "flags" members to obstack + structure. Add obstack_chunkfun() and obstack_freefun() to + set functions explicitly. Convert maybe_empty_object to + a bit in "flags". + +Thu Feb 27 22:01:02 1992 Per Bothner (bothner@cygnus.com) + + * wait.h (WIFSTOPPED): Add IBM rs6000-specific version. + +Fri Feb 21 20:49:20 1992 John Gilmore (gnu at cygnus.com) + + * obstack.h: Add obstack_full_begin. + * bfd.h, obstack.h: Protolint. + +Thu Jan 30 01:18:42 1992 John Gilmore (gnu at cygnus.com) + + * bfd.h: Remove comma from enum declaration. + +Mon Jan 27 22:01:13 1992 Steve Chamberlain (sac at cygnus.com) + + * bfd.h : new target entr, bfd_relax_section + +Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com) + + * bfd.h, ieee.h: ANSIfy enums. + +Thu Dec 12 20:59:56 1991 John Gilmore (gnu at cygnus.com) + + * fopen-same.h, fopen-bin.h: New files for configuring + whether fopen distinguishes binary files or not. For use + by host-dependent config files. + +Sat Nov 30 20:46:43 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * bfd.h: change the documentation format. + + * created coff, elf and opcode and aout directories. Moved: + + aout64.h ==> aout/aout64.h + ar.h ==> aout/ar.h + a.out.encap.h ==> aout/encap.h + a.out.host.h ==> aout/host.h + a.out.hp.h ==> aout/hp.h + a.out.sun4.h ==> aout/sun4.h + ranlib.h ==> aout/ranlib.h + reloc.h ==> aout/reloc.h + stab.def ==> aout/stab.def + stab.gnu.h ==> aout/stab_gnu.h + + coff-a29k.h ==> coff/a29k.h + coff-h8300.h ==> coff/h8300.h + coff-i386.h ==> coff/i386.h + coff-i960.h ==> coff/i960.h + internalcoff.h ==> coff/internal.h + coff-m68k.h ==> coff/m68k.h + coff-m88k.h ==> coff/m88k.h + coff-mips.h ==> coff/mips.h + coff-rs6000.h ==> coff/rs6000.h + + elf-common.h ==> elf/common.h + dwarf.h ==> elf/dwarf.h + elf-external.h ==> elf/external.h + elf-internal.h ==> elf/internal.h + + a29k-opcode.h ==> opcode/a29k.h + arm-opcode.h ==> opcode/arm.h + h8300-opcode.h ==> opcode/h8300.h + i386-opcode.h ==> opcode/i386.h + i860-opcode.h ==> opcode/i860.h + i960-opcode.h ==> opcode/i960.h + m68k-opcode.h ==> opcode/m68k.h + m88k-opcode.h ==> opcode/m88k.h + mips-opcode.h ==> opcode/mips.h + np1-opcode.h ==> opcode/np1.h + ns32k-opcode.h ==> opcode/ns32k.h + pn-opcode.h ==> opcode/pn.h + pyr-opcode.h ==> opcode/pyr.h + sparc-opcode.h ==> opcode/sparc.h + tahoe-opcode.h ==> opcode/tahoe.h + vax-opcode.h ==> opcode/vax.h + + + +Wed Nov 27 10:38:31 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * internalcoff.h: (internal_scnhdr) took out #def dependency, now + s_nreloc and s_nlnno are always long. (internal_reloc): allways + has an offset field now. + +Fri Nov 22 08:12:58 1991 John Gilmore (gnu at cygnus.com) + + * coff-rs6000.h: Lint; use unsigned chars for external fields. + * internalcoff.h: Lint; cast storage classes to signed char. + +Thu Nov 21 21:01:05 1991 Per Bothner (bothner at cygnus.com) + + * stab.def: Remove the GNU extended type codes (e.g. N_SETT). + * aout64.h: The heuristic for distinguishing between + sunos-style and bsd-style ZMAGIC files (wrt. where the + text segment starts) is moved into (the default definition of) + the macro N_HEADER_IN_TEXT. This definition is only used + if no other definition is used - e.g. bfd/newsos3.c defines + N_HEADER_IN_TEXT(x) to be always 0 (as before). + +Thu Nov 21 11:53:03 1991 John Gilmore (gnu at cygnus.com) + + * aout64.h (N_TXTADDR, N_TXTOFF, N_TXTSIZE): New definitions + that should handle all uses. LOGICAL_ versions deleted. + Eliminate N_HEADER_IN_TEXT, using a_entry to determine which + kind of zmagic a.out file we are looking at. + * coff-rs6000.h: Typo. + +Tue Nov 19 18:43:37 1991 Per Bothner (bothner at cygnus.com) + + (Note: This is a revised entry, as was aout64.h.) + * aout64.h: Some cleanups of N_TXTADDR and N_TXTOFF: + Will now work for both old- and new-style ZMAGIC files, + depending on N_HEADER_IN_TEXT macro. + Add LOGICAL_TXTADDR, LOICAL_TXTOFF and LOGICAL_TXTSIZE + that don't count the exec header as part + of the text segment, to be consistent with bfd. + * a.out.sun4.h: Simplified/fixed for previous change. + +Mon Nov 18 00:02:06 1991 Fred Fish (fnf at cygnus.com) + + * dwarf.h: Update to DWARF draft 5 version from gcc2. + +Thu Nov 14 19:44:59 1991 Per Bothner (bothner at cygnus.com) + + * stab.def: Added defs for extended GNU symbol types, + such as N_SETT. These are normally ifdef'd out (because + of conflicts with a.out.gnu.h), but are used by bfb_stab_name(). + +Thu Nov 14 19:17:03 1991 Fred Fish (fnf at cygnus.com) + + * elf-common.h: Add defines to support ELF symbol table code. + +Mon Nov 11 19:01:06 1991 Fred Fish (fnf at cygnus.com) + + * elf-internal.h, elf-external.h, elf-common.h: Add support for + note sections, which are used in ELF core files to hold copies + of various /proc structures. + +Thu Nov 7 08:58:26 1991 Steve Chamberlain (sac at cygnus.com) + + * internalcoff.h: took out the M88 dependency in the lineno + struct. + * coff-m88k.h: defines GET_LINENO_LNNO and PUT_LINENO_LNNO to use + 32bit linno entries. + * a29k-opcode.h: fixed encoding of mtacc + +Sun Nov 3 11:54:22 1991 Per Bothner (bothner at cygnus.com) + + * bfd.h: Updated from ../bfd/bfd-in.h (q.v). + +Fri Nov 1 11:13:53 1991 John Gilmore (gnu at cygnus.com) + + * internalcoff.h: Add x_csect defines. + +Fri Oct 25 03:18:20 1991 John Gilmore (gnu at cygnus.com) + + * Rename COFF-related files in `coff-ARCH.h' form. + coff-a29k.h, coff-i386.h, coff-i960.h, coff-m68k.h, coff-m88k.h, + coff-mips.h, coff-rs6000.h to be exact. + +Thu Oct 24 22:11:11 1991 John Gilmore (gnu at cygnus.com) + + RS/6000 support, by Metin G. Ozisik, Mimi Phûông-Thåo Võ, and + John Gilmore. + + * a.out.gnu.h: Update slightly. + * bfd.h: Add new error code, fix doc, add bfd_arch_rs6000. + * internalcoff.h: Add more F_ codes for filehdr. Add + rs/6000-dependent fields to aouthdr. Add storage classes + to syments. Add 6000-specific auxent. Add r_size in reloc. + * rs6000coff.c: New file. + +Thu Oct 24 04:13:20 1991 Fred Fish (fnf at cygnus.com) + + * dwarf.h: New file for dwarf support. Copied from gcc2 + distribution. + +Wed Oct 16 13:31:45 1991 John Gilmore (gnu at cygnus.com) + + * aout64.h: Remove PAGE_SIZE defines; they are target-dependent. + Add N_FN_SEQ for N_FN symbol type used on Sequent machines. + * stab.def: Include N_FN_SEQ in table. + * bout.h: External formats of structures use unsigned chars. + +Fri Oct 11 12:40:43 1991 Steve Chamberlain (steve at cygnus.com) + + * bfd.h:upgrade from bfd.c + * internalcoff.h: add n_name, n_zeroes and n_offset macros + * amdcoff.h: Define OMAGIC and AOUTHDRSZ. + +Fri Oct 11 10:58:06 1991 Per Bothner (bothner at cygnus.com) + + * a.out.host.h: Change SEGMENT_SIZE to 0x1000 for Sony. + * bfd.h (align_power): Add (actually move) comment. + +Tue Oct 8 15:29:32 1991 Per Bothner (bothner at cygnus.com) + + * sys/h-rtbsd.h: Define MISSING_VFPRINT (for binutils/bucomm.c). + +Sun Oct 6 19:24:39 1991 John Gilmore (gnu at cygnus.com) + + * aout64.h: Move struct internal_exec to ../bfd/libaout.h so + it can be shared by all `a.out-family' code. Rename + EXTERNAL_LIST_SIZE to EXTERNAL_NLIST_SIZE. Use basic types + for nlist members, and make strx integral rather than pointer. + More commentary on n_type values. + * bout.h: Provide a struct external_exec rather than an + internal_exec. + * m68kcoff.h: Remove `tagentries' which snuck in from the i960 + COFF port. + +Fri Oct 4 01:25:59 1991 John Gilmore (gnu at cygnus.com) + + * h8300-opcode.h: Remove `_enum' from the typedef for an enum. + * bfd.h: Update to match bfd changes. + + * sys/h-i386mach.h, sysdep.h: Add 386 Mach host support. + +Tue Oct 1 04:58:42 1991 John Gilmore (gnu at cygnus.com) + + * bfd.h, elf-common.h, elf-external.h, elf-internal.h: + Add preliminary ELF support, sufficient for GDB, from Fred Fish. + * sysdep.h, sys/h-amix.h: Support Amiga SVR4. + + * sys/h-vaxult.h: Make it work. (David Taylor <taylor@think.com>) + * a.out.vax.h: Remove unused and confusing file. + +Mon Sep 30 12:52:35 1991 Per Bothner (bothner at cygnus.com) + + * sysdep.h: Define NEWSOS3_SYS, and use it. + +Fri Sep 20 13:38:21 1991 John Gilmore (gnu at cygnus.com) + + * a.out.gnu.h (N_FN): Its value *really is* 0x1F. + Fix it, and add comments warning about or-ing N_EXT with it + and/or N_WARNING. + * aout64.h (N_FN): Fix value, add comments about N_EXT. + * stab.def (table at end): Update to show all the type + values <0x20, including low order bits. Move N_FN to + its rightful place. + +Tue Sep 17 17:41:37 1991 Stu Grossman (grossman at cygnus.com) + + * sys/h-irix3.h: sgi/irix support. + +Tue Sep 17 07:52:59 1991 John Gilmore (gnu at cygint.cygnus.com) + + * stab.def (N_DEFD): Add GNU Modula-2 debug stab, from Andrew + Beers. + +Thu Sep 12 14:12:59 1991 John Gilmore (gnu at cygint.cygnus.com) + + * internalcoff.h (SYMNMLEN, FILNMLEN, DIMNUM): Define these + for internalcoff, separately from the various external coff's. + * amdcoff.h, bcs88kcoff.h, i386coff.h, intel-coff.h, m68kcoff.h, + m88k-bcs.h: Prefix SYMNMLEN, FILNMLEN, and DIMNUM with E_'s for + the external struct definitions. + * ecoff.h: Remove these #define's, kludge no longer needed. + + * sys/h-ultra3.h: Add new Ultracomputer host. + * sysdep.h: Add ULTRA3_SYM1_SYS and use it. + +Tue Sep 10 10:11:46 1991 John Gilmore (gnu at cygint.cygnus.com) + + * i386coff.h (LINESZ): Always 6, not based on sizeof(). + (Fix from Peter Schauer <pes@regent.e-technik.tu-muenchen.de>.) + +Wed Sep 4 08:58:37 1991 John Gilmore (gnu at cygint.cygnus.com) + + * a.out.gnu.h, aout64.h: Add N_WARNING. Change N_FN to 0x0E, + to match SunOS and BSD. Add N_COMM as 0x12 for SunOS shared lib + support. + * stab.def: Add N_COMM to table, fix overlap comment. + +Tue Sep 3 06:29:20 1991 John Gilmore (gnu at cygint.cygnus.com) + + Merge with latest FSF versions of these files. + + * stab.gnu.h: Add LAST_UNUSED_STAB_CODE. + * stab.def: Update to GPL2. Move N_WARNING out, since not a + debug symbol. Change comments, and reorder table to numeric + order. Update final table comment. + (N_DSLINE, N_BSLINE): Renumber from 0x66 and 0x68, to 0x46 and 0x48. + + * obstack.h: GPL2. Merge. + +Fri Aug 23 01:54:23 1991 John Gilmore (gnu at cygint.cygnus.com) + + * a.out.gnu.h, a.out.sun4.h: Make SEGMENT_SIZE able to depend + on the particular a.out being examined. + * a.out.sun4.h: Define segment sizes for Sun-3's and Sun-4's. + * FIXME: a.out.gnu.h is almost obsolete. + * FIXME: a.out.sun4.h should be renamed a.out.sun.h now. + +Wed Aug 21 20:32:13 1991 John Gilmore (gnu at cygint.cygnus.com) + + * Start a ChangeLog for the includes directory. + + * a.out.gnu.h (N_FN): Fix value -- was 15, should be 0x1E. + * stab.def: Update allocation table in comments at end, + to reflect reality as I know it. + + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/include/aout/adobe.h b/include/aout/adobe.h new file mode 100644 index 000000000000..c751d103ac9a --- /dev/null +++ b/include/aout/adobe.h @@ -0,0 +1,313 @@ +/* `a.out.adobe' differences from standard a.out files + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef __A_OUT_ADOBE_H__ +#define __A_OUT_ADOBE_H__ + +#define BYTES_IN_WORD 4 + +/* Struct external_exec is the same. */ + +/* This is the layout on disk of the 32-bit or 64-bit exec header. */ + +struct external_exec +{ + bfd_byte e_info[4]; /* magic number and stuff */ + bfd_byte e_text[BYTES_IN_WORD]; /* length of text section in bytes */ + bfd_byte e_data[BYTES_IN_WORD]; /* length of data section in bytes */ + bfd_byte e_bss[BYTES_IN_WORD]; /* length of bss area in bytes */ + bfd_byte e_syms[BYTES_IN_WORD]; /* length of symbol table in bytes */ + bfd_byte e_entry[BYTES_IN_WORD]; /* start address */ + bfd_byte e_trsize[BYTES_IN_WORD]; /* length of text relocation info */ + bfd_byte e_drsize[BYTES_IN_WORD]; /* length of data relocation info */ +}; + +#define EXEC_BYTES_SIZE (4 + BYTES_IN_WORD * 7) + +/* Magic numbers for a.out files */ + +#undef ZMAGIC +#define ZMAGIC 0xAD0BE /* Cute, eh? */ +#undef OMAGIC +#undef NMAGIC + +#define N_BADMAG(x) ((x).a_info != ZMAGIC) + +/* By default, segment size is constant. But some machines override this + to be a function of the a.out header (e.g. machine type). */ +#ifndef N_SEGSIZE +#define N_SEGSIZE(x) SEGMENT_SIZE +#endif +#undef N_SEGSIZE /* FIXMEXXXX */ + +/* Segment information for the a.out.Adobe format is specified after the + file header. It contains N segment descriptors, followed by one with + a type of zero. + + The actual text of the segments starts at N_TXTOFF in the file, + regardless of how many or how few segment headers there are. */ + +struct external_segdesc { + unsigned char e_type[1]; + unsigned char e_size[3]; + unsigned char e_virtbase[4]; + unsigned char e_filebase[4]; +}; + +struct internal_segdesc { + unsigned int a_type:8; /* Segment type N_TEXT, N_DATA, 0 */ + unsigned int a_size:24; /* Segment size */ + bfd_vma a_virtbase; /* Virtual address */ + unsigned int a_filebase; /* Base address in object file */ +}; + +#define N_TXTADDR(x) \ + +/* This is documented to be at 1024, but appears to really be at 2048. + FIXME?! */ +#define N_TXTOFF(x) 2048 + +#define N_TXTSIZE(x) ((x).a_text) + +#define N_DATADDR(x) + +#define N_BSSADDR(x) + +/* Offsets of the various portions of the file after the text segment. */ + +#define N_DATOFF(x) ( N_TXTOFF(x) + N_TXTSIZE(x) ) +#define N_TRELOFF(x) ( N_DATOFF(x) + (x).a_data ) +#define N_DRELOFF(x) ( N_TRELOFF(x) + (x).a_trsize ) +#define N_SYMOFF(x) ( N_DRELOFF(x) + (x).a_drsize ) +#define N_STROFF(x) ( N_SYMOFF(x) + (x).a_syms ) + +/* Symbols */ +struct external_nlist { + bfd_byte e_strx[BYTES_IN_WORD]; /* index into string table of name */ + bfd_byte e_type[1]; /* type of symbol */ + bfd_byte e_other[1]; /* misc info (usually empty) */ + bfd_byte e_desc[2]; /* description field */ + bfd_byte e_value[BYTES_IN_WORD]; /* value of symbol */ +}; + +#define EXTERNAL_NLIST_SIZE (BYTES_IN_WORD+4+BYTES_IN_WORD) + +struct internal_nlist { + unsigned long n_strx; /* index into string table of name */ + unsigned char n_type; /* type of symbol */ + unsigned char n_other; /* misc info (usually empty) */ + unsigned short n_desc; /* description field */ + bfd_vma n_value; /* value of symbol */ +}; + +/* The n_type field is the symbol type, containing: */ + +#define N_UNDF 0 /* Undefined symbol */ +#define N_ABS 2 /* Absolute symbol -- defined at particular addr */ +#define N_TEXT 4 /* Text sym -- defined at offset in text seg */ +#define N_DATA 6 /* Data sym -- defined at offset in data seg */ +#define N_BSS 8 /* BSS sym -- defined at offset in zero'd seg */ +#define N_COMM 0x12 /* Common symbol (visible after shared lib dynlink) */ +#define N_FN 0x1f /* File name of .o file */ +#define N_FN_SEQ 0x0C /* N_FN from Sequent compilers (sigh) */ +/* Note: N_EXT can only be usefully OR-ed with N_UNDF, N_ABS, N_TEXT, + N_DATA, or N_BSS. When the low-order bit of other types is set, + (e.g. N_WARNING versus N_FN), they are two different types. */ +#define N_EXT 1 /* External symbol (as opposed to local-to-this-file) */ +#define N_TYPE 0x1e +#define N_STAB 0xe0 /* If any of these bits are on, it's a debug symbol */ + +#define N_INDR 0x0a + +/* The following symbols refer to set elements. + All the N_SET[ATDB] symbols with the same name form one set. + Space is allocated for the set in the text section, and each set + elements value is stored into one word of the space. + The first word of the space is the length of the set (number of elements). + + The address of the set is made into an N_SETV symbol + whose name is the same as the name of the set. + This symbol acts like a N_DATA global symbol + in that it can satisfy undefined external references. */ + +/* These appear as input to LD, in a .o file. */ +#define N_SETA 0x14 /* Absolute set element symbol */ +#define N_SETT 0x16 /* Text set element symbol */ +#define N_SETD 0x18 /* Data set element symbol */ +#define N_SETB 0x1A /* Bss set element symbol */ + +/* This is output from LD. */ +#define N_SETV 0x1C /* Pointer to set vector in data area. */ + +/* Warning symbol. The text gives a warning message, the next symbol + in the table will be undefined. When the symbol is referenced, the + message is printed. */ + +#define N_WARNING 0x1e + +/* Relocations + + There are two types of relocation flavours for a.out systems, + standard and extended. The standard form is used on systems where the + instruction has room for all the bits of an offset to the operand, whilst + the extended form is used when an address operand has to be split over n + instructions. Eg, on the 68k, each move instruction can reference + the target with a displacement of 16 or 32 bits. On the sparc, move + instructions use an offset of 14 bits, so the offset is stored in + the reloc field, and the data in the section is ignored. +*/ + +/* This structure describes a single relocation to be performed. + The text-relocation section of the file is a vector of these structures, + all of which apply to the text section. + Likewise, the data-relocation section applies to the data section. */ + +struct reloc_std_external { + bfd_byte r_address[BYTES_IN_WORD]; /* offset of of data to relocate */ + bfd_byte r_index[3]; /* symbol table index of symbol */ + bfd_byte r_type[1]; /* relocation type */ +}; + +#define RELOC_STD_BITS_PCREL_BIG 0x80 +#define RELOC_STD_BITS_PCREL_LITTLE 0x01 + +#define RELOC_STD_BITS_LENGTH_BIG 0x60 +#define RELOC_STD_BITS_LENGTH_SH_BIG 5 /* To shift to units place */ +#define RELOC_STD_BITS_LENGTH_LITTLE 0x06 +#define RELOC_STD_BITS_LENGTH_SH_LITTLE 1 + +#define RELOC_STD_BITS_EXTERN_BIG 0x10 +#define RELOC_STD_BITS_EXTERN_LITTLE 0x08 + +#define RELOC_STD_BITS_BASEREL_BIG 0x08 +#define RELOC_STD_BITS_BASEREL_LITTLE 0x08 + +#define RELOC_STD_BITS_JMPTABLE_BIG 0x04 +#define RELOC_STD_BITS_JMPTABLE_LITTLE 0x04 + +#define RELOC_STD_BITS_RELATIVE_BIG 0x02 +#define RELOC_STD_BITS_RELATIVE_LITTLE 0x02 + +#define RELOC_STD_SIZE (BYTES_IN_WORD + 3 + 1) /* Bytes per relocation entry */ + +struct reloc_std_internal +{ + bfd_vma r_address; /* Address (within segment) to be relocated. */ + /* The meaning of r_symbolnum depends on r_extern. */ + unsigned int r_symbolnum:24; + /* Nonzero means value is a pc-relative offset + and it should be relocated for changes in its own address + as well as for changes in the symbol or section specified. */ + unsigned int r_pcrel:1; + /* Length (as exponent of 2) of the field to be relocated. + Thus, a value of 2 indicates 1<<2 bytes. */ + unsigned int r_length:2; + /* 1 => relocate with value of symbol. + r_symbolnum is the index of the symbol + in files the symbol table. + 0 => relocate with the address of a segment. + r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS + (the N_EXT bit may be set also, but signifies nothing). */ + unsigned int r_extern:1; + /* The next three bits are for SunOS shared libraries, and seem to + be undocumented. */ + unsigned int r_baserel:1; /* Linkage table relative */ + unsigned int r_jmptable:1; /* pc-relative to jump table */ + unsigned int r_relative:1; /* "relative relocation" */ + /* unused */ + unsigned int r_pad:1; /* Padding -- set to zero */ +}; + + +/* EXTENDED RELOCS */ + +struct reloc_ext_external { + bfd_byte r_address[BYTES_IN_WORD]; /* offset of of data to relocate */ + bfd_byte r_index[3]; /* symbol table index of symbol */ + bfd_byte r_type[1]; /* relocation type */ + bfd_byte r_addend[BYTES_IN_WORD]; /* datum addend */ +}; + +#define RELOC_EXT_BITS_EXTERN_BIG 0x80 +#define RELOC_EXT_BITS_EXTERN_LITTLE 0x01 + +#define RELOC_EXT_BITS_TYPE_BIG 0x1F +#define RELOC_EXT_BITS_TYPE_SH_BIG 0 +#define RELOC_EXT_BITS_TYPE_LITTLE 0xF8 +#define RELOC_EXT_BITS_TYPE_SH_LITTLE 3 + +/* Bytes per relocation entry */ +#define RELOC_EXT_SIZE (BYTES_IN_WORD + 3 + 1 + BYTES_IN_WORD) + +enum reloc_type +{ + /* simple relocations */ + RELOC_8, /* data[0:7] = addend + sv */ + RELOC_16, /* data[0:15] = addend + sv */ + RELOC_32, /* data[0:31] = addend + sv */ + /* pc-rel displacement */ + RELOC_DISP8, /* data[0:7] = addend - pc + sv */ + RELOC_DISP16, /* data[0:15] = addend - pc + sv */ + RELOC_DISP32, /* data[0:31] = addend - pc + sv */ + /* Special */ + RELOC_WDISP30, /* data[0:29] = (addend + sv - pc)>>2 */ + RELOC_WDISP22, /* data[0:21] = (addend + sv - pc)>>2 */ + RELOC_HI22, /* data[0:21] = (addend + sv)>>10 */ + RELOC_22, /* data[0:21] = (addend + sv) */ + RELOC_13, /* data[0:12] = (addend + sv) */ + RELOC_LO10, /* data[0:9] = (addend + sv) */ + RELOC_SFA_BASE, + RELOC_SFA_OFF13, + /* P.I.C. (base-relative) */ + RELOC_BASE10, /* Not sure - maybe we can do this the */ + RELOC_BASE13, /* right way now */ + RELOC_BASE22, + /* for some sort of pc-rel P.I.C. (?) */ + RELOC_PC10, + RELOC_PC22, + /* P.I.C. jump table */ + RELOC_JMP_TBL, + /* reputedly for shared libraries somehow */ + RELOC_SEGOFF16, + RELOC_GLOB_DAT, + RELOC_JMP_SLOT, + RELOC_RELATIVE, + + RELOC_11, + RELOC_WDISP2_14, + RELOC_WDISP19, + RELOC_HHI22, /* data[0:21] = (addend + sv) >> 42 */ + RELOC_HLO10, /* data[0:9] = (addend + sv) >> 32 */ + + /* 29K relocation types */ + RELOC_JUMPTARG, + RELOC_CONST, + RELOC_CONSTH, + + NO_RELOC + }; + + +struct reloc_internal { + bfd_vma r_address; /* offset of of data to relocate */ + long r_index; /* symbol table index of symbol */ + enum reloc_type r_type; /* relocation type */ + bfd_vma r_addend; /* datum addend */ +}; + +#endif /* __A_OUT_ADOBE_H__ */ diff --git a/include/aout/dynix3.h b/include/aout/dynix3.h new file mode 100644 index 000000000000..b09d5d70e124 --- /dev/null +++ b/include/aout/dynix3.h @@ -0,0 +1,86 @@ +/* a.out specifics for Sequent Symmetry running Dynix 3.x + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef A_OUT_DYNIX3_H +#define A_OUT_DYNIX3_H + +#define external_exec dynix_external_exec + +/* struct exec for Dynix 3 + + a_gdtbl and a_bootstrap are only for standalone binaries. + Shared data fields are not supported by the kernel as of Dynix 3.1, + but are supported by Dynix compiler programs. */ +struct dynix_external_exec + { + unsigned char e_info[4]; + unsigned char e_text[4]; + unsigned char e_data[4]; + unsigned char e_bss[4]; + unsigned char e_syms[4]; + unsigned char e_entry[4]; + unsigned char e_trsize[4]; + unsigned char e_drsize[4]; + unsigned char e_g_code[8]; + unsigned char e_g_data[8]; + unsigned char e_g_desc[8]; + unsigned char e_shdata[4]; + unsigned char e_shbss[4]; + unsigned char e_shdrsize[4]; + unsigned char e_bootstrap[44]; + unsigned char e_reserved[12]; + unsigned char e_version[4]; + }; + +#define EXEC_BYTES_SIZE (128) + +/* All executables under Dynix are demand paged with read-only text, + Thus no NMAGIC. + + ZMAGIC has a page of 0s at virtual 0, + XMAGIC has an invalid page at virtual 0. */ +#define OMAGIC 0x12eb /* .o */ +#define ZMAGIC 0x22eb /* zero @ 0, demand load */ +#define XMAGIC 0x32eb /* invalid @ 0, demand load */ +#define SMAGIC 0x42eb /* standalone, not supported here */ + +#define N_BADMAG(x) ((OMAGIC != N_MAGIC(x)) && \ + (ZMAGIC != N_MAGIC(x)) && \ + (XMAGIC != N_MAGIC(x)) && \ + (SMAGIC != N_MAGIC(x))) + +#define N_ADDRADJ(x) ((ZMAGIC == N_MAGIC(x) || XMAGIC == N_MAGIC(x)) ? 0x1000 : 0) + +#define N_TXTOFF(x) (EXEC_BYTES_SIZE) +#define N_DATOFF(x) (N_TXTOFF(x) + N_TXTSIZE(x)) +#define N_SHDATOFF(x) (N_DATOFF(x) + (x).a_data) +#define N_TRELOFF(x) (N_SHDATOFF(x) + (x).a_shdata) +#define N_DRELOFF(x) (N_TRELOFF(x) + (x).a_trsize) +#define N_SHDRELOFF(x) (N_DRELOFF(x) + (x).a_drsize) +#define N_SYMOFF(x) (N_SHDRELOFF(x) + (x).a_shdrsize) +#define N_STROFF(x) (N_SYMOFF(x) + (x).a_syms) + +#define N_TXTADDR(x) \ + (((OMAGIC == N_MAGIC(x)) || (SMAGIC == N_MAGIC(x))) ? 0 \ + : TEXT_START_ADDR + EXEC_BYTES_SIZE) + +#define N_TXTSIZE(x) \ + (((OMAGIC == N_MAGIC(x)) || (SMAGIC == N_MAGIC(x))) ? ((x).a_text) \ + : ((x).a_text - N_ADDRADJ(x) - EXEC_BYTES_SIZE)) + +#endif /* A_OUT_DYNIX3_H */ diff --git a/include/aout/hp.h b/include/aout/hp.h new file mode 100644 index 000000000000..002f49cf453d --- /dev/null +++ b/include/aout/hp.h @@ -0,0 +1,82 @@ +/* Special version of <a.out.h> for use under hp-ux. + Copyright 1988, 1991 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* THIS FILE IS OBSOLETE. It needs to be revised as a variant "external" + a.out format for use with BFD. */ + +/* The `exec' structure and overall layout must be close to HP's when + we are running on an HP system, otherwise we will not be able to + execute the resulting file. */ + +/* Allow this file to be included twice. */ +#ifndef __GNU_EXEC_MACROS__ + +struct exec +{ + unsigned short a_machtype; /* machine type */ + unsigned short a_magic; /* magic number */ + unsigned long a_spare1; + unsigned long a_spare2; + unsigned long a_text; /* length of text, in bytes */ + unsigned long a_data; /* length of data, in bytes */ + unsigned long a_bss; /* length of uninitialized data area for file, in bytes */ + unsigned long a_trsize; /* length of relocation info for text, in bytes */ + unsigned long a_drsize; /* length of relocation info for data, in bytes */ + unsigned long a_spare3; /* HP = pascal interface size */ + unsigned long a_spare4; /* HP = symbol table size */ + unsigned long a_spare5; /* HP = debug name table size */ + unsigned long a_entry; /* start address */ + unsigned long a_spare6; /* HP = source line table size */ + unsigned long a_spare7; /* HP = value table size */ + unsigned long a_syms; /* length of symbol table data in file, in bytes */ + unsigned long a_spare8; +}; + +/* Tell a.out.gnu.h not to define `struct exec'. */ +#define __STRUCT_EXEC_OVERRIDE__ + +#include "../a.out.gnu.h" + +#undef N_MAGIC +#undef N_MACHTYPE +#undef N_FLAGS +#undef N_SET_INFO +#undef N_SET_MAGIC +#undef N_SET_MACHTYPE +#undef N_SET_FLAGS + +#define N_MAGIC(exec) ((exec) . a_magic) +#define N_MACHTYPE(exec) ((exec) . a_machtype) +#define N_SET_MAGIC(exec, magic) (((exec) . a_magic) = (magic)) +#define N_SET_MACHTYPE(exec, machtype) (((exec) . a_machtype) = (machtype)) + +#undef N_BADMAG +#define N_BADMAG(x) ((_N_BADMAG (x)) || (_N_BADMACH (x))) + +#define _N_BADMACH(x) \ +(((N_MACHTYPE (x)) != HP9000S200_ID) && \ + ((N_MACHTYPE (x)) != HP98x6_ID)) + +#define HP98x6_ID 0x20A +#define HP9000S200_ID 0x20C + +#undef _N_HDROFF +#define _N_HDROFF(x) (SEGMENT_SIZE - (sizeof (struct exec))) + +#define SEGMENT_SIZE 0x1000 + +#endif /* __GNU_EXEC_MACROS__ */ diff --git a/include/aout/hp300hpux.h b/include/aout/hp300hpux.h new file mode 100644 index 000000000000..11747613c20b --- /dev/null +++ b/include/aout/hp300hpux.h @@ -0,0 +1,119 @@ +/* Special version of <a.out.h> for use under hp-ux. + Copyright 1988, 1993, 1995, 2001 Free Software Foundation, Inc. */ + +struct hp300hpux_exec_bytes +{ + unsigned char e_info[4]; /* a_machtype/a_magic */ + unsigned char e_spare1[4]; + unsigned char e_spare2[4]; + unsigned char e_text[4]; /* length of text, in bytes */ + unsigned char e_data[4]; /* length of data, in bytes */ + unsigned char e_bss[4]; /* length of uninitialized data area , in bytes */ + unsigned char e_trsize[4]; /* length of relocation info for text, in bytes*/ + unsigned char e_drsize[4]; /* length of relocation info for data, in bytes*/ + unsigned char e_passize[4];/* HP = pascal interface size */ + unsigned char e_syms[4]; /* HP = symbol table size */ + unsigned char e_spare5[4]; /* HP = debug name table size */ + unsigned char e_entry[4]; /* start address */ + unsigned char e_spare6[4]; /* HP = source line table size */ + unsigned char e_supsize[4];/* HP = value table size */ + unsigned char e_drelocs[4]; + unsigned char e_extension[4]; /* file offset of extension */ +}; +#define EXEC_BYTES_SIZE 64 + +struct hp300hpux_nlist_bytes + { + unsigned char e_value[4]; + unsigned char e_type[1]; + unsigned char e_length[1]; /* length of ascii symbol name */ + unsigned char e_almod[2]; /* alignment mod */ + unsigned char e_shlib[2]; /* info about dynamic linking */ + }; +#define EXTERNAL_NLIST_SIZE 10 + +struct hp300hpux_reloc + { + unsigned char r_address[4];/* offset of of data to relocate */ + unsigned char r_index[2]; /* symbol table index of symbol */ + unsigned char r_type[1]; /* relocation type */ + unsigned char r_length[1]; /* length of item to reloc */ + }; + +struct hp300hpux_header_extension +{ + unsigned char e_syms[4]; + unsigned char unique_headers[12*4]; + unsigned char e_header[2]; /* type of header */ + unsigned char e_version[2]; /* version */ + unsigned char e_size[4]; /* bytes following*/ + unsigned char e_extension[4];/* file offset of next extension */ +}; +#define EXTERNAL_EXTENSION_HEADER_SIZE (16*4) + +/* hpux separates object files (0x106) and impure executables (0x107) */ +/* but the bfd code does not distinguish between them. Since we want to*/ +/* read hpux .o files, we add an special define and use it below in */ +/* offset and address calculations. */ + +#define HPUX_DOT_O_MAGIC 0x106 +#define OMAGIC 0x107 /* object file or impure executable. */ +#define NMAGIC 0x108 /* Code indicating pure executable. */ +#define ZMAGIC 0x10B /* demand-paged executable. */ + +#define N_HEADER_IN_TEXT(x) 0 + +#if 0 /* libaout.h only uses the lower 8 bits */ +#define HP98x6_ID 0x20A +#define HP9000S200_ID 0x20C +#endif +#define HP98x6_ID 0x0A +#define HP9000S200_ID 0x0C + +#define N_BADMAG(x) ((_N_BADMAG (x)) || (_N_BADMACH (x))) + +#define N_DATADDR(x) \ + ((N_MAGIC (x) == OMAGIC || N_MAGIC (x) == HPUX_DOT_O_MAGIC) \ + ? (N_TXTADDR (x) + N_TXTSIZE (x)) \ + : (N_SEGSIZE (x) + ((N_TXTADDR (x) + N_TXTSIZE (x) - 1) \ + & ~ (bfd_vma) (N_SEGSIZE (x) - 1)))) + +#define _N_BADMACH(x) \ + (((N_MACHTYPE (x)) != HP9000S200_ID) && ((N_MACHTYPE (x)) != HP98x6_ID)) + +#define _N_BADMAG(x) (N_MAGIC(x) != HPUX_DOT_O_MAGIC \ + && N_MAGIC(x) != OMAGIC \ + && N_MAGIC(x) != NMAGIC \ + && N_MAGIC(x) != ZMAGIC ) + +#undef _N_HDROFF +#define _N_HDROFF(x) (SEGMENT_SIZE - (sizeof (struct exec))) + +#undef N_DATOFF +#undef N_PASOFF +#undef N_SYMOFF +#undef N_SUPOFF +#undef N_TRELOFF +#undef N_DRELOFF +#undef N_STROFF + +#define N_DATOFF(x) ( N_TXTOFF(x) + N_TXTSIZE(x) ) +#define N_PASOFF(x) ( N_DATOFF(x) + (x).a_data) +#define N_SYMOFF(x) ( N_PASOFF(x) /* + (x).a_passize*/ ) +#define N_SUPOFF(x) ( N_SYMOFF(x) + (x).a_syms ) +#define N_TRELOFF(x) ( N_SUPOFF(x) /* + 0 (x).a_supsize*/ ) +#define N_DRELOFF(x) ( N_TRELOFF(x) + (x).a_trsize ) +#define N_EXTHOFF(x) ( N_DRELOFF(x) /* + 0 (x).a_drsize */) +#define N_STROFF(x) ( 0 /* no string table */ ) + +/* use these when the file has gnu symbol tables */ +#define N_GNU_TRELOFF(x) (N_DATOFF(x) + (x).a_data) +#define N_GNU_DRELOFF(x) (N_GNU_TRELOFF(x) + (x).a_trsize) +#define N_GNU_SYMOFF(x) (N_GNU_DRELOFF(x) + (x).a_drsize) + +#define TARGET_PAGE_SIZE 0x1000 +#define SEGMENT_SIZE 0x1000 +#define TEXT_START_ADDR 0 + +#undef N_SHARED_LIB +#define N_SHARED_LIB(x) ( 0 /* no shared libraries */ ) diff --git a/include/aout/hppa.h b/include/aout/hppa.h new file mode 100644 index 000000000000..7e185de768a4 --- /dev/null +++ b/include/aout/hppa.h @@ -0,0 +1,7 @@ +#include "filehdr.h" +#include "aouthdr.h" +#include "scnhdr.h" +#include "spacehdr.h" +#include "syms.h" + + diff --git a/include/bout.h b/include/bout.h new file mode 100644 index 000000000000..a69e280cb187 --- /dev/null +++ b/include/bout.h @@ -0,0 +1,191 @@ +/* This file is a modified version of 'a.out.h'. It is to be used in all + GNU tools modified to support the i80960 (or tools that operate on + object files created by such tools). + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* All i80960 development is done in a CROSS-DEVELOPMENT environment. I.e., + object code is generated on, and executed under the direction of a symbolic + debugger running on, a host system. We do not want to be subject to the + vagaries of which host it is or whether it supports COFF or a.out format, + or anything else. We DO want to: + + o always generate the same format object files, regardless of host. + + o have an 'a.out' header that we can modify for our own purposes + (the 80960 is typically an embedded processor and may require + enhanced linker support that the normal a.out.h header can't + accommodate). + + As for byte-ordering, the following rules apply: + + o Text and data that is actually downloaded to the target is always + in i80960 (little-endian) order. + + o All other numbers (in the header, symbols, relocation directives) + are in host byte-order: object files CANNOT be lifted from a + little-end host and used on a big-endian (or vice versa) without + modification. + ==> THIS IS NO LONGER TRUE USING BFD. WE CAN GENERATE ANY BYTE ORDER + FOR THE HEADER, AND READ ANY BYTE ORDER. PREFERENCE WOULD BE TO + USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST. <== + + o The downloader ('comm960') takes care to generate a pseudo-header + with correct (i80960) byte-ordering before shipping text and data + off to the NINDY monitor in the target systems. Symbols and + relocation info are never sent to the target. */ + +#define BMAGIC 0415 +/* We don't accept the following (see N_BADMAG macro). + They're just here so GNU code will compile. */ +#define OMAGIC 0407 /* old impure format */ +#define NMAGIC 0410 /* read-only text */ +#define ZMAGIC 0413 /* demand load format */ + +/* FILE HEADER + All 'lengths' are given as a number of bytes. + All 'alignments' are for relinkable files only; an alignment of + 'n' indicates the corresponding segment must begin at an + address that is a multiple of (2**n). */ +struct external_exec + { + /* Standard stuff */ + unsigned char e_info[4]; /* Identifies this as a b.out file */ + unsigned char e_text[4]; /* Length of text */ + unsigned char e_data[4]; /* Length of data */ + unsigned char e_bss[4]; /* Length of uninitialized data area */ + unsigned char e_syms[4]; /* Length of symbol table */ + unsigned char e_entry[4]; /* Runtime start address */ + unsigned char e_trsize[4]; /* Length of text relocation info */ + unsigned char e_drsize[4]; /* Length of data relocation info */ + + /* Added for i960 */ + unsigned char e_tload[4]; /* Text runtime load address */ + unsigned char e_dload[4]; /* Data runtime load address */ + unsigned char e_talign[1]; /* Alignment of text segment */ + unsigned char e_dalign[1]; /* Alignment of data segment */ + unsigned char e_balign[1]; /* Alignment of bss segment */ + unsigned char e_relaxable[1];/* Assembled with enough info to allow linker to relax */ + }; + +#define EXEC_BYTES_SIZE (sizeof (struct external_exec)) + +/* These macros use the a_xxx field names, since they operate on the exec + structure after it's been byte-swapped and realigned on the host machine. */ +#define N_BADMAG(x) (((x).a_info)!=BMAGIC) +#define N_TXTOFF(x) EXEC_BYTES_SIZE +#define N_DATOFF(x) ( N_TXTOFF(x) + (x).a_text ) +#define N_TROFF(x) ( N_DATOFF(x) + (x).a_data ) +#define N_TRELOFF N_TROFF +#define N_DROFF(x) ( N_TROFF(x) + (x).a_trsize ) +#define N_DRELOFF N_DROFF +#define N_SYMOFF(x) ( N_DROFF(x) + (x).a_drsize ) +#define N_STROFF(x) ( N_SYMOFF(x) + (x).a_syms ) +#define N_DATADDR(x) ( (x).a_dload ) + +/* Address of text segment in memory after it is loaded. */ +#if !defined (N_TXTADDR) +#define N_TXTADDR(x) 0 +#endif + +/* A single entry in the symbol table. */ +struct nlist + { + union + { + char* n_name; + struct nlist * n_next; + long n_strx; /* Index into string table */ + } n_un; + + unsigned char n_type; /* See below */ + char n_other; /* Used in i80960 support -- see below */ + short n_desc; + unsigned long n_value; + }; + + +/* Legal values of n_type. */ +#define N_UNDF 0 /* Undefined symbol */ +#define N_ABS 2 /* Absolute symbol */ +#define N_TEXT 4 /* Text symbol */ +#define N_DATA 6 /* Data symbol */ +#define N_BSS 8 /* BSS symbol */ +#define N_FN 31 /* Filename symbol */ + +#define N_EXT 1 /* External symbol (OR'd in with one of above) */ +#define N_TYPE 036 /* Mask for all the type bits */ +#define N_STAB 0340 /* Mask for all bits used for SDB entries */ + +/* MEANING OF 'n_other' + + If non-zero, the 'n_other' fields indicates either a leaf procedure or + a system procedure, as follows: + + 1 <= n_other <= 32 : + The symbol is the entry point to a system procedure. + 'n_value' is the address of the entry, as for any other + procedure. The system procedure number (which can be used in + a 'calls' instruction) is (n_other-1). These entries come from + '.sysproc' directives. + + n_other == N_CALLNAME + the symbol is the 'call' entry point to a leaf procedure. + The *next* symbol in the symbol table must be the corresponding + 'bal' entry point to the procedure (see following). These + entries come from '.leafproc' directives in which two different + symbols are specified (the first one is represented here). + + + n_other == N_BALNAME + the symbol is the 'bal' entry point to a leaf procedure. + These entries result from '.leafproc' directives in which only + one symbol is specified, or in which the same symbol is + specified twice. + + Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry, + but not every N_BALNAME entry must have an N_CALLNAME entry. */ +#define N_CALLNAME ((char)-1) +#define N_BALNAME ((char)-2) +#define IS_CALLNAME(x) (N_CALLNAME == (x)) +#define IS_BALNAME(x) (N_BALNAME == (x)) +#define IS_OTHER(x) ((x)>0 && (x) <=32) + +#define b_out_relocation_info relocation_info +struct relocation_info + { + int r_address; /* File address of item to be relocated. */ + unsigned +#define r_index r_symbolnum + r_symbolnum:24, /* Index of symbol on which relocation is based, + if r_extern is set. Otherwise set to + either N_TEXT, N_DATA, or N_BSS to + indicate section on which relocation is + based. */ + r_pcrel:1, /* 1 => relocate PC-relative; else absolute + On i960, pc-relative implies 24-bit + address, absolute implies 32-bit. */ + r_length:2, /* Number of bytes to relocate: + 0 => 1 byte + 1 => 2 bytes -- used for 13 bit pcrel + 2 => 4 bytes. */ + r_extern:1, + r_bsr:1, /* Something for the GNU NS32K assembler. */ + r_disp:1, /* Something for the GNU NS32K assembler. */ + r_callj:1, /* 1 if relocation target is an i960 'callj'. */ + r_relaxable:1; /* 1 if enough info is left to relax the data. */ +}; diff --git a/include/coff/ChangeLog-9103 b/include/coff/ChangeLog-9103 new file mode 100644 index 000000000000..d18113d52e92 --- /dev/null +++ b/include/coff/ChangeLog-9103 @@ -0,0 +1,1160 @@ +2003-12-02 Graham Reed <grahamr@algorithmics.com> + + * internal.h (C_WEAKEXT): Add alternative value for AIX 5.2 + based targets. + +2003-08-23 Jason Eckhardt <jle@rice.edu> + + * coff/i860.h (COFF860_R_PAIR, COFF860_R_LOW0, COFF860_R_LOW1, + COFF860_R_LOW2, COFF860_R_LOW3, COFF860_R_LOW4, COFF860_R_SPLIT0, + COFF860_R_SPLIT1, COFF860_R_SPLIT2, COFF860_R_HIGHADJ, + COFF860_R_BRADDR): Define new relocation constants and document. + Minor formatting adjustments. + +2003-08-07 Alan Modra <amodra@bigpond.net.au> + + * ti.h (GET_SCNHDR_NRELOC): Rename PTR param to LOC. + (PUT_SCNHDR_NRELOC, GET_SCNHDR_NLNNO, PUT_SCNHDR_NLNNO): Likewise. + (GET_SCNHDR_FLAGS, PUT_SCNHDR_FLAGS): Likewise. + (GET_SCNHDR_PAGE, PUT_SCNHDR_PAGE): Likewise. + +2003-07-17 Jeff Muizelaar <muizelaar@rogers.com> + + * pe.h: (IMAGE_FILE_NET_RUN_FROM_SWAP): Define. + (IMAGE_FILE_MACHINE_WCEMIPSV2): Define. + (IMAGE_FILE_MACHINE_SH3DSP): Define. + (IMAGE_FILE_MACHINE_SH3E): Define. + (IMAGE_FILE_MACHINE_SH5): Define. + (IMAGE_FILE_MACHINE_AM33): Define. + (IMAGE_FILE_MACHINE_POWERPCFP): Define. + (IMAGE_FILE_MACHINE_AXP64): Define. + (IMAGE_FILE_MACHINE_TRICORE): Define. + (IMAGE_FILE_MACHINE_CEF): Define. + (IMAGE_FILE_MACHINE_EBC): Define. + (IMAGE_FILE_MACHINE_AMD64): Define. + (IMAGE_FILE_MACHINE_M32R): Define. + (IMAGE_FILE_MACHINE_CEE): Define. + +2003-07-14 Christian Groessler <chris@groessler.org> + + * i860.h (AOUTSZ): Define for i860 coff. + +2003-06-29 Andreas Jaeger <aj@suse.de> + + * xcoff.h (struct __rtinit ): Convert to ISO C90 prototypes. + + * ecoff.h: Convert to ISO C90 prototypes. Replace PTR by void *. + +2003-04-24 Dhananjay Deshpande <dhananjayd@kpitcummins.com> + + * coff/h8300.h (H8300HNMAGIC, H8300SNMAGIC): New. + (H8300HNBADMAG, H8300SNBADMAG): New. + +2003-04-15 Rohit Kumar Srivastava <rohits@kpitcummins.com> + + * sh.h: Replace occurrances of 'Hitachi' with 'Renesas'. + * h8300.h: Likewise. + * h8500.h: Likewise. + +2003-03-25 Stan Cox <scox@redhat.com> + Nick Clifton <nickc@redhat.com> + + Contribute support for Intel's iWMMXt chip - an ARM variant: + + * arm.h (ARM_NOTE_SECTION): Define. + +2002-11-30 Alan Modra <amodra@bigpond.net.au> + + * ecoff.h: Replace boolean with bfd_boolean. + * xcoff.h: Likewise. + +2002-03-18 Tom Rix <trix@redhat.com> + + * rs6k64.h: Add U64_TOCMAGIC, AIX 5 64 bit magic number. + +2002-02-01 Tom Rix <trix@redhat.com> + + * xcoff.h: Conditionally support <aiaff> for pre AIX 4.3. + +2002-01-31 Ivan Guzvinec <ivang@opencores.org> + + * or32.h: New file. + +2001-12-24 Tom Rix <trix@redhat.com> + + * xcoff.h (xcoff_big_format_p): Make <bigaf> the default archive + format. + (XCOFFARMAG_ELEMENT_SIZE, XCOFFARMAGBIG_ELEMENT_SIZE): Define for + archive header ascii elements. + +2001-12-17 Tom Rix <trix@redhat.com> + + * xcoff.h : Add .except and .typchk section string and styp flags. + Fix xcoff_big_format_p macro. + +2001-12-16 Tom Rix <trix@redhat.com> + + * xcoff.h : Clean up formatting. + +2002-01-15 Richard Earnshaw <rearnsha@arm.com> + + * arm.h (F_VFP_FLOAT): Define. + +2001-11-11 Timothy Wall <twall@alum.mit.edu> + + * ti.h: Move arch-specific stuff from here... + (COFF_ADJUST_SYM_IN/OUT): Optionally put page flag into symbol + value. + * tic54x.h: ...to here. + +2001-10-26 Christian Groessler <cpg@aladdin.de> + + * external.h (GET_LINENO_LNNO): Fix usage of H_GET_32/16. + (PUT_LINENO_LNNO): Likewise with H_PUT_32/16. + +2001-09-21 Nick Clifton <nickc@cambridge.redhat.com> + + * ti.h (GET_SCNHDR_PAGE): Fix compile time warning. + +2001-09-18 Alan Modra <amodra@bigpond.net.au> + + * external.h (GET_LINENO_LNNO): Use H_GET_32/16. + (PUT_LINENO_LNNO): Use H_PUT_32/16. + * m88k.h (GET_LNSZ_SIZE, GET_LNSZ_LNNO, GET_SCN_NRELOC, + GET_SCN_NLINNO): Use H_GET_32. + (PUT_LNSZ_LNNO, PUT_LNSZ_SIZE, PUT_SCN_NRELOC, PUT_SCN_NLINNO): + Use H_PUT_32. + * ti.h: Formatting fixes. Make use of H_GET_* and H_PUT_* throughout. + * xcoff.h: White space changes. + +2001-09-05 Tom Rix <trix@redhat.com> + + * xcoff.h : Add XCOFF_SYSCALL32 and XCOFF_SYSCALL64 hash table flags. + +2001-08-27 Andreas Jaeger <aj@suse.de> + + * xcoff.h (struct __rtinit): Make proper prototype for rtl. + +Fri Aug 24 01:18:51 2001 J"orn Rennecke <amylaar@redhat.com> + + * internal.h (R_JMP2, R_JMPL2, R_MOVL2): Comment spelling fix. + +2001-04-05 Tom Rix <trix@redhat.com> + + * rs6000.h : move xcoff32 external structures from xcofflink. + * rs6k64.h : move xcoff64 external structures from xcofflink. + * internal.h : promote 32 bit structure elements to 64 bit + for xcoff64 support + * xcoff.h : New file. + +2001-03-23 Nick Clifton <nickc@redhat.com> + + * a29k.h: Fix compile time warning. + * external.h: Fix compile time warning. + * m88k.h: Fix compile time warning. + +2001-03-13 Nick Clifton <nickc@redhat.com> + + * external.h: New file. Common structure definitions found in + other COFF header files. + + * a29k.h: Use external.h. + * apollo.h: Use external.h. + * arm.h: Use external.h. + * h8300.h: Use external.h. + * h8500.h: Use external.h. + * i386.h: Use external.h. + * i860.h: Use external.h. + * ia64.h: Use external.h. + * m68k.h: Use external.h. + * m88k.h: Use external.h. + * mcore.h: Use external.h. + * mips.h: Use external.h. + * mipspe.h: Use external.h. + * powerpc.h: Use external.h. + * rs6000.h: Use external.h. + * rs6k64.h: Use external.h. + * sh.h: Use external.h. + * sparc.h: Use external.h. + * tic30.h: Use external.h. + * tic80.h: Use external.h. + * w65.h: Use external.h. + * we32k.h: Use external.h. + * z8k.h: Use external.h. + +2001-02-09 David Mosberger <davidm@hpl.hp.com> + + * pe.h (PEPAOUTSZ): Rename from PEP64AOUTSZ. + Rename from PEPAOUTHDR. + +2001-01-23 H.J. Lu <hjl@gnu.org> + + * pe.h (struct external_PEI_DOS_hdr): New. + (struct external_PEI_IMAGE_hdr): New. + +2000-12-11 Alan Modra <alan@linuxcare.com.au> + + * ti.h (OCTETS_PER_BYTE_POWER): Change #warning to #error. + +2000-12-08 Alan Modra <alan@linuxcare.com.au> + + * ti.h (OCTETS_PER_BYTE_POWER): Change #warn to #warning. + +2000-06-30 DJ Delorie <dj@cygnus.com> + + * pe.h: Clarify a comment. + +2000-05-05 Clinton Popetz <cpopetz@cygnus.com> + + * rs6k64.h (U802TOC64MAGIC): Change to U803XTOCMAGIC. + +2000-04-24 Clinton Popetz <cpopetz@cygnus.com> + + * rs6k64.h: New file. + +2000-04-17 Timothy Wall <twall@cygnus.com> + + * ti.h: Load page cleanup. + * intental.h: Add load page field. + +Mon Apr 17 16:44:01 2000 David Mosberger <davidm@hpl.hp.com> + + * pe.h (PEP64AOUTHDR): New header for PE+. + (PEP64AOUTSZ): New macro. + (IMAGE_SUBSYSTEM_UNKNOWN): New macro. + (IMAGE_SUBSYSTEM_NATIVE): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_GUI): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_CUI): Ditto. + (IMAGE_SUBSYSTEM_POSIX_CUI): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_CE_GUI): Ditto. + (IMAGE_SUBSYSTEM_EFI_APPLICATION): Ditto. + (IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER): Ditto. + (IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER): Ditto. + * internal.h (PE_DEF_FILE_ALIGNMENT): Define only if not defined + already. + * ia64.h: New file. + +2000-04-13 Alan Modra <alan@linuxcare.com.au> + + * ti.h (ADDR_MASK): Don't use ul suffix on constants. + (PG_MASK): Ditto. + +2000-04-11 Timothy Wall <twall@cygnus.com> + + * ti.h: Remove load page references until load pages are + reimplemented. + * tic54x.h: Ditto. + +2000-04-07 Timothy Wall <twall@cygnus.com> + + * internal.h: Fix some comments related to TI COFF (instead of tic80). + * ti.h: New. + * tic54x.h: New. + +Wed Apr 5 22:08:41 2000 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): Define. + +2000-03-15 Kazu Hirata <kazu@hxi.com> + + * internal.h: Fix a typo in the comment for R_MOVL2. + +2000-02-28 Nick Clifton <nickc@cygnus.com> + + * mipspe.h (MIPS_PE_MAGIC): Define. + * sh.h (SH_PE_MAGIC): Define. + +2000-02-22 Nick Clifton <nickc@cygnus.com> DJ Delorie <dj@cygnus.com> + + * sh.h: Add Windows CE definitions. + * arm.h: Add Windows CE definitions. + * mipspe.h: New file: Windows CE definitions for MIPS. + * pe.h: Add constants for ILF support. + +2000-01-05 Nick Clifton <nickc@cygnus.com> + + * pe.h: Fix formatting of comments. + (IMAGE_FILE_AGGRESSIVE_WS_TRIM): Define. + (IMAGE_FILE_LARGE_ADDRESS_AWARE): Define. + (IMAGE_FILE_16BIT_MACHINE): Define. + (IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP): Define. + (IMAGE_FILE_UP_SYSTEM_ONLY): Define. + (IMAGE_FILE_MACHINE_UNKNOWN): Define. + (IMAGE_FILE_MACHINE_ALPHA): Define. + (IMAGE_FILE_MACHINE_ALPHA64): Define. + (IMAGE_FILE_MACHINE_I386): Define. + (IMAGE_FILE_MACHINE_IA64): Define. + (IMAGE_FILE_MACHINE_M68K): Define. + (IMAGE_FILE_MACHINE_MIPS16): Define. + (IMAGE_FILE_MACHINE_MIPSFPU): Define. + (IMAGE_FILE_MACHINE_MIPSFPU16): Define. + (IMAGE_FILE_MACHINE_POWERPC): Define. + (IMAGE_FILE_MACHINE_R3000): Define. + (IMAGE_FILE_MACHINE_R4000): Define. + (IMAGE_FILE_MACHINE_R10000): Define. + (IMAGE_FILE_MACHINE_SH3): Define. + (IMAGE_FILE_MACHINE_SH4): Define. + (IMAGE_FILE_MACHINE_THUMB): Define. + +1999-09-20 Alan Modra <alan@spri.levels.unisa.edu.au> + + * internal.h: Delete bogus R_PCLONG, duplicate R_RELBYTE and + R_RELWORD, and rewrite some R_* as decimal. + +1999-09-06 Donn Terry <donn@interix.com> + + * internal.h (DTYPE): Define. + * pe.h (struct external_PEI_filehdr): Rename from + external_PE_filehdr. Define even if COFF_IMAGE_WITH_PE is not + defined. + +1999-07-17 Nick Clifton <nickc@cygnus.com> + + * arm.h (F_SOFT_FLOAT): Rename from F_SOFTFLOAT. + +1999-06-21 Philip Blundell <pb@nexus.co.uk> + + * arm.h (F_SOFTFLOAT): Define. + +1999-07-05 Nick Clifton <nickc@cygnus.com> + + * arm.h (F_ARM_5): Define. + +Wed Jun 2 18:08:18 1999 Richard Henderson <rth@cygnus.com> + + * internal.h (BEOS_EXE_IMAGE_BASE, BEOS_DLL_IMAGE_BASE): New. + +Mon May 17 13:35:35 1999 Stan Cox <scox@cygnus.com> + + * arm.h (F_PIC, F_ARM_2, F_ARM_2a, F_ARM_3, F_ARM_3M, + F_ARM_4, F_ARM_4T, F_APCS26): Changed values to distinguish + F_ARM_2a, F_ARM_3M, F_ARM_4T. + +1999-05-15 Nick Clifton <nickc@cygnus.com> + + * mcore.h (IMAGE_REL_MCORE_RVA): Define. + +1999-04-21 Nick Clifton <nickc@cygnus.com> + + * mcore.h (GET_LINENO_LNNO): New macro. + (PUT_LINENO_LNNO): New macro. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * mcore.h: New header file. Defines for Motorola's MCore + processor. + +Sun Dec 6 21:36:37 1998 Mark Elbrecht <snowball3@usa.net> + + * internal.h (C_WEAKEXT): Define. + +Wed Jan 27 13:35:35 1999 Stan Cox <scox@cygnus.com> + + * arm.h (F_PIC_INT, F_ARM_2, F_ARM_3, F_ARM_4, F_APCS26): + Changed values to avoid clashing with IMAGE_FILE_* coff header + flag values. + +Wed Apr 1 16:06:15 1998 Nick Clifton <nickc@cygnus.com> + + * internal.h: Document numbers associated with Thumb symbol + types. + +Fri Mar 27 17:16:57 1998 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (ISPTR, ISFCN, ISARY): Add casts to unsigned long. + +Mon Feb 2 17:10:38 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> + + * tic30.h: New file. + +Fri Dec 12 11:49:07 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (R_MPPCR15W): New relocation type, for 15 bit PC relative + offsets. + +Tue Dec 2 10:21:40 1997 Nick Clifton <nickc@cygnus.com> + + * arm.h (COFFARM): New define. + +Mon Dec 1 20:24:18 1997 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h (R_SH_SWITCH8): New. + +Sat Nov 22 15:10:14 1997 Nick Clifton <nickc@cygnus.com> + + * internal.h (C_THUMBEXTFUNC, C_THUMBSTATFUNC): Constants to + define static and external functions. + + * arm.h: Add bits to support PIC and APCS-FLOAT type binaries, + when implemented. + +Fri Oct 3 14:25:17 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (R_PPL16B): Make constant uppercase for consistency. + +Tue Jul 22 18:18:58 1997 Robert Hoehne <robert.hoehne@Mathematik.TU-Chemnitz.DE> + + * go32exe.h: New file. + +Tue Jul 8 12:23:55 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_TARGET_ID): Add define. + * internal.h (struct internal_filehdr): Add f_target_id field. + +Tue Jun 3 16:44:18 1997 Nick Clifton <nickc@cygnus.com> + + * internal.h: Add storage classes for Thumb symbols + +Mon May 26 14:07:55 1997 Ian Lance Taylor <ian@cygnus.com> + + * tic80.h (R_PPL16B): Correct value. + +Tue May 13 10:21:14 1997 Nick Clifton <nickc@cygnus.com> + + * arm.h (constants): Added new flag bits F_APCS_26 and + F_APCS_SET for the f_flags field of the filehdr structure. Added new + flags: F_APCS26, F_ARM_2, F_ARM_3, F_ARM_7, F_ARM_7T to store + information in the flags field of the internal_f structure used by BFD + routines. + +Sat May 3 08:24:59 1997 Fred Fish <fnf@cygnus.com> + + * internal.h (C_UEXT, C_STATLAB, C_EXTLAB, C_SYSTEM): + New storage classes for TIc80. + +Fri Apr 18 11:52:55 1997 Niklas Hallqvist <niklas@appli.se> + + * alpha.h (ALPHA_ECOFF_BADMAG): Recognize *BSD/alpha magic too. + (ALPHA_R_LITERALSLEAZY): Define. + * ecoff.h (ALPHA_MAGIC_BSD): Define. + +Wed Jan 29 11:31:51 1997 Ian Lance Taylor <ian@cygnus.com> + + * i960.h (R_IPR13, R_ALIGN): Define. + +Mon Jan 27 13:34:30 1997 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (R_IPRMED, R_OPTCALL, R_OPTCALLX): Move definitions + from here... + * i960.h (R_IPRMED, R_OPTCALL, R_OPTCALLX): ...to here. + +Wed Jan 22 20:10:47 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80MAGIC): Renamed to TIC80_AOUTHDR_MAGIC. + +Fri Dec 27 22:05:45 1996 Fred Fish <fnf@cygnus.com> + + * tic80.h: New file for TIc80 support. + +Thu Dec 19 16:18:11 1996 Ian Lance Taylor <ian@cygnus.com> + + * arm.h (_LIT): Define. + +Fri Jun 28 12:54:38 1996 Ian Lance Taylor <ian@cygnus.com> + + * pe.h (FILHSZ): Define. + +Wed Jun 26 16:24:26 1996 Ian Lance Taylor <ian@cygnus.com> + + * All files: Define FILHSZ, AOUTSZ, AOUTHDRSZ, SCNHSZ, SYMESZ, + AUXESZ, LINESZ, RELSZ as numeric constants rather than uses of + sizeof. Define AOUTHDRSZ in all files. + * pe.h (AOUTSZ): Define by adding to AOUTHDRSZ. + +Fri Jun 21 11:17:46 1996 Richard Henderson <rth@tamu.edu> + + * alpha.h: Add declarations for relocation types added for Alpha + OSF/1 3.0. + +Tue Jun 18 16:04:29 1996 Jeffrey A. Law <law@rtl.cygnus.com> + + * h8300.h (H8300SMAGIC): Define. + (H8300SBADMAG): Define. + +Mon Jun 10 11:53:28 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_BCC_INV, R_JMP_DEL): New relocations for + relaxing in the H8/300 series. + +Thu May 16 15:49:22 1996 Ian Lance Taylor <ian@cygnus.com> + + * sh.h (R_SH_CODE, R_SH_DATA, R_SH_LABEL): Define. + +Tue May 7 00:36:39 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_JMPL2): Renamed from R_JMPL_B8 to be + consistent with other similar relocs. + + * internal.h (H8/300 specific relocs): Add comments better + explaining what each reloc is used for. + (R_MOV16B1, R_MOV16B2): Renamed from R_MOVB1 and R_MOVB2. + (R_MOV24B1, R_MOV24B2): Renamed from R_MOVLB1 and R_MOVLB2. + (R_MOVL1, R_MOVL2): New relocs. + +Fri May 3 13:01:12 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_PCRWORD_B): Define for the h8300 relaxing + linker. + +Wed May 1 19:21:03 1996 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (SCNNMLEN): Define. + (struct internal_scnhdr): Use SCNNMLEN for s_name field. + +Fri Mar 29 13:41:25 1996 Ian Lance Taylor <ian@cygnus.com> + + * pe.h: Define IMAGE_COMDAT codes. + +Wed Mar 27 17:29:42 1996 Ian Lance Taylor <ian@cygnus.com> + + * arm.h (union external_auxent): Add x_checksum, x_associated, and + x_comdat fields to x_scn struct. + * i386.h (union external_auxent): Likewise. + * powerpc.h (union external_auxent): Likewise. + * internal.h (union internal_auxent): Likewise. + +Thu Mar 21 16:25:57 1996 David Mosberger-Tang <davidm@azstarnet.com> + + * ecoff.h (struct ecoff_find_line): Add caching fields. + +Thu Mar 14 15:22:44 1996 Jeffrey A Law (law@cygnus.com) + + * internal.h (R_MEM_INDIRECT): New reloc for the h8300. + +Fri Feb 9 10:44:11 1996 Ian Lance Taylor <ian@cygnus.com> + + * aux-coff.h: Rename from aux.h, to avoid problems on hapless DOS + systems which think that aux is a com port. + +Mon Feb 5 18:35:00 1996 Ian Lance Taylor <ian@cygnus.com> + + * i960.h (F_I960HX): Define. + +Wed Jan 31 13:11:54 1996 Richard Henderson <rth@tamu.edu> + + * aux.h: New file. + * internal.h, m68k.h: Protect against multiple inclusion. + +Wed Nov 22 13:48:39 1995 Ian Lance Taylor <ian@cygnus.com> + + * ecoff.h (_RCONST, STYP_RCONST, RELOC_SECTION_RCONST): Define. + (NUM_RELOC_SECTIONS): Update. + * symconst.h (scRConst): Define. + +Tue Nov 14 18:54:29 1995 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (C_NT_WEAK): Define. + +Thu Nov 9 14:08:30 1995 Ian Lance Taylor <ian@cygnus.com> + + * rs6000.h (STYP_OVRFLO): Define. + +Tue Nov 7 14:38:45 1995 Kim Knuttila <krk@cygnus.com> + + * powerpc.h (IMAGE_NT_OPTIONAL_HDR_MAGIC): Added define. + * pe.h: Added defines for file level flags + +Mon Nov 6 17:28:01 1995 Harry Dolan <dolan@ssd.intel.com> + + * i860.h: New file, based on i386.h. + +Wed Nov 1 15:25:18 1995 Manfred Hollstein KS/EF4A 60/1F/110 #40283 <manfred@lts.sel.alcatel.de> + + * m68k.h (PAGEMAGICEXECSWAPPED): Define. + (PAGEMAGICPEXECSWAPPED): Define. + (PAGEMAGICPEXECTSHLIB): Define. + (PAGEMAGICPEXECPAGED): Define. + (_COMMENT): DEFINE. + * m88k.h (_COMMENT): Define. + +Wed Oct 18 18:36:19 1995 Geoffrey Noer <noer@cygnus.com> + + * sym.h: #if 0'd out runtime_pdr struct because it chokes + Visual C++ and there aren't any references to it elsewhere in gdb. + +Mon Oct 16 11:12:24 1995 Ian Lance Taylor <ian@cygnus.com> + + * rs6000.h (SMALL_AOUTSZ): Define. + + * internal.h (XMC_TD): Define. + +Tue Oct 10 18:41:03 1995 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (struct internal_aouthdr): Add o_cputype field. + * rs6000.h (AOUTHDR): Rename o_resv1 to o_cputype. + +Mon Oct 9 14:45:46 1995 Ian Lance Taylor <ian@cygnus.com> + + * rs6000.h (AOUTHDR): Add o_maxdata field. Add comments. + (_PAD, _LOADER): Define. + (STYP_LOADER): Define. + * internal.h (struct internal_aouthdr): Add o_maxdata field. + +Thu Oct 5 10:02:57 1995 Ian Lance Taylor <ian@cygnus.com> + + * ecoff.h: Define section name macros and STYP macros for various + Alpha sections: .got, .hash, .dynsym, .dynstr, .rel.dyn, .conflic, + .comment, .liblist, .dynamic. + +Wed Oct 4 10:56:35 1995 Kim Knuttila <krk@cygnus.com> + + * pe.h: Moved DOSMAGIC and NT_SIGNATURE defines here + * powerpc.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines + Also removed other unused defines (various MAGIC ones) + * i386.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines + * arm.h: removed DOSMAGIC, NT_SIGNATURE, and DEFAULT_* defines + * apollo.h: removed unused DEFAULT_* defines + * alpha.h: removed unused DEFAULT_* defines + * h8500.h: removed unused DEFAULT_* defines + * h8300.h: removed unused DEFAULT_* defines + * i960.h: removed unused DEFAULT_* defines + * m88k.h: removed unused DEFAULT_* defines + * we32k.h: removed unused DEFAULT_* defines + * rs6000.h: removed unused DEFAULT_* defines + * mips.h: removed unused DEFAULT_* defines + * m68k.h: removed unused DEFAULT_* defines + * z8k.h: removed unused DEFAULT_* defines + * w65.h: removed unused DEFAULT_* defines + * sparc.h: removed unused DEFAULT_* defines + * sh.h: removed unused DEFAULT_* defines + +Fri Sep 29 08:40:08 1995 Kim Knuttila <krk@cygnus.com> + + * powerpc.h: Reformatted to GNU coding conventions. + +Wed Sep 27 06:50:50 1995 Kim Knuttila <krk@nellie> + + * pe.h: added defines for more section characteristics + * powerpc.h (new file): base coff definitions for ppc PE + +Tue Sep 12 12:08:20 1995 Ian Lance Taylor <ian@cygnus.com> + + * internal.h (struct internal_syment): Change n_numaux field from + char to unsigned char. + +Fri Sep 1 15:39:36 1995 Kazumoto Kojima <kkojima@info.kanagawa-u.ac.jp> + + * mips.h (struct rpdr_ext): Define. + +Thu Aug 31 16:51:50 1995 steve chamberlain <sac@slash.cygnus.com> + + * internal.h (internal_aouthdr, internal_filehdr): + don't indirect the pe stuff. + +Tue Aug 29 14:16:07 1995 steve chamberlain <sac@slash.cygnus.com> + + * i386.h (NT_DEF_RESERVE, NT_DEF_COMMIT): Make the same + as 'the other' compiler. + * internal.h (NT_IMAGE_BASE): Deleted. + (NT_EXE_IMAGE_BASE, NT_DLL_IMAGE_BASE): New. + (PE_DEF_SECTION_ALIGNMENT, PE_DEF_FILE_ALIGNMENT): New. + (R_IMAGEBASE): New. + +Mon Aug 21 18:12:19 1995 steve chamberlain <sac@slash.cygnus.com> + + * internal.h: (internal_filehdr): Moved PE stuff into + internal_extra_pe_filehdr. + (internal_aouthdr): Moved PE stuff into + interanl_extra_pe_aouthdr. + +Mon Jul 24 14:05:39 1995 Ian Lance Taylor <ian@cygnus.com> + + * internal.h: Move R_SH_* relocs from here... + * sh.h: ...to here. + (R_SH_SWITCH16, R_SH_SWITCH32): Define. + (R_SH_USES, R_SH_COUNT, R_SH_ALIGN): Define. + +Thu Jun 29 00:04:25 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * internal.h (NT_DEF_RESERVE, NT_DEF_COMMIT): Increase a lot. + +Tue May 16 15:08:20 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * internal.h (NT_subsystem, NT_stack_heap): Delete + +Tue May 16 15:08:20 1995 Ken Raeburn <raeburn@cujo.cygnus.com> + + * internal.h (NT_subsystem, NT_stack_heap): Now extern. + +Sat May 13 10:14:08 1995 Steve Chamberlain <sac@slash.cygnus.com> + + * pe.h: New file. + * i386.h (NT_SECTION_ALIGNMENT, NT_FILE_ALIGNMENT, + NT_DEF_RESERVE, NT_DEF_COMMIT): New. + * internal.h (internal_filehdr): New fields for PE. + (IMAGE_DATA_DIRECTORY): New. + (internal_aouthdr): New fields for PE. + +Tue Feb 14 17:59:37 1995 Ian Lance Taylor <ian@cygnus.com> + + * ecoff.h (struct ecoff_fdrtab_entry): Define. + (struct ecoff_find_line): Define. + +Sat Feb 4 14:38:03 1995 David Mosberger-Tang <davidm@piston.cs.arizona.edu> + + * sym.h (struct pdr): field "prof" added. + + * alpha.h (PDR_BITS1_PROF_*): added, macros for PDR_BITS*_RESERVED_* + updated accordingly. + +Sun Jan 15 18:38:33 1995 Steve Chamberlain <sac@splat> + + * w65.h: New file. + +Wed Nov 23 22:43:38 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * sh.h (SH_ARCH_MAGIC_BIG, SH_ARCH_MAGIC_LITTLE): New. + (SHBADMAG): Changed to suit. + +Tue Jul 26 17:46:08 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * i960.h (F_I960JX): New macro. + +Wed Jul 6 00:48:57 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * alpha.h: Add definitions for alpha file header flags, encoding + the object type of the file. + +Mon Jun 20 13:47:01 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) + + * ecoff.h (ecoff_swap_tir_in): Remove declaration. + (ecoff_swap_tir_out): Likewise. + (ecoff_swap_rndx_in, ecoff_swap_rndx_out): Likewise. + (struct ecoff_debug_swap): Add new fields: swap_tir_in, + swap_rndx_in, swap_tir_out, swap_rndx_out, read_debug_info. + +Sun Jun 12 03:51:52 1994 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * symconst.h: Pick up SGI define for stIndirect. + +Fri Apr 22 13:05:28 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (REGINFO): Don't define. + (struct ecoff_reginfo): Don't define. + + * sh.h (SH_ARCH_MAGIC): Rename from SHMAGIC. SHMAGIC is used by + several targets to mean a shared library. + (SHBADMAG): Corresponding change. + +Thu Apr 14 13:00:53 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (RELOC_BITS3_TYPE_BIG): Changed from 0x1e to 0x3e. + (RELOC_BITS3_TYPEHI_LITTLE): Define. + (RELOC_BITS3_TYPEHI_SH_LITTLE): Define. + (MIPS_R_PCREL16): Change value from 8 to 12 to match Irix 4. + (MIPS_R_RELHI): Define. + (MIPS_R_RELLO): Define. + (MIPS_R_SWITCH): Change value from 9 to 22. + +Thu Apr 7 14:19:35 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (MIPS_R_SWITCH): Define. + +Thu Mar 31 19:28:33 1994 Ken Raeburn (raeburn@cujo.cygnus.com) + + * internal.h (internal_aouthdr): Added comments for Apollo fields. + +Thu Mar 31 16:28:02 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (STYP_ECOFF_LIB): Define as used on Irix 4. + +Fri Mar 25 17:16:55 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (struct ecoff_debug_info): Add adjust field. + (struct ecoff_value_adjust): Define. + +Tue Mar 22 13:22:47 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (MIPS_R_PCREL16): Define. + +Sat Feb 26 10:26:38 1994 Ian Lance Taylor (ian@cygnus.com) + + * ecoff.h: Add casts to avoid warnings from SVR4 cc. + +Mon Feb 21 09:48:46 1994 Ian Lance Taylor (ian@lisa.cygnus.com) + + * sym.h (struct runtime_pdr): Make field adr bfd_vma, not unsigned + long. + (SYMR): Make field value bfd_vma, not long. + +Fri Feb 4 23:35:53 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * rs6000.h (STYP_DEBUG): Define. + +Wed Feb 2 14:31:37 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (union internal_auxent): Change x_csect.x_scnlen into + a union of a long and a pointer to a symbol. XCOFF sometimes uses + this field as a symbol index. + +Mon Jan 10 23:54:25 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (ecoff_debug_info): Remove fields line_end, + external_dnr_end, external_pdr_end, external_sym_end, + external_opt_end, external_aux_end, ss_end, external_fdr_end. + Replace ifdbase with ifdmap. + +Wed Jan 5 17:05:36 1994 Ken Raeburn (raeburn@deneb.cygnus.com) + + * ecoff.h (STYP_EXTENDESC, STYP_COMMENT, STYP_XDATA, STYP_PDATA): + Define. + +Wed Jan 5 16:58:24 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (NUM_RELOC_SECTIONS): Define. + +Tue Dec 21 09:24:56 1993 Ken Raeburn (raeburn@rtl.cygnus.com) + + * sparc.h (struct external_reloc): Rename field r_addend to + r_offset. + +Sat Dec 11 16:12:32 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h (R_DISP7, R_SH_IMM16): New reloc types. + +Tue Nov 23 14:23:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (struct ecoff_debug_swap): Added *_end fields for all + the symbolic information pointers. + + * sym.h: Named the EXTR structure ecoff_extr. + +Fri Nov 19 08:21:18 1993 Ken Raeburn (raeburn@rover.cygnus.com) + + * sparc.h (RELSZ): Use correct size. + +Wed Nov 17 17:18:16 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (struct ecoff_debug_info): Define. + +Tue Nov 2 17:56:57 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (struct ecoff_debug_swap): Define. + +Thu Oct 28 17:07:50 1993 Stan Shebs (shebs@rtl.cygnus.com) + + * i386.h (I386LYNXMAGIC): Rename to LYNXCOFFMAGIC. + * m68k.h (LYNXCOFFMAGIC): Define. + * sparc.h: New file. + +Tue Oct 19 15:34:50 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * alpha.h (external_aouthdr): Split four byte padding field into + two byte bldrev field and two byte padding field. + + * ecoff.h (_LITA, _PDATA, _XDATA, STYP_LITA): Defined. + +Wed Oct 13 15:52:34 1993 Ken Raeburn (raeburn@cygnus.com) + + Sun Oct 10 17:27:10 1993 Troy Rollo (troy@cbme.unsw.edu.au) + + * internal.h: Added o_sri, o_inlib and o_vid for Apollos as well + as R_DIR16. + + * apollo.h: New file + +Mon Oct 11 17:16:48 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (REGINFO, struct ecoff_reginfo): Define. + +Tue Oct 5 10:52:53 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * rs6000.h: Change non-ASCII characters in comment to octal + escapes. + +Tue Sep 28 03:27:04 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de) + + * ecoff.h (_FINI, STYP_ECOFF_FINI): Add to support .fini section. + +Fri Sep 24 11:53:53 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * mips.h (BADMAG): Recognize MIPS_MAGIC_LITTLE3 and MIPS_MAGIC_BIG3. + * ecoff.h: Define MIPS_MAGIC_LITTLE3 and MIPS_MAGIC_BIG3. + +Thu Sep 23 21:07:14 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * mips.h (BADMAG): Recognize MIPS_MAGIC_LITTLE2 and MIPS_MAGIC_BIG2. + * ecoff.h: Define MIPS_MAGIC_LITTLE2 and MIPS_MAGIC_BIG2. + +Thu Sep 16 20:27:21 1993 Jim Kingdon (kingdon@cirdan.cygnus.com) + + * sym.h, symconst.h: Add comment stating these files are not part + of GDB, GAS, etc. In 1991, when we asked rms whether we could + include these files in GDB (although they are copyrighted by + someone besides the FSF), he said it was OK if they were not + considered part of GDB. + +Fri Sep 10 17:40:35 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (AUX_PUT_ANY): Cast val argument to bfd_vma. + + * alpha.c (external_aouthdr): Need four bytes of padding between + vstamp and tsize. + +Tue Sep 7 14:20:43 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff.h (AUX_GET_ANY, AUX_PUT_ANY): Changed to reflect further + change in bfd swapping routine names. + +Tue Sep 7 10:15:17 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * ecoff.h (AUX_GET_ANY): Change name of _do_getb32 to reflect bfd + changes. + +Fri Aug 13 14:30:32 1993 Ian Lance Taylor (ian@cygnus.com) + + * ecoff.h (RELOC_SECTION_NONE): Define. + +Thu Aug 12 11:24:42 1993 Ian Lance Taylor (ian@cygnus.com) + + * alpha.h (struct external_reloc): Add r_symndx field. + (RELSZ): Correct. + (RELOC_BITS*): Correct. + (ALPHA_R_*): Define. + * ecoff.h (RELOC_SECTION_{XDATA,PDATA,FINI,LITA,ABS}): Define. + (r_extern): Undefine. + * internal.h (struct internal_reloc): Make r_vaddr bfd_vma rather + than long. Add r_extern field. + + * alpha.h (PDR_BITS*): Define. + * sym.h (PDR): Give correct names to new fields. + + * ecoff.h: Moved MIPS reloc definitions from here... + * mips.h: to here. + +Mon Aug 2 16:37:14 1993 Stu Grossman (grossman at cygnus.com) + + * i386.h: Add Lynx magic number. + +Tue Aug 3 11:17:53 1993 Ian Lance Taylor (ian@cygnus.com) + + * alpha.h: Corrected external symbolic debugging structures to + match actual usage. + * internal.h (internal_filehdr, internal_aouthdr, + internal_scnhdr): Changed type of some fields to bfd_vma so they + can hold 64 bits. + * sym.h (HDRR, FDR, PDR, EXTR): Likewise. + (PDR): Added new fields found on Alpha. + * symconst.h (magicSym2): Define; new value found on Alpha. + + * ecoff.h: New file. + * alpha.h, mips.h: Moved common information into ecoff.h. Moved + external structure definitions in from ecoff-ext.h. + * ecoff-ext.h: Removed; information now in alpha.h and mips.h. + +Sun Jul 18 21:43:59 1993 Jim Kingdon (kingdon@rtl.cygnus.com) + + * i386.h: Recognize I386PTXMAGIC. + +Fri Jul 16 09:54:35 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (MIPS_AOUT_{OZ}MAGIC): Renamed from {OZ}MAGIC. + +Thu Jul 15 12:23:55 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * m88k.h (union external_auxent): Move x_fcn back inside x_fcnary. + ({GET,PUT}_FCN_{LNNOPTR,ENDNDX}): Adjust accordingly. + +Sun Jul 11 18:00:18 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * m68k.h: Define MC68KBCSMAGIC. + +Thu Jun 10 11:46:28 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (_INIT, STYP_MIPS_INIT): Define (used on Irix4). + (STYP_OTHER_LOAD): Define as STYP_MIPS_INIT. + +Wed Jun 9 15:09:09 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (OMAGIC): Define. + +Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + Support for H8/300-H + * h8300.h: New magic number. + * internal.h: New relocations. + +Mon Apr 26 18:04:47 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h, sh.h: Support for SH. + +Sat Apr 24 21:34:59 1993 Jim Kingdon (kingdon@cygnus.com) + + * a29k.h: Define _LIT. + +Fri Apr 23 18:41:23 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * alpha.h: New file. + +Thu Apr 8 12:36:34 1993 Ian Lance Taylor (ian@cygnus.com) + + * internal.h (C_SHADOW, C_VERSION): Copied in from m88k.h. + * m88k.h, i386.h, we32k.h: Don't define all the storage classes; + they're already in internal.h. + +Wed Apr 7 11:51:24 1993 Jim Kingdon (kingdon@cygnus.com) + + * internal.h: Change n_sclass to unsigned char. + Change C_EFCN to 0xff, change RS/6000 dbx symbols + to no longer be signed. + +Fri Mar 19 14:52:56 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: Add H8/500 reloc types. + +Wed Mar 17 09:46:03 1993 Ian Lance Taylor (ian@cygnus.com) + + * ecoff-ext.h (AUX_PUT_ANY): Don't use void values in branches of + conditional expression. + +Thu Mar 4 14:12:06 1993 Ian Lance Taylor (ian@cygnus.com) + + * ecoff-ext.h (AUX_GET_*): Rewrote to use new macro AUX_GET_ANY. + (AUX_PUT_*): New macros corresponding to the AUX_GET macros. + (ecoff_swap_tir_out): Added prototype. + + * mips.h (N_BTMASK, N_TMASK, N_BTSHFT, N_TSHIFT): Define; these + are needed to interpret gcc debugging output. + +Tue Feb 9 07:43:27 1993 Ian Lance Taylor (ian@cygnus.com) + + * we32k.h (BTYPE, ISPTR, ISFCN, ISARY, DECREF): Removed + more definitions duplicated in internal.h. + +Wed Feb 3 09:18:24 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (RELOC_BITS3_TYPE_*): Correct for big endian machines. + +Mon Jan 25 11:35:51 1993 Ian Lance Taylor (ian@cygnus.com) + + * internal.h (internal_aouthdr): Added additional fields used only + by MIPS ECOFF. + +Thu Jan 21 10:28:38 1993 Ian Lance Taylor (ian@cygnus.com) + + * mips.h (AOUTHDR): Added additional fields used by ECOFF. + +Tue Jan 19 12:21:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i386.h, we32k.h (N_*, T_*, DT_*): Removed still more definitions + duplicated in internal.h. + + * mips.h (RELOC_SECTION_*, ECOFF_R_*): Defined constants for ECOFF + relocs. + +Fri Jan 15 18:17:00 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff-ext.h: Added prototypes for new ECOFF swapping functions. + (opt_ext): New structure. + * mips.h (ZMAGIC): Defined to be 0413. + (_LIB): Defined to be ".lib" + (external_reloc): MIPS ECOFF relocs are only 8 bytes. Added + macros to aid in swapping. + +Fri Jan 8 16:19:26 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * ecoff-ext.h: Added prototypes for ECOFF swapping functions. + * internal.h (internal_scnhdr): Always provide s_align field, not + just on i960. + (internal_reloc): Always provide r_size field, not just on + RS/6000. + * mips.h (_RDATA, _SDATA, _SBSS, _LIT4, _LIT8, STYP_RDATA, + STYP_SDATA, STYP_SBSS, STYP_LIT4, STYP_LIT8): Defined. + (CODE_MASK, MIPS_IS_STAB, MIPS_MARK_STAB, MIPS_UNMARK_STAB, + STABS_SYMBOL): Moved in from gdb/mipsread.c. + +Wed Jan 6 14:01:46 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * i386.h, we32k.h: removed STYP_* defines, since they duplicated + those in internal.h. + +Tue Dec 29 15:40:07 1992 Ian Lance Taylor (ian@cygnus.com) + + * i386.h: define I386AIXMAGIC for Danbury AIX PS/2 compiler. + +Sat Dec 12 16:07:57 1992 Ian Lance Taylor (ian@cygnus.com) + + * i386.h: don't define BTYPE, ISPTR, ISFCN, ISARY, DECREF: they + are defined in internal.h. + +Thu Nov 12 09:52:01 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: (internal_reloc): r_offset is now a long. + * z8k.h: slight comment enhancement + +Wed Sep 30 07:46:08 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: changed z8k reloc types + +Fri Aug 28 10:16:31 1992 Brendan Kehoe (brendan@cygnus.com) + + * we32k.h: new file + +Thu Aug 27 13:00:01 1992 Brendan Kehoe (brendan@cygnus.com) + + * symconst.h: comment out cruft at the end of #endif + +Tue Aug 25 15:06:49 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: added #define for STYP_LIT, removed from a29k and + h8300. + + * z8k.h: added z8000 support + +Thu Jul 16 16:32:00 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * internal.h: added R_RELLONG_NEG reloc type + +Fri Jun 12 20:11:04 1992 John Gilmore (gnu at cygnus.com) + + * symconst.h: Fix unterminated comment. + +Wed Jun 10 07:57:49 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * i386.h: a.out magic numbers from + mohring@informatik.tu-muenchen.de + +Mon Jun 8 20:13:33 1992 John Gilmore (gnu at cygnus.com) + + * ecoff-ext.h, mips.h: Use unsigned chars everywhere. + (Suggested by Antti Miettinen.) + +Tue Apr 14 15:18:44 1992 John Gilmore (gnu at cygnus.com) + + * sym.h: Add comments. + * symconst.h: Merge with Fred's changes. + +Tue Apr 14 14:30:05 1992 Fred Fish (fnf@cygnus.com) + + * symconst.h: Pick up SGI defines for stStruct, stUnion, stEnum, + langCplusplus, and langCplusplusV2. + +Thu Apr 2 19:47:43 1992 John Gilmore (gnu at cygnus.com) + + * sym.h, symconst.h: MIPS has provided redistributable versions + of these files. Thanks! + * ecoff-ext.h: Add weakext bit to match new sym.h. + +Fri Mar 6 00:10:46 1992 John Gilmore (gnu at cygnus.com) + + * ecoff-ext.h: Add relative file descriptors. + +Thu Feb 27 11:53:04 1992 John Gilmore (gnu at cygnus.com) + + * ecoff-ext.h: New file for external (in-file) form of ecoff + symbol structures. + +Thu Feb 6 11:33:32 1992 Steve Chamberlain (sac at rtl.cygnus.com) + + * h8300.h: made the external_lineno l_lnno field 4 bytes wide. + andded GET/PUT_LINENO_LNNO macros + +Sat Nov 30 20:38:35 1991 Steve Chamberlain (sac at rtl.cygnus.com) + + * a29k.h, h8300.h, i386.h, i960.h, internal.h, m68k.h, m88k.h, + mips.h, rs6000.h: Move from above coff-<foo>.h. + + +Local Variables: +version-control: never +End: diff --git a/include/coff/a29k.h b/include/coff/a29k.h new file mode 100644 index 000000000000..673e71696a60 --- /dev/null +++ b/include/coff/a29k.h @@ -0,0 +1,148 @@ +/* COFF spec for AMD 290*0 + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Contributed by David Wood @ New York University. */ + +#ifndef AMD +# define AMD +#endif + +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* +** Magic numbers for Am29000 +** (AT&T will assign the "real" magic number) +*/ + +#define SIPFBOMAGIC 0572 /* Am29000 (Byte 0 is MSB) */ +#define SIPRBOMAGIC 0573 /* Am29000 (Byte 0 is LSB) */ + +#define A29K_MAGIC_BIG SIPFBOMAGIC +#define A29K_MAGIC_LITTLE SIPRBOMAGIC +#define A29KBADMAG(x) ( ((x).f_magic != A29K_MAGIC_BIG) && \ + ((x).f_magic != A29K_MAGIC_LITTLE)) + +#define OMAGIC A29K_MAGIC_BIG +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** File header flags currently known to us. +** +** Am29000 will use the F_AR32WR and F_AR32W flags to indicate +** the byte ordering in the file. +*/ + +/*--------------------------------------------------------------*/ + + +/* aouthdr magic numbers */ +#define NMAGIC 0410 /* separate i/d executable */ +#define SHMAGIC 0406 /* NYU/Ultra3 shared data executable + (writable text) */ +#undef _ETEXT +#define _ETEXT "_etext" + +/*--------------------------------------------------------------*/ + + +/* More names of "special" sections. */ +#define _LIT ".lit" + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Section types - with additional section type for global +** registers which will be relocatable for the Am29000. +** +** In instances where it is necessary for a linker to produce an +** output file which contains text or data not based at virtual +** address 0, e.g. for a ROM, then the linker should accept +** address base information as command input and use PAD sections +** to skip over unused addresses. +*/ + +#define STYP_BSSREG 0x1200 /* Global register area (like STYP_INFO) */ +#define STYP_ENVIR 0x2200 /* Environment (like STYP_INFO) */ +#define STYP_ABS 0x4000 /* Absolute (allocated, not reloc, loaded) */ + +/*--------------------------------------------------------------*/ + +/* +** Relocation information declaration and related definitions +*/ + +struct external_reloc +{ + char r_vaddr[4]; /* (virtual) address of reference */ + char r_symndx[4]; /* index into symbol table */ + char r_type[2]; /* relocation type */ +}; + +#define RELOC struct external_reloc +#define RELSZ 10 /* sizeof (RELOC) */ + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Relocation types for the Am29000 +*/ + +#define R_ABS 0 /* reference is absolute */ + +#define R_IREL 030 /* instruction relative (jmp/call) */ +#define R_IABS 031 /* instruction absolute (jmp/call) */ +#define R_ILOHALF 032 /* instruction low half (const) */ +#define R_IHIHALF 033 /* instruction high half (consth) part 1 */ +#define R_IHCONST 034 /* instruction high half (consth) part 2 */ + /* constant offset of R_IHIHALF relocation */ +#define R_BYTE 035 /* relocatable byte value */ +#define R_HWORD 036 /* relocatable halfword value */ +#define R_WORD 037 /* relocatable word value */ + +#define R_IGLBLRC 040 /* instruction global register RC */ +#define R_IGLBLRA 041 /* instruction global register RA */ +#define R_IGLBLRB 042 /* instruction global register RB */ + +/* +NOTE: +All the "I" forms refer to 29000 instruction formats. The linker is +expected to know how the numeric information is split and/or aligned +within the instruction word(s). R_BYTE works for instructions, too. + +If the parameter to a CONSTH instruction is a relocatable type, two +relocation records are written. The first has an r_type of R_IHIHALF +(33 octal) and a normal r_vaddr and r_symndx. The second relocation +record has an r_type of R_IHCONST (34 octal), a normal r_vaddr (which +is redundant), and an r_symndx containing the 32-bit constant offset +to the relocation instead of the actual symbol table index. This +second record is always written, even if the constant offset is zero. +The constant fields of the instruction are set to zero. +*/ + +/*--------------------------------------------------------------*/ + +/* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -*/ + +/* +** Storage class definitions - new classes for global registers. +*/ + +#define C_GLBLREG 19 /* global register */ +#define C_EXTREG 20 /* external global register */ +#define C_DEFREG 21 /* ext. def. of global register */ diff --git a/include/coff/apollo.h b/include/coff/apollo.h new file mode 100644 index 000000000000..46284594bbf9 --- /dev/null +++ b/include/coff/apollo.h @@ -0,0 +1,124 @@ +/* coff information for Apollo M68K + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define DO_NOT_DEFINE_AOUTHDR +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Motorola 68000/68008/68010/68020 */ +#define MC68MAGIC 0520 +#define MC68KWRMAGIC 0520 /* writeable text segments */ +#define MC68TVMAGIC 0521 +#define MC68KROMAGIC 0521 /* readonly shareable text segments */ +#define MC68KPGMAGIC 0522 /* demand paged text segments */ +#define M68MAGIC 0210 +#define M68TVMAGIC 0211 + +/* Apollo 68000-based machines have a different magic number. This comes + * from /usr/include/apollo/filehdr.h + */ +#define APOLLOM68KMAGIC 0627 + +#define OMAGIC M68MAGIC +#define M68KBADMAG(x) (((x).f_magic!=MC68MAGIC) && ((x).f_magic!=MC68KWRMAGIC) && ((x).f_magic!=MC68TVMAGIC) && \ + ((x).f_magic!=MC68KROMAGIC) && ((x).f_magic!=MC68KPGMAGIC) && ((x).f_magic!=M68MAGIC) && ((x).f_magic!=M68TVMAGIC) && \ + ((x).f_magic!=APOLLOM68KMAGIC) ) + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ + char o_sri[4]; /* Apollo specific - .sri data pointer */ + char o_inlib[4]; /* Apollo specific - .inlib data pointer */ + char vid[8]; /* Apollo specific - 64 bit version ID */ +} +AOUTHDR; + +#define APOLLO_COFF_VERSION_NUMBER 1 /* the value of the aouthdr magic */ +#define AOUTHDRSZ 44 +#define AOUTSZ 44 + +/* Apollo allowa for larger section names by allowing + them to be in the string table. */ + +/* If s_zeores is all zeroes, s_offset gives the real + location of the name in the string table. */ + +#define s_zeroes section_name.s_name +#define s_offset (section_name.s_name+4) + +/* More names of "special" sections. */ +#define _TV ".tv" +#define _INIT ".init" +#define _FINI ".fini" +#define _LINES ".lines" +#define _BLOCKS ".blocks" +#define _SRI ".sri" /* Static Resource Information (systype, + et al.) */ +#define _MIR ".mir" /* Module Information Records */ +#define _APTV ".aptv" /* Apollo-style transfer vectors. */ +#define _INLIB ".inlib" /* Shared Library information */ +#define _RWDI ".rwdi" /* Read/write data initialization directives for + compressed sections */ +#define _UNWIND ".unwind" /* Stack unwind information */ + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +#ifdef M68K_COFF_OFFSET + char r_offset[4]; +#endif + +}; + +#define RELOC struct external_reloc + +#ifdef M68K_COFF_OFFSET +#define RELSZ 14 +#else +#define RELSZ 10 +#endif + +/* Apollo specific STYP flags */ + +#define STYP_RELOCATED_NOT_LOADED 0x00010000 /* Section is relocated normally during linking, but need + not be loaded during program execution */ +#define STYP_DEBUG 0x00020000 /* debug section */ +#define STYP_OVERLAY 0x00040000 /* Section is overlayed */ +#define STYP_INSTRUCTION 0x00200000 /* Section contains executable code */ + +#define STYP_ZERO 0x00800000 /* Section is initialized to zero */ +#define STYP_INSTALLED 0x02000000 /* Section should be installable in KGT */ +#define STYP_LOOK_INSTALLED 0x04000000 /* Look for section in KGT */ +#define STYP_SECALIGN1 0x08000000 /* Specially aligned section */ +#define STYP_SECALIGN2 0x10000000 /* " " " */ +#define STYP_COMPRESSED 0x20000000 /* No section data per se (s_scnptr = 0), but there are + initialization directives for it in .rwdi section + (used in conjunction with STYP_BSS) */ diff --git a/include/coff/go32exe.h b/include/coff/go32exe.h new file mode 100644 index 000000000000..ccd5c917d1a4 --- /dev/null +++ b/include/coff/go32exe.h @@ -0,0 +1,37 @@ +/* COFF information for PC running go32. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define STUBSIZE 2048 + +struct external_filehdr_go32_exe + { + char stub[STUBSIZE];/* the stub to load the image */ + /* the standard COFF header */ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + }; + +#undef FILHDR +#define FILHDR struct external_filehdr_go32_exe +#undef FILHSZ +#define FILHSZ STUBSIZE+20 diff --git a/include/coff/h8300.h b/include/coff/h8300.h new file mode 100644 index 000000000000..908848c181f4 --- /dev/null +++ b/include/coff/h8300.h @@ -0,0 +1,54 @@ +/* coff information for Renesas H8/300 and H8/300-H + + Copyright 2001, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define H8300MAGIC 0x8300 +#define H8300HMAGIC 0x8301 +#define H8300SMAGIC 0x8302 +#define H8300HNMAGIC 0x8303 +#define H8300SNMAGIC 0x8304 + +#define H8300BADMAG(x) (((x).f_magic != H8300MAGIC)) +#define H8300HBADMAG(x) (((x).f_magic != H8300HMAGIC)) +#define H8300SBADMAG(x) (((x).f_magic != H8300SMAGIC)) +#define H8300HNBADMAG(x) (((x).f_magic != H8300HNMAGIC)) +#define H8300SNBADMAG(x) (((x).f_magic != H8300SNMAGIC)) + +/* Relocation directives. */ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + + + + diff --git a/include/coff/h8500.h b/include/coff/h8500.h new file mode 100644 index 000000000000..62968cad976e --- /dev/null +++ b/include/coff/h8500.h @@ -0,0 +1,46 @@ +/* coff information for Renesas H8/500 + + Copyright 2001, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define H8500MAGIC 0x8500 + +#define H8500BADMAG(x) ((0xffff && ((x).f_magic) != H8500MAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + + + + diff --git a/include/coff/i860.h b/include/coff/i860.h new file mode 100644 index 000000000000..c7072b26b232 --- /dev/null +++ b/include/coff/i860.h @@ -0,0 +1,86 @@ +/* COFF information for the Intel i860. + + Copyright 2001, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file was hacked from i386.h [dolan@ssd.intel.com] */ + +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax). */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + +#define I860MAGIC 0x14d + +#define I860BADMAG(x) ((x).f_magic != I860MAGIC) + +#undef AOUTSZ +#define AOUTSZ 36 + +/* FIXME: What are the a.out magic numbers? */ + +#define _ETEXT "etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + +/* The relocation directory entry types. + PAIR : The low half that follows relates to the preceeding HIGH[ADJ]. + HIGH : The high half of a 32-bit constant. + LOWn : The low half, insn bits 15..(n-1), 2^n-byte aligned. + SPLITn : The low half, insn bits 20..16 and 10..(n-1), 2^n-byte aligned. + HIGHADJ: Similar to HIGH, but with adjustment. + BRADDR : 26-bit branch displacement. + + Note: The Intel assembler manual lists LOW4 as one of the + relocation types, but it appears to be useless for the i860. + We will recognize it anyway, just in case it actually appears in + any object files. */ + +enum { + COFF860_R_PAIR = 0x1c, + COFF860_R_HIGH = 0x1e, + COFF860_R_LOW0 = 0x1f, + COFF860_R_LOW1 = 0x20, + COFF860_R_LOW2 = 0x21, + COFF860_R_LOW3 = 0x22, + COFF860_R_LOW4 = 0x23, + COFF860_R_SPLIT0 = 0x24, + COFF860_R_SPLIT1 = 0x25, + COFF860_R_SPLIT2 = 0x26, + COFF860_R_HIGHADJ = 0x27, + COFF860_R_BRADDR = 0x28 +}; + diff --git a/include/coff/i960.h b/include/coff/i960.h new file mode 100644 index 000000000000..b9d167e254df --- /dev/null +++ b/include/coff/i960.h @@ -0,0 +1,319 @@ +/* coff information for 80960. Origins: Intel corp, natch. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* NOTE: Tagentries (cf TAGBITS) are no longer used by the 960 */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +#define OMAGIC (0407) /* old impure format. data immediately + follows text. both sections are rw. */ +#define NMAGIC (0410) /* split i&d, read-only text */ + +/* +* Intel 80960 (I960) processor flags. +* F_I960TYPE == mask for processor type field. +*/ + +#define F_I960TYPE (0xf000) +#define F_I960CORE (0x1000) +#define F_I960KB (0x2000) +#define F_I960SB (0x2000) +#define F_I960MC (0x3000) +#define F_I960XA (0x4000) +#define F_I960CA (0x5000) +#define F_I960KA (0x6000) +#define F_I960SA (0x6000) +#define F_I960JX (0x7000) +#define F_I960HX (0x8000) + + +/** i80960 Magic Numbers +*/ + +#define I960ROMAGIC (0x160) /* read-only text segments */ +#define I960RWMAGIC (0x161) /* read-write text segments */ + +#define I960BADMAG(x) (((x).f_magic!=I960ROMAGIC) && ((x).f_magic!=I960RWMAGIC)) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct +{ + unsigned long phys_addr; + unsigned long bitarray; +} TAGBITS; + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ + char tagentries[4]; /* number of tag entries to follow */ +} +AOUTHDR; + +/* return a pointer to the tag bits array */ + +#define TAGPTR(aout) ((TAGBITS *) (&(aout.tagentries)+1)) + +/* compute size of a header */ + +/*#define AOUTSZ(aout) (sizeof(AOUTHDR)+(aout.tagentries*sizeof(TAGBITS)))*/ +#define AOUTSZ 32 +#define AOUTHDRSZ 32 + + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ + char s_align[4]; /* section alignment */ +}; + + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 44 + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + + char l_lnno[2]; /* line number */ + char padding[2]; /* force alignment */ +}; + + +#define LINENO struct external_lineno +#define LINESZ 8 + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + + struct + { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + + char e_value[4]; + char e_scnum[2]; + char e_flags[2]; + char e_type[4]; + char e_sclass[1]; + char e_numaux[1]; + char pad2[2]; +}; + +#define N_BTMASK (0x1f) +#define N_TMASK (0x60) +#define N_BTSHFT (5) +#define N_TSHIFT (2) + +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + + union + { + struct + { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + + char x_fsize[4]; /* size of function */ + + } x_misc; + + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } x_ary; + + } x_fcnary; + + char x_tvndx[2]; /* tv index */ + + } x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + + } x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + + } x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + /****************************************** + * I960-specific *2nd* aux. entry formats + ******************************************/ + struct + { + /* This is a very old typo that keeps getting propagated. */ +#define x_stdindx x_stindx + char x_stindx[4]; /* sys. table entry */ + } x_sc; /* system call entry */ + + struct + { + char x_balntry[4]; /* BAL entry point */ + } x_bal; /* BAL-callable function */ + + struct + { + char x_timestamp[4]; /* time stamp */ + char x_idstring[20]; /* producer identity string */ + + } x_ident; /* Producer ident info */ +}; + +#define SYMENT struct external_syment +#define SYMESZ 24 +#define AUXENT union external_auxent +#define AUXESZ 24 + +# define _ETEXT "_etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char pad[2]; +}; + +/* r_type values for the i960. */ + +/* The i960 uses R_RELLONG, which is defined in internal.h as 0x11. + It is an absolute 32 bit relocation. */ + +#define R_IPRMED (0x19) /* 24-bit ip-relative relocation */ +#define R_OPTCALL (0x1b) /* 32-bit optimizable call (leafproc/sysproc) */ +#define R_OPTCALLX (0x1c) /* 64-bit optimizable call (leafproc/sysproc) */ + +/* The following relocation types are defined use by relaxing linkers, + which convert 32 bit calls (which require a 64 bit instruction) + into 24 bit calls (which require a 32 bit instruction) when + possible. It will be possible whenever the target of the call is + within a 24 bit range of the call instruction. + + It is always safe to ignore these relocations. They only serve to + mark points which the relaxing linker will have to consider. The + assembler must ensure that the correct code is generated even if + the relocations are ignored. In particular, this means that the + R_IPR13 relocation may not appear with an external symbol. */ + +#define R_IPR13 (0x1d) /* 13 bit ip-relative branch */ +#define R_ALIGN (0x1e) /* alignment marker. This has no + associated symbol. Instead, the + r_symndx field indicates the + require alignment at this point in + the file. It must be a power of 2. */ + +#define RELOC struct external_reloc +#define RELSZ 12 + diff --git a/include/coff/m68k.h b/include/coff/m68k.h new file mode 100644 index 000000000000..5c5f758f50db --- /dev/null +++ b/include/coff/m68k.h @@ -0,0 +1,81 @@ +/* coff information for M68K + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef GNU_COFF_M68K_H +#define GNU_COFF_M68K_H 1 + +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Motorola 68000/68008/68010/68020 */ +#define MC68MAGIC 0520 +#define MC68KWRMAGIC 0520 /* writeable text segments */ +#define MC68TVMAGIC 0521 +#define MC68KROMAGIC 0521 /* readonly shareable text segments */ +#define MC68KPGMAGIC 0522 /* demand paged text segments */ +#define M68MAGIC 0210 +#define M68TVMAGIC 0211 + +/* This is the magic of the Bull dpx/2 */ +#define MC68KBCSMAGIC 0526 + +/* This is Lynx's all-platform magic number for executables. */ + +#define LYNXCOFFMAGIC 0415 + +#define OMAGIC M68MAGIC + +/* This intentionally does not include MC68KBCSMAGIC; it only includes + magic numbers which imply that names do not have underscores. */ +#define M68KBADMAG(x) (((x).f_magic != MC68MAGIC) \ + && ((x).f_magic != MC68KWRMAGIC) \ + && ((x).f_magic != MC68TVMAGIC) \ + && ((x).f_magic != MC68KROMAGIC) \ + && ((x).f_magic != MC68KPGMAGIC) \ + && ((x).f_magic != M68MAGIC) \ + && ((x).f_magic != M68TVMAGIC) \ + && ((x).f_magic != LYNXCOFFMAGIC)) + +/* Magic numbers for the a.out header. */ + +#define PAGEMAGICEXECSWAPPED 0407 /* executable (swapped) */ +#define PAGEMAGICPEXECSWAPPED 0410 /* pure executable (swapped) */ +#define PAGEMAGICPEXECTSHLIB 0443 /* pure executable (target shared library) */ +#define PAGEMAGICPEXECPAGED 0413 /* pure executable (paged) */ + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +#ifdef M68K_COFF_OFFSET + char r_offset[4]; +#endif +}; + +#define RELOC struct external_reloc + +#ifdef M68K_COFF_OFFSET +#define RELSZ 14 +#else +#define RELSZ 10 +#endif + +#endif /* GNU_COFF_M68K_H */ diff --git a/include/coff/m88k.h b/include/coff/m88k.h new file mode 100644 index 000000000000..331d97c92a0c --- /dev/null +++ b/include/coff/m88k.h @@ -0,0 +1,196 @@ +/* coff information for 88k bcs + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define DO_NOT_DEFINE_SCNHDR +#define L_LNNO_SIZE 4 +#define DO_NOT_DEFINE_SYMENT +#define DO_NOT_DEFINE_AUXENT +#include "coff/external.h" + +#define MC88MAGIC 0540 /* 88k BCS executable */ +#define MC88DMAGIC 0541 /* DG/UX executable */ +#define MC88OMAGIC 0555 /* Object file */ + +#define MC88BADMAG(x) (((x).f_magic != MC88MAGIC) \ + && ((x).f_magic != MC88DMAGIC) \ + && ((x).f_magic != MC88OMAGIC)) + +#define PAGEMAGIC3 0414 /* Split i&d, zero mapped */ +#define PAGEMAGICBCS 0413 + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[4]; /* number of relocation entries */ + char s_nlnno[4]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 44 + +/* Names of "special" sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _COMMENT ".comment" + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + + struct + { + char e_zeroes[4]; + char e_offset[4]; + } e; + + } e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; + char pad2[2]; +}; + +#define N_BTMASK 017 +#define N_TMASK 060 +#define N_BTSHFT 4 +#define N_TSHIFT 2 + +/* Note that this isn't the same shape as other coffs */ +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + /* 4 */ + + union + { + char x_fsize[4]; /* size of function */ + + struct + { + char x_lnno[4]; /* declaration line number */ + char x_size[4]; /* str/union/array size */ + } x_lnsz; + + } x_misc; + + /* 12 */ + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } x_ary; + + } x_fcnary; + /* 20 */ + + } x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + + } x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[4]; /* # relocation entries */ + char x_nlinno[4]; /* # line numbers */ + } x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ +}; + +#define GET_LNSZ_SIZE(abfd, ext) \ + H_GET_32 (abfd, ext->x_sym.x_misc.x_lnsz.x_size) +#define GET_LNSZ_LNNO(abfd, ext) \ + H_GET_32 (abfd, ext->x_sym.x_misc.x_lnsz.x_lnno) +#define PUT_LNSZ_LNNO(abfd, in, ext) \ + H_PUT_32 (abfd, in, ext->x_sym.x_misc.x_lnsz.x_lnno) +#define PUT_LNSZ_SIZE(abfd, in, ext) \ + H_PUT_32 (abfd, in, ext->x_sym.x_misc.x_lnsz.x_size) +#define GET_SCN_NRELOC(abfd, ext) \ + H_GET_32 (abfd, ext->x_scn.x_nreloc) +#define GET_SCN_NLINNO(abfd, ext) \ + H_GET_32 (abfd, ext->x_scn.x_nlinno) +#define PUT_SCN_NRELOC(abfd, in, ext) \ + H_PUT_32 (abfd, in, ext->x_scn.x_nreloc) +#define PUT_SCN_NLINNO(abfd, in, ext) \ + H_PUT_32 (abfd,in, ext->x_scn.x_nlinno) + +#define SYMENT struct external_syment +#define SYMESZ 20 +#define AUXENT union external_auxent +#define AUXESZ 20 + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char r_offset[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 12 + +#define NO_TVNDX diff --git a/include/coff/mcore.h b/include/coff/mcore.h new file mode 100644 index 000000000000..980cf133da92 --- /dev/null +++ b/include/coff/mcore.h @@ -0,0 +1,71 @@ +/* Motorola MCore support for BFD. + Copyright 1999 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the MCore COFF/PE ABI. */ + +#ifndef _COFF_MORE_H +#define _COFF_MORE_H + +#define INCLUDE_COMDAT_FIELDS_IN_AUXENT +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +#define MCOREMAGIC 0xb00 /* I just made this up */ + +#define MCOREBADMAG(x) (((x).f_magic != MCOREMAGIC)) + +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +#define IMAGE_REL_MCORE_ABSOLUTE 0x0000 +#define IMAGE_REL_MCORE_ADDR32 0x0001 +#define IMAGE_REL_MCORE_PCREL_IMM8BY4 0x0002 +#define IMAGE_REL_MCORE_PCREL_IMM11BY2 0x0003 +#define IMAGE_REL_MCORE_PCREL_IMM4BY2 0x0004 +#define IMAGE_REL_MCORE_PCREL_32 0x0005 +#define IMAGE_REL_MCORE_PCREL_JSR_IMM11BY2 0x0006 +#define IMAGE_REL_MCORE_RVA 0x0007 + +#define PEMCORE + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/* From winnt.h */ +#define IMAGE_NT_OPTIONAL_HDR_MAGIC 0x10b + +/* Define some NT default values. */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +struct external_reloc +{ + char r_vaddr [4]; + char r_symndx [4]; + char r_type [2]; + char r_offset [4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 14 + +#endif /* __COFF_MCORE_H */ diff --git a/include/coff/or32.h b/include/coff/or32.h new file mode 100644 index 000000000000..c2797aa9029f --- /dev/null +++ b/include/coff/or32.h @@ -0,0 +1,287 @@ +/* COFF specification for OpenRISC 1000. + Copyright (C) 1993-2000, 2002 Free Software Foundation, Inc. + Contributed by David Wood @ New York University. + Modified by Johan Rydberg, <johan.rydberg@netinsight.se> + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef OR32 +# define OR32 +#endif + +/* File Header and related definitions. */ +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + +/* Magic numbers for OpenRISC 1000. As it is know we use the + numbers for Am29000. + + (AT&T will assign the "real" magic number). */ +#define SIPFBOMAGIC 0572 /* Am29000 (Byte 0 is MSB). */ +#define SIPRBOMAGIC 0573 /* Am29000 (Byte 0 is LSB). */ + +#define OR32_MAGIC_BIG SIPFBOMAGIC +#define OR32_MAGIC_LITTLE SIPRBOMAGIC +#define OR32BADMAG(x) (((x).f_magic!=OR32_MAGIC_BIG) && \ + ((x).f_magic!=OR32_MAGIC_LITTLE)) + +#define OMAGIC OR32_MAGIC_BIG + +/* Optional (a.out) header. */ +typedef struct external_aouthdr +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry */ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} AOUTHDR; + +#define AOUTSZ 28 +#define AOUTHDRSZ 28 + +/* aouthdr magic numbers. */ +#define NMAGIC 0410 /* separate i/d executable. */ +#define SHMAGIC 0406 /* NYU/Ultra3 shared data executable + (writable text). */ + +#define _ETEXT "_etext" + +/* Section header and related definitions. */ +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries */ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* Names of "special" sections: */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _LIT ".lit" + +/* Section types - with additional section type for global + registers which will be relocatable for the OpenRISC 1000. + + In instances where it is necessary for a linker to produce an + output file which contains text or data not based at virtual + address 0, e.g. for a ROM, then the linker should accept + address base information as command input and use PAD sections + to skip over unused addresses. */ +#define STYP_BSSREG 0x1200 /* Global register area (like STYP_INFO) */ +#define STYP_ENVIR 0x2200 /* Environment (like STYP_INFO) */ +#define STYP_ABS 0x4000 /* Absolute (allocated, not reloc, loaded) */ + +/* Relocation information declaration and related definitions: */ +struct external_reloc +{ + char r_vaddr[4]; /* (virtual) address of reference */ + char r_symndx[4]; /* index into symbol table */ + char r_type[2]; /* relocation type */ +}; + +#define RELOC struct external_reloc +#define RELSZ 10 /* sizeof (RELOC) */ + +/* Relocation types for the OpenRISC 1000: */ + +#define R_ABS 0 /* reference is absolute */ +#define R_IREL 030 /* instruction relative (jmp/call) */ +#define R_IABS 031 /* instruction absolute (jmp/call) */ +#define R_ILOHALF 032 /* instruction low half (const) */ +#define R_IHIHALF 033 /* instruction high half (consth) part 1 */ +#define R_IHCONST 034 /* instruction high half (consth) part 2 */ + /* constant offset of R_IHIHALF relocation */ +#define R_BYTE 035 /* relocatable byte value */ +#define R_HWORD 036 /* relocatable halfword value */ +#define R_WORD 037 /* relocatable word value */ + +#define R_IGLBLRC 040 /* instruction global register RC */ +#define R_IGLBLRA 041 /* instruction global register RA */ +#define R_IGLBLRB 042 /* instruction global register RB */ + +/* + NOTE: + All the "I" forms refer to 29000 instruction formats. The linker is + expected to know how the numeric information is split and/or aligned + within the instruction word(s). R_BYTE works for instructions, too. + + If the parameter to a CONSTH instruction is a relocatable type, two + relocation records are written. The first has an r_type of R_IHIHALF + (33 octal) and a normal r_vaddr and r_symndx. The second relocation + record has an r_type of R_IHCONST (34 octal), a normal r_vaddr (which + is redundant), and an r_symndx containing the 32-bit constant offset + to the relocation instead of the actual symbol table index. This + second record is always written, even if the constant offset is zero. + The constant fields of the instruction are set to zero. */ + +/* Line number entry declaration and related definitions: */ +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } + l_addr; + + char l_lnno[2]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ 6 /* sizeof (LINENO) */ + +/* Symbol entry declaration and related definitions: */ +#define E_SYMNMLEN 8 /* Number of characters in a symbol name */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + struct + { + char e_zeroes[4]; + char e_offset[4]; + } + e; + } + e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 + +/* Storage class definitions - new classes for global registers: */ +#define C_GLBLREG 19 /* global register */ +#define C_EXTREG 20 /* external global register */ +#define C_DEFREG 21 /* ext. def. of global register */ + +/* Derived symbol mask/shifts: */ +#define N_BTMASK (0xf) +#define N_BTSHFT (4) +#define N_TMASK (0x30) +#define N_TSHIFT (2) + +/* Auxiliary symbol table entry declaration and related + definitions. */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union + { + struct + { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } + x_lnsz; + + char x_fsize[4]; /* size of function */ + } + x_misc; + + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } + x_fcn; + + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } + x_ary; + } + x_fcnary; + + char x_tvndx[2]; /* tv index */ + } + x_sym; + + union + { + char x_fname[E_FILNMLEN]; + + struct + { + char x_zeroes[4]; + char x_offset[4]; + } + x_n; + } + x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } + x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } + x_tv; /* info about .tv section + (in auxent of symbol .tv)) */ +}; + +#define AUXENT union external_auxent +#define AUXESZ 18 diff --git a/include/coff/tic30.h b/include/coff/tic30.h new file mode 100644 index 000000000000..30bf9dca9491 --- /dev/null +++ b/include/coff/tic30.h @@ -0,0 +1,50 @@ +/* coff information for Texas Instruments TMS320C3X + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define TIC30MAGIC 0xC000 + +#define TIC30BADMAG(x) (((x).f_magic != TIC30MAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the z8k don't have room in the instruction for the entire + offset - eg with segments */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + +/* TMS320C30 relocation types. */ + +#define R_TIC30_ABS16 0x100 /* 16 bit absolute. */ +#define R_TIC30_ABS24 0x101 /* 24 bit absolute. */ +#define R_TIC30_ABS32 0x102 /* 32 bit absolute. */ +#define R_TIC30_LDP 0x103 /* LDP bits 23-16 to 7-0. */ +#define R_TIC30_PC16 0x104 /* 16 bit pc relative. */ diff --git a/include/coff/tic4x.h b/include/coff/tic4x.h new file mode 100644 index 000000000000..0d224b25335f --- /dev/null +++ b/include/coff/tic4x.h @@ -0,0 +1,46 @@ +/* TI COFF information for Texas Instruments TMS320C4X/C3X. + This file customizes the settings in coff/ti.h. + + Copyright 2002, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef COFF_TIC4X_H +#define COFF_TIC4X_H + +#define TIC4X_TARGET_ID 0x0093 +/* Octets per byte, as a power of two. */ +#define TI_TARGET_ID TIC4X_TARGET_ID +#define OCTETS_PER_BYTE_POWER 2 +/* Add to howto to get absolute/sect-relative version. */ +#define HOWTO_BANK 6 +#define TICOFF_TARGET_ARCH bfd_arch_tic4x +/* We use COFF2. */ +#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC + +#define TICOFF_TARGET_MACHINE_GET(FLAGS) \ + (((FLAGS) & F_VERS) ? bfd_mach_tic4x : bfd_mach_tic3x) + +#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE) \ + do \ + { \ + if ((MACHINE) == bfd_mach_tic4x) \ + *(FLAGSP) |= F_VERS; \ + } \ + while (0) + +#include "coff/ti.h" + +#endif /* COFF_TIC4X_H */ diff --git a/include/coff/tic54x.h b/include/coff/tic54x.h new file mode 100644 index 000000000000..a7b7003a9f2b --- /dev/null +++ b/include/coff/tic54x.h @@ -0,0 +1,59 @@ +/* TI COFF information for Texas Instruments TMS320C54X. + This file customizes the settings in coff/ti.h. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef COFF_TIC54X_H +#define COFF_TIC54X_H + +#define TIC54X_TARGET_ID 0x98 +#define TIC54XALGMAGIC 0x009B /* c54x algebraic assembler output */ +#define TIC5X_TARGET_ID 0x92 +#define TI_TARGET_ID TIC54X_TARGET_ID +#define OCTETS_PER_BYTE_POWER 1 /* octets per byte, as a power of two */ +#define HOWTO_BANK 6 /* add to howto to get absolute/sect-relative version */ +#define TICOFF_TARGET_ARCH bfd_arch_tic54x +#define TICOFF_DEFAULT_MAGIC TICOFF1MAGIC /* we use COFF1 for compatibility */ + +/* Page macros + + The first GDB port requires flags in its remote memory access commands to + distinguish between data/prog space. Hopefully we can make this go away + eventually. Stuff the page in the upper bits of a 32-bit address, since + the c5x family only uses 16 or 23 bits. + + c2x, c5x and most c54x devices have 16-bit addresses, but the c548 has + 23-bit program addresses. Make sure the page flags don't interfere. + These flags are used by GDB to identify the destination page for + addresses. +*/ + +/* Recognized load pages (by common convention). */ +#define PG_PROG 0x0 /* PROG page */ +#define PG_DATA 0x1 /* DATA page */ +#define PG_IO 0x2 /* I/O page */ + +/** Indicate whether the given storage class requires a page flag. */ +#define NEEDS_PAGE(X) ((X)==C_EXT) +#define PAGE_MASK 0xFF000000 +#define ADDR_MASK 0x00FFFFFF +#define PG_TO_FLAG(p) (((unsigned long)(p) & 0xFF) << 24) +#define FLAG_TO_PG(f) (((f) >> 24) & 0xFF) + +#include "coff/ti.h" + +#endif /* COFF_TIC54X_H */ diff --git a/include/coff/tic80.h b/include/coff/tic80.h new file mode 100644 index 000000000000..c9347eb9eabe --- /dev/null +++ b/include/coff/tic80.h @@ -0,0 +1,122 @@ +/* coff information for TI TMS320C80 (MVP) + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define DO_NOT_DEFINE_FILHDR +#define DO_NOT_DEFINE_SCNHDR +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/********************** FILE HEADER **********************/ + +struct external_filehdr + { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + char f_target_id[2];/* target id (TIc80 specific) */ +}; + +#define TIC80_ARCH_MAGIC 0x0C1 /* Goes in the file header magic number field */ +#define TIC80_TARGET_ID 0x95 /* Goes in the target id field */ + +#define TIC80BADMAG(x) ((x).f_magic != TIC80_ARCH_MAGIC) + +#define FILHDR struct external_filehdr +#define FILHSZ 22 + +#define TIC80_AOUTHDR_MAGIC 0x108 /* Goes in the optional file header magic number field */ + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[2]; /* flags */ + char s_reserved[1]; /* reserved (TIc80 specific) */ + char s_mempage[1]; /* memory page number (TIc80) */ +}; + +/* Names of "special" sections. */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _CINIT ".cinit" +#define _CONST ".const" +#define _SWITCH ".switch" +#define _STACK ".stack" +#define _SYSMEM ".sysmem" + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* FIXME - need to correlate external_auxent with + TIc80 Code Generation Tools User's Guide, CG:A-25 */ + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the h8 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_reserved[2]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 12 + +/* TIc80 relocation types. */ + +#define R_ABS 0x00 /* Absolute address - no relocation */ +#define R_RELLONGX 0x11 /* PP: 32 bits, direct */ +#define R_PPBASE 0x34 /* PP: Global base address type */ +#define R_PPLBASE 0x35 /* PP: Local base address type */ +#define R_PP15 0x38 /* PP: Global 15 bit offset */ +#define R_PP15W 0x39 /* PP: Global 15 bit offset divided by 4 */ +#define R_PP15H 0x3A /* PP: Global 15 bit offset divided by 2 */ +#define R_PP16B 0x3B /* PP: Global 16 bit offset for bytes */ +#define R_PPL15 0x3C /* PP: Local 15 bit offset */ +#define R_PPL15W 0x3D /* PP: Local 15 bit offset divided by 4 */ +#define R_PPL15H 0x3E /* PP: Local 15 bit offset divided by 2 */ +#define R_PPL16B 0x3F /* PP: Local 16 bit offset for bytes */ +#define R_PPN15 0x40 /* PP: Global 15 bit negative offset */ +#define R_PPN15W 0x41 /* PP: Global 15 bit negative offset divided by 4 */ +#define R_PPN15H 0x42 /* PP: Global 15 bit negative offset divided by 2 */ +#define R_PPN16B 0x43 /* PP: Global 16 bit negative byte offset */ +#define R_PPLN15 0x44 /* PP: Local 15 bit negative offset */ +#define R_PPLN15W 0x45 /* PP: Local 15 bit negative offset divided by 4 */ +#define R_PPLN15H 0x46 /* PP: Local 15 bit negative offset divided by 2 */ +#define R_PPLN16B 0x47 /* PP: Local 16 bit negative byte offset */ +#define R_MPPCR15W 0x4E /* MP: 15 bit PC-relative divided by 4 */ +#define R_MPPCR 0x4F /* MP: 32 bit PC-relative divided by 4 */ diff --git a/include/coff/w65.h b/include/coff/w65.h new file mode 100644 index 000000000000..0baa3d39bb46 --- /dev/null +++ b/include/coff/w65.h @@ -0,0 +1,46 @@ +/* coff information for WDC 65816 + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +#define W65MAGIC 0x6500 + +#define W65BADMAG(x) (((x).f_magic != W65MAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the w65 don't have room in the instruction for the entire + offset - eg the strange jump and high page addressing modes */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + + + + diff --git a/include/coff/we32k.h b/include/coff/we32k.h new file mode 100644 index 000000000000..7e2791c27f21 --- /dev/null +++ b/include/coff/we32k.h @@ -0,0 +1,60 @@ +/* coff information for we32k + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#define L_LNNO_SIZE 2 +#include "coff/external.h" + +/* Bits for f_flags: + F_RELFLG relocation info stripped from file + F_EXEC file is executable (no unresolved external references) + F_LNNO line numbers stripped from file + F_LSYMS local symbols stripped from file + F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax). */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) +#define F_BM32B (0020000) +#define F_BM32MAU (0040000) + +#define WE32KMAGIC 0x170 /* we32k sans transfer vector */ +#define FBOMAGIC 0x170 /* we32k sans transfer vector */ +#define MTVMAGIC 0x171 /* we32k with transfer vector */ +#define RBOMAGIC 0x172 /* reserved */ +#define WE32KBADMAG(x) ( ((x).f_magic != WE32KMAGIC) \ + && ((x).f_magic != FBOMAGIC) \ + && ((x).f_magic != RBOMAGIC) \ + && ((x).f_magic != MTVMAGIC)) + +/* More names of "special" sections. */ +#define _TV ".tv" +#define _INIT ".init" +#define _FINI ".fini" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + diff --git a/include/coff/z8k.h b/include/coff/z8k.h new file mode 100644 index 000000000000..50cbd6b3ac9c --- /dev/null +++ b/include/coff/z8k.h @@ -0,0 +1,48 @@ +/* coff information for Zilog Z800N + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define L_LNNO_SIZE 4 +#include "coff/external.h" + +/* Type of cpu is stored in flags */ +#define F_Z8001 0x1000 +#define F_Z8002 0x2000 +#define F_MACHMASK 0xf000 + +#define Z8KMAGIC 0x8000 + +#define Z8KBADMAG(x) (((x).f_magic != Z8KMAGIC)) + +/********************** RELOCATION DIRECTIVES **********************/ + +/* The external reloc has an offset field, because some of the reloc + types on the z8k don't have room in the instruction for the entire + offset - eg with segments. */ + +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_offset[4]; + char r_type[2]; + char r_stuff[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + diff --git a/include/elf/arm-oabi.h b/include/elf/arm-oabi.h deleted file mode 100644 index da5e7316eed6..000000000000 --- a/include/elf/arm-oabi.h +++ /dev/null @@ -1,88 +0,0 @@ -/* ARM ELF support for BFD. - Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#ifndef _ELF_ARM_H -#define _ELF_ARM_H - -#include "elf/reloc-macros.h" - -/* Processor specific flags for the ELF header e_flags field. */ -#define EF_ARM_RELEXEC 0x01 -#define EF_ARM_HASENTRY 0x02 -#define EF_INTERWORK 0x04 -#define EF_APCS_26 0x08 -#define EF_APCS_FLOAT 0x10 -#define EF_PIC 0x20 -#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use. */ -#define EF_NEW_ABI 0x80 -#define EF_OLD_ABI 0x100 - -/* Local aliases for some flags to match names used by COFF port. */ -#define F_INTERWORK EF_INTERWORK -#define F_APCS26 EF_APCS_26 -#define F_APCS_FLOAT EF_APCS_FLOAT -#define F_PIC EF_PIC - -/* Additional symbol types for Thumb. */ -#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ -#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ - -/* ARM-specific values for sh_flags. */ -#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point. */ -#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */ - -/* ARM-specific program header flags. */ -#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ - -/* Relocation types. */ -START_RELOC_NUMBERS (elf_arm_reloc_type) - RELOC_NUMBER (R_ARM_NONE, 0) - RELOC_NUMBER (R_ARM_PC24, 1) - RELOC_NUMBER (R_ARM_ABS32, 2) - RELOC_NUMBER (R_ARM_REL32, 3) - RELOC_NUMBER (R_ARM_ABS8, 4) - RELOC_NUMBER (R_ARM_ABS16, 5) - RELOC_NUMBER (R_ARM_ABS12, 6) - RELOC_NUMBER (R_ARM_THM_ABS5, 7) - RELOC_NUMBER (R_ARM_THM_PC22, 8) - RELOC_NUMBER (R_ARM_SBREL32, 9) - RELOC_NUMBER (R_ARM_AMP_VCALL9, 10) - RELOC_NUMBER (R_ARM_THM_PC11, 11) /* Cygnus extension to abi: Thumb unconditional branch. */ - RELOC_NUMBER (R_ARM_THM_PC9, 12) /* Cygnus extension to abi: Thumb conditional branch. */ - RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 13) - RELOC_NUMBER (R_ARM_GNU_VTENTRY, 14) - RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */ - RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */ - RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */ - RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */ - RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT. */ - RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT. */ - RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry. */ - RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address. */ - FAKE_RELOC (FIRST_INVALID_RELOC, 28) - FAKE_RELOC (LAST_INVALID_RELOC, 249) - RELOC_NUMBER (R_ARM_RSBREL32, 250) - RELOC_NUMBER (R_ARM_THM_RPC22, 251) - RELOC_NUMBER (R_ARM_RREL32, 252) - RELOC_NUMBER (R_ARM_RABS32, 253) - RELOC_NUMBER (R_ARM_RPC24, 254) - RELOC_NUMBER (R_ARM_RBASE, 255) -END_RELOC_NUMBERS - -#endif diff --git a/include/elf/po/Make-in b/include/elf/po/Make-in deleted file mode 100644 index 0552db1feef3..000000000000 --- a/include/elf/po/Make-in +++ /dev/null @@ -1,251 +0,0 @@ -# Makefile for program source directory in GNU NLS utilities package. -# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper <drepper@gnu.ai.mit.edu> -# -# This file file be copied and used freely without restrictions. It can -# be used in projects which are not available under the GNU Public License -# but which still want to provide support for the GNU gettext functionality. -# Please note that the actual code is *not* freely available. - -PACKAGE = @PACKAGE@ -VERSION = @VERSION@ - -SHELL = /bin/sh -@SET_MAKE@ - -srcdir = @srcdir@ -top_srcdir = @top_srcdir@ -VPATH = @srcdir@ - -prefix = @prefix@ -exec_prefix = @exec_prefix@ -datadir = $(prefix)/@DATADIRNAME@ -localedir = $(datadir)/locale -gnulocaledir = $(prefix)/share/locale -gettextsrcdir = $(prefix)/share/gettext/po -subdir = po - -INSTALL = @INSTALL@ -INSTALL_DATA = @INSTALL_DATA@ -MKINSTALLDIRS = @MKINSTALLDIRS@ - -CC = @CC@ -GENCAT = @GENCAT@ -GMSGFMT = PATH=../src:$$PATH @GMSGFMT@ -MSGFMT = @MSGFMT@ -XGETTEXT = PATH=../src:$$PATH @XGETTEXT@ -MSGMERGE = PATH=../src:$$PATH msgmerge - -DEFS = @DEFS@ -CFLAGS = @CFLAGS@ -CPPFLAGS = @CPPFLAGS@ - -INCLUDES = -I.. -I$(top_srcdir)/intl - -COMPILE = $(CC) -c $(DEFS) $(INCLUDES) $(CPPFLAGS) $(CFLAGS) $(XCFLAGS) - -SOURCES = cat-id-tbl.c -POFILES = @POFILES@ -GMOFILES = @GMOFILES@ -DISTFILES = ChangeLog Makefile.in.in POTFILES.in $(PACKAGE).pot \ -stamp-cat-id $(POFILES) $(GMOFILES) $(SOURCES) - -POTFILES = \ - -CATALOGS = @CATALOGS@ -CATOBJEXT = @CATOBJEXT@ -INSTOBJEXT = @INSTOBJEXT@ - -.SUFFIXES: -.SUFFIXES: .c .o .po .pox .gmo .mo .msg .cat - -.c.o: - $(COMPILE) $< - -.po.pox: - $(MAKE) $(PACKAGE).pot - $(MSGMERGE) $< $(srcdir)/$(PACKAGE).pot -o $*.pox - -.po.mo: - $(MSGFMT) -o $@ $< - -.po.gmo: - file=$(srcdir)/`echo $* | sed 's,.*/,,'`.gmo \ - && rm -f $$file && $(GMSGFMT) -o $$file $< - -.po.cat: - sed -f ../intl/po2msg.sed < $< > $*.msg \ - && rm -f $@ && $(GENCAT) $@ $*.msg - - -all: all-@USE_NLS@ - -all-yes: $(CATALOGS) @MAINT@ $(PACKAGE).pot -all-no: - -$(srcdir)/$(PACKAGE).pot: $(POTFILES) - $(XGETTEXT) --default-domain=$(PACKAGE) --directory=$(top_srcdir) \ - --add-comments --keyword=_ --keyword=N_ \ - --files-from=$(srcdir)/POTFILES.in - rm -f $(srcdir)/$(PACKAGE).pot - mv $(PACKAGE).po $(srcdir)/$(PACKAGE).pot - -$(srcdir)/cat-id-tbl.c: stamp-cat-id; @: -$(srcdir)/stamp-cat-id: $(PACKAGE).pot - rm -f cat-id-tbl.tmp - sed -f ../intl/po2tbl.sed $(srcdir)/$(PACKAGE).pot \ - | sed -e "s/@PACKAGE NAME@/$(PACKAGE)/" > cat-id-tbl.tmp - if cmp -s cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; then \ - rm cat-id-tbl.tmp; \ - else \ - echo cat-id-tbl.c changed; \ - rm -f $(srcdir)/cat-id-tbl.c; \ - mv cat-id-tbl.tmp $(srcdir)/cat-id-tbl.c; \ - fi - cd $(srcdir) && rm -f stamp-cat-id && echo timestamp > stamp-cat-id - - -install: install-exec install-data -install-exec: -install-info: -install-data: install-data-@USE_NLS@ -install-data-no: all -install-data-yes: all - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(datadir); \ - else \ - $(top_srcdir)/mkinstalldirs $(datadir); \ - fi - @catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - case "$$cat" in \ - *.gmo) destdir=$(gnulocaledir);; \ - *) destdir=$(localedir);; \ - esac; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - dir=$$destdir/$$lang/LC_MESSAGES; \ - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $$dir; \ - else \ - $(top_srcdir)/mkinstalldirs $$dir; \ - fi; \ - if test -r $$cat; then \ - $(INSTALL_DATA) $$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ - echo "installing $$cat as $$dir/$(PACKAGE)$(INSTOBJEXT)"; \ - else \ - $(INSTALL_DATA) $(srcdir)/$$cat $$dir/$(PACKAGE)$(INSTOBJEXT); \ - echo "installing $(srcdir)/$$cat as" \ - "$$dir/$(PACKAGE)$(INSTOBJEXT)"; \ - fi; \ - if test -r $$cat.m; then \ - $(INSTALL_DATA) $$cat.m $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ - echo "installing $$cat.m as $$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ - else \ - if test -r $(srcdir)/$$cat.m ; then \ - $(INSTALL_DATA) $(srcdir)/$$cat.m \ - $$dir/$(PACKAGE)$(INSTOBJEXT).m; \ - echo "installing $(srcdir)/$$cat as" \ - "$$dir/$(PACKAGE)$(INSTOBJEXT).m"; \ - else \ - true; \ - fi; \ - fi; \ - done - if test "$(PACKAGE)" = "gettext"; then \ - if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(gettextsrcdir); \ - else \ - $(top_srcdir)/mkinstalldirs $(gettextsrcdir); \ - fi; \ - $(INSTALL_DATA) $(srcdir)/Makefile.in.in \ - $(gettextsrcdir)/Makefile.in.in; \ - else \ - : ; \ - fi - -# Define this as empty until I found a useful application. -installcheck: - -uninstall: - catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ - rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ - done - rm -f $(gettextsrcdir)/po-Makefile.in.in - -check: all - -cat-id-tbl.o: ../intl/libgettext.h - -dvi info tags TAGS ID: - -mostlyclean: - rm -f core core.* *.pox $(PACKAGE).po *.old.po cat-id-tbl.tmp - rm -fr *.o - -clean: mostlyclean - -distclean: clean - rm -f Makefile Makefile.in POTFILES *.mo *.msg *.cat *.cat.m - -maintainer-clean: distclean - @echo "This command is intended for maintainers to use;" - @echo "it deletes files that may require special tools to rebuild." - rm -f $(GMOFILES) - -distdir = ../$(PACKAGE)-$(VERSION)/$(subdir) -dist distdir: update-po $(DISTFILES) - dists="$(DISTFILES)"; \ - for file in $$dists; do \ - ln $(srcdir)/$$file $(distdir) 2> /dev/null \ - || cp -p $(srcdir)/$$file $(distdir); \ - done - -update-po: Makefile - $(MAKE) $(PACKAGE).pot - PATH=`pwd`/../src:$$PATH; \ - cd $(srcdir); \ - catalogs='$(CATALOGS)'; \ - for cat in $$catalogs; do \ - cat=`basename $$cat`; \ - lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - mv $$lang.po $$lang.old.po; \ - echo "$$lang:"; \ - if $(MSGMERGE) $$lang.old.po $(PACKAGE).pot -o $$lang.po; then \ - rm -f $$lang.old.po; \ - else \ - echo "msgmerge for $$cat failed!"; \ - rm -f $$lang.po; \ - mv $$lang.old.po $$lang.po; \ - fi; \ - done - -POTFILES: POTFILES.in - ( if test 'x$(srcdir)' != 'x.'; then \ - posrcprefix='$(top_srcdir)/'; \ - else \ - posrcprefix="../"; \ - fi; \ - rm -f $@-t $@ \ - && (sed -e '/^#/d' -e '/^[ ]*$$/d' \ - -e "s@.*@ $$posrcprefix& \\\\@" < $(srcdir)/$@.in \ - | sed -e '$$s/\\$$//') > $@-t \ - && chmod a-w $@-t \ - && mv $@-t $@ ) - -POTFILES.in: @MAINT@ ../Makefile - cd .. && $(MAKE) po/POTFILES.in - -Makefile: Make-in ../config.status POTFILES - cd .. \ - && CONFIG_FILES=$(subdir)/Makefile.in:$(subdir)/Make-in \ - CONFIG_HEADERS= $(SHELL) ./config.status - -# Tell versions [3.59,3.63) of GNU make not to export all variables. -# Otherwise a system limit (for SysV at least) may be exceeded. -.NOEXPORT: diff --git a/include/elf/po/POTFILES.in b/include/elf/po/POTFILES.in deleted file mode 100644 index a3a05867fb25..000000000000 --- a/include/elf/po/POTFILES.in +++ /dev/null @@ -1,55 +0,0 @@ -addr2line.c -ar.c -arsup.c -arsup.h -bucomm.c -bucomm.h -budbg.h -coffdump.c -coffgrok.c -coffgrok.h -debug.c -debug.c -debug.h -dlltool.c -dlltool.h -dllwrap.c -dyn-string.c -dyn-string.h -filemode.c -ieee.c -ieee.c -is-ranlib.c -is-strip.c -maybe-ranlib.c -maybe-strip.c -nlmconv.c -nlmconv.h -nm.c -not-ranlib.c -not-strip.c -objcopy.c -objdump.c -prdbg.c -rdcoff.c -rdcoff.c -rddbg.c -rddbg.c -readelf.c -rename.c -resbin.c -rescoff.c -resrc.c -resres.c -size.c -srconv.c -stabs.c -stabs.c -strings.c -sysdump.c -version.c -windres.c -windres.h -winduni.c -winduni.h -wrstabs.c diff --git a/include/elf/po/binutils.pot b/include/elf/po/binutils.pot deleted file mode 100644 index ed7ba0c4282b..000000000000 --- a/include/elf/po/binutils.pot +++ /dev/null @@ -1,3756 +0,0 @@ -# SOME DESCRIPTIVE TITLE. -# Copyright (C) YEAR Free Software Foundation, Inc. -# FIRST AUTHOR <EMAIL@ADDRESS>, YEAR. -# -#, fuzzy -msgid "" -msgstr "" -"Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2000-04-05 14:09+0930\n" -"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" -"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" -"Language-Team: LANGUAGE <LL@li.org>\n" -"MIME-Version: 1.0\n" -"Content-Type: text/plain; charset=CHARSET\n" -"Content-Transfer-Encoding: ENCODING\n" - -#: addr2line.c:76 -#, c-format -msgid "" -"Usage: %s [-CfsHV] [-b bfdname] [--target=bfdname]\n" -" [-e executable] [--exe=executable] [--demangle]\n" -" [--basenames] [--functions] [addr addr ...]\n" -msgstr "" - -#: addr2line.c:83 ar.c:286 nlmconv.c:1141 nm.c:306 objcopy.c:358 objcopy.c:390 -#: objdump.c:277 readelf.c:1703 size.c:89 strings.c:512 windres.c:737 -#, c-format -msgid "Report bugs to %s\n" -msgstr "" - -#: addr2line.c:243 -#, c-format -msgid "%s: can not get addresses from archive" -msgstr "" - -#: ar.c:235 -#, c-format -msgid "no entry %s in archive\n" -msgstr "" - -#: ar.c:252 -#, c-format -msgid "" -"Usage: %s [-]{dmpqrstx}[abcfilNoPsSuvV] [member-name] [count] archive-file " -"file...\n" -msgstr "" - -#: ar.c:255 -#, c-format -msgid " %s -M [<mri-script]\n" -msgstr "" - -#: ar.c:256 -msgid " commands:\n" -msgstr "" - -#: ar.c:257 -msgid " d - delete file(s) from the archive\n" -msgstr "" - -#: ar.c:258 -msgid " m[ab] - move file(s) in the archive\n" -msgstr "" - -#: ar.c:259 -msgid " p - print file(s) found in the archive\n" -msgstr "" - -#: ar.c:260 -msgid " q[f] - quick append file(s) to the archive\n" -msgstr "" - -#: ar.c:261 -msgid "" -" r[ab][f][u] - replace existing or insert new file(s) into the archive\n" -msgstr "" - -#: ar.c:262 -msgid " t - display contents of archive\n" -msgstr "" - -#: ar.c:263 -msgid " x[o] - extract file(s) from the archive\n" -msgstr "" - -#: ar.c:264 -msgid " command specific modifiers:\n" -msgstr "" - -#: ar.c:265 -msgid " [a] - put file(s) after [member-name]\n" -msgstr "" - -#: ar.c:266 -msgid " [b] - put file(s) before [member-name] (same as [i])\n" -msgstr "" - -#: ar.c:267 -msgid " [N] - use instance [count] of name\n" -msgstr "" - -#: ar.c:268 -msgid " [f] - truncate inserted file names\n" -msgstr "" - -#: ar.c:269 -msgid " [P] - use full path names when matching\n" -msgstr "" - -#: ar.c:270 -msgid " [o] - preserve original dates\n" -msgstr "" - -#: ar.c:271 -msgid "" -" [u] - only replace files that are newer than current archive " -"contents\n" -msgstr "" - -#: ar.c:272 -msgid " generic modifiers:\n" -msgstr "" - -#: ar.c:273 -msgid " [c] - do not warn if the library had to be created\n" -msgstr "" - -#: ar.c:274 -msgid " [s] - create an archive index (cf. ranlib)\n" -msgstr "" - -#: ar.c:275 -msgid " [S] - do not build a symbol table\n" -msgstr "" - -#: ar.c:276 -msgid " [v] - be verbose\n" -msgstr "" - -#: ar.c:277 -msgid " [V] - display the version number\n" -msgstr "" - -#: ar.c:281 -#, c-format -msgid "Usage: %s [-vV] archive\n" -msgstr "" - -#: ar.c:466 -msgid "two different operation options specified" -msgstr "" - -#: ar.c:541 -#, c-format -msgid "%s: illegal option -- %c\n" -msgstr "" - -#: ar.c:573 -msgid "no operation specified" -msgstr "" - -#: ar.c:576 -msgid "`u' is only meaningful with the `r' option." -msgstr "" - -#: ar.c:586 -msgid "`N' is only meaningful with the `x' and 'd' options." -msgstr "" - -#: ar.c:589 -msgid "Value for `N' must be positive." -msgstr "" - -#: ar.c:672 -#, c-format -msgid "%s: internal error -- this option not implemented\n" -msgstr "" - -#: ar.c:790 ar.c:841 ar.c:1283 objcopy.c:1104 -#, c-format -msgid "internal stat error on %s" -msgstr "" - -#: ar.c:810 ar.c:878 -#, c-format -msgid "%s is not a valid archive" -msgstr "" - -#: ar.c:846 -#, c-format -msgid "stat returns negative size for %s" -msgstr "" - -#: ar.c:967 -#, c-format -msgid "%s is not an archive" -msgstr "" - -#: ar.c:974 -#, c-format -msgid "%s: creating %s\n" -msgstr "" - -#: ar.c:1181 -#, c-format -msgid "No member named `%s'\n" -msgstr "" - -#: ar.c:1233 -#, c-format -msgid "%s: no entry %s in archive %s!\n" -msgstr "" - -#: ar.c:1395 -#, c-format -msgid "%s: no archive map to update" -msgstr "" - -#: arsup.c:87 -#, c-format -msgid "No entry %s in archive.\n" -msgstr "" - -#: arsup.c:119 -#, c-format -msgid "Can't open file %s\n" -msgstr "" - -#: arsup.c:167 -#, c-format -msgid "%s: Can't open output archive %s\n" -msgstr "" - -#: arsup.c:179 -#, c-format -msgid "%s: Can't open input archive %s\n" -msgstr "" - -#: arsup.c:185 -#, c-format -msgid "%s: file %s is not an archive\n" -msgstr "" - -#: arsup.c:226 -#, c-format -msgid "%s: no output archive specified yet\n" -msgstr "" - -#: arsup.c:246 arsup.c:281 arsup.c:317 arsup.c:337 arsup.c:395 -#, c-format -msgid "%s: no open output archive\n" -msgstr "" - -#: arsup.c:254 arsup.c:355 arsup.c:375 -#, c-format -msgid "%s: can't open file %s\n" -msgstr "" - -#: arsup.c:302 arsup.c:371 arsup.c:450 -#, c-format -msgid "%s: can't find module file %s\n" -msgstr "" - -#: arsup.c:402 -#, c-format -msgid "Current open archive is %s\n" -msgstr "" - -#: arsup.c:429 -#, c-format -msgid "%s: no open archive\n" -msgstr "" - -#: bucomm.c:139 -#, c-format -msgid "can't set BFD default target to `%s': %s" -msgstr "" - -#: bucomm.c:151 -#, c-format -msgid "%s: Matching formats:" -msgstr "" - -#: bucomm.c:168 -msgid "Supported targets:" -msgstr "" - -#: bucomm.c:170 -#, c-format -msgid "%s: supported targets:" -msgstr "" - -#: bucomm.c:263 -#, c-format -msgid "%s: bad number: %s" -msgstr "" - -#: coffdump.c:94 -#, c-format -msgid "#lines %d " -msgstr "" - -#: coffdump.c:456 sysdump.c:719 -#, c-format -msgid "%s: Print a human readable interpretation of a SYSROFF object file\n" -msgstr "" - -#: coffdump.c:498 srconv.c:1940 sysdump.c:755 -#, c-format -msgid "GNU %s version %s\n" -msgstr "" - -#: coffdump.c:516 srconv.c:1977 sysdump.c:775 -#, c-format -msgid "%s: no input file specified\n" -msgstr "" - -#: debug.c:653 -msgid "debug_add_to_current_namespace: no current file" -msgstr "" - -#: debug.c:736 -msgid "debug_start_source: no debug_set_filename call" -msgstr "" - -#: debug.c:795 -msgid "debug_record_function: no debug_set_filename call" -msgstr "" - -#: debug.c:851 -msgid "debug_record_parameter: no current function" -msgstr "" - -#: debug.c:885 -msgid "debug_end_function: no current function" -msgstr "" - -#: debug.c:891 -msgid "debug_end_function: some blocks were not closed" -msgstr "" - -#: debug.c:921 -msgid "debug_start_block: no current block" -msgstr "" - -#: debug.c:959 -msgid "debug_end_block: no current block" -msgstr "" - -#: debug.c:966 -msgid "debug_end_block: attempt to close top level block" -msgstr "" - -#: debug.c:992 -msgid "debug_record_line: no current unit" -msgstr "" - -#. FIXME -#: debug.c:1046 -msgid "debug_start_common_block: not implemented" -msgstr "" - -#. FIXME -#: debug.c:1058 -msgid "debug_end_common_block: not implemented" -msgstr "" - -#. FIXME. -#: debug.c:1152 -msgid "debug_record_label not implemented" -msgstr "" - -#: debug.c:1178 -msgid "debug_record_variable: no current file" -msgstr "" - -#: debug.c:1194 -msgid "debug_record_variable: no current block" -msgstr "" - -#: debug.c:1764 -msgid "debug_make_undefined_type: unsupported kind" -msgstr "" - -#: debug.c:1970 -msgid "debug_name_type: no current file" -msgstr "" - -#: debug.c:2018 -msgid "debug_tag_type: no current file" -msgstr "" - -#: debug.c:2026 -msgid "debug_tag_type: extra tag attempted" -msgstr "" - -#: debug.c:2066 -#, c-format -msgid "Warning: changing type size from %d to %d\n" -msgstr "" - -#: debug.c:2090 -msgid "debug_find_named_type: no current compilation unit" -msgstr "" - -#: debug.c:2197 -#, c-format -msgid "debug_get_real_type: circular debug information for %s\n" -msgstr "" - -#: debug.c:2662 -msgid "debug_write_type: illegal type encountered" -msgstr "" - -#: dlltool.c:770 dlltool.c:794 dlltool.c:819 -#, c-format -msgid "Internal error: Unknown machine type: %d\n" -msgstr "" - -#: dlltool.c:856 -#, c-format -msgid "Can't open def file: %s" -msgstr "" - -#: dlltool.c:861 -#, c-format -msgid "Processing def file: %s" -msgstr "" - -#: dlltool.c:865 -msgid "Processed def file" -msgstr "" - -#: dlltool.c:890 -#, c-format -msgid "Syntax error in def file %s:%d\n" -msgstr "" - -#: dlltool.c:923 -#, c-format -msgid "NAME: %s base: %x" -msgstr "" - -#: dlltool.c:926 -msgid "Can't have LIBRARY and NAME\n" -msgstr "" - -#: dlltool.c:942 -#, c-format -msgid "LIBRARY: %s base: %x" -msgstr "" - -#: dlltool.c:945 -#, c-format -msgid "%s: Can't have LIBRARY and NAME\n" -msgstr "" - -#: dlltool.c:1200 resrc.c:271 -#, c-format -msgid "wait: %s" -msgstr "" - -#: dlltool.c:1205 resrc.c:276 -#, c-format -msgid "subprocess got fatal signal %d" -msgstr "" - -#: dlltool.c:1211 -#, c-format -msgid "%s exited with status %d\n" -msgstr "" - -#: dlltool.c:1243 -#, c-format -msgid "Sucking in info from %s section in %s\n" -msgstr "" - -#: dlltool.c:1367 -#, c-format -msgid "Excluding symbol: %s\n" -msgstr "" - -#: dlltool.c:1462 dlltool.c:1473 nm.c:904 nm.c:915 objdump.c:444 objdump.c:461 -#, c-format -msgid "%s: no symbols\n" -msgstr "" - -#. FIXME: we ought to read in and block out the base relocations -#: dlltool.c:1500 -#, c-format -msgid "Done reading %s\n" -msgstr "" - -#: dlltool.c:1511 -#, c-format -msgid "Unable to open object file: %s" -msgstr "" - -#: dlltool.c:1514 -#, c-format -msgid "Scanning object file %s" -msgstr "" - -#: dlltool.c:1529 -#, c-format -msgid "Cannot produce mcore-elf dll from archive file: %s" -msgstr "" - -#: dlltool.c:1621 -msgid "Adding exports to output file" -msgstr "" - -#: dlltool.c:1666 -msgid "Added exports to output file" -msgstr "" - -#: dlltool.c:1790 -#, c-format -msgid "Generating export file: %s\n" -msgstr "" - -#: dlltool.c:1795 -#, c-format -msgid "Unable to open temporary assembler file: %s" -msgstr "" - -#: dlltool.c:1798 -#, c-format -msgid "Opened temporary file: %s" -msgstr "" - -#: dlltool.c:2012 -msgid "Generated exports file" -msgstr "" - -#: dlltool.c:2267 -#, c-format -msgid "bfd_open failed open stub file: %s" -msgstr "" - -#: dlltool.c:2270 -#, c-format -msgid "Creating stub file: %s" -msgstr "" - -#: dlltool.c:2657 -#, c-format -msgid "failed to open temporary head file: %s" -msgstr "" - -#: dlltool.c:2716 -#, c-format -msgid "failed to open temporary tail file: %s" -msgstr "" - -#: dlltool.c:2784 -#, c-format -msgid "Can't open .lib file: %s" -msgstr "" - -#: dlltool.c:2787 -#, c-format -msgid "Creating library file: %s\n" -msgstr "" - -#: dlltool.c:2846 -#, c-format -msgid "cannot delete %s: %s\n" -msgstr "" - -#: dlltool.c:2850 -msgid "Created lib file" -msgstr "" - -#: dlltool.c:2955 -#, c-format -msgid "Warning, ignoring duplicate EXPORT %s %d,%d\n" -msgstr "" - -#: dlltool.c:2961 -#, c-format -msgid "Error, duplicate EXPORT with oridinals: %s" -msgstr "" - -#: dlltool.c:3088 -msgid "Processing definitions" -msgstr "" - -#: dlltool.c:3126 -msgid "Processed definitions" -msgstr "" - -#. xgetext:c-format -#: dlltool.c:3137 -#, c-format -msgid "Usage %s <options> <object-files>\n" -msgstr "" - -#. xgetext:c-format -#: dlltool.c:3139 -#, c-format -msgid "" -" -m --machine <machine> Create as DLL for <machine>. [default: %s]\n" -msgstr "" - -#: dlltool.c:3140 -msgid "" -" possible <machine>: arm[_interwork], i386, mcore[-elf]{-le|-be}, " -"ppc, thumb\n" -msgstr "" - -#: dlltool.c:3141 -msgid " -e --output-exp <outname> Generate an export file.\n" -msgstr "" - -#: dlltool.c:3142 -msgid " -l --output-lib <outname> Generate an interface library.\n" -msgstr "" - -#: dlltool.c:3143 -msgid " -a --add-indirect Add dll indirects to export file.\n" -msgstr "" - -#: dlltool.c:3144 -msgid "" -" -D --dllname <name> Name of input dll to put into interface lib.\n" -msgstr "" - -#: dlltool.c:3145 -msgid " -d --input-def <deffile> Name of .def file to be read in.\n" -msgstr "" - -#: dlltool.c:3146 -msgid " -z --output-def <deffile> Name of .def file to be created.\n" -msgstr "" - -#: dlltool.c:3147 -msgid " --export-all-symbols Export all symbols to .def\n" -msgstr "" - -#: dlltool.c:3148 -msgid " --no-export-all-symbols Only export listed symbols\n" -msgstr "" - -#: dlltool.c:3149 -msgid " --exclude-symbols <list> Don't export <list>\n" -msgstr "" - -#: dlltool.c:3150 -msgid " --no-default-excludes Clear default exclude symbols\n" -msgstr "" - -#: dlltool.c:3151 -msgid " -b --base-file <basefile> Read linker generated base file.\n" -msgstr "" - -#: dlltool.c:3152 -msgid " -x --no-idata4 Don't generate idata$4 section.\n" -msgstr "" - -#: dlltool.c:3153 -msgid " -c --no-idata5 Don't generate idata$5 section.\n" -msgstr "" - -#: dlltool.c:3154 -msgid "" -" -U --add-underscore Add underscores to symbols in interface " -"library.\n" -msgstr "" - -#: dlltool.c:3155 -msgid " -k --kill-at Kill @<n> from exported names.\n" -msgstr "" - -#: dlltool.c:3156 -msgid " -A --add-stdcall-alias Add aliases without @<n>.\n" -msgstr "" - -#: dlltool.c:3157 -msgid " -S --as <name> Use <name> for assembler.\n" -msgstr "" - -#: dlltool.c:3158 -msgid " -f --as-flags <flags> Pass <flags> to the assembler.\n" -msgstr "" - -#: dlltool.c:3159 -msgid "" -" -C --compat-implib Create backward compatible import library.\n" -msgstr "" - -#: dlltool.c:3160 -msgid "" -" -n --no-delete Keep temp files (repeat for extra " -"preservation).\n" -msgstr "" - -#: dlltool.c:3161 -msgid " -v --verbose Be verbose.\n" -msgstr "" - -#: dlltool.c:3162 -msgid " -V --version Display the program version.\n" -msgstr "" - -#: dlltool.c:3163 -msgid " -h --help Display this information.\n" -msgstr "" - -#: dlltool.c:3165 -msgid "" -" -M --mcore-elf <outname> Process mcore-elf object files into <outname>.\n" -msgstr "" - -#: dlltool.c:3166 -msgid " -L --linker <name> Use <name> as the linker.\n" -msgstr "" - -#: dlltool.c:3167 -msgid " -F --linker-flags <flags> Pass <flags> to the linker.\n" -msgstr "" - -#: dlltool.c:3311 -#, c-format -msgid "Unable to open base-file: %s" -msgstr "" - -#: dlltool.c:3340 -#, c-format -msgid "Machine '%s' not supported" -msgstr "" - -#: dlltool.c:3443 dllwrap.c:215 -#, c-format -msgid "Tried file: %s" -msgstr "" - -#: dlltool.c:3450 dllwrap.c:222 -#, c-format -msgid "Using file: %s" -msgstr "" - -#: ieee.c:316 -msgid "unexpected end of debugging information" -msgstr "" - -#: ieee.c:411 -msgid "invalid number" -msgstr "" - -#: ieee.c:470 -msgid "invalid string length" -msgstr "" - -#: ieee.c:527 ieee.c:568 -msgid "expression stack overflow" -msgstr "" - -#: ieee.c:547 -msgid "unsupported IEEE expression operator" -msgstr "" - -#: ieee.c:562 -msgid "unknown section" -msgstr "" - -#: ieee.c:583 -msgid "expression stack underflow" -msgstr "" - -#: ieee.c:597 -msgid "expression stack mismatch" -msgstr "" - -#: ieee.c:636 -msgid "unknown builtin type" -msgstr "" - -#: ieee.c:781 -msgid "BCD float type not supported" -msgstr "" - -#: ieee.c:927 -msgid "unexpected number" -msgstr "" - -#: ieee.c:934 -msgid "unexpected record type" -msgstr "" - -#: ieee.c:967 -msgid "blocks left on stack at end" -msgstr "" - -#: ieee.c:1232 -msgid "unknown BB type" -msgstr "" - -#: ieee.c:1241 -msgid "stack overflow" -msgstr "" - -#: ieee.c:1266 -msgid "stack underflow" -msgstr "" - -#: ieee.c:1380 ieee.c:1452 ieee.c:2151 -msgid "illegal variable index" -msgstr "" - -#: ieee.c:1430 -msgid "illegal type index" -msgstr "" - -#: ieee.c:1440 ieee.c:1477 -msgid "unknown TY code" -msgstr "" - -#: ieee.c:1459 -msgid "undefined variable in TY" -msgstr "" - -#. Pascal file name. FIXME. -#: ieee.c:1870 -msgid "Pascal file name not supported" -msgstr "" - -#: ieee.c:1918 -msgid "unsupported qualifer" -msgstr "" - -#: ieee.c:2189 -msgid "undefined variable in ATN" -msgstr "" - -#: ieee.c:2232 -msgid "unknown ATN type" -msgstr "" - -#. Reserved for FORTRAN common. -#: ieee.c:2354 -msgid "unsupported ATN11" -msgstr "" - -#. We have no way to record this information. FIXME. -#: ieee.c:2381 -msgid "unsupported ATN12" -msgstr "" - -#: ieee.c:2441 -msgid "unexpected string in C++ misc" -msgstr "" - -#: ieee.c:2454 -msgid "bad misc record" -msgstr "" - -#: ieee.c:2497 -msgid "unrecognized C++ misc record" -msgstr "" - -#: ieee.c:2614 -msgid "undefined C++ object" -msgstr "" - -#: ieee.c:2648 -msgid "unrecognized C++ object spec" -msgstr "" - -#: ieee.c:2684 -msgid "unsupported C++ object type" -msgstr "" - -#: ieee.c:2694 -msgid "C++ base class not defined" -msgstr "" - -#: ieee.c:2706 ieee.c:2811 -msgid "C++ object has no fields" -msgstr "" - -#: ieee.c:2725 -msgid "C++ base class not found in container" -msgstr "" - -#: ieee.c:2832 -msgid "C++ data member not found in container" -msgstr "" - -#: ieee.c:2873 ieee.c:3023 -msgid "unknown C++ visibility" -msgstr "" - -#: ieee.c:2907 -msgid "bad C++ field bit pos or size" -msgstr "" - -#: ieee.c:2999 -msgid "bad type for C++ method function" -msgstr "" - -#: ieee.c:3009 -msgid "no type information for C++ method function" -msgstr "" - -#: ieee.c:3048 -msgid "C++ static virtual method" -msgstr "" - -#: ieee.c:3143 -msgid "unrecognized C++ object overhead spec" -msgstr "" - -#: ieee.c:3182 -msgid "undefined C++ vtable" -msgstr "" - -#: ieee.c:3253 -msgid "C++ default values not in a function" -msgstr "" - -#: ieee.c:3293 -msgid "unrecognized C++ default type" -msgstr "" - -#: ieee.c:3324 -msgid "reference parameter is not a pointer" -msgstr "" - -#: ieee.c:3409 -msgid "unrecognized C++ reference type" -msgstr "" - -#: ieee.c:3491 -msgid "C++ reference not found" -msgstr "" - -#: ieee.c:3499 -msgid "C++ reference is not pointer" -msgstr "" - -#: ieee.c:3528 ieee.c:3536 -msgid "missing required ASN" -msgstr "" - -#: ieee.c:3566 ieee.c:3574 -msgid "missing required ATN65" -msgstr "" - -#: ieee.c:3588 -msgid "bad ATN65 record" -msgstr "" - -#: ieee.c:4235 -msgid "IEEE numeric overflow: 0x" -msgstr "" - -#: ieee.c:4281 -#, c-format -msgid "IEEE string length overflow: %u\n" -msgstr "" - -#: ieee.c:5315 -#, c-format -msgid "IEEE unsupported integer type size %u\n" -msgstr "" - -#: ieee.c:5351 -#, c-format -msgid "IEEE unsupported float type size %u\n" -msgstr "" - -#: ieee.c:5387 -#, c-format -msgid "IEEE unsupported complex type size %u\n" -msgstr "" - -#: nlmconv.c:275 srconv.c:1966 -#, c-format -msgid "%s: input and output files must be different\n" -msgstr "" - -#: nlmconv.c:325 -#, c-format -msgid "%s: input file named both on command line and with INPUT\n" -msgstr "" - -#: nlmconv.c:336 -#, c-format -msgid "%s: no input file\n" -msgstr "" - -#: nlmconv.c:366 -#, c-format -msgid "%s: no name for output file\n" -msgstr "" - -#: nlmconv.c:381 -#, c-format -msgid "%s: warning:input and output formats are not compatible\n" -msgstr "" - -#: nlmconv.c:411 -msgid "make .bss section" -msgstr "" - -#: nlmconv.c:420 -msgid "make .nlmsections section" -msgstr "" - -#: nlmconv.c:422 -msgid "set .nlmsections flags" -msgstr "" - -#: nlmconv.c:450 -msgid "set .bss vma" -msgstr "" - -#: nlmconv.c:457 -msgid "set .data size" -msgstr "" - -#: nlmconv.c:638 -#, c-format -msgid "%s: warning: symbol %s imported but not in import list\n" -msgstr "" - -#: nlmconv.c:658 -msgid "set start address" -msgstr "" - -#: nlmconv.c:707 -#, c-format -msgid "%s: warning: START procedure %s not defined\n" -msgstr "" - -#: nlmconv.c:710 -#, c-format -msgid "%s: warning: EXIT procedure %s not defined\n" -msgstr "" - -#: nlmconv.c:714 -#, c-format -msgid "%s: warning: CHECK procedure %s not defined\n" -msgstr "" - -#: nlmconv.c:736 nlmconv.c:928 -msgid "custom section" -msgstr "" - -#: nlmconv.c:757 nlmconv.c:960 -msgid "help section" -msgstr "" - -#: nlmconv.c:779 nlmconv.c:979 -msgid "message section" -msgstr "" - -#: nlmconv.c:795 nlmconv.c:1012 -msgid "module section" -msgstr "" - -#: nlmconv.c:815 nlmconv.c:1029 -msgid "rpc section" -msgstr "" - -#: nlmconv.c:852 -#, c-format -msgid "%s:%s: warning: shared libraries can not have uninitialized data\n" -msgstr "" - -#: nlmconv.c:873 nlmconv.c:1049 -msgid "shared section" -msgstr "" - -#: nlmconv.c:881 -#, c-format -msgid "%s: warning: No version number given\n" -msgstr "" - -#: nlmconv.c:922 nlmconv.c:954 nlmconv.c:973 nlmconv.c:1023 nlmconv.c:1043 -#, c-format -msgid "%s:%s: read: %s\n" -msgstr "" - -#: nlmconv.c:946 -#, c-format -msgid "%s: warning: MAP and FULLMAP are not supported; try ld -M\n" -msgstr "" - -#: nlmconv.c:1121 -#, c-format -msgid "%s: Convert an object file into a NetWare Loadable Module\n" -msgstr "" - -#: nlmconv.c:1133 -#, c-format -msgid "" -"Usage: %s [-dhV] [-I bfdname] [-O bfdname] [-T header-file] [-l linker]\n" -" [--input-target=bfdname] [--output-target=bfdname]\n" -" [--header-file=file] [--linker=linker] [--debug]\n" -" [--help] [--version]\n" -" [in-file [out-file]]\n" -msgstr "" - -#: nlmconv.c:1173 -#, c-format -msgid "%s: support not compiled in for %s\n" -msgstr "" - -#: nlmconv.c:1216 -msgid "make section" -msgstr "" - -#: nlmconv.c:1230 -msgid "set section size" -msgstr "" - -#: nlmconv.c:1236 -msgid "set section alignment" -msgstr "" - -#: nlmconv.c:1240 -msgid "set section flags" -msgstr "" - -#: nlmconv.c:1251 -msgid "set .nlmsections size" -msgstr "" - -#: nlmconv.c:1339 nlmconv.c:1347 nlmconv.c:1356 nlmconv.c:1361 -msgid "set .nlmsection contents" -msgstr "" - -#: nlmconv.c:1864 -msgid "stub section sizes" -msgstr "" - -#: nlmconv.c:1913 -msgid "writing stub" -msgstr "" - -#: nlmconv.c:2003 -#, c-format -msgid "%s: unresolved PC relative reloc against %s\n" -msgstr "" - -#: nlmconv.c:2068 -#, c-format -msgid "%s: overflow when adjusting relocation against %s\n" -msgstr "" - -#: nlmconv.c:2191 -#, c-format -msgid "%s: execution of %s failed: " -msgstr "" - -#: nlmconv.c:2206 -#, c-format -msgid "%s: Execution of %s failed\n" -msgstr "" - -#: nm.c:294 -#, c-format -msgid "" -"Usage: %s [-aABCDglnopPrsuvV] [-t radix] [--radix=radix] [--target=bfdname]\n" -" [--debug-syms] [--extern-only] [--print-armap] [--print-file-name]\n" -" [--numeric-sort] [--no-sort] [--reverse-sort] [--size-sort]\n" -" [--undefined-only] [--portability] [-f {bsd,sysv,posix}]\n" -" [--format={bsd,sysv,posix}] [--demangle] [--no-demangle] [--dynamic]\n" -" [--defined-only] [--line-numbers]\n" -" [--version] [--help]\n" -" [file...]\n" -msgstr "" - -#: nm.c:339 -#, c-format -msgid "%s: %s: invalid radix\n" -msgstr "" - -#: nm.c:365 -#, c-format -msgid "%s: %s: invalid output format\n" -msgstr "" - -#: nm.c:492 -#, c-format -msgid "%s: data size %ld\n" -msgstr "" - -#: nm.c:1283 -#, c-format -msgid "" -"\n" -"\n" -"Undefined symbols from %s:\n" -"\n" -msgstr "" - -#: nm.c:1285 -#, c-format -msgid "" -"\n" -"\n" -"Symbols from %s:\n" -"\n" -msgstr "" - -#: nm.c:1286 nm.c:1340 -msgid "" -"Name Value Class Type Size Line " -"Section\n" -"\n" -msgstr "" - -#: nm.c:1337 -#, c-format -msgid "" -"\n" -"\n" -"Undefined symbols from %s[%s]:\n" -"\n" -msgstr "" - -#: nm.c:1339 -#, c-format -msgid "" -"\n" -"\n" -"Symbols from %s[%s]:\n" -"\n" -msgstr "" - -#: nm.c:1510 -msgid "" -"\n" -"Archive index:\n" -msgstr "" - -#: objcopy.c:309 -#, c-format -msgid "Usage: %s <switches> in-file [out-file]\n" -msgstr "" - -#: objcopy.c:310 objcopy.c:368 -msgid " The switches are:\n" -msgstr "" - -#: objcopy.c:311 -msgid "" -" -I --input-target <bfdname> Assume input file is in format <bfdname>\n" -" -O --output-target <bfdname> Create an output file in format " -"<bfdname>\n" -" -F --target <bfdname> Set both input and output format to " -"<bfdname>\n" -" --debugging Convert debugging information, if " -"possible\n" -" -p --preserve-dates Copy modified/access timestamps to the " -"output\n" -" -j --only-section <name> Only copy section <name> into the output\n" -" -R --remove-section <name> Remove section <name> from the output\n" -" -S --strip-all Remove all symbol and relocation " -"information\n" -" -g --strip-debug Remove all debugging symbols\n" -" --strip-unneeded Remove all symbols not needed by " -"relocations\n" -" -N --strip-symbol <name> Do not copy symbol <name>\n" -" -K --keep-symbol <name> Only copy symbol <name>\n" -" -L --localize-symbol <name> Force symbol <name> to be marked as a " -"local\n" -" -W --weaken-symbol <name> Force symbol <name> to be marked as a " -"weak\n" -" --weaken Force all global symbols to be marked as " -"weak\n" -" -x --discard-all Remove all non-global symbols\n" -" -X --discard-locals Remove any compiler-generated symbols\n" -" -i --interleave <number> Only copy one out of every <number> " -"bytes\n" -" -b --byte <num> Select byte <num> in every interleaved " -"block\n" -" --gap-fill <val> Fill gaps between sections with <val>\n" -" --pad-to <addr> Pad the last section up to address " -"<addr>\n" -" --set-start <addr> Set the start address to <addr>\n" -" {--change-start|--adjust-start} <incr>\n" -" Add <incr> to the start address\n" -" {--change-addresses|--adjust-vma} <incr>\n" -" Add <incr> to LMA, VMA and start " -"addresses\n" -" {--change-section-address|--adjust-section-vma} <name>{=|+|-}<val>\n" -" Change LMA and VMA of section <name> by " -"<val>\n" -" --change-section-lma <name>{=|+|-}<val>\n" -" Change the LMA of section <name> by " -"<val>\n" -" --change-section-vma <name>{=|+|-}<val>\n" -" Change the VMA of section <name> by " -"<val>\n" -" {--[no-]change-warnings|--[no-]adjust-warnings}\n" -" Warn if a named section does not exist\n" -" --set-section-flags <name>=<flags>\n" -" Set section <name>'s properties to " -"<flags>\n" -" --add-section <name>=<file> Add section <name> found in <file> to " -"output\n" -" --change-leading-char Force output format's leading character " -"style\n" -" --remove-leading-char Remove leading character from global " -"symbols\n" -" --redefine-sym <old>=<new> Redefine symbol name <old> to <new>\n" -" -v --verbose List all object files modified\n" -" -V --version Display this program's version number\n" -" -h --help Display this output\n" -msgstr "" - -#: objcopy.c:367 -#, c-format -msgid "Usage: %s <switches> in-file(s)\n" -msgstr "" - -#: objcopy.c:369 -msgid "" -" -I --input-target <bfdname> Assume input file is in format <bfdname>\n" -" -O --output-target <bfdname> Create an output file in format " -"<bfdname>\n" -" -F --target <bfdname> Set both input and output format to " -"<bfdname>\n" -" -p --preserve-dates Copy modified/access timestamps to the " -"output\n" -" -R --remove-section <name> Remove section <name> from the output\n" -" -s --strip-all Remove all symbol and relocation " -"information\n" -" -g -S --strip-debug Remove all debugging symbols\n" -" --strip-unneeded Remove all symbols not needed by " -"relocations\n" -" -N --strip-symbol <name> Do not copy symbol <name>\n" -" -K --keep-symbol <name> Only copy symbol <name>\n" -" -x --discard-all Remove all non-global symbols\n" -" -X --discard-locals Remove any compiler-generated symbols\n" -" -v --verbose List all object files modified\n" -" -V --version Display this program's version number\n" -" -h --help Display this output\n" -" -o <file> Place stripped output into <file>\n" -msgstr "" - -#: objcopy.c:439 -#, c-format -msgid "unrecognized section flag `%s'" -msgstr "" - -#: objcopy.c:440 -#, c-format -msgid "supported flags: %s" -msgstr "" - -#: objcopy.c:692 -#, c-format -msgid "%s: Multiple redefinition of symbol \"%s\"" -msgstr "" - -#: objcopy.c:699 -#, c-format -msgid "%s: Symbol \"%s\" is target of more than one redefinition" -msgstr "" - -#: objcopy.c:753 -#, c-format -msgid "copy from %s(%s) to %s(%s)\n" -msgstr "" - -#: objcopy.c:772 -#, c-format -msgid "Warning: Output file cannot represent architecture %s" -msgstr "" - -#: objcopy.c:799 -#, c-format -msgid "can't create section `%s': %s" -msgstr "" - -#: objcopy.c:885 -#, c-format -msgid "Can't fill gap after %s: %s" -msgstr "" - -#: objcopy.c:910 -#, c-format -msgid "Can't add padding to %s: %s" -msgstr "" - -#: objcopy.c:1048 -#, c-format -msgid "%s: error copying private BFD data: %s" -msgstr "" - -#: objcopy.c:1082 -#, c-format -msgid "cannot mkdir %s for archive copying (error: %s)" -msgstr "" - -#: objcopy.c:1351 -#, c-format -msgid "%s: section `%s': error in %s: %s" -msgstr "" - -#: objcopy.c:1625 -#, c-format -msgid "%s: can't create debugging section: %s" -msgstr "" - -#: objcopy.c:1640 -#, c-format -msgid "%s: can't set debugging section contents: %s" -msgstr "" - -#: objcopy.c:1649 -#, c-format -msgid "%s: don't know how to write debugging information for %s" -msgstr "" - -#: objcopy.c:1754 -#, c-format -msgid "%s: cannot stat: %s" -msgstr "" - -#: objcopy.c:1804 -msgid "byte number must be non-negative" -msgstr "" - -#: objcopy.c:1810 -msgid "interleave must be positive" -msgstr "" - -#: objcopy.c:1830 objcopy.c:1838 -#, c-format -msgid "%s both copied and removed" -msgstr "" - -#: objcopy.c:1907 objcopy.c:1977 objcopy.c:2078 objcopy.c:2106 -#, c-format -msgid "bad format for %s" -msgstr "" - -#: objcopy.c:1910 -#, c-format -msgid "cannot stat: %s: %s" -msgstr "" - -#: objcopy.c:1928 -#, c-format -msgid "cannot open: %s: %s" -msgstr "" - -#: objcopy.c:1932 -#, c-format -msgid "%s: fread failed" -msgstr "" - -#: objcopy.c:2046 -#, c-format -msgid "Warning: truncating gap-fill from 0x%s to 0x%x" -msgstr "" - -#: objcopy.c:2140 -msgid "byte number must be less than interleave" -msgstr "" - -#: objcopy.c:2159 -#, c-format -msgid "Cannot stat: %s: %s" -msgstr "" - -#: objcopy.c:2199 objcopy.c:2213 -#, c-format -msgid "%s %s%c0x%s never used" -msgstr "" - -#: objdump.c:229 -#, c-format -msgid "Usage: %s <switches> file(s)\n" -msgstr "" - -#: objdump.c:230 -msgid " At least one of the following switches must be given:\n" -msgstr "" - -#: objdump.c:231 -msgid "" -" -a --archive-headers Display archive header information\n" -" -f --file-headers Display the contents of the overall file header\n" -" -p --private-headers Display object format specific file header " -"contents\n" -" -h --[section-]headers Display the contents of the section headers\n" -" -x --all-headers Display the contents of all headers\n" -" -d --disassemble Display assembler contents of executable " -"sections\n" -" -D --disassemble-all Display assembler contents of all sections\n" -" -S --source Intermix source code with disassembly\n" -" -s --full-contents Display the full contents of all sections " -"requested\n" -" -g --debugging Display debug information in object file\n" -" -G --stabs Display the STABS contents of an ELF format file\n" -" -t --syms Display the contents of the symbol table(s)\n" -" -T --dynamic-syms Display the contents of the dynamic symbol table\n" -" -r --reloc Display the relocation entries in the file\n" -" -R --dynamic-reloc Display the dynamic relocation entries in the " -"file\n" -" -V --version Display this program's version number\n" -" -i --info List object formats and architectures supported\n" -" -H --help Display this information\n" -msgstr "" - -#: objdump.c:253 -msgid "" -"\n" -" The following switches are optional:\n" -msgstr "" - -#: objdump.c:254 -msgid "" -" -b --target <bfdname> Specify the target object format as " -"<bfdname>\n" -" -m --architecture <machine> Specify the target architecture as " -"<machine>\n" -" -j --section <name> Only display information for section " -"<name>\n" -" -M --disassembler-options <o> Pass text <o> on to the disassembler\n" -" -EB --endian=big Assume big endian format when " -"disassembling\n" -" -EL --endian=little Assume little endian format when " -"disassembling\n" -" --file-start-context Include context from start of file (with " -"-S)\n" -" -l --line-numbers Include line numbers and filenames in " -"output\n" -" -C --demangle Decode mangled/processed symbol names\n" -" -w --wide Format output for more than 80 columns\n" -" -z --disassemble-zeroes Do not skip blocks of zeroes when " -"disassembling\n" -" --start-address <addr> Only process data whoes address is >= " -"<addr>\n" -" --stop-address <addr> Only process data whoes address is <= " -"<addr>\n" -" --prefix-addresses Print complete address alongside " -"disassembly\n" -" --[no-]show-raw-insn Display hex alongside symbolic disassembly\n" -" --adjust-vma <offset> Add <offset> to all displayed section " -"addresses\n" -"\n" -msgstr "" - -#: objdump.c:420 -msgid "Sections:\n" -msgstr "" - -#: objdump.c:423 -msgid "Idx Name Size VMA LMA File off Algn" -msgstr "" - -#: objdump.c:425 -msgid "" -"Idx Name Size VMA LMA File off " -"Algn" -msgstr "" - -#: objdump.c:429 -msgid " Flags" -msgstr "" - -#: objdump.c:479 -#, c-format -msgid "%s: %s: not a dynamic object\n" -msgstr "" - -#: objdump.c:496 -#, c-format -msgid "%s: %s: No dynamic symbols\n" -msgstr "" - -#: objdump.c:1200 -msgid "Out of virtual memory\n" -msgstr "" - -#: objdump.c:1611 -#, c-format -msgid "%s: Can't use supplied machine %s\n" -msgstr "" - -#: objdump.c:1632 -#, c-format -msgid "%s: Can't disassemble for architecture %s\n" -msgstr "" - -#: objdump.c:1709 -#, c-format -msgid "Disassembly of section %s:\n" -msgstr "" - -#: objdump.c:1883 -#, c-format -msgid "" -"No %s section present\n" -"\n" -msgstr "" - -#: objdump.c:1890 -#, c-format -msgid "%s: %s has no %s section\n" -msgstr "" - -#: objdump.c:1904 objdump.c:1916 -#, c-format -msgid "%s: Reading %s section of %s failed: %s\n" -msgstr "" - -#: objdump.c:1959 -#, c-format -msgid "" -"Contents of %s section:\n" -"\n" -msgstr "" - -#: objdump.c:2059 -#, c-format -msgid "architecture: %s, " -msgstr "" - -#: objdump.c:2062 -#, c-format -msgid "flags 0x%08x:\n" -msgstr "" - -#: objdump.c:2075 -msgid "" -"\n" -"start address 0x" -msgstr "" - -#: objdump.c:2107 -#, c-format -msgid "" -"\n" -"%s: file format %s\n" -msgstr "" - -#: objdump.c:2150 -#, c-format -msgid "%s: printing debugging information failed\n" -msgstr "" - -#: objdump.c:2227 -#, c-format -msgid "In archive %s:\n" -msgstr "" - -#: objdump.c:2279 -#, c-format -msgid "Contents of section %s:\n" -msgstr "" - -#: objdump.c:2788 -#, c-format -msgid "BFD header file version %s\n" -msgstr "" - -#: objdump.c:2861 -#, c-format -msgid "%s: unrecognized -E option\n" -msgstr "" - -#: objdump.c:2873 -#, c-format -msgid "%s: unrecognized --endian type `%s'\n" -msgstr "" - -#: rdcoff.c:204 -#, c-format -msgid "%s: parse_coff_type: Bad type code 0x%x\n" -msgstr "" - -#: rdcoff.c:423 rdcoff.c:531 rdcoff.c:712 -#, c-format -msgid "%s: bfd_coff_get_syment failed: %s\n" -msgstr "" - -#: rdcoff.c:439 rdcoff.c:732 -#, c-format -msgid "%s: bfd_coff_get_auxent failed: %s\n" -msgstr "" - -#: rdcoff.c:798 -#, c-format -msgid "%s: %ld: .bf without preceding function\n" -msgstr "" - -#: rdcoff.c:848 -#, c-format -msgid "%s: %ld: unexpected .ef\n" -msgstr "" - -#: rddbg.c:87 -#, c-format -msgid "%s: no recognized debugging information\n" -msgstr "" - -#: rddbg.c:410 -msgid "Last stabs entries before error:\n" -msgstr "" - -#: readelf.c:303 readelf.c:329 -#, c-format -msgid "%s: Error: " -msgstr "" - -#: readelf.c:315 readelf.c:344 -#, c-format -msgid "%s: Warning: " -msgstr "" - -#: readelf.c:394 readelf.c:532 -#, c-format -msgid "Unhandled data length: %d\n" -msgstr "" - -#: readelf.c:591 -msgid "Don't know about relocations on this machine architecture\n" -msgstr "" - -#: readelf.c:631 readelf.c:660 readelf.c:692 readelf.c:720 -msgid "out of memory parsing relocs" -msgstr "" - -#: readelf.c:738 -msgid "" -" Offset Info Type Symbol's Value Symbol's Name " -"Addend\n" -msgstr "" - -#: readelf.c:741 -msgid " Offset Info Type Symbol's Value Symbol's Name\n" -msgstr "" - -#: readelf.c:885 readelf.c:887 -#, c-format -msgid "unrecognised: %-7lx" -msgstr "" - -#: readelf.c:912 -#, c-format -msgid "<string table index %3ld>" -msgstr "" - -#: readelf.c:1119 -#, c-format -msgid "Processor Specific: %lx" -msgstr "" - -#: readelf.c:1138 -#, c-format -msgid "Operating System specific: %lx" -msgstr "" - -#: readelf.c:1141 readelf.c:1506 -#, c-format -msgid "<unknown>: %lx" -msgstr "" - -#: readelf.c:1155 -msgid "NONE (None)" -msgstr "" - -#: readelf.c:1156 -msgid "REL (Relocatable file)" -msgstr "" - -#: readelf.c:1157 -msgid "EXEC (Executable file)" -msgstr "" - -#: readelf.c:1158 -msgid "DYN (Shared object file)" -msgstr "" - -#: readelf.c:1159 -msgid "CORE (Core file)" -msgstr "" - -#: readelf.c:1163 -#, c-format -msgid "Processor Specific: (%x)" -msgstr "" - -#: readelf.c:1165 -#, c-format -msgid "OS Specific: (%x)" -msgstr "" - -#: readelf.c:1167 readelf.c:1244 readelf.c:1638 -#, c-format -msgid "<unknown>: %x" -msgstr "" - -#: readelf.c:1180 -msgid "None" -msgstr "" - -#: readelf.c:1676 -msgid "Usage: readelf {options} elf-file(s)\n" -msgstr "" - -#: readelf.c:1677 -msgid " Options are:\n" -msgstr "" - -#: readelf.c:1678 -msgid " -a or --all Equivalent to: -h -l -S -s -r -d -V -A -I\n" -msgstr "" - -#: readelf.c:1679 -msgid " -h or --file-header Display the ELF file header\n" -msgstr "" - -#: readelf.c:1680 -msgid " -l or --program-headers or --segments\n" -msgstr "" - -#: readelf.c:1681 -msgid " Display the program headers\n" -msgstr "" - -#: readelf.c:1682 -msgid " -S or --section-headers or --sections\n" -msgstr "" - -#: readelf.c:1683 -msgid " Display the sections' header\n" -msgstr "" - -#: readelf.c:1684 -msgid " -e or --headers Equivalent to: -h -l -S\n" -msgstr "" - -#: readelf.c:1685 -msgid " -s or --syms or --symbols Display the symbol table\n" -msgstr "" - -#: readelf.c:1686 -msgid " -n or --notes Display the core notes (if present)\n" -msgstr "" - -#: readelf.c:1687 -msgid " -r or --relocs Display the relocations (if present)\n" -msgstr "" - -#: readelf.c:1688 -msgid " -d or --dynamic Display the dynamic segment (if present)\n" -msgstr "" - -#: readelf.c:1689 -msgid " -V or --version-info Display the version sections (if present)\n" -msgstr "" - -#: readelf.c:1690 -msgid "" -" -A or --arch-specific Display architecture specific information (if " -"any).\n" -msgstr "" - -#: readelf.c:1691 -msgid "" -" -D or --use-dynamic Use the dynamic section info when displaying " -"symbols\n" -msgstr "" - -#: readelf.c:1692 -msgid " -x <number> or --hex-dump=<number>\n" -msgstr "" - -#: readelf.c:1693 -msgid " Dump the contents of section <number>\n" -msgstr "" - -#: readelf.c:1694 -msgid " -w[liapr] or --debug-dump[=line,=info,=abbrev,=pubnames,=ranges]\n" -msgstr "" - -#: readelf.c:1695 -msgid "" -" Display the contents of DWARF2 debug sections\n" -msgstr "" - -#: readelf.c:1697 -msgid " -i <number> or --instruction-dump=<number>\n" -msgstr "" - -#: readelf.c:1698 -msgid "" -" Disassemble the contents of section <number>\n" -msgstr "" - -#: readelf.c:1700 -msgid " -I or --histogram Display histogram of bucket list lengths\n" -msgstr "" - -#: readelf.c:1701 -msgid " -v or --version Display the version number of readelf\n" -msgstr "" - -#: readelf.c:1702 -msgid " -H or --help Display this information\n" -msgstr "" - -#: readelf.c:1720 -msgid "Out of memory allocating dump request table." -msgstr "" - -#: readelf.c:1855 -#, c-format -msgid "Unrecognised debug option '%s'\n" -msgstr "" - -#: readelf.c:1880 -#, c-format -msgid "Invalid option '-%c'\n" -msgstr "" - -#: readelf.c:1893 -msgid "Nothing to do.\n" -msgstr "" - -#: readelf.c:1906 readelf.c:1923 readelf.c:3493 -msgid "none" -msgstr "" - -#: readelf.c:1907 -msgid "ELF32" -msgstr "" - -#: readelf.c:1908 -msgid "ELF64" -msgstr "" - -#: readelf.c:1910 readelf.c:1927 readelf.c:1946 -#, c-format -msgid "<unknown: %x>" -msgstr "" - -#: readelf.c:1924 -msgid "2's complement, little endian" -msgstr "" - -#: readelf.c:1925 -msgid "2's complement, big endian" -msgstr "" - -#: readelf.c:1940 -msgid "UNIX - System V" -msgstr "" - -#: readelf.c:1941 -msgid "UNIX - HP-UX" -msgstr "" - -#: readelf.c:1942 -msgid "UNIX - Linux" -msgstr "" - -#: readelf.c:1943 -msgid "Standalone App" -msgstr "" - -#: readelf.c:1944 -msgid "ARM" -msgstr "" - -#: readelf.c:1961 -msgid "Not an ELF file - it has the wrong magic bytes at the start\n" -msgstr "" - -#: readelf.c:1969 -msgid "ELF Header:\n" -msgstr "" - -#: readelf.c:1970 -msgid " Magic: " -msgstr "" - -#: readelf.c:1974 -#, c-format -msgid " Class: %s\n" -msgstr "" - -#: readelf.c:1976 -#, c-format -msgid " Data: %s\n" -msgstr "" - -#: readelf.c:1978 -#, c-format -msgid " Version: %d %s\n" -msgstr "" - -#: readelf.c:1985 -#, c-format -msgid " OS/ABI: %s\n" -msgstr "" - -#: readelf.c:1987 -#, c-format -msgid " ABI Version: %d\n" -msgstr "" - -#: readelf.c:1989 -#, c-format -msgid " Type: %s\n" -msgstr "" - -#: readelf.c:1991 -#, c-format -msgid " Machine: %s\n" -msgstr "" - -#: readelf.c:1993 -#, c-format -msgid " Version: 0x%lx\n" -msgstr "" - -#: readelf.c:1996 -msgid " Entry point address: " -msgstr "" - -#: readelf.c:1998 -msgid "" -"\n" -" Start of program headers: " -msgstr "" - -#: readelf.c:2000 -msgid "" -" (bytes into file)\n" -" Start of section headers: " -msgstr "" - -#: readelf.c:2002 -msgid " (bytes into file)\n" -msgstr "" - -#: readelf.c:2004 -#, c-format -msgid " Flags: 0x%lx%s\n" -msgstr "" - -#: readelf.c:2007 -#, c-format -msgid " Size of this header: %ld (bytes)\n" -msgstr "" - -#: readelf.c:2009 -#, c-format -msgid " Size of program headers: %ld (bytes)\n" -msgstr "" - -#: readelf.c:2011 -#, c-format -msgid " Number of program headers: %ld\n" -msgstr "" - -#: readelf.c:2013 -#, c-format -msgid " Size of section headers: %ld (bytes)\n" -msgstr "" - -#: readelf.c:2015 -#, c-format -msgid " Number of section headers: %ld\n" -msgstr "" - -#: readelf.c:2017 -#, c-format -msgid " Section header string table index: %ld\n" -msgstr "" - -#: readelf.c:2102 -msgid "" -"\n" -"There are no program headers in this file.\n" -msgstr "" - -#: readelf.c:2108 -#, c-format -msgid "" -"\n" -"Elf file type is %s\n" -msgstr "" - -#: readelf.c:2109 -msgid "Entry point " -msgstr "" - -#: readelf.c:2111 -#, c-format -msgid "" -"\n" -"There are %d program headers, starting at offset " -msgstr "" - -#: readelf.c:2122 readelf.c:2298 readelf.c:2340 readelf.c:2383 readelf.c:2424 -#: readelf.c:2932 readelf.c:2973 readelf.c:3149 readelf.c:4111 readelf.c:4125 -#: readelf.c:7023 readelf.c:7063 -msgid "Out of memory\n" -msgstr "" - -#: readelf.c:2140 -#, c-format -msgid "" -"\n" -"Program Header%s:\n" -msgstr "" - -#: readelf.c:2144 -msgid "" -" Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align\n" -msgstr "" - -#: readelf.c:2148 -msgid " Type Offset VirtAddr PhysAddr\n" -msgstr "" - -#: readelf.c:2150 -msgid " FileSiz MemSiz Flags Align\n" -msgstr "" - -#: readelf.c:2208 -msgid "more than one dynamic segment\n" -msgstr "" - -#: readelf.c:2216 -msgid "Unable to find program interpreter name\n" -msgstr "" - -#: readelf.c:2223 -#, c-format -msgid "" -"\n" -" [Requesting program interpreter: %s]" -msgstr "" - -#: readelf.c:2241 -msgid "" -"\n" -" Section to Segment mapping:\n" -msgstr "" - -#: readelf.c:2242 -msgid " Segment Sections...\n" -msgstr "" - -#: readelf.c:2505 -msgid "" -"\n" -"There are no sections in this file.\n" -msgstr "" - -#: readelf.c:2511 -#, c-format -msgid "There are %d section headers, starting at offset 0x%lx:\n" -msgstr "" - -#: readelf.c:2551 -msgid "File contains multiple dynamic symbol tables\n" -msgstr "" - -#: readelf.c:2564 -msgid "File contains multiple dynamic string tables\n" -msgstr "" - -#: readelf.c:2591 -#, c-format -msgid "" -"\n" -"Section Header%s:\n" -msgstr "" - -#: readelf.c:2595 -msgid "" -" [Nr] Name Type Addr Off Size ES Flg Lk " -"Inf Al\n" -msgstr "" - -#: readelf.c:2598 -msgid " [Nr] Name Type Address Offset\n" -msgstr "" - -#: readelf.c:2599 -msgid " Size EntSize Flags Link Info Align\n" -msgstr "" - -#: readelf.c:2646 -msgid "" -"Key to Flags: W (write), A (alloc), X (execute), M (merge), S (strings)\n" -msgstr "" - -#: readelf.c:2647 -msgid "" -" I (info), L (link order), O (extra OS processing required)\n" -msgstr "" - -#: readelf.c:2648 -msgid " o (os specific), p (processor specific) x (unknown)\n" -msgstr "" - -#: readelf.c:2706 -#, c-format -msgid "" -"\n" -"Relocation section at offset 0x%lx contains %ld bytes:\n" -msgstr "" - -#: readelf.c:2713 -msgid "" -"\n" -"There are no dynamic relocations in this file.\n" -msgstr "" - -#: readelf.c:2741 -msgid "" -"\n" -"Relocation section " -msgstr "" - -#: readelf.c:2748 -#, c-format -msgid " at offset 0x%lx contains %lu entries:\n" -msgstr "" - -#: readelf.c:2776 -msgid "" -"\n" -"There are no relocations in this file.\n" -msgstr "" - -#: readelf.c:3026 -msgid "" -"\n" -"There is no dynamic segment in this file.\n" -msgstr "" - -#: readelf.c:3060 -msgid "Unable to seek to end of file!" -msgstr "" - -#: readelf.c:3069 -msgid "Unable to determine the number of symbols to load\n" -msgstr "" - -#: readelf.c:3099 -msgid "Unable to seek to end of file\n" -msgstr "" - -#: readelf.c:3105 -msgid "Unable to determine the length of the dynamic string table\n" -msgstr "" - -#: readelf.c:3166 -#, c-format -msgid "" -"\n" -"Dynamic segment at offset 0x%x contains %ld entries:\n" -msgstr "" - -#: readelf.c:3169 -msgid " Tag Type Name/Value\n" -msgstr "" - -#: readelf.c:3200 -msgid "Auxiliary library" -msgstr "" - -#: readelf.c:3202 -msgid "Filter library" -msgstr "" - -#: readelf.c:3218 readelf.c:3239 readelf.c:3265 -msgid "Flags:" -msgstr "" - -#: readelf.c:3220 readelf.c:3241 readelf.c:3267 -msgid " None\n" -msgstr "" - -#: readelf.c:3370 -#, c-format -msgid "Shared library: [%s]" -msgstr "" - -#: readelf.c:3373 -msgid " program interpreter" -msgstr "" - -#: readelf.c:3377 -#, c-format -msgid "Library soname: [%s]" -msgstr "" - -#: readelf.c:3381 -#, c-format -msgid "Library rpath: [%s]" -msgstr "" - -#: readelf.c:3442 -#, c-format -msgid "Not needed object: [%s]\n" -msgstr "" - -#: readelf.c:3539 -#, c-format -msgid "" -"\n" -"Version definition section '%s' contains %ld entries:\n" -msgstr "" - -#: readelf.c:3542 -msgid " Addr: 0x" -msgstr "" - -#: readelf.c:3544 readelf.c:3732 -#, c-format -msgid " Offset: %#08lx Link: %lx (%s)\n" -msgstr "" - -#: readelf.c:3574 -#, c-format -msgid " %#06x: Rev: %d Flags: %s" -msgstr "" - -#: readelf.c:3577 -#, c-format -msgid " Index: %d Cnt: %d " -msgstr "" - -#: readelf.c:3588 -#, c-format -msgid "Name: %s\n" -msgstr "" - -#: readelf.c:3590 -#, c-format -msgid "Name index: %ld\n" -msgstr "" - -#: readelf.c:3605 -#, c-format -msgid " %#06x: Parent %d: %s\n" -msgstr "" - -#: readelf.c:3608 -#, c-format -msgid " %#06x: Parent %d, name index: %ld\n" -msgstr "" - -#: readelf.c:3627 -#, c-format -msgid "" -"\n" -"Version needs section '%s' contains %ld entries:\n" -msgstr "" - -#: readelf.c:3630 -msgid " Addr: 0x" -msgstr "" - -#: readelf.c:3632 -#, c-format -msgid " Offset: %#08lx Link to section: %ld (%s)\n" -msgstr "" - -#: readelf.c:3658 -#, c-format -msgid " %#06x: Version: %d" -msgstr "" - -#: readelf.c:3661 -#, c-format -msgid " File: %s" -msgstr "" - -#: readelf.c:3663 -#, c-format -msgid " File: %lx" -msgstr "" - -#: readelf.c:3665 -#, c-format -msgid " Cnt: %d\n" -msgstr "" - -#: readelf.c:3683 -#, c-format -msgid " %#06x: Name: %s" -msgstr "" - -#: readelf.c:3686 -#, c-format -msgid " %#06x: Name index: %lx" -msgstr "" - -#: readelf.c:3689 -#, c-format -msgid " Flags: %s Version: %d\n" -msgstr "" - -#: readelf.c:3727 -#, c-format -msgid "" -"\n" -"Version symbols section '%s' contains %d entries:\n" -msgstr "" - -#: readelf.c:3730 -msgid " Addr: " -msgstr "" - -#: readelf.c:3760 -msgid " 0 (*local*) " -msgstr "" - -#: readelf.c:3764 -msgid " 1 (*global*) " -msgstr "" - -#: readelf.c:3986 -msgid "" -"\n" -"No version information found in this file.\n" -msgstr "" - -#: readelf.c:4004 readelf.c:4039 -#, c-format -msgid "<processor specific>: %d" -msgstr "" - -#: readelf.c:4006 readelf.c:4051 -#, c-format -msgid "<OS specific>: %d" -msgstr "" - -#: readelf.c:4008 readelf.c:4054 -#, c-format -msgid "<unknown>: %d" -msgstr "" - -#: readelf.c:4117 -msgid "Unable to read in dynamic data\n" -msgstr "" - -#: readelf.c:4159 -msgid "Unable to seek to start of dynamic information" -msgstr "" - -#: readelf.c:4165 -msgid "Failed to read in number of buckets\n" -msgstr "" - -#: readelf.c:4171 -msgid "Failed to read in number of chains\n" -msgstr "" - -#: readelf.c:4191 -msgid "" -"\n" -"Symbol table for image:\n" -msgstr "" - -#: readelf.c:4193 -msgid " Num Buc: Value Size Type Bind Vis Ndx Name\n" -msgstr "" - -#: readelf.c:4195 -msgid " Num Buc: Value Size Type Bind Vis Ndx Name\n" -msgstr "" - -#: readelf.c:4239 -#, c-format -msgid "" -"\n" -"Symbol table '%s' contains %lu entries:\n" -msgstr "" - -#: readelf.c:4243 -msgid " Num: Value Size Type Bind Vis Ndx Name\n" -msgstr "" - -#: readelf.c:4245 -msgid " Num: Value Size Type Bind Vis Ndx Name\n" -msgstr "" - -#: readelf.c:4354 -msgid "bad dynamic symbol" -msgstr "" - -#: readelf.c:4413 -msgid "" -"\n" -"Dynamic symbol information is not available for displaying symbols.\n" -msgstr "" - -#: readelf.c:4425 -#, c-format -msgid "" -"\n" -"Histogram for bucket list length (total of %d buckets):\n" -msgstr "" - -#: readelf.c:4427 -msgid " Length Number %% of total Coverage\n" -msgstr "" - -#: readelf.c:4432 readelf.c:4451 readelf.c:6704 readelf.c:6897 -msgid "Out of memory" -msgstr "" - -#: readelf.c:4500 -#, c-format -msgid "" -"\n" -"Dynamic info segment at offset 0x%lx contains %d entries:\n" -msgstr "" - -#: readelf.c:4503 -msgid " Num: Name BoundTo Flags\n" -msgstr "" - -#: readelf.c:4551 -#, c-format -msgid "" -"\n" -"Assembly dump of section %s\n" -msgstr "" - -#: readelf.c:4574 -#, c-format -msgid "" -"\n" -"Section '%s' has no data to dump.\n" -msgstr "" - -#: readelf.c:4579 -#, c-format -msgid "" -"\n" -"Hex dump of section '%s':\n" -msgstr "" - -#: readelf.c:4731 -msgid "badly formed extended line op encountered!" -msgstr "" - -#: readelf.c:4738 -#, c-format -msgid " Extended opcode %d: " -msgstr "" - -#: readelf.c:4743 -msgid "" -"End of Sequence\n" -"\n" -msgstr "" - -#: readelf.c:4749 -#, c-format -msgid "set Address to 0x%lx\n" -msgstr "" - -#: readelf.c:4754 -msgid " define new File Table entry\n" -msgstr "" - -#: readelf.c:4755 readelf.c:4877 -msgid " Entry\tDir\tTime\tSize\tName\n" -msgstr "" - -#: readelf.c:4757 -#, c-format -msgid " %d\t" -msgstr "" - -#: readelf.c:4760 readelf.c:4762 readelf.c:4764 readelf.c:4889 readelf.c:4891 -#: readelf.c:4893 -#, c-format -msgid "%lu\t" -msgstr "" - -#: readelf.c:4765 -#, c-format -msgid "" -"%s\n" -"\n" -msgstr "" - -#: readelf.c:4769 -#, c-format -msgid "UNKNOWN: length %d\n" -msgstr "" - -#: readelf.c:4795 -#, c-format -msgid "" -"\n" -"Dump of debug contents of section %s:\n" -"\n" -msgstr "" - -#: readelf.c:4807 -msgid "The line info appears to be corrupt - the section is too small\n" -msgstr "" - -#: readelf.c:4815 -msgid "Only DWARF version 2 line info is currently supported.\n" -msgstr "" - -#: readelf.c:4830 -#, c-format -msgid " Length: %ld\n" -msgstr "" - -#: readelf.c:4831 -#, c-format -msgid " DWARF Version: %d\n" -msgstr "" - -#: readelf.c:4832 -#, c-format -msgid " Prolgue Length: %d\n" -msgstr "" - -#: readelf.c:4833 -#, c-format -msgid " Minimum Instruction Length: %d\n" -msgstr "" - -#: readelf.c:4834 -#, c-format -msgid " Initial value of 'is_stmt': %d\n" -msgstr "" - -#: readelf.c:4835 -#, c-format -msgid " Line Base: %d\n" -msgstr "" - -#: readelf.c:4836 -#, c-format -msgid " Line Range: %d\n" -msgstr "" - -#: readelf.c:4837 -#, c-format -msgid " Opcode Base: %d\n" -msgstr "" - -#: readelf.c:4846 -msgid "" -"\n" -" Opcodes:\n" -msgstr "" - -#: readelf.c:4849 -#, c-format -msgid " Opcode %d has %d args\n" -msgstr "" - -#: readelf.c:4855 -msgid "" -"\n" -" The Directory Table is empty.\n" -msgstr "" - -#: readelf.c:4858 -msgid "" -"\n" -" The Directory Table:\n" -msgstr "" - -#: readelf.c:4862 -#, c-format -msgid " %s\n" -msgstr "" - -#: readelf.c:4873 -msgid "" -"\n" -" The File Name Table is empty.\n" -msgstr "" - -#: readelf.c:4876 -msgid "" -"\n" -" The File Name Table:\n" -msgstr "" - -#: readelf.c:4884 -#, c-format -msgid " %d\t" -msgstr "" - -#: readelf.c:4895 -#, c-format -msgid "%s\n" -msgstr "" - -#. Now display the statements. -#: readelf.c:4903 -msgid "" -"\n" -" Line Number Statements:\n" -msgstr "" - -#: readelf.c:4922 -msgid " Copy\n" -msgstr "" - -#: readelf.c:4929 -#, c-format -msgid " Advance PC by %d to %lx\n" -msgstr "" - -#: readelf.c:4937 -#, c-format -msgid " Advance Line by %d to %d\n" -msgstr "" - -#: readelf.c:4944 -#, c-format -msgid " Set File Name to entry %d in the File Name Table\n" -msgstr "" - -#: readelf.c:4952 -#, c-format -msgid " Set column to %d\n" -msgstr "" - -#: readelf.c:4959 -#, c-format -msgid " Set is_stmt to %d\n" -msgstr "" - -#: readelf.c:4964 -msgid " Set basic block\n" -msgstr "" - -#: readelf.c:4972 -#, c-format -msgid " Advance PC by constant %d to 0x%lx\n" -msgstr "" - -#: readelf.c:4980 -#, c-format -msgid " Advance PC by fixed size amount %d to 0x%lx\n" -msgstr "" - -#: readelf.c:4988 -#, c-format -msgid " Special opcode %d: advance Address by %d to 0x%lx" -msgstr "" - -#: readelf.c:4992 -#, c-format -msgid " and Line by %d to %d\n" -msgstr "" - -#: readelf.c:5015 readelf.c:5437 -#, c-format -msgid "" -"Contents of the %s section:\n" -"\n" -msgstr "" - -#: readelf.c:5034 -msgid "Only DWARF 2 pubnames are currently supported" -msgstr "" - -#: readelf.c:5038 -#, c-format -msgid " Length: %ld\n" -msgstr "" - -#: readelf.c:5040 -#, c-format -msgid " Version: %d\n" -msgstr "" - -#: readelf.c:5042 -#, c-format -msgid " Offset into .debug_info section: %ld\n" -msgstr "" - -#: readelf.c:5044 -#, c-format -msgid " Size of area in .debug_info section: %ld\n" -msgstr "" - -#: readelf.c:5047 -msgid "" -"\n" -" Offset\tName\n" -msgstr "" - -#: readelf.c:5129 -#, c-format -msgid "Unknown TAG value: %lx" -msgstr "" - -#: readelf.c:5224 -#, c-format -msgid "Unknown AT value: %lx" -msgstr "" - -#: readelf.c:5261 -#, c-format -msgid "Unknown FORM value: %lx" -msgstr "" - -#: readelf.c:5443 -msgid " Number TAG\n" -msgstr "" - -#: readelf.c:5449 -#, c-format -msgid " %ld %s [%s]\n" -msgstr "" - -#: readelf.c:5452 -msgid "has children" -msgstr "" - -#: readelf.c:5452 -msgid "no children" -msgstr "" - -#: readelf.c:5456 -#, c-format -msgid " %-18s %s\n" -msgstr "" - -#: readelf.c:5475 -#, c-format -msgid " %lu byte block: " -msgstr "" - -#: readelf.c:5939 -msgid "(User defined location op)" -msgstr "" - -#: readelf.c:5941 -msgid "(Unknown location op)" -msgstr "" - -#: readelf.c:6058 -#, c-format -msgid "Unable to handle FORM: %d" -msgstr "" - -#: readelf.c:6062 -#, c-format -msgid "Unrecognised form: %d" -msgstr "" - -#: readelf.c:6075 -msgid "(not inlined)" -msgstr "" - -#: readelf.c:6076 -msgid "(inlined)" -msgstr "" - -#: readelf.c:6077 -msgid "(declared as inline but ignored)" -msgstr "" - -#: readelf.c:6078 -msgid "(declared as inline and inlined)" -msgstr "" - -#: readelf.c:6079 -#, c-format -msgid " (Unknown inline attribute value: %lx)" -msgstr "" - -#: readelf.c:6209 readelf.c:6333 -#, c-format -msgid "" -"The section %s contains:\n" -"\n" -msgstr "" - -#: readelf.c:6231 -msgid "Only version 2 DWARF debug information is currently supported.\n" -msgstr "" - -#: readelf.c:6235 -msgid " Compilation Unit:\n" -msgstr "" - -#: readelf.c:6236 -#, c-format -msgid " Length: %ld\n" -msgstr "" - -#: readelf.c:6237 -#, c-format -msgid " Version: %d\n" -msgstr "" - -#: readelf.c:6238 -#, c-format -msgid " Abbrev Offset: %ld\n" -msgstr "" - -#: readelf.c:6239 -#, c-format -msgid " Pointer Size: %d\n" -msgstr "" - -#: readelf.c:6259 -msgid "Unable to locate .debug_abbrev section!\n" -msgstr "" - -#: readelf.c:6299 -#, c-format -msgid "Unable to locate entry %lu in the abbreviation table\n" -msgstr "" - -#: readelf.c:6304 -#, c-format -msgid " <%d><%x>: Abbrev Number: %lu (%s)\n" -msgstr "" - -#: readelf.c:6352 -#, c-format -msgid " Length: %ld\n" -msgstr "" - -#: readelf.c:6353 -#, c-format -msgid " Version: %d\n" -msgstr "" - -#: readelf.c:6354 -#, c-format -msgid " Offset into .debug_info: %lx\n" -msgstr "" - -#: readelf.c:6355 -#, c-format -msgid " Pointer Size: %d\n" -msgstr "" - -#: readelf.c:6356 -#, c-format -msgid " Segment Size: %d\n" -msgstr "" - -#: readelf.c:6358 -msgid "" -"\n" -" Address Length\n" -msgstr "" - -#: readelf.c:6399 -#, c-format -msgid "Displaying the debug contents of section %s is not yet supported.\n" -msgstr "" - -#: readelf.c:6461 -#, c-format -msgid "" -"\n" -"Section '%s' has no debugging data.\n" -msgstr "" - -#: readelf.c:6477 -#, c-format -msgid "Unrecognised debug section: %s\n" -msgstr "" - -#: readelf.c:6549 -msgid "Some sections were not dumped because they do not exist!\n" -msgstr "" - -#: readelf.c:6728 -#, c-format -msgid "" -"\n" -"Section '%s' contains %d entries:\n" -msgstr "" - -#: readelf.c:6890 -msgid "conflict list with without table" -msgstr "" - -#: readelf.c:6918 -#, c-format -msgid "" -"\n" -"Section '.conflict' contains %d entries:\n" -msgstr "" - -#: readelf.c:6919 -msgid " Num: Index Value Name" -msgstr "" - -#: readelf.c:6944 -msgid "NT_PRSTATUS (prstatus structure)" -msgstr "" - -#: readelf.c:6945 -msgid "NT_FPREGSET (floating point registers)" -msgstr "" - -#: readelf.c:6946 -msgid "NT_PRPSINFO (prpsinfo structure)" -msgstr "" - -#: readelf.c:6947 -msgid "NT_TASKSTRUCT (task structure)" -msgstr "" - -#: readelf.c:6948 -msgid "NT_PRXFPREG (user_xfpregs structure)" -msgstr "" - -#: readelf.c:6949 -msgid "NT_PSTATUS (pstatus structure)" -msgstr "" - -#: readelf.c:6950 -msgid "NT_FPREGS (floating point registers)" -msgstr "" - -#: readelf.c:6951 -msgid "NT_PSINFO (psinfo structure)" -msgstr "" - -#: readelf.c:6952 -msgid "NT_LWPSTATUS (lwpstatus_t structure)" -msgstr "" - -#: readelf.c:6953 -msgid "NT_LWPSINFO (lwpsinfo_t structure)" -msgstr "" - -#: readelf.c:6954 -msgid "NT_WIN32PSTATUS (win32_pstatus strcuture)" -msgstr "" - -#: readelf.c:6956 -#, c-format -msgid "Unknown note type: (0x%08x)" -msgstr "" - -#: readelf.c:6994 -#, c-format -msgid "" -"\n" -"Notes at offset 0x%08lx with length 0x%08lx:\n" -msgstr "" - -#: readelf.c:6997 -msgid " Owner\t\tData size\tDescription\n" -msgstr "" - -#: readelf.c:7108 -msgid "No note segments present in the core file.\n" -msgstr "" - -#: readelf.c:7186 -msgid "This instance of readelf has been built without support for a\n" -msgstr "" - -#: readelf.c:7187 -msgid "64 bit data type and so it cannot read 64 bit ELF files.\n" -msgstr "" - -#: readelf.c:7222 -#, c-format -msgid "Cannot stat input file %s.\n" -msgstr "" - -#: readelf.c:7229 -#, c-format -msgid "Input file %s not found.\n" -msgstr "" - -#: readelf.c:7235 -#, c-format -msgid "%s: Failed to read file header\n" -msgstr "" - -#: readelf.c:7249 -#, c-format -msgid "" -"\n" -"File: %s\n" -msgstr "" - -#: rename.c:131 -#, c-format -msgid "%s: cannot set time: %s" -msgstr "" - -#. We have to clean up here. -#: rename.c:170 rename.c:203 -#, c-format -msgid "%s: rename: %s" -msgstr "" - -#: rename.c:211 -#, c-format -msgid "%s: simple_copy: %s" -msgstr "" - -#: resbin.c:130 -#, c-format -msgid "%s: not enough binary data" -msgstr "" - -#: resbin.c:149 -msgid "null terminated unicode string" -msgstr "" - -#: resbin.c:179 resbin.c:185 -msgid "resource ID" -msgstr "" - -#: resbin.c:229 -msgid "cursor" -msgstr "" - -#: resbin.c:263 resbin.c:270 -msgid "menu header" -msgstr "" - -#: resbin.c:280 -msgid "menuex header" -msgstr "" - -#: resbin.c:284 -msgid "menuex offset" -msgstr "" - -#: resbin.c:291 -#, c-format -msgid "unsupported menu version %d" -msgstr "" - -#: resbin.c:319 resbin.c:334 resbin.c:400 -msgid "menuitem header" -msgstr "" - -#: resbin.c:430 -msgid "menuitem" -msgstr "" - -#: resbin.c:471 resbin.c:499 -msgid "dialog header" -msgstr "" - -#: resbin.c:489 -#, c-format -msgid "unexpected dialog signature %d" -msgstr "" - -#: resbin.c:531 -msgid "dialog font point size" -msgstr "" - -#: resbin.c:539 -msgid "dialogex font information" -msgstr "" - -#: resbin.c:564 resbin.c:582 -msgid "dialog control" -msgstr "" - -#: resbin.c:574 -msgid "dialogex control" -msgstr "" - -#: resbin.c:603 -msgid "dialog control end" -msgstr "" - -#: resbin.c:615 -msgid "dialog control data" -msgstr "" - -#: resbin.c:658 -msgid "stringtable string length" -msgstr "" - -#: resbin.c:668 -msgid "stringtable string" -msgstr "" - -#: resbin.c:701 -msgid "fontdir header" -msgstr "" - -#: resbin.c:714 -msgid "fontdir" -msgstr "" - -#: resbin.c:730 -msgid "fontdir device name" -msgstr "" - -#: resbin.c:736 -msgid "fontdir face name" -msgstr "" - -#: resbin.c:779 -msgid "accelerator" -msgstr "" - -#: resbin.c:843 -msgid "group cursor header" -msgstr "" - -#: resbin.c:847 -#, c-format -msgid "unexpected group cursor type %d" -msgstr "" - -#: resbin.c:862 -msgid "group cursor" -msgstr "" - -#: resbin.c:901 -msgid "group icon header" -msgstr "" - -#: resbin.c:905 -#, c-format -msgid "unexpected group icon type %d" -msgstr "" - -#: resbin.c:920 -msgid "group icon" -msgstr "" - -#: resbin.c:991 resbin.c:1210 -msgid "unexpected version string" -msgstr "" - -#: resbin.c:1025 -#, c-format -msgid "version length %d does not match resource length %lu" -msgstr "" - -#: resbin.c:1029 -#, c-format -msgid "unexpected version type %d" -msgstr "" - -#: resbin.c:1041 -#, c-format -msgid "unexpected fixed version information length %d" -msgstr "" - -#: resbin.c:1044 -msgid "fixed version info" -msgstr "" - -#: resbin.c:1048 -#, c-format -msgid "unexpected fixed version signature %lu" -msgstr "" - -#: resbin.c:1052 -#, c-format -msgid "unexpected fixed version info version %lu" -msgstr "" - -#: resbin.c:1081 -msgid "version var info" -msgstr "" - -#: resbin.c:1098 -#, c-format -msgid "unexpected stringfileinfo value length %d" -msgstr "" - -#: resbin.c:1108 -#, c-format -msgid "unexpected version stringtable value length %d" -msgstr "" - -#: resbin.c:1142 -#, c-format -msgid "unexpected version string length %d != %d + %d" -msgstr "" - -#: resbin.c:1153 -#, c-format -msgid "unexpected version string length %d < %d" -msgstr "" - -#: resbin.c:1170 -#, c-format -msgid "unexpected varfileinfo value length %d" -msgstr "" - -#: resbin.c:1189 -msgid "version varfileinfo" -msgstr "" - -#: resbin.c:1204 -#, c-format -msgid "unexpected version value length %d" -msgstr "" - -#: rescoff.c:128 -msgid "filename required for COFF input" -msgstr "" - -#: rescoff.c:145 -#, c-format -msgid "%s: %s: no resource section\n" -msgstr "" - -#: rescoff.c:154 -msgid "can't read resource section" -msgstr "" - -#: rescoff.c:180 -#, c-format -msgid "%s: %s: address out of bounds" -msgstr "" - -#: rescoff.c:199 -msgid "directory" -msgstr "" - -#: rescoff.c:227 -msgid "named directory entry" -msgstr "" - -#: rescoff.c:236 -msgid "directory entry name" -msgstr "" - -#: rescoff.c:256 -msgid "named subdirectory" -msgstr "" - -#: rescoff.c:264 -msgid "named resource" -msgstr "" - -#: rescoff.c:279 -msgid "ID directory entry" -msgstr "" - -#: rescoff.c:296 -msgid "ID subdirectory" -msgstr "" - -#: rescoff.c:304 -msgid "ID resource" -msgstr "" - -#: rescoff.c:330 -msgid "resource type unknown" -msgstr "" - -#: rescoff.c:333 -msgid "data entry" -msgstr "" - -#: rescoff.c:341 -msgid "resource data" -msgstr "" - -#: rescoff.c:346 -msgid "resource data size" -msgstr "" - -#: rescoff.c:441 -msgid "filename required for COFF output" -msgstr "" - -#: rescoff.c:740 -msgid "can't get BFD_RELOC_RVA relocation type" -msgstr "" - -#: resrc.c:240 resrc.c:312 -#, c-format -msgid "can't open temporary file `%s': %s" -msgstr "" - -#: resrc.c:246 -#, c-format -msgid "can't redirect stdout: `%s': %s" -msgstr "" - -#: resrc.c:262 -#, c-format -msgid "%s %s: %s" -msgstr "" - -#: resrc.c:283 -#, c-format -msgid "%s exited with status %d" -msgstr "" - -#: resrc.c:308 -#, c-format -msgid "can't execute `%s': %s" -msgstr "" - -#: resrc.c:317 -#, c-format -msgid "Using temporary file `%s' to read preprocessor output\n" -msgstr "" - -#: resrc.c:324 -#, c-format -msgid "can't popen `%s': %s" -msgstr "" - -#: resrc.c:326 -msgid "Using popen to read preprocessor output\n" -msgstr "" - -#: resrc.c:369 -#, c-format -msgid "Tried `%s'\n" -msgstr "" - -#: resrc.c:380 -#, c-format -msgid "Using `%s'\n" -msgstr "" - -#: resrc.c:544 -#, c-format -msgid "%s:%d: %s\n" -msgstr "" - -#: resrc.c:553 -#, c-format -msgid "%s: unexpected EOF" -msgstr "" - -#: resrc.c:610 -#, c-format -msgid "%s: read of %lu returned %lu" -msgstr "" - -#: resrc.c:652 resrc.c:883 resrc.c:1156 resrc.c:1310 -#, c-format -msgid "stat failed on bitmap file `%s': %s" -msgstr "" - -#: resrc.c:705 -#, c-format -msgid "cursor file `%s' does not contain cursor data" -msgstr "" - -#: resrc.c:737 resrc.c:1027 -#, c-format -msgid "%s: fseek to %lu failed: %s" -msgstr "" - -#: resrc.c:996 -#, c-format -msgid "icon file `%s' does not contain icon data" -msgstr "" - -#: resrc.c:1515 -#, c-format -msgid "can't open `%s' for output: %s" -msgstr "" - -#: size.c:79 -#, c-format -msgid "" -"Usage: %s [-ABdoxV] [--format=berkeley|sysv] [--radix=8|10|16]\n" -" [--target=bfdname] [--version] [--help] [file...]\n" -msgstr "" - -#: size.c:83 -msgid "default is --format=berkeley\n" -msgstr "" - -#: size.c:85 -msgid "default is --format=sysv\n" -msgstr "" - -#: size.c:139 -#, c-format -msgid "invalid argument to --format: %s\n" -msgstr "" - -#: size.c:166 -#, c-format -msgid "Invalid radix: %s\n" -msgstr "" - -#: srconv.c:1879 -#, c-format -msgid "Usage: %s [-dhVq] in-file [out-file]\n" -msgstr "" - -#: srconv.c:1886 -#, c-format -msgid "%s: Convert a COFF object file into a SYSROFF object file\n" -msgstr "" - -#: srconv.c:2024 -#, c-format -msgid "%s: unable to open output file %s\n" -msgstr "" - -#: stabs.c:349 stabs.c:1769 -msgid "numeric overflow" -msgstr "" - -#: stabs.c:360 -#, c-format -msgid "Bad stab: %s\n" -msgstr "" - -#: stabs.c:370 -#, c-format -msgid "Warning: %s: %s\n" -msgstr "" - -#: stabs.c:492 -msgid "N_LBRAC not within function\n" -msgstr "" - -#: stabs.c:531 -msgid "Too many N_RBRACs\n" -msgstr "" - -#: stabs.c:780 -msgid "unknown C++ encoded name" -msgstr "" - -#. Complain and keep going, so compilers can invent new -#. cross-reference types. -#: stabs.c:1306 -msgid "unrecognized cross reference type" -msgstr "" - -#. Does this actually ever happen? Is that why we are worrying -#. about dealing with it rather than just calling error_type? -#: stabs.c:1861 -msgid "missing index type" -msgstr "" - -#: stabs.c:2188 -msgid "unknown virtual character for baseclass" -msgstr "" - -#: stabs.c:2206 -msgid "unknown visibility character for baseclass" -msgstr "" - -#: stabs.c:2398 -msgid "unnamed $vb type" -msgstr "" - -#: stabs.c:2404 -msgid "unrecognized C++ abbreviation" -msgstr "" - -#: stabs.c:2484 -msgid "unknown visibility character for field" -msgstr "" - -#: stabs.c:2740 -msgid "const/volatile indicator missing" -msgstr "" - -#: stabs.c:2980 -#, c-format -msgid "No mangling for \"%s\"\n" -msgstr "" - -#: stabs.c:3293 -msgid "Undefined N_EXCL" -msgstr "" - -#: stabs.c:3381 -#, c-format -msgid "Type file number %d out of range\n" -msgstr "" - -#: stabs.c:3386 -#, c-format -msgid "Type index number %d out of range\n" -msgstr "" - -#: stabs.c:3473 -#, c-format -msgid "Unrecognized XCOFF type %d\n" -msgstr "" - -#: stabs.c:3772 -#, c-format -msgid "bad mangled name `%s'\n" -msgstr "" - -#: stabs.c:3868 -msgid "no argument types in mangled string\n" -msgstr "" - -#: strings.c:159 -#, c-format -msgid "%s: invalid number %s\n" -msgstr "" - -#: strings.c:494 -#, c-format -msgid "%s: invalid integer argument %s\n" -msgstr "" - -#: strings.c:505 -#, c-format -msgid "" -"Usage: %s [-afov] [-n min-len] [-min-len] [-t {o,x,d}] [-]\n" -" [--all] [--print-file-name] [--bytes=min-len] [--radix={o,x,d}]\n" -" [--target=bfdname] [--help] [--version] file...\n" -msgstr "" - -#: sysdump.c:712 -#, c-format -msgid "Usage: %s [-hV] in-file\n" -msgstr "" - -#: sysdump.c:783 -#, c-format -msgid "%s: cannot open input file %s\n" -msgstr "" - -#: version.c:39 -msgid "Copyright 1997, 1998, 1999 Free Software Foundation, Inc.\n" -msgstr "" - -#: version.c:40 -msgid "" -"This program is free software; you may redistribute it under the terms of\n" -"the GNU General Public License. This program has absolutely no warranty.\n" -msgstr "" - -#: windres.c:237 -#, c-format -msgid "can't open %s `%s': %s" -msgstr "" - -#: windres.c:416 -msgid ": expected to be a directory\n" -msgstr "" - -#: windres.c:428 -msgid ": expected to be a leaf\n" -msgstr "" - -#: windres.c:437 -#, c-format -msgid "%s: warning: " -msgstr "" - -#: windres.c:439 -msgid ": duplicate value\n" -msgstr "" - -#: windres.c:602 -#, c-format -msgid "%s: unknown format type `%s'\n" -msgstr "" - -#: windres.c:603 -#, c-format -msgid "%s: supported formats:" -msgstr "" - -#. Otherwise, we give up. -#: windres.c:690 -#, c-format -msgid "can not determine type of file `%s'; use the -I option" -msgstr "" - -#: windres.c:704 -#, c-format -msgid "Usage: %s [options] [input-file] [output-file]\n" -msgstr "" - -#: windres.c:706 -msgid "" -"Options:\n" -" -i FILE, --input FILE Name input file\n" -" -o FILE, --output FILE Name output file\n" -" -I FORMAT, --input-format FORMAT\n" -" Specify input format\n" -" -O FORMAT, --output-format FORMAT\n" -" Specify output format\n" -" -F TARGET, --target TARGET Specify COFF target\n" -" --preprocessor PROGRAM Program to use to preprocess rc file\n" -" --include-dir DIR Include directory when preprocessing rc file\n" -" -DSYM[=VAL], --define SYM[=VAL]\n" -" Define SYM when preprocessing rc file\n" -" -v Verbose - tells you what it's doing\n" -" --language VAL Set language when reading rc file\n" -" --use-temp-file Use a temporary file instead of popen to read\n" -" the preprocessor output\n" -" --no-use-temp-file Use popen (default)\n" -msgstr "" - -#: windres.c:725 -msgid " --yydebug Turn on parser debugging\n" -msgstr "" - -#: windres.c:728 -msgid "" -" --help Print this help message\n" -" --version Print version information\n" -msgstr "" - -#: windres.c:731 -msgid "" -"FORMAT is one of rc, res, or coff, and is deduced from the file name\n" -"extension if not specified. A single file name is an input file.\n" -"No input-file is stdin, default rc. No output-file is stdout, default rc.\n" -msgstr "" - -#: windres.c:980 -msgid "no resources" -msgstr "" - -#: wrstabs.c:366 wrstabs.c:2028 -#, c-format -msgid "string_hash_lookup failed: %s\n" -msgstr "" - -#: wrstabs.c:666 -#, c-format -msgid "stab_int_type: bad size %u\n" -msgstr "" - -#: wrstabs.c:1468 -#, c-format -msgid "%s: warning: unknown size for field `%s' in struct\n" -msgstr "" diff --git a/include/fopen-vms.h b/include/fopen-vms.h new file mode 100644 index 000000000000..da76b7fb59cb --- /dev/null +++ b/include/fopen-vms.h @@ -0,0 +1,24 @@ +/* Macros for the 'type' part of an fopen, freopen or fdopen. + + <Read|Write>[Update]<Binary file|text file> + + This version is for VMS systems, where text and binary files are + different. + This file is designed for inclusion by host-dependent .h files. No + user application should include it directly, since that would make + the application unable to be configured for both "same" and "binary" + variant systems. */ + +#define FOPEN_RB "rb","rfm=var" +#define FOPEN_WB "wb","rfm=var" +#define FOPEN_AB "ab","rfm=var" +#define FOPEN_RUB "r+b","rfm=var" +#define FOPEN_WUB "w+b","rfm=var" +#define FOPEN_AUB "a+b","rfm=var" + +#define FOPEN_RT "r" +#define FOPEN_WT "w" +#define FOPEN_AT "a" +#define FOPEN_RUT "r+" +#define FOPEN_WUT "w+" +#define FOPEN_AUT "a+" diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog new file mode 100644 index 000000000000..3a17b1d797f2 --- /dev/null +++ b/include/gdb/ChangeLog @@ -0,0 +1,110 @@ +2003-10-31 Kevin Buettner <kevin@redhat.com> + + * sim-frv.h: New file. + +2003-10-15 J"orn Rennecke <joern.rennecke@superh.com> + + * callback.h (struct host_callback_struct): New members ftruncate + and truncate. + +2003-06-10 Corinna Vinschen <vinschen@redhat.com> + + * gdb/fileio.h: New file. + +2003-05-07 Andrew Cagney <cagney@redhat.com> + + * sim-d10v.h (sim_d10v_translate_addr): Add regcache parameter. + (sim_d10v_translate_imap_addr): Add regcache parameter. + (sim_d10v_translate_dmap_addr): Ditto. + +2003-03-27 Nick Clifton <nickc@redhat.com> + + * sim-arm.h (sim_arm_regs): Add iWMMXt registers. + +2003-03-20 Nick Clifton <nickc@redhat.com> + + * sim-arm.h (sim_arm_regs): Add Maverick co-processor + registers. + +2003-02-27 Andrew Cagney <cagney@redhat.com> + + * remote-sim.h (sim_open, sim_load, sim_create_inferior): Rename + _bfd to bfd. + +2003-02-20 Andrew Cagney <ac131313@redhat.com> + + * remote-sim.h (SIM_RC): Delete unused SIM_RC_UNKNOWN_BREAKPOINT, + SIM_RC_INSUFFICIENT_RESOURCES and SIM_RC_DUPLICATE_BREAKPOINT. + (sim_set_breakpoint, sim_clear_breakpoint): Delete declarations. + (sim_clear_all_breakpoints, sim_enable_breakpoint): Ditto. + (sim_enable_all_breakpoints, sim_disable_breakpoint): Ditto. + (sim_disable_all_breakpoints): Ditto. + +2002-12-26 Kazu Hirata <kazu@cs.umass.edu> + + * sim-h8300.h: Remove ^M. + +2002-07-29 Andrey Volkov <avolkov@transas.com> + + * sim-h8300.h: Rename all enums from H8300_ to SIM_H8300_ + prefix. + +2002-07-23 Andrey Volkov <avolkov@transas.com> + + * sim-h8300.h: New file. + +2002-07-17 Andrew Cagney <cagney@redhat.com> + + * remote-sim.h: Update copyright. + (sim_set_callbacks, sim_size, sim_trace) + (sim_set_trace, sim_set_profile_size, sim_kill): Delete. Moved to + "sim/common/run-sim.h". + +Wed Jul 17 19:36:38 2002 J"orn Rennecke <joern.rennecke@superh.com> + + * sim-sh.h: Add enum constants for sh[1-4], sh3e, sh3?-dsp, + renumbering the sh-dsp registers to use distinct numbers. + +2002-06-15 Andrew Cagney <ac131313@redhat.com> + + * sim-arm.h (enum sim_arm_regs): Rename sim_arm_regnum. + +2002-06-12 Andrew Cagney <ac131313@redhat.com> + + * sim-arm.h: New file. + +2002-06-08 Andrew Cagney <cagney@redhat.com> + + * callback.h: Copy to here from directory above. + * remote-sim.h: Copy to here from directory above. + +2002-06-01 Andrew Cagney <ac131313@redhat.com> + + * sim-d10v.h (sim_d10v_regs): Expand to include all registers. + Update copyright. + +2002-05-23 Andrew Cagney <ac131313@redhat.com> + + * sim-d10v.h: New file. Moved from include/sim-d10v.h. + +2002-05-10 Elena Zannoni <ezannoni@redhat.com> + + * sim-sh.h: New file, for sh gdb<->sim interface. + +2002-05-09 Daniel Jacobowitz <drow@mvista.com> + + * signals.h: Update comments. + (enum target_signal): Remove conditional compilation around + Mach-specific signals. Move them to after TARGET_SIGNAL_DEFAULT. + +2002-03-10 Daniel Jacobowitz <drow@mvista.com> + + * signals.h: New file, from gdb/defs.h. + + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/include/callback.h b/include/gdb/callback.h index 30752842ed90..3fa419143aed 100644 --- a/include/callback.h +++ b/include/gdb/callback.h @@ -93,6 +93,8 @@ struct host_callback_struct void (*flush_stderr) PARAMS ((host_callback *)); int (*stat) PARAMS ((host_callback *, const char *, struct stat *)); int (*fstat) PARAMS ((host_callback *, int, struct stat *)); + int (*ftruncate) PARAMS ((host_callback *, int, long)); + int (*truncate) PARAMS ((host_callback *, const char *, long)); /* When present, call to the client to give it the oportunity to poll any io devices for a request to quit (indicated by a nonzero diff --git a/include/gdb/fileio.h b/include/gdb/fileio.h new file mode 100644 index 000000000000..d84478103e2a --- /dev/null +++ b/include/gdb/fileio.h @@ -0,0 +1,146 @@ +/* Hosted File I/O interface definitions, for GDB, the GNU Debugger. + + Copyright 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef GDB_FILEIO_H_ +#define GDB_FILEIO_H_ + +/* The following flags are defined to be independent of the host + as well as the target side implementation of these constants. + All constants are defined with a leading FILEIO_ in the name + to allow the usage of these constants together with the + corresponding implementation dependent constants in one module. */ + +/* open(2) flags */ +#define FILEIO_O_RDONLY 0x0 +#define FILEIO_O_WRONLY 0x1 +#define FILEIO_O_RDWR 0x2 +#define FILEIO_O_APPEND 0x8 +#define FILEIO_O_CREAT 0x200 +#define FILEIO_O_TRUNC 0x400 +#define FILEIO_O_EXCL 0x800 +#define FILEIO_O_SUPPORTED (FILEIO_O_RDONLY | FILEIO_O_WRONLY| \ + FILEIO_O_RDWR | FILEIO_O_APPEND| \ + FILEIO_O_CREAT | FILEIO_O_TRUNC| \ + FILEIO_O_EXCL) + +/* mode_t bits */ +#define FILEIO_S_IFREG 0100000 +#define FILEIO_S_IFDIR 040000 +#define FILEIO_S_IFCHR 020000 +#define FILEIO_S_IRUSR 0400 +#define FILEIO_S_IWUSR 0200 +#define FILEIO_S_IXUSR 0100 +#define FILEIO_S_IRWXU 0700 +#define FILEIO_S_IRGRP 040 +#define FILEIO_S_IWGRP 020 +#define FILEIO_S_IXGRP 010 +#define FILEIO_S_IRWXG 070 +#define FILEIO_S_IROTH 04 +#define FILEIO_S_IWOTH 02 +#define FILEIO_S_IXOTH 01 +#define FILEIO_S_IRWXO 07 +#define FILEIO_S_SUPPORTED (FILEIO_S_IFREG|FILEIO_S_IFDIR| \ + FILEIO_S_IRWXU|FILEIO_S_IRWXG| \ + FILEIO_S_IRWXO) + +/* lseek(2) flags */ +#define FILEIO_SEEK_SET 0 +#define FILEIO_SEEK_CUR 1 +#define FILEIO_SEEK_END 2 + +/* errno values */ +#define FILEIO_EPERM 1 +#define FILEIO_ENOENT 2 +#define FILEIO_EINTR 4 +#define FILEIO_EIO 5 +#define FILEIO_EBADF 9 +#define FILEIO_EACCES 13 +#define FILEIO_EFAULT 14 +#define FILEIO_EBUSY 16 +#define FILEIO_EEXIST 17 +#define FILEIO_ENODEV 19 +#define FILEIO_ENOTDIR 20 +#define FILEIO_EISDIR 21 +#define FILEIO_EINVAL 22 +#define FILEIO_ENFILE 23 +#define FILEIO_EMFILE 24 +#define FILEIO_EFBIG 27 +#define FILEIO_ENOSPC 28 +#define FILEIO_ESPIPE 29 +#define FILEIO_EROFS 30 +#define FILEIO_ENOSYS 88 +#define FILEIO_ENAMETOOLONG 91 +#define FILEIO_EUNKNOWN 9999 + +/* limits */ +#define FILEIO_INT_MIN -2147483648L +#define FILEIO_INT_MAX 2147483647L +#define FILEIO_UINT_MAX 4294967295UL +#define FILEIO_LONG_MIN -9223372036854775808LL +#define FILEIO_LONG_MAX 9223372036854775807LL +#define FILEIO_ULONG_MAX 18446744073709551615ULL + +/* Integral types as used in protocol. */ +#if 0 +typedef __int32_t fio_int_t; +typedef __uint32_t fio_uint_t, fio_mode_t, fio_time_t; +typedef __int64_t fio_long_t; +typedef __uint64_t fio_ulong_t; +#endif + +#define FIO_INT_LEN 4 +#define FIO_UINT_LEN 4 +#define FIO_MODE_LEN 4 +#define FIO_TIME_LEN 4 +#define FIO_LONG_LEN 8 +#define FIO_ULONG_LEN 8 + +typedef char fio_int_t[FIO_INT_LEN]; +typedef char fio_uint_t[FIO_UINT_LEN]; +typedef char fio_mode_t[FIO_MODE_LEN]; +typedef char fio_time_t[FIO_TIME_LEN]; +typedef char fio_long_t[FIO_LONG_LEN]; +typedef char fio_ulong_t[FIO_ULONG_LEN]; + +/* Struct stat as used in protocol. For complete independence + of host/target systems, it's defined as an array with offsets + to the members. */ + +struct fio_stat { + fio_uint_t fst_dev; + fio_uint_t fst_ino; + fio_mode_t fst_mode; + fio_uint_t fst_nlink; + fio_uint_t fst_uid; + fio_uint_t fst_gid; + fio_uint_t fst_rdev; + fio_ulong_t fst_size; + fio_ulong_t fst_blksize; + fio_ulong_t fst_blocks; + fio_time_t fst_atime; + fio_time_t fst_mtime; + fio_time_t fst_ctime; +}; + +struct fio_timeval { + fio_time_t ftv_sec; + fio_long_t ftv_usec; +}; + +#endif /* GDB_FILEIO_H_ */ diff --git a/include/remote-sim.h b/include/gdb/remote-sim.h index 726ec623fbdf..a49ba1a89e91 100644 --- a/include/remote-sim.h +++ b/include/gdb/remote-sim.h @@ -1,6 +1,7 @@ /* This file defines the interface between the simulator and gdb. - Copyright 1993, 1994, 1996, 1997, 1998, 2000 - Free Software Foundation, Inc. + + Copyright 1993, 1994, 1996, 1997, 1998, 2000, 2002 Free Software + Foundation, Inc. This file is part of GDB. @@ -57,16 +58,13 @@ typedef enum { typedef enum { SIM_RC_FAIL = 0, - SIM_RC_OK = 1, - SIM_RC_UNKNOWN_BREAKPOINT = 2, - SIM_RC_INSUFFICIENT_RESOURCES = 3, - SIM_RC_DUPLICATE_BREAKPOINT = 4 + SIM_RC_OK = 1 } SIM_RC; /* The bfd struct, as an opaque type. */ -struct _bfd; +struct bfd; /* Main simulator entry points. */ @@ -107,7 +105,7 @@ struct _bfd; sim_create_inferior. FIXME: What should the state of the simulator be? */ -SIM_DESC sim_open PARAMS ((SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct _bfd *abfd, char **argv)); +SIM_DESC sim_open PARAMS ((SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct bfd *abfd, char **argv)); /* Destory a simulator instance. @@ -144,7 +142,7 @@ void sim_close PARAMS ((SIM_DESC sd, int quitting)); Such manipulation should probably (?) occure in sim_create_inferior. */ -SIM_RC sim_load PARAMS ((SIM_DESC sd, char *prog, struct _bfd *abfd, int from_tty)); +SIM_RC sim_load PARAMS ((SIM_DESC sd, char *prog, struct bfd *abfd, int from_tty)); /* Prepare to run the simulated program. @@ -164,7 +162,7 @@ SIM_RC sim_load PARAMS ((SIM_DESC sd, char *prog, struct _bfd *abfd, int from_tt address space (according to the applicable ABI) and the program counter and stack pointer set accordingly. */ -SIM_RC sim_create_inferior PARAMS ((SIM_DESC sd, struct _bfd *abfd, char **argv, char **env)); +SIM_RC sim_create_inferior PARAMS ((SIM_DESC sd, struct bfd *abfd, char **argv, char **env)); /* Fetch LENGTH bytes of the simulated program's memory. Start fetch @@ -277,76 +275,6 @@ void sim_stop_reason PARAMS ((SIM_DESC sd, enum sim_stop *reason, int *sigrc)); void sim_do_command PARAMS ((SIM_DESC sd, char *cmd)); -/* Call these functions to set and clear breakpoints at ADDR. */ - -SIM_RC sim_set_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); -SIM_RC sim_clear_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); -SIM_RC sim_clear_all_breakpoints PARAMS ((SIM_DESC sd)); - -/* These functions are used to enable and disable breakpoints. */ - -SIM_RC sim_enable_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); -SIM_RC sim_disable_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr)); -SIM_RC sim_enable_all_breakpoints PARAMS ((SIM_DESC sd)); -SIM_RC sim_disable_all_breakpoints PARAMS ((SIM_DESC sd)); - - -/* Provide simulator with a default (global) host_callback_struct. - THIS PROCEDURE IS DEPRECIATED. - GDB and NRUN do not use this interface. - This procedure does not take a SIM_DESC argument as it is - used before sim_open. */ - -void sim_set_callbacks PARAMS ((struct host_callback_struct *)); - - -/* Set the size of the simulator memory array. - THIS PROCEDURE IS DEPRECIATED. - GDB and NRUN do not use this interface. - This procedure does not take a SIM_DESC argument as it is - used before sim_open. */ - -void sim_size PARAMS ((int i)); - - -/* Single-step simulator with tracing enabled. - THIS PROCEDURE IS DEPRECIATED. - THIS PROCEDURE IS EVEN MORE DEPRECATED THAN SIM_SET_TRACE - GDB and NRUN do not use this interface. - This procedure returns: ``0'' indicating that the simulator should - be continued using sim_trace() calls; ``1'' indicating that the - simulation has finished. */ - -int sim_trace PARAMS ((SIM_DESC sd)); - - -/* Enable tracing. - THIS PROCEDURE IS DEPRECIATED. - GDB and NRUN do not use this interface. - This procedure returns: ``0'' indicating that the simulator should - be continued using sim_trace() calls; ``1'' indicating that the - simulation has finished. */ - -void sim_set_trace PARAMS ((void)); - - -/* Configure the size of the profile buffer. - THIS PROCEDURE IS DEPRECIATED. - GDB and NRUN do not use this interface. - This procedure does not take a SIM_DESC argument as it is - used before sim_open. */ - -void sim_set_profile_size PARAMS ((int n)); - - -/* Kill the running program. - THIS PROCEDURE IS DEPRECIATED. - GDB and NRUN do not use this interface. - This procedure will be replaced as part of the introduction of - multi-cpu simulators. */ - -void sim_kill PARAMS ((SIM_DESC sd)); - #ifdef __cplusplus } #endif diff --git a/include/gdb/signals.h b/include/gdb/signals.h new file mode 100644 index 000000000000..b6f5d4853125 --- /dev/null +++ b/include/gdb/signals.h @@ -0,0 +1,237 @@ +/* Target signal numbers for GDB and the GDB remote protocol. + Copyright 1986, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, + 1997, 1998, 1999, 2000, 2001, 2002 + Free Software Foundation, Inc. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +#ifndef GDB_SIGNALS_H +#define GDB_SIGNALS_H + +/* The numbering of these signals is chosen to match traditional unix + signals (insofar as various unices use the same numbers, anyway). + It is also the numbering of the GDB remote protocol. Other remote + protocols, if they use a different numbering, should make sure to + translate appropriately. + + Since these numbers have actually made it out into other software + (stubs, etc.), you mustn't disturb the assigned numbering. If you + need to add new signals here, add them to the end of the explicitly + numbered signals, at the comment marker. Add them unconditionally, + not within any #if or #ifdef. + + This is based strongly on Unix/POSIX signals for several reasons: + (1) This set of signals represents a widely-accepted attempt to + represent events of this sort in a portable fashion, (2) we want a + signal to make it from wait to child_wait to the user intact, (3) many + remote protocols use a similar encoding. However, it is + recognized that this set of signals has limitations (such as not + distinguishing between various kinds of SIGSEGV, or not + distinguishing hitting a breakpoint from finishing a single step). + So in the future we may get around this either by adding additional + signals for breakpoint, single-step, etc., or by adding signal + codes; the latter seems more in the spirit of what BSD, System V, + etc. are doing to address these issues. */ + +/* For an explanation of what each signal means, see + target_signal_to_string. */ + +enum target_signal + { + /* Used some places (e.g. stop_signal) to record the concept that + there is no signal. */ + TARGET_SIGNAL_0 = 0, + TARGET_SIGNAL_FIRST = 0, + TARGET_SIGNAL_HUP = 1, + TARGET_SIGNAL_INT = 2, + TARGET_SIGNAL_QUIT = 3, + TARGET_SIGNAL_ILL = 4, + TARGET_SIGNAL_TRAP = 5, + TARGET_SIGNAL_ABRT = 6, + TARGET_SIGNAL_EMT = 7, + TARGET_SIGNAL_FPE = 8, + TARGET_SIGNAL_KILL = 9, + TARGET_SIGNAL_BUS = 10, + TARGET_SIGNAL_SEGV = 11, + TARGET_SIGNAL_SYS = 12, + TARGET_SIGNAL_PIPE = 13, + TARGET_SIGNAL_ALRM = 14, + TARGET_SIGNAL_TERM = 15, + TARGET_SIGNAL_URG = 16, + TARGET_SIGNAL_STOP = 17, + TARGET_SIGNAL_TSTP = 18, + TARGET_SIGNAL_CONT = 19, + TARGET_SIGNAL_CHLD = 20, + TARGET_SIGNAL_TTIN = 21, + TARGET_SIGNAL_TTOU = 22, + TARGET_SIGNAL_IO = 23, + TARGET_SIGNAL_XCPU = 24, + TARGET_SIGNAL_XFSZ = 25, + TARGET_SIGNAL_VTALRM = 26, + TARGET_SIGNAL_PROF = 27, + TARGET_SIGNAL_WINCH = 28, + TARGET_SIGNAL_LOST = 29, + TARGET_SIGNAL_USR1 = 30, + TARGET_SIGNAL_USR2 = 31, + TARGET_SIGNAL_PWR = 32, + /* Similar to SIGIO. Perhaps they should have the same number. */ + TARGET_SIGNAL_POLL = 33, + TARGET_SIGNAL_WIND = 34, + TARGET_SIGNAL_PHONE = 35, + TARGET_SIGNAL_WAITING = 36, + TARGET_SIGNAL_LWP = 37, + TARGET_SIGNAL_DANGER = 38, + TARGET_SIGNAL_GRANT = 39, + TARGET_SIGNAL_RETRACT = 40, + TARGET_SIGNAL_MSG = 41, + TARGET_SIGNAL_SOUND = 42, + TARGET_SIGNAL_SAK = 43, + TARGET_SIGNAL_PRIO = 44, + TARGET_SIGNAL_REALTIME_33 = 45, + TARGET_SIGNAL_REALTIME_34 = 46, + TARGET_SIGNAL_REALTIME_35 = 47, + TARGET_SIGNAL_REALTIME_36 = 48, + TARGET_SIGNAL_REALTIME_37 = 49, + TARGET_SIGNAL_REALTIME_38 = 50, + TARGET_SIGNAL_REALTIME_39 = 51, + TARGET_SIGNAL_REALTIME_40 = 52, + TARGET_SIGNAL_REALTIME_41 = 53, + TARGET_SIGNAL_REALTIME_42 = 54, + TARGET_SIGNAL_REALTIME_43 = 55, + TARGET_SIGNAL_REALTIME_44 = 56, + TARGET_SIGNAL_REALTIME_45 = 57, + TARGET_SIGNAL_REALTIME_46 = 58, + TARGET_SIGNAL_REALTIME_47 = 59, + TARGET_SIGNAL_REALTIME_48 = 60, + TARGET_SIGNAL_REALTIME_49 = 61, + TARGET_SIGNAL_REALTIME_50 = 62, + TARGET_SIGNAL_REALTIME_51 = 63, + TARGET_SIGNAL_REALTIME_52 = 64, + TARGET_SIGNAL_REALTIME_53 = 65, + TARGET_SIGNAL_REALTIME_54 = 66, + TARGET_SIGNAL_REALTIME_55 = 67, + TARGET_SIGNAL_REALTIME_56 = 68, + TARGET_SIGNAL_REALTIME_57 = 69, + TARGET_SIGNAL_REALTIME_58 = 70, + TARGET_SIGNAL_REALTIME_59 = 71, + TARGET_SIGNAL_REALTIME_60 = 72, + TARGET_SIGNAL_REALTIME_61 = 73, + TARGET_SIGNAL_REALTIME_62 = 74, + TARGET_SIGNAL_REALTIME_63 = 75, + + /* Used internally by Solaris threads. See signal(5) on Solaris. */ + TARGET_SIGNAL_CANCEL = 76, + + /* Yes, this pains me, too. But LynxOS didn't have SIG32, and now + GNU/Linux does, and we can't disturb the numbering, since it's + part of the remote protocol. Note that in some GDB's + TARGET_SIGNAL_REALTIME_32 is number 76. */ + TARGET_SIGNAL_REALTIME_32, + /* Yet another pain, IRIX 6 has SIG64. */ + TARGET_SIGNAL_REALTIME_64, + /* Yet another pain, GNU/Linux MIPS might go up to 128. */ + TARGET_SIGNAL_REALTIME_65, + TARGET_SIGNAL_REALTIME_66, + TARGET_SIGNAL_REALTIME_67, + TARGET_SIGNAL_REALTIME_68, + TARGET_SIGNAL_REALTIME_69, + TARGET_SIGNAL_REALTIME_70, + TARGET_SIGNAL_REALTIME_71, + TARGET_SIGNAL_REALTIME_72, + TARGET_SIGNAL_REALTIME_73, + TARGET_SIGNAL_REALTIME_74, + TARGET_SIGNAL_REALTIME_75, + TARGET_SIGNAL_REALTIME_76, + TARGET_SIGNAL_REALTIME_77, + TARGET_SIGNAL_REALTIME_78, + TARGET_SIGNAL_REALTIME_79, + TARGET_SIGNAL_REALTIME_80, + TARGET_SIGNAL_REALTIME_81, + TARGET_SIGNAL_REALTIME_82, + TARGET_SIGNAL_REALTIME_83, + TARGET_SIGNAL_REALTIME_84, + TARGET_SIGNAL_REALTIME_85, + TARGET_SIGNAL_REALTIME_86, + TARGET_SIGNAL_REALTIME_87, + TARGET_SIGNAL_REALTIME_88, + TARGET_SIGNAL_REALTIME_89, + TARGET_SIGNAL_REALTIME_90, + TARGET_SIGNAL_REALTIME_91, + TARGET_SIGNAL_REALTIME_92, + TARGET_SIGNAL_REALTIME_93, + TARGET_SIGNAL_REALTIME_94, + TARGET_SIGNAL_REALTIME_95, + TARGET_SIGNAL_REALTIME_96, + TARGET_SIGNAL_REALTIME_97, + TARGET_SIGNAL_REALTIME_98, + TARGET_SIGNAL_REALTIME_99, + TARGET_SIGNAL_REALTIME_100, + TARGET_SIGNAL_REALTIME_101, + TARGET_SIGNAL_REALTIME_102, + TARGET_SIGNAL_REALTIME_103, + TARGET_SIGNAL_REALTIME_104, + TARGET_SIGNAL_REALTIME_105, + TARGET_SIGNAL_REALTIME_106, + TARGET_SIGNAL_REALTIME_107, + TARGET_SIGNAL_REALTIME_108, + TARGET_SIGNAL_REALTIME_109, + TARGET_SIGNAL_REALTIME_110, + TARGET_SIGNAL_REALTIME_111, + TARGET_SIGNAL_REALTIME_112, + TARGET_SIGNAL_REALTIME_113, + TARGET_SIGNAL_REALTIME_114, + TARGET_SIGNAL_REALTIME_115, + TARGET_SIGNAL_REALTIME_116, + TARGET_SIGNAL_REALTIME_117, + TARGET_SIGNAL_REALTIME_118, + TARGET_SIGNAL_REALTIME_119, + TARGET_SIGNAL_REALTIME_120, + TARGET_SIGNAL_REALTIME_121, + TARGET_SIGNAL_REALTIME_122, + TARGET_SIGNAL_REALTIME_123, + TARGET_SIGNAL_REALTIME_124, + TARGET_SIGNAL_REALTIME_125, + TARGET_SIGNAL_REALTIME_126, + TARGET_SIGNAL_REALTIME_127, + + TARGET_SIGNAL_INFO, + + /* Some signal we don't know about. */ + TARGET_SIGNAL_UNKNOWN, + + /* Use whatever signal we use when one is not specifically specified + (for passing to proceed and so on). */ + TARGET_SIGNAL_DEFAULT, + + /* Mach exceptions. In versions of GDB before 5.2, these were just before + TARGET_SIGNAL_INFO if you were compiling on a Mach host (and missing + otherwise). */ + TARGET_EXC_BAD_ACCESS, + TARGET_EXC_BAD_INSTRUCTION, + TARGET_EXC_ARITHMETIC, + TARGET_EXC_EMULATION, + TARGET_EXC_SOFTWARE, + TARGET_EXC_BREAKPOINT, + + /* If you are adding a new signal, add it just above this comment. */ + + /* Last and unused enum value, for sizing arrays, etc. */ + TARGET_SIGNAL_LAST + }; + +#endif /* #ifndef GDB_SIGNALS_H */ diff --git a/include/gdb/sim-arm.h b/include/gdb/sim-arm.h new file mode 100644 index 000000000000..5598f73fa8fa --- /dev/null +++ b/include/gdb/sim-arm.h @@ -0,0 +1,114 @@ +/* This file defines the interface between the Arm simulator and GDB. + + Copyright 2002, 2003 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#if !defined (SIM_ARM_H) +#define SIM_ARM_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +enum sim_arm_regs +{ + SIM_ARM_R0_REGNUM, + SIM_ARM_R1_REGNUM, + SIM_ARM_R2_REGNUM, + SIM_ARM_R3_REGNUM, + SIM_ARM_R4_REGNUM, + SIM_ARM_R5_REGNUM, + SIM_ARM_R6_REGNUM, + SIM_ARM_R7_REGNUM, + SIM_ARM_R8_REGNUM, + SIM_ARM_R9_REGNUM, + SIM_ARM_R10_REGNUM, + SIM_ARM_R11_REGNUM, + SIM_ARM_R12_REGNUM, + SIM_ARM_R13_REGNUM, + SIM_ARM_R14_REGNUM, + SIM_ARM_R15_REGNUM, /* PC */ + SIM_ARM_FP0_REGNUM, + SIM_ARM_FP1_REGNUM, + SIM_ARM_FP2_REGNUM, + SIM_ARM_FP3_REGNUM, + SIM_ARM_FP4_REGNUM, + SIM_ARM_FP5_REGNUM, + SIM_ARM_FP6_REGNUM, + SIM_ARM_FP7_REGNUM, + SIM_ARM_FPS_REGNUM, + SIM_ARM_PS_REGNUM, + SIM_ARM_MAVERIC_COP0R0_REGNUM, + SIM_ARM_MAVERIC_COP0R1_REGNUM, + SIM_ARM_MAVERIC_COP0R2_REGNUM, + SIM_ARM_MAVERIC_COP0R3_REGNUM, + SIM_ARM_MAVERIC_COP0R4_REGNUM, + SIM_ARM_MAVERIC_COP0R5_REGNUM, + SIM_ARM_MAVERIC_COP0R6_REGNUM, + SIM_ARM_MAVERIC_COP0R7_REGNUM, + SIM_ARM_MAVERIC_COP0R8_REGNUM, + SIM_ARM_MAVERIC_COP0R9_REGNUM, + SIM_ARM_MAVERIC_COP0R10_REGNUM, + SIM_ARM_MAVERIC_COP0R11_REGNUM, + SIM_ARM_MAVERIC_COP0R12_REGNUM, + SIM_ARM_MAVERIC_COP0R13_REGNUM, + SIM_ARM_MAVERIC_COP0R14_REGNUM, + SIM_ARM_MAVERIC_COP0R15_REGNUM, + SIM_ARM_MAVERIC_DSPSC_REGNUM, + SIM_ARM_IWMMXT_COP0R0_REGNUM, + SIM_ARM_IWMMXT_COP0R1_REGNUM, + SIM_ARM_IWMMXT_COP0R2_REGNUM, + SIM_ARM_IWMMXT_COP0R3_REGNUM, + SIM_ARM_IWMMXT_COP0R4_REGNUM, + SIM_ARM_IWMMXT_COP0R5_REGNUM, + SIM_ARM_IWMMXT_COP0R6_REGNUM, + SIM_ARM_IWMMXT_COP0R7_REGNUM, + SIM_ARM_IWMMXT_COP0R8_REGNUM, + SIM_ARM_IWMMXT_COP0R9_REGNUM, + SIM_ARM_IWMMXT_COP0R10_REGNUM, + SIM_ARM_IWMMXT_COP0R11_REGNUM, + SIM_ARM_IWMMXT_COP0R12_REGNUM, + SIM_ARM_IWMMXT_COP0R13_REGNUM, + SIM_ARM_IWMMXT_COP0R14_REGNUM, + SIM_ARM_IWMMXT_COP0R15_REGNUM, + SIM_ARM_IWMMXT_COP1R0_REGNUM, + SIM_ARM_IWMMXT_COP1R1_REGNUM, + SIM_ARM_IWMMXT_COP1R2_REGNUM, + SIM_ARM_IWMMXT_COP1R3_REGNUM, + SIM_ARM_IWMMXT_COP1R4_REGNUM, + SIM_ARM_IWMMXT_COP1R5_REGNUM, + SIM_ARM_IWMMXT_COP1R6_REGNUM, + SIM_ARM_IWMMXT_COP1R7_REGNUM, + SIM_ARM_IWMMXT_COP1R8_REGNUM, + SIM_ARM_IWMMXT_COP1R9_REGNUM, + SIM_ARM_IWMMXT_COP1R10_REGNUM, + SIM_ARM_IWMMXT_COP1R11_REGNUM, + SIM_ARM_IWMMXT_COP1R12_REGNUM, + SIM_ARM_IWMMXT_COP1R13_REGNUM, + SIM_ARM_IWMMXT_COP1R14_REGNUM, + SIM_ARM_IWMMXT_COP1R15_REGNUM +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/gdb/sim-d10v.h b/include/gdb/sim-d10v.h new file mode 100644 index 000000000000..8294b14858bb --- /dev/null +++ b/include/gdb/sim-d10v.h @@ -0,0 +1,142 @@ +/* This file defines the interface between the d10v simulator and gdb. + + Copyright 1999, 2002 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (SIM_D10V_H) +#define SIM_D10V_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +/* GDB interprets addresses as: + + 0x00xxxxxx: Physical unified memory segment (Unified memory) + 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) + 0x02xxxxxx: Physical data memory segment (On-chip data memory) + 0x10xxxxxx: Logical data address segment (DMAP translated memory) + 0x11xxxxxx: Logical instruction address segment (IMAP translated memory) + + The remote d10v board interprets addresses as: + + 0x00xxxxxx: Physical unified memory segment (Unified memory) + 0x01xxxxxx: Physical instruction memory segment (On-chip insn memory) + 0x02xxxxxx: Physical data memory segment (On-chip data memory) + + The following translate a virtual DMAP/IMAP offset into a physical + memory segment assigning the translated address to PHYS. Since a + memory access may cross a page boundrary the number of bytes for + which the translation is applicable (or 0 for an invalid virtual + offset) is returned. */ + +enum + { + SIM_D10V_MEMORY_UNIFIED = 0x00000000, + SIM_D10V_MEMORY_INSN = 0x01000000, + SIM_D10V_MEMORY_DATA = 0x02000000, + SIM_D10V_MEMORY_DMAP = 0x10000000, + SIM_D10V_MEMORY_IMAP = 0x11000000 + }; + +extern unsigned long sim_d10v_translate_dmap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*dmap_register) (void *regcache, int reg_nr)); + +extern unsigned long sim_d10v_translate_imap_addr + (unsigned long offset, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*imap_register) (void *regcache, int reg_nr)); + +extern unsigned long sim_d10v_translate_addr + (unsigned long vaddr, + int nr_bytes, + unsigned long *phys, + void *regcache, + unsigned long (*dmap_register) (void *regcache, int reg_nr), + unsigned long (*imap_register) (void *regcache, int reg_nr)); + + +/* The simulator makes use of the following register information. */ + +enum sim_d10v_regs +{ + SIM_D10V_R0_REGNUM, + SIM_D10V_R1_REGNUM, + SIM_D10V_R2_REGNUM, + SIM_D10V_R3_REGNUM, + SIM_D10V_R4_REGNUM, + SIM_D10V_R5_REGNUM, + SIM_D10V_R6_REGNUM, + SIM_D10V_R7_REGNUM, + SIM_D10V_R8_REGNUM, + SIM_D10V_R9_REGNUM, + SIM_D10V_R10_REGNUM, + SIM_D10V_R11_REGNUM, + SIM_D10V_R12_REGNUM, + SIM_D10V_R13_REGNUM, + SIM_D10V_R14_REGNUM, + SIM_D10V_R15_REGNUM, + SIM_D10V_CR0_REGNUM, + SIM_D10V_CR1_REGNUM, + SIM_D10V_CR2_REGNUM, + SIM_D10V_CR3_REGNUM, + SIM_D10V_CR4_REGNUM, + SIM_D10V_CR5_REGNUM, + SIM_D10V_CR6_REGNUM, + SIM_D10V_CR7_REGNUM, + SIM_D10V_CR8_REGNUM, + SIM_D10V_CR9_REGNUM, + SIM_D10V_CR10_REGNUM, + SIM_D10V_CR11_REGNUM, + SIM_D10V_CR12_REGNUM, + SIM_D10V_CR13_REGNUM, + SIM_D10V_CR14_REGNUM, + SIM_D10V_CR15_REGNUM, + SIM_D10V_A0_REGNUM, + SIM_D10V_A1_REGNUM, + SIM_D10V_SPI_REGNUM, + SIM_D10V_SPU_REGNUM, + SIM_D10V_IMAP0_REGNUM, + SIM_D10V_IMAP1_REGNUM, + SIM_D10V_DMAP0_REGNUM, + SIM_D10V_DMAP1_REGNUM, + SIM_D10V_DMAP2_REGNUM, + SIM_D10V_DMAP3_REGNUM, + SIM_D10V_TS2_DMAP_REGNUM +}; + +enum +{ + SIM_D10V_NR_R_REGS = 16, + SIM_D10V_NR_A_REGS = 2, + SIM_D10V_NR_IMAP_REGS = 2, + SIM_D10V_NR_DMAP_REGS = 4, + SIM_D10V_NR_CR_REGS = 16 +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/gdb/sim-frv.h b/include/gdb/sim-frv.h new file mode 100644 index 000000000000..0a1e0212e521 --- /dev/null +++ b/include/gdb/sim-frv.h @@ -0,0 +1,53 @@ +/* This file defines the interface between the FR-V simulator and GDB. + + Copyright 2003 Free Software Foundation, Inc. + + Contributed by Red Hat. + + This file is part of GDB. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#if !defined (SIM_FRV_H) +#define SIM_FRV_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +enum sim_frv_regs +{ + SIM_FRV_GR0_REGNUM = 0, + SIM_FRV_GR63_REGNUM = 63, + SIM_FRV_FR0_REGNUM = 64, + SIM_FRV_FR63_REGNUM = 127, + SIM_FRV_PC_REGNUM = 128, + + /* An FR-V architecture may have up to 4096 special purpose registers + (SPRs). In order to determine a specific constant used to access + a particular SPR, one of the H_SPR_ prefixed offsets defined in + opcodes/frv-desc.h should be added to SIM_FRV_SPR0_REGNUM. So, + for example, the number that GDB uses to fetch the link register + from the simulator is (SIM_FRV_SPR0_REGNUM + H_SPR_LR). */ + SIM_FRV_SPR0_REGNUM = 129, + SIM_FRV_SPR4095_REGNUM = SIM_FRV_SPR0_REGNUM + 4095 +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/gdb/sim-h8300.h b/include/gdb/sim-h8300.h new file mode 100644 index 000000000000..246370aec23a --- /dev/null +++ b/include/gdb/sim-h8300.h @@ -0,0 +1,78 @@ +/* This file defines the interface between the h8300 simulator and gdb. + Copyright (C) 2002 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (SIM_H8300_H) +#define SIM_H8300_H + +#ifdef __cplusplus +extern "C" { //} +#endif + +/* The simulator makes use of the following register information. */ + + enum sim_h8300_regs + { + /* Registers common to all the H8 variants. */ + /* Start here: */ + SIM_H8300_R0_REGNUM, + SIM_H8300_R1_REGNUM, + SIM_H8300_R2_REGNUM, + SIM_H8300_R3_REGNUM, + SIM_H8300_R4_REGNUM, + SIM_H8300_R5_REGNUM, + SIM_H8300_R6_REGNUM, + SIM_H8300_R7_REGNUM, + + SIM_H8300_CCR_REGNUM, /* Contains processor status */ + SIM_H8300_PC_REGNUM, /* Contains program counter */ + /* End here */ + + SIM_H8300_EXR_REGNUM, /* Contains extended processor status + H8S and higher */ + SIM_H8300_MACL_REGNUM, /* Lower part of MAC register (26xx only)*/ + SIM_H8300_MACH_REGNUM, /* High part of MAC register (26xx only) */ + + SIM_H8300_CYCLE_REGNUM, + SIM_H8300_INST_REGNUM, + SIM_H8300_TICK_REGNUM + }; + + enum + { + SIM_H8300_ARG_FIRST_REGNUM = SIM_H8300_R0_REGNUM, /* first reg in which an arg + may be passed */ + SIM_H8300_ARG_LAST_REGNUM = SIM_H8300_R3_REGNUM, /* last reg in which an arg + may be passed */ + SIM_H8300_FP_REGNUM = SIM_H8300_R6_REGNUM, /* Contain address of executing + stack frame */ + SIM_H8300_SP_REGNUM = SIM_H8300_R7_REGNUM /* Contains address of top of stack */ + }; + + enum + { + SIM_H8300_NUM_COMMON_REGS = 10, + SIM_H8300_S_NUM_REGS = 13, + SIM_H8300_NUM_REGS = 16 + }; + +#ifdef __cplusplus +} +#endif + +#endif /* SIM_H8300_H */ diff --git a/include/gdb/sim-sh.h b/include/gdb/sim-sh.h new file mode 100644 index 000000000000..ec0d6276b4b0 --- /dev/null +++ b/include/gdb/sim-sh.h @@ -0,0 +1,161 @@ +/* This file defines the interface between the sh simulator and gdb. + Copyright (C) 2000, 2002 Free Software Foundation, Inc. + +This file is part of GDB. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined (SIM_SH_H) +#define SIM_SH_H + +#ifdef __cplusplus +extern "C" { // } +#endif + +/* The simulator makes use of the following register information. */ + +enum +{ + SIM_SH_R0_REGNUM = 0, + SIM_SH_R1_REGNUM, + SIM_SH_R2_REGNUM, + SIM_SH_R3_REGNUM, + SIM_SH_R4_REGNUM, + SIM_SH_R5_REGNUM, + SIM_SH_R6_REGNUM, + SIM_SH_R7_REGNUM, + SIM_SH_R8_REGNUM, + SIM_SH_R9_REGNUM, + SIM_SH_R10_REGNUM, + SIM_SH_R11_REGNUM, + SIM_SH_R12_REGNUM, + SIM_SH_R13_REGNUM, + SIM_SH_R14_REGNUM, + SIM_SH_R15_REGNUM, + SIM_SH_PC_REGNUM, + SIM_SH_PR_REGNUM, + SIM_SH_GBR_REGNUM, + SIM_SH_VBR_REGNUM, + SIM_SH_MACH_REGNUM, + SIM_SH_MACL_REGNUM, + SIM_SH_SR_REGNUM, + SIM_SH_FPUL_REGNUM, + SIM_SH_FPSCR_REGNUM, + SIM_SH_FR0_REGNUM, /* FRn registers: sh3e / sh4 */ + SIM_SH_FR1_REGNUM, + SIM_SH_FR2_REGNUM, + SIM_SH_FR3_REGNUM, + SIM_SH_FR4_REGNUM, + SIM_SH_FR5_REGNUM, + SIM_SH_FR6_REGNUM, + SIM_SH_FR7_REGNUM, + SIM_SH_FR8_REGNUM, + SIM_SH_FR9_REGNUM, + SIM_SH_FR10_REGNUM, + SIM_SH_FR11_REGNUM, + SIM_SH_FR12_REGNUM, + SIM_SH_FR13_REGNUM, + SIM_SH_FR14_REGNUM, + SIM_SH_FR15_REGNUM, + SIM_SH_SSR_REGNUM, /* sh3{,e,-dsp}, sh4 */ + SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */ + SIM_SH_R0_BANK0_REGNUM, /* SIM_SH_Rn_BANKm_REGNUM: sh3[e] / sh4 */ + SIM_SH_R1_BANK0_REGNUM, + SIM_SH_R2_BANK0_REGNUM, + SIM_SH_R3_BANK0_REGNUM, + SIM_SH_R4_BANK0_REGNUM, + SIM_SH_R5_BANK0_REGNUM, + SIM_SH_R6_BANK0_REGNUM, + SIM_SH_R7_BANK0_REGNUM, + SIM_SH_R0_BANK1_REGNUM, + SIM_SH_R1_BANK1_REGNUM, + SIM_SH_R2_BANK1_REGNUM, + SIM_SH_R3_BANK1_REGNUM, + SIM_SH_R4_BANK1_REGNUM, + SIM_SH_R5_BANK1_REGNUM, + SIM_SH_R6_BANK1_REGNUM, + SIM_SH_R7_BANK1_REGNUM, + SIM_SH_XF0_REGNUM, + SIM_SH_XF1_REGNUM, + SIM_SH_XF2_REGNUM, + SIM_SH_XF3_REGNUM, + SIM_SH_XF4_REGNUM, + SIM_SH_XF5_REGNUM, + SIM_SH_XF6_REGNUM, + SIM_SH_XF7_REGNUM, + SIM_SH_XF8_REGNUM, + SIM_SH_XF9_REGNUM, + SIM_SH_XF10_REGNUM, + SIM_SH_XF11_REGNUM, + SIM_SH_XF12_REGNUM, + SIM_SH_XF13_REGNUM, + SIM_SH_XF14_REGNUM, + SIM_SH_XF15_REGNUM, + SIM_SH_SGR_REGNUM, + SIM_SH_DBR_REGNUM, + SIM_SH4_NUM_REGS, /* 77 */ + + /* sh[3]-dsp */ + SIM_SH_DSR_REGNUM, + SIM_SH_A0G_REGNUM, + SIM_SH_A0_REGNUM, + SIM_SH_A1G_REGNUM, + SIM_SH_A1_REGNUM, + SIM_SH_M0_REGNUM, + SIM_SH_M1_REGNUM, + SIM_SH_X0_REGNUM, + SIM_SH_X1_REGNUM, + SIM_SH_Y0_REGNUM, + SIM_SH_Y1_REGNUM, + SIM_SH_MOD_REGNUM, + SIM_SH_RS_REGNUM, + SIM_SH_RE_REGNUM, + SIM_SH_R0_BANK_REGNUM, + SIM_SH_R1_BANK_REGNUM, + SIM_SH_R2_BANK_REGNUM, + SIM_SH_R3_BANK_REGNUM, + SIM_SH_R4_BANK_REGNUM, + SIM_SH_R5_BANK_REGNUM, + SIM_SH_R6_BANK_REGNUM, + SIM_SH_R7_BANK_REGNUM + /* 100..127: room for expansion. */ +}; + +enum +{ + SIM_SH64_R0_REGNUM = 0, + SIM_SH64_SP_REGNUM = 15, + SIM_SH64_PC_REGNUM = 64, + SIM_SH64_SR_REGNUM = 65, + SIM_SH64_SSR_REGNUM = 66, + SIM_SH64_SPC_REGNUM = 67, + SIM_SH64_TR0_REGNUM = 68, + SIM_SH64_FPCSR_REGNUM = 76, + SIM_SH64_FR0_REGNUM = 77 +}; + +enum +{ + SIM_SH64_NR_REGS = 141, /* total number of architectural registers */ + SIM_SH64_NR_R_REGS = 64, /* number of general registers */ + SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ + SIM_SH64_NR_FP_REGS = 64 /* number of floating point registers */ +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/hp-symtab.h b/include/hp-symtab.h new file mode 100644 index 000000000000..6267d5572c46 --- /dev/null +++ b/include/hp-symtab.h @@ -0,0 +1,1866 @@ +/* Definitions and structures for reading debug symbols from the + native HP C compiler. + + Written by the Center for Software Science at the University of Utah + and by Cygnus Support. + + Copyright 1994, 1995, 1998, 1999, 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef HP_SYMTAB_INCLUDED +#define HP_SYMTAB_INCLUDED + +/* General information: + + This header file defines and describes only the data structures + necessary to read debug symbols produced by the HP C compiler, + HP ANSI C++ compiler, and HP FORTRAN 90 compiler using the + SOM object file format. + (For a full description of the debug format, ftp hpux-symtab.h from + jaguar.cs.utah.edu:/dist). + + Additional notes (Rich Title) + This file is a reverse-engineered version of a file called + "symtab.h" which exists internal to HP's Computer Languages Organization + in /CLO/Components/DDE/obj/som/symtab.h. Because HP's version of + the file is copyrighted and not distributed, it is necessary for + GDB to use the reverse-engineered version that follows. + Work was done by Cygnus to reverse-engineer the C subset of symtab.h. + The WDB project has extended this to also contain the C++ + symbol definitions, the F90 symbol definitions, + and the DOC (debugging-optimized-code) symbol definitions. + In some cases (the C++ symbol definitions) + I have added internal documentation here that + goes beyond what is supplied in HP's symtab.h. If we someday + unify these files again, the extra comments should be merged back + into HP's symtab.h. + + ------------------------------------------------------------------- + + Debug symbols are contained entirely within an unloadable space called + $DEBUG$. $DEBUG$ contains several subspaces which group related + debug symbols. + + $GNTT$ contains information for global variables, types and contants. + + $LNTT$ contains information for procedures (including nesting), scoping + information, local variables, types, and constants. + + $SLT$ contains source line information so that code addresses may be + mapped to source lines. + + $VT$ contains various strings and constants for named objects (variables, + typedefs, functions, etc). Strings are stored as null-terminated character + lists. Constants always begin on word boundaries. The first byte of + the VT must be zero (a null string). + + $XT$ is not currently used by GDB. + + Many structures within the subspaces point to other structures within + the same subspace, or to structures within a different subspace. These + pointers are represented as a structure index from the beginning of + the appropriate subspace. */ + +/* Used to describe where a constant is stored. */ +enum location_type +{ + LOCATION_IMMEDIATE, + LOCATION_PTR, + LOCATION_VT, +}; + +/* Languages supported by this debug format. Within the data structures + this type is limited to 4 bits for a maximum of 16 languages. */ +enum hp_language +{ + HP_LANGUAGE_UNKNOWN, + HP_LANGUAGE_C, + HP_LANGUAGE_FORTRAN, + HP_LANGUAGE_F77 = HP_LANGUAGE_FORTRAN, + HP_LANGUAGE_PASCAL, + HP_LANGUAGE_MODCAL, + HP_LANGUAGE_COBOL, + HP_LANGUAGE_BASIC, + HP_LANGUAGE_ADA, + HP_LANGUAGE_CPLUSPLUS, + HP_LANGUAGE_DMPASCAL +}; + + +/* Basic data types available in this debug format. Within the data + structures this type is limited to 5 bits for a maximum of 32 basic + data types. */ +enum hp_type +{ + HP_TYPE_UNDEFINED, /* 0 */ + HP_TYPE_BOOLEAN, /* 1 */ + HP_TYPE_CHAR, /* 2 */ + HP_TYPE_INT, /* 3 */ + HP_TYPE_UNSIGNED_INT, /* 4 */ + HP_TYPE_REAL, /* 5 */ + HP_TYPE_COMPLEX, /* 6 */ + HP_TYPE_STRING200, /* 7 */ + HP_TYPE_LONGSTRING200, /* 8 */ + HP_TYPE_TEXT, /* 9 */ + HP_TYPE_FLABEL, /* 10 */ + HP_TYPE_FTN_STRING_SPEC, /* 11 */ + HP_TYPE_MOD_STRING_SPEC, /* 12 */ + HP_TYPE_PACKED_DECIMAL, /* 13 */ + HP_TYPE_REAL_3000, /* 14 */ + HP_TYPE_MOD_STRING_3000, /* 15 */ + HP_TYPE_ANYPOINTER, /* 16 */ + HP_TYPE_GLOBAL_ANYPOINTER, /* 17 */ + HP_TYPE_LOCAL_ANYPOINTER, /* 18 */ + HP_TYPE_COMPLEXS3000, /* 19 */ + HP_TYPE_FTN_STRING_S300_COMPAT, /* 20 */ + HP_TYPE_FTN_STRING_VAX_COMPAT, /* 21 */ + HP_TYPE_BOOLEAN_S300_COMPAT, /* 22 */ + HP_TYPE_BOOLEAN_VAX_COMPAT, /* 23 */ + HP_TYPE_WIDE_CHAR, /* 24 */ + HP_TYPE_LONG, /* 25 */ + HP_TYPE_UNSIGNED_LONG, /* 26 */ + HP_TYPE_DOUBLE, /* 27 */ + HP_TYPE_TEMPLATE_ARG, /* 28 */ + HP_TYPE_VOID /* 29 */ +}; + +/* An immediate name and type table entry. + + extension and immediate will always be one. + global will always be zero. + hp_type is the basic type this entry describes. + bitlength is the length in bits for the basic type. */ +struct dnttp_immediate +{ + unsigned int extension: 1; + unsigned int immediate: 1; + unsigned int global: 1; + unsigned int type: 5; + unsigned int bitlength: 24; +}; + +/* A nonimmediate name and type table entry. + + extension will always be one. + immediate will always be zero. + if global is zero, this entry points into the LNTT + if global is one, this entry points into the GNTT + index is the index within the GNTT or LNTT for this entry. */ +struct dnttp_nonimmediate +{ + unsigned int extension: 1; + unsigned int immediate: 1; + unsigned int global: 1; + unsigned int index: 29; +}; + +/* A pointer to an entry in the GNTT and LNTT tables. It has two + forms depending on the type being described. + + The immediate form is used for simple entries and is one + word. + + The nonimmediate form is used for complex entries and contains + an index into the LNTT or GNTT which describes the entire type. + + If a dnttpointer is -1, then it is a NIL entry. */ + +#define DNTTNIL (-1) +typedef union dnttpointer +{ + struct dnttp_immediate dntti; + struct dnttp_nonimmediate dnttp; + int word; +} dnttpointer; + +/* An index into the source line table. As with dnttpointers, a sltpointer + of -1 indicates a NIL entry. */ +#define SLTNIL (-1) +typedef int sltpointer; + +/* Index into DOC (= "Debugging Optimized Code") line table. */ +#define LTNIL (-1) +typedef int ltpointer; + +/* Index into context table. */ +#define CTXTNIL (-1) +typedef int ctxtpointer; + +/* Unsigned byte offset into the VT. */ +typedef unsigned int vtpointer; + +/* A DNTT entry (used within the GNTT and LNTT). + + DNTT entries are variable sized objects, but are always a multiple + of 3 words (we call each group of 3 words a "block"). + + The first bit in each block is an extension bit. This bit is zero + for the first block of a DNTT entry. If the entry requires more + than one block, then this bit is set to one in all blocks after + the first one. */ + +/* Each DNTT entry describes a particular debug symbol (beginning of + a source file, a function, variables, structures, etc. + + The type of the DNTT entry is stored in the "kind" field within the + DNTT entry itself. */ + +enum dntt_entry_type +{ + DNTT_TYPE_NIL = -1, + DNTT_TYPE_SRCFILE, + DNTT_TYPE_MODULE, + DNTT_TYPE_FUNCTION, + DNTT_TYPE_ENTRY, + DNTT_TYPE_BEGIN, + DNTT_TYPE_END, + DNTT_TYPE_IMPORT, + DNTT_TYPE_LABEL, + DNTT_TYPE_FPARAM, + DNTT_TYPE_SVAR, + DNTT_TYPE_DVAR, + DNTT_TYPE_HOLE1, + DNTT_TYPE_CONST, + DNTT_TYPE_TYPEDEF, + DNTT_TYPE_TAGDEF, + DNTT_TYPE_POINTER, + DNTT_TYPE_ENUM, + DNTT_TYPE_MEMENUM, + DNTT_TYPE_SET, + DNTT_TYPE_SUBRANGE, + DNTT_TYPE_ARRAY, + DNTT_TYPE_STRUCT, + DNTT_TYPE_UNION, + DNTT_TYPE_FIELD, + DNTT_TYPE_VARIANT, + DNTT_TYPE_FILE, + DNTT_TYPE_FUNCTYPE, + DNTT_TYPE_WITH, + DNTT_TYPE_COMMON, + DNTT_TYPE_COBSTRUCT, + DNTT_TYPE_XREF, + DNTT_TYPE_SA, + DNTT_TYPE_MACRO, + DNTT_TYPE_BLOCKDATA, + DNTT_TYPE_CLASS_SCOPE, + DNTT_TYPE_REFERENCE, + DNTT_TYPE_PTRMEM, + DNTT_TYPE_PTRMEMFUNC, + DNTT_TYPE_CLASS, + DNTT_TYPE_GENFIELD, + DNTT_TYPE_VFUNC, + DNTT_TYPE_MEMACCESS, + DNTT_TYPE_INHERITANCE, + DNTT_TYPE_FRIEND_CLASS, + DNTT_TYPE_FRIEND_FUNC, + DNTT_TYPE_MODIFIER, + DNTT_TYPE_OBJECT_ID, + DNTT_TYPE_MEMFUNC, + DNTT_TYPE_TEMPLATE, + DNTT_TYPE_TEMPLATE_ARG, + DNTT_TYPE_FUNC_TEMPLATE, + DNTT_TYPE_LINK, + DNTT_TYPE_DYN_ARRAY_DESC, + DNTT_TYPE_DESC_SUBRANGE, + DNTT_TYPE_BEGIN_EXT, + DNTT_TYPE_INLN, + DNTT_TYPE_INLN_LIST, + DNTT_TYPE_ALIAS, + DNTT_TYPE_DOC_FUNCTION, + DNTT_TYPE_DOC_MEMFUNC, + DNTT_TYPE_MAX +}; + +/* DNTT_TYPE_SRCFILE: + + One DNTT_TYPE_SRCFILE symbol is output for the start of each source + file and at the begin and end of an included file. A DNTT_TYPE_SRCFILE + entry is also output before each DNTT_TYPE_FUNC symbol so that debuggers + can determine what file a function was defined in. + + LANGUAGE describes the source file's language. + + NAME points to an VT entry providing the source file's name. + + Note the name used for DNTT_TYPE_SRCFILE entries are exactly as seen + by the compiler (ie they may be relative or absolute). C include files + via <> inclusion must use absolute paths. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. */ + +struct dntt_type_srcfile +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_SRCFILE */ + unsigned int language: 4; + unsigned int unused: 17; + vtpointer name; + sltpointer address; +}; + +/* DNTT_TYPE_MODULE: + + A DNTT_TYPE_MODULE symbol is emitted for the start of a pascal + module or C source file. A module indicates a compilation unit + for name-scoping purposes; in that regard there should be + a 1-1 correspondence between GDB "symtab"'s and MODULE symbol records. + + Each DNTT_TYPE_MODULE must have an associated DNTT_TYPE_END symbol. + + NAME points to a VT entry providing the module's name. Note C + source files are considered nameless modules. + + ALIAS point to a VT entry providing a secondary name. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. */ + +struct dntt_type_module +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_MODULE */ + unsigned int unused: 21; + vtpointer name; + vtpointer alias; + dnttpointer unused2; + sltpointer address; +}; + +/* DNTT_TYPE_FUNCTION, + DNTT_TYPE_ENTRY, + DNTT_TYPE_BLOCKDATA, + DNTT_TYPE_MEMFUNC: + + A DNTT_TYPE_FUNCTION symbol is emitted for each function definition; + a DNTT_TYPE_ENTRY symbols is used for secondary entry points. Both + symbols used the dntt_type_function structure. + A DNTT_TYPE_BLOCKDATA symbol is emitted ...? + A DNTT_TYPE_MEMFUNC symbol is emitted for inlined member functions (C++). + + Each of DNTT_TYPE_FUNCTION must have a matching DNTT_TYPE_END. + + GLOBAL is nonzero if the function has global scope. + + LANGUAGE describes the function's source language. + + OPT_LEVEL describes the optimization level the function was compiled + with. + + VARARGS is nonzero if the function uses varargs. + + NAME points to a VT entry providing the function's name. + + ALIAS points to a VT entry providing a secondary name for the function. + + FIRSTPARAM points to a LNTT entry which describes the parameter list. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. + + ENTRYADDR is the memory address corresponding the function's entry point + + RETVAL points to a LNTT entry describing the function's return value. + + LOWADDR is the lowest memory address associated with this function. + + HIADDR is the highest memory address associated with this function. */ + +struct dntt_type_function +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_FUNCTION, + DNTT_TYPE_ENTRY, + DNTT_TYPE_BLOCKDATA + or DNTT_TYPE_MEMFUNC */ + unsigned int global: 1; + unsigned int language: 4; + unsigned int nest_level: 5; + unsigned int opt_level: 2; + unsigned int varargs: 1; + unsigned int lang_info: 4; + unsigned int inlined: 1; + unsigned int localalloc: 1; + unsigned int expansion: 1; + unsigned int unused: 1; + vtpointer name; + vtpointer alias; + dnttpointer firstparam; + sltpointer address; + CORE_ADDR entryaddr; + dnttpointer retval; + CORE_ADDR lowaddr; + CORE_ADDR hiaddr; +}; + +/* DNTT_TYPE_BEGIN: + + A DNTT_TYPE_BEGIN symbol is emitted to begin a new nested scope. + Every DNTT_TYPE_BEGIN symbol must have a matching DNTT_TYPE_END symbol. + + CLASSFLAG is nonzero if this is the beginning of a c++ class definition. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. */ + +struct dntt_type_begin +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int classflag: 1; + unsigned int unused: 20; + sltpointer address; +}; + +/* DNTT_TYPE_END: + + A DNTT_TYPE_END symbol is emitted when closing a scope started by + a DNTT_TYPE_MODULE, DNTT_TYPE_FUNCTION, DNTT_TYPE_WITH, + DNTT_TYPE_COMMON, DNTT_TYPE_BEGIN, and DNTT_TYPE_CLASS_SCOPE symbols. + + ENDKIND describes what type of scope the DNTT_TYPE_END is closing + (one of the above 6 kinds). + + CLASSFLAG is nonzero if this is the end of a c++ class definition. + + ADDRESS points to an SLT entry from which line number and code locations + may be determined. + + BEGINSCOPE points to the LNTT entry which opened the scope. */ + +struct dntt_type_end +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int endkind: 10; + unsigned int classflag: 1; + unsigned int unused: 10; + sltpointer address; + dnttpointer beginscope; +}; + +/* DNTT_TYPE_IMPORT is unused by GDB. */ +/* DNTT_TYPE_LABEL is unused by GDB. */ + +/* DNTT_TYPE_FPARAM: + + A DNTT_TYPE_FPARAM symbol is emitted for a function argument. When + chained together the symbols represent an argument list for a function. + + REGPARAM is nonzero if this parameter was passed in a register. + + INDIRECT is nonzero if this parameter is a pointer to the parameter + (pass by reference or pass by value for large items). + + LONGADDR is nonzero if the parameter is a 64bit pointer. + + NAME is a pointer into the VT for the parameter's name. + + LOCATION describes where the parameter is stored. Depending on the + parameter type LOCATION could be a register number, or an offset + from the stack pointer. + + TYPE points to a NTT entry describing the type of this parameter. + + NEXTPARAM points to the LNTT entry describing the next parameter. */ + +struct dntt_type_fparam +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int regparam: 1; + unsigned int indirect: 1; + unsigned int longaddr: 1; + unsigned int copyparam: 1; + unsigned int dflt: 1; + unsigned int doc_ranges: 1; + unsigned int misc_kind: 1; + unsigned int unused: 14; + vtpointer name; + CORE_ADDR location; + dnttpointer type; + dnttpointer nextparam; + int misc; +}; + +/* DNTT_TYPE_SVAR: + + A DNTT_TYPE_SVAR is emitted to describe a variable in static storage. + + GLOBAL is nonzero if the variable has global scope. + + INDIRECT is nonzero if the variable is a pointer to an object. + + LONGADDR is nonzero if the variable is in long pointer space. + + STATICMEM is nonzero if the variable is a member of a class. + + A_UNION is nonzero if the variable is an anonymous union member. + + NAME is a pointer into the VT for the variable's name. + + LOCATION provides the memory address for the variable. + + TYPE is a pointer into either the GNTT or LNTT which describes + the type of this variable. */ + +struct dntt_type_svar +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int global: 1; + unsigned int indirect: 1; + unsigned int longaddr: 1; + unsigned int staticmem: 1; + unsigned int a_union: 1; + unsigned int unused1: 1; + unsigned int thread_specific: 1; + unsigned int unused2: 14; + vtpointer name; + CORE_ADDR location; + dnttpointer type; + unsigned int offset; + unsigned int displacement; +}; + +/* DNTT_TYPE_DVAR: + + A DNTT_TYPE_DVAR is emitted to describe automatic variables and variables + held in registers. + + GLOBAL is nonzero if the variable has global scope. + + INDIRECT is nonzero if the variable is a pointer to an object. + + REGVAR is nonzero if the variable is in a register. + + A_UNION is nonzero if the variable is an anonymous union member. + + NAME is a pointer into the VT for the variable's name. + + LOCATION provides the memory address or register number for the variable. + + TYPE is a pointer into either the GNTT or LNTT which describes + the type of this variable. */ + +struct dntt_type_dvar +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int global: 1; + unsigned int indirect: 1; + unsigned int regvar: 1; + unsigned int a_union: 1; + unsigned int unused: 17; + vtpointer name; + int location; + dnttpointer type; + unsigned int offset; +}; + +/* DNTT_TYPE_CONST: + + A DNTT_TYPE_CONST symbol is emitted for program constants. + + GLOBAL is nonzero if the constant has global scope. + + INDIRECT is nonzero if the constant is a pointer to an object. + + LOCATION_TYPE describes where to find the constant's value + (in the VT, memory, or embedded in an instruction). + + CLASSMEM is nonzero if the constant is a member of a class. + + NAME is a pointer into the VT for the constant's name. + + LOCATION provides the memory address, register number or pointer + into the VT for the constant's value. + + TYPE is a pointer into either the GNTT or LNTT which describes + the type of this variable. */ + +struct dntt_type_const +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int global: 1; + unsigned int indirect: 1; + unsigned int location_type: 3; + unsigned int classmem: 1; + unsigned int unused: 15; + vtpointer name; + CORE_ADDR location; + dnttpointer type; + unsigned int offset; + unsigned int displacement; +}; + +/* DNTT_TYPE_TYPEDEF and DNTT_TYPE_TAGDEF: + + The same structure is used to describe typedefs and tagdefs. + + DNTT_TYPE_TYPEDEFS are associated with C "typedefs". + + DNTT_TYPE_TAGDEFs are associated with C "struct", "union", and "enum" + tags, which may have the same name as a typedef in the same scope. + Also they are associated with C++ "class" tags, which implicitly have + the same name as the class type. + + GLOBAL is nonzero if the typedef/tagdef has global scope. + + TYPEINFO is used to determine if full type information is available + for a tag. (usually 1, but can be zero for opaque types in C). + + NAME is a pointer into the VT for the constant's name. + + TYPE points to the underlying type for the typedef/tagdef in the + GNTT or LNTT. */ + +struct dntt_type_type +{ + unsigned int extension: 1; + unsigned int kind: 10; /* DNTT_TYPE_TYPEDEF or + DNTT_TYPE_TAGDEF. */ + unsigned int global: 1; + unsigned int typeinfo: 1; + unsigned int unused: 19; + vtpointer name; + dnttpointer type; /* Underlying type, which for TAGDEF's may be + DNTT_TYPE_STRUCT, DNTT_TYPE_UNION, + DNTT_TYPE_ENUM, or DNTT_TYPE_CLASS. + For TYPEDEF's other underlying types + are also possible. */ +}; + +/* DNTT_TYPE_POINTER: + + Used to describe a pointer to an underlying type. + + POINTSTO is a pointer into the GNTT or LNTT for the type which this + pointer points to. + + BITLENGTH is the length of the pointer (not the underlying type). */ + +struct dntt_type_pointer +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + dnttpointer pointsto; + unsigned int bitlength; +}; + + +/* DNTT_TYPE_ENUM: + + Used to describe enumerated types. + + FIRSTMEM is a pointer to a DNTT_TYPE_MEMENUM in the GNTT/LNTT which + describes the first member (and contains a pointer to the chain of + members). + + BITLENGTH is the number of bits used to hold the values of the enum's + members. */ + +struct dntt_type_enum +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + dnttpointer firstmem; + unsigned int bitlength; +}; + +/* DNTT_TYPE_MEMENUM + + Used to describe members of an enumerated type. + + CLASSMEM is nonzero if this member is part of a class. + + NAME points into the VT for the name of this member. + + VALUE is the value of this enumeration member. + + NEXTMEM points to the next DNTT_TYPE_MEMENUM in the chain. */ + +struct dntt_type_memenum +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int classmem: 1; + unsigned int unused: 20; + vtpointer name; + unsigned int value; + dnttpointer nextmem; +}; + +/* DNTT_TYPE_SET + + Used to describe PASCAL "set" type. + + DECLARATION describes the bitpacking of the set. + + SUBTYPE points to a DNTT entry describing the type of the members. + + BITLENGTH is the size of the set. */ + +struct dntt_type_set +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int declaration: 2; + unsigned int unused: 19; + dnttpointer subtype; + unsigned int bitlength; +}; + +/* DNTT_TYPE_SUBRANGE + + Used to describe subrange type. + + DYN_LOW describes the lower bound of the subrange: + + 00 for a constant lower bound (found in LOWBOUND). + + 01 for a dynamic lower bound with the lower bound found in the + memory address pointed to by LOWBOUND. + + 10 for a dynamic lower bound described by an variable found in the + DNTT/LNTT (LOWBOUND would be a pointer into the DNTT/LNTT). + + DYN_HIGH is similar to DYN_LOW, except it describes the upper bound. + + SUBTYPE points to the type of the subrange. + + BITLENGTH is the length in bits needed to describe the subrange's + values. */ + +struct dntt_type_subrange +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int dyn_low: 2; + unsigned int dyn_high: 2; + unsigned int unused: 17; + int lowbound; + int highbound; + dnttpointer subtype; + unsigned int bitlength; +}; + +/* DNTT_TYPE_ARRAY + + Used to describe an array type. + + DECLARATION describes the bit packing used in the array. + + ARRAYISBYTES is nonzero if the field in arraylength describes the + length in bytes rather than in bits. A value of zero is used to + describe an array with size 2**32. + + ELEMISBYTES is nonzero if the length if each element in the array + is describes in bytes rather than bits. A value of zero is used + to an element with size 2**32. + + ELEMORDER is nonzero if the elements are indexed in increasing order. + + JUSTIFIED if the elements are left justified to index zero. + + ARRAYLENGTH is the length of the array. + + INDEXTYPE is a DNTT pointer to the type used to index the array. + + ELEMTYPE is a DNTT pointer to the type for the array elements. + + ELEMLENGTH is the length of each element in the array (including + any padding). + + Multi-dimensional arrays are represented by ELEMTYPE pointing to + another DNTT_TYPE_ARRAY. */ + +struct dntt_type_array +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int declaration: 2; + unsigned int dyn_low: 2; + unsigned int dyn_high: 2; + unsigned int arrayisbytes: 1; + unsigned int elemisbytes: 1; + unsigned int elemorder: 1; + unsigned int justified: 1; + unsigned int unused: 11; + unsigned int arraylength; + dnttpointer indextype; + dnttpointer elemtype; + unsigned int elemlength; +}; + +/* DNTT_TYPE_STRUCT + + DNTT_TYPE_STRUCT is used to describe a C structure. + + DECLARATION describes the bitpacking used. + + FIRSTFIELD is a DNTT pointer to the first field of the structure + (each field contains a pointer to the next field, walk the list + to access all fields of the structure). + + VARTAGFIELD and VARLIST are used for Pascal variant records. + + BITLENGTH is the size of the structure in bits. */ + +struct dntt_type_struct +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int declaration: 2; + unsigned int unused: 19; + dnttpointer firstfield; + dnttpointer vartagfield; + dnttpointer varlist; + unsigned int bitlength; +}; + +/* DNTT_TYPE_UNION + + DNTT_TYPE_UNION is used to describe a C union. + + FIRSTFIELD is a DNTT pointer to the beginning of the field chain. + + BITLENGTH is the size of the union in bits. */ + +struct dntt_type_union +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + dnttpointer firstfield; + unsigned int bitlength; +}; + +/* DNTT_TYPE_FIELD + + DNTT_TYPE_FIELD describes one field in a structure or union + or C++ class. + + VISIBILITY is used to describe the visibility of the field + (for c++. public = 0, protected = 1, private = 2). + + A_UNION is nonzero if this field is a member of an anonymous union. + + STATICMEM is nonzero if this field is a static member of a template. + + NAME is a pointer into the VT for the name of the field. + + BITOFFSET gives the offset of this field in bits from the beginning + of the structure or union this field is a member of. + + TYPE is a DNTT pointer to the type describing this field. + + BITLENGTH is the size of the entry in bits. + + NEXTFIELD is a DNTT pointer to the next field in the chain. */ + +struct dntt_type_field +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int visibility: 2; + unsigned int a_union: 1; + unsigned int staticmem: 1; + unsigned int unused: 17; + vtpointer name; + unsigned int bitoffset; + dnttpointer type; + unsigned int bitlength; + dnttpointer nextfield; +}; + +/* DNTT_TYPE_VARIANT is unused by GDB. */ +/* DNTT_TYPE_FILE is unused by GDB. */ + +/* DNTT_TYPE_FUNCTYPE + + I think this is used to describe a function type (e.g., would + be emitted as part of a function-pointer description). + + VARARGS is nonzero if this function uses varargs. + + FIRSTPARAM is a DNTT pointer to the first entry in the parameter + chain. + + RETVAL is a DNTT pointer to the type of the return value. */ + +struct dntt_type_functype +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int varargs: 1; + unsigned int info: 4; + unsigned int unused: 16; + unsigned int bitlength; + dnttpointer firstparam; + dnttpointer retval; +}; + +/* DNTT_TYPE_WITH is emitted by C++ to indicate "with" scoping semantics. + (Probably also emitted by PASCAL to support "with"...). + + C++ example: Say "memfunc" is a method of class "c", and say + "m" is a data member of class "c". Then from within "memfunc", + it is legal to reference "m" directly (e.g. you don't have to + say "this->m". The symbol table indicates + this by emitting a DNTT_TYPE_WITH symbol within the function "memfunc", + pointing to the type symbol for class "c". + + In GDB, this symbol record is unnecessary, + because GDB's symbol lookup algorithm + infers the "with" semantics when it sees a "this" argument to the member + function. So GDB can safely ignore the DNTT_TYPE_WITH record. + + A DNTT_TYPE_WITH has a matching DNTT_TYPE_END symbol. */ + +struct dntt_type_with +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_WITH */ + unsigned int addrtype: 2; /* 0 => STATTYPE */ + /* 1 => DYNTYPE */ + /* 2 => REGTYPE */ + unsigned int indirect: 1; /* 1 => pointer to object */ + unsigned int longaddr: 1; /* 1 => in long pointer space */ + unsigned int nestlevel: 6; /* # of nesting levels back */ + unsigned int doc_ranges: 1; /* 1 => location is range list */ + unsigned int unused: 10; + long location; /* where stored (allocated) */ + sltpointer address; + dnttpointer type; /* type of with expression */ + vtpointer name; /* name of with expression */ + unsigned long offset; /* byte offset from location */ +}; + +/* DNTT_TYPE_COMMON is unsupported by GDB. */ +/* A DNTT_TYPE_COMMON symbol must have a matching DNTT_TYPE_END symbol */ + +/* DNTT_TYPE_COBSTRUCT is unsupported by GDB. */ +/* DNTT_TYPE_XREF is unsupported by GDB. */ +/* DNTT_TYPE_SA is unsupported by GDB. */ +/* DNTT_TYPE_MACRO is unsupported by GDB */ + +/* DNTT_TYPE_BLOCKDATA has the same structure as DNTT_TYPE_FUNCTION */ + +/* The following are the C++ specific SOM records */ + +/* The purpose of the DNTT_TYPE_CLASS_SCOPE is to bracket C++ methods + and indicate the method name belongs in the "class scope" rather + than in the module they are being defined in. For example: + + class c { + ... + void memfunc(); // member function + }; + + void c::memfunc() // definition of class c's "memfunc" + { + ... + } + + main() + { + ... + } + + In the above, the name "memfunc" is not directly visible from "main". + I.e., you have to say "break c::memfunc". + If it were a normal function (not a method), it would be visible + via the simple "break memfunc". Since "memfunc" otherwise looks + like a normal FUNCTION in the symbol table, the bracketing + CLASS_SCOPE is what is used to indicate it is really a method. + + + A DNTT_TYPE_CLASS_SCOPE symbol must have a matching DNTT_TYPE_END symbol. */ + +struct dntt_type_class_scope +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_CLASS_SCOPE. */ + unsigned int unused: 21; + sltpointer address ; /* Pointer to SLT entry. */ + dnttpointer type ; /* Pointer to class type DNTT. */ +}; + +/* C++ reference parameter. + The structure of this record is the same as DNTT_TYPE_POINTER - + refer to struct dntt_type_pointer. */ + +/* The next two describe C++ pointer-to-data-member type, and + pointer-to-member-function type, respectively. + DNTT_TYPE_PTRMEM and DNTT_TYPE_PTRMEMFUNC have the same structure. */ + +struct dntt_type_ptrmem +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_PTRMEM. */ + unsigned int unused: 21; + dnttpointer pointsto ; /* Pointer to class DNTT. */ + dnttpointer memtype ; /* Type of member. */ +}; + +struct dntt_type_ptrmemfunc +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_PTRMEMFUNC. */ + unsigned int unused: 21; + dnttpointer pointsto ; /* Pointer to class DNTT. */ + dnttpointer memtype ; /* Type of member. */ +}; + +/* The DNTT_TYPE_CLASS symbol is emitted to describe a class type. + "memberlist" points to a chained list of FIELD or GENFIELD records + indicating the class members. "parentlist" points to a chained list + of INHERITANCE records indicating classes from which we inherit + fields. */ + +struct dntt_type_class +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_CLASS. */ + unsigned int abstract: 1; /* Is this an abstract class? */ + unsigned int class_decl: 2; /* 0=class,1=union,2=struct. */ + unsigned int expansion: 1; /* 1=template expansion. */ + unsigned int unused: 17; + dnttpointer memberlist ; /* Ptr to chain of [GEN]FIELDs. */ + unsigned long vtbl_loc ; /* Offset in obj of ptr to vtbl. */ + dnttpointer parentlist ; /* Ptr to K_INHERITANCE list. */ + unsigned long bitlength ; /* Total at this level. */ + dnttpointer identlist ; /* Ptr to chain of class ident's. */ + dnttpointer friendlist ; /* Ptr to K_FRIEND list. */ + dnttpointer templateptr ; /* Ptr to template. */ + dnttpointer nextexp ; /* Ptr to next expansion. */ +}; + +/* Class members are indicated via either the FIELD record (for + data members, same as for C struct fields), or by the GENFIELD record + (for member functions). */ + +struct dntt_type_genfield +{ + unsigned int extension: 1; /* Always zero. */ + unsigned int kind: 10; /* Always DNTT_TYPE_GENFIELD. */ + unsigned int visibility: 2; /* Pub = 0, prot = 1, priv = 2. */ + unsigned int a_union: 1; /* 1 => anonymous union member. */ + unsigned int unused: 18; + dnttpointer field ; /* Pointer to field or qualifier. */ + dnttpointer nextfield ; /* Pointer to next field. */ +}; + +/* C++ virtual functions. */ + +struct dntt_type_vfunc +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_VFUNC */ + unsigned int pure: 1; /* pure virtual function ? */ + unsigned int unused: 20; + dnttpointer funcptr ; /* points to FUNCTION symbol */ + unsigned long vtbl_offset ; /* offset into vtbl for virtual */ +}; + +/* Not precisely sure what this is intended for - DDE ignores it. */ + +struct dntt_type_memaccess +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_MEMACCESS */ + unsigned int unused: 21; + dnttpointer classptr ; /* pointer to base class */ + dnttpointer field ; /* pointer field */ +}; + +/* The DNTT_TYPE_INHERITANCE record describes derived classes. + In particular, the "parentlist" field of the CLASS record points + to a list of INHERITANCE records for classes from which we + inherit members. */ + +struct dntt_type_inheritance +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_INHERITANCE */ + unsigned int Virtual: 1; /* virtual base class ? */ + unsigned int visibility: 2; /* pub = 0, prot = 1, priv = 2 */ + unsigned int unused: 18; + dnttpointer classname ; /* first parent class, if any */ + unsigned long offset ; /* offset to start of base class */ + dnttpointer next ; /* pointer to next K_INHERITANCE */ + unsigned long future[2] ; /* padding to 3-word block end */ +}; + +/* C++ "friend" classes ... */ + +struct dntt_type_friend_class +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_FRIEND_CLASS */ + unsigned int unused: 21; + dnttpointer classptr ; /* pointer to class DNTT */ + dnttpointer next ; /* next DNTT_FRIEND */ +}; + +struct dntt_type_friend_func +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_FRIEND_FUNC */ + unsigned int unused: 21; + dnttpointer funcptr ; /* pointer to function */ + dnttpointer classptr ; /* pointer to class DNTT */ + dnttpointer next ; /* next DNTT_FRIEND */ + unsigned long future[2] ; /* padding to 3-word block end */ +}; + +/* DDE appears to ignore the DNTT_TYPE_MODIFIER record. + It could perhaps be used to give better "ptype" output in GDB; + otherwise it is probably safe for GDB to ignore it also. */ + +struct dntt_type_modifier +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_MODIFIER */ + unsigned int m_const: 1; /* const */ + unsigned int m_static: 1; /* static */ + unsigned int m_void: 1; /* void */ + unsigned int m_volatile: 1; /* volatile */ + unsigned int m_duplicate: 1; /* duplicate */ + unsigned int unused: 16; + dnttpointer type ; /* subtype */ + unsigned long future ; /* padding to 3-word block end */ +}; + +/* I'm not sure what this was intended for - DDE ignores it. */ + +struct dntt_type_object_id +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_OBJECT_ID */ + unsigned int indirect: 1; /* Is object_ident addr of addr? */ + unsigned int unused: 20; + unsigned long object_ident ; /* object identifier */ + unsigned long offset ; /* offset to start of base class */ + dnttpointer next ; /* pointer to next K_OBJECT_ID */ + unsigned long segoffset ; /* for linker fixup */ + unsigned long future ; /* padding to 3-word block end */ +}; + +/* No separate dntt_type_memfunc; same as dntt_type_func */ + +/* Symbol records to support templates. These only get used + in DDE's "describe" output (like GDB's "ptype"). */ + +/* The TEMPLATE record is the header for a template-class. + Like the CLASS record, a TEMPLATE record has a memberlist that + points to a list of template members. It also has an arglist + pointing to a list of TEMPLATE_ARG records. */ + +struct dntt_type_template +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_TEMPLATE */ + unsigned int abstract: 1; /* is this an abstract class? */ + unsigned int class_decl: 2; /* 0=class,1=union,2=struct */ + unsigned int unused: 18; + dnttpointer memberlist ; /* ptr to chain of K_[GEN]FIELDs */ + long unused2 ; /* offset in obj of ptr to vtbl */ + dnttpointer parentlist ; /* ptr to K_INHERITANCE list */ + unsigned long bitlength ; /* total at this level */ + dnttpointer identlist ; /* ptr to chain of class ident's */ + dnttpointer friendlist ; /* ptr to K_FRIEND list */ + dnttpointer arglist ; /* ptr to argument list */ + dnttpointer expansions ; /* ptr to expansion list */ +}; + +/* Template-class arguments are a list of TEMPL_ARG records + chained together. The "name" field is the name of the formal. + E.g.: + + template <class T> class q { ... }; + + Then "T" is the name of the formal argument. */ + +struct dntt_type_templ_arg +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_TEMPL_ARG */ + unsigned int usagetype: 1; /* 0 type-name 1 expression */ + unsigned int unused: 20; + vtpointer name ; /* name of argument */ + dnttpointer type ; /* for non type arguments */ + dnttpointer nextarg ; /* Next argument if any */ + long future[2] ; /* padding to 3-word block end */ +}; + +/* FUNC_TEMPLATE records are sort of like FUNCTION, but are emitted + for template member functions. E.g., + + template <class T> class q + { + ... + void f(); + ... + }; + + Within the list of FIELDs/GENFIELDs defining the member list + of the template "q", "f" would appear as a FUNC_TEMPLATE. + We'll also see instances of FUNCTION "f" records for each + instantiation of the template. */ + +struct dntt_type_func_template +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_FUNC_TEMPLATE */ + unsigned int public: 1; /* 1 => globally visible */ + unsigned int language: 4; /* type of language */ + unsigned int level: 5; /* nesting level (top level = 0)*/ + unsigned int optimize: 2; /* level of optimization */ + unsigned int varargs: 1; /* ellipses. Pascal/800 later */ + unsigned int info: 4; /* lang-specific stuff; F_xxxx */ + unsigned int inlined: 1; + unsigned int localloc: 1; /* 0 at top, 1 at end of block */ + unsigned int unused: 2; + vtpointer name ; /* name of function */ + vtpointer alias ; /* alternate name, if any */ + dnttpointer firstparam ; /* first FPARAM, if any */ + dnttpointer retval ; /* return type, if any */ + dnttpointer arglist ; /* ptr to argument list */ +}; + +/* LINK is apparently intended to link together function template + definitions with their instantiations. However, it is not clear + why this would be needed, except to provide the information on + a "ptype" command. And as far as I can tell, aCC does not + generate this record. */ + +struct dntt_type_link +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* always DNTT_TYPE_LINK */ + unsigned int linkKind: 4; /* always LINK_UNKNOWN */ + unsigned int unused: 17; + long future1 ; /* expansion */ + dnttpointer ptr1 ; /* link from template */ + dnttpointer ptr2 ; /* to expansion */ + long future[2] ; /* padding to 3-word block end */ +}; + +/* end of C++ specific SOM's. */ + +/* DNTT_TYPE_DYN_ARRAY_DESC is unused by GDB */ +/* DNTT_TYPE_DESC_SUBRANGE is unused by GDB */ +/* DNTT_TYPE_BEGIN_EXT is unused by GDB */ +/* DNTT_TYPE_INLN is unused by GDB */ +/* DNTT_TYPE_INLN_LIST is unused by GDB */ +/* DNTT_TYPE_ALIAS is unused by GDB */ + +struct dntt_type_doc_function +{ + unsigned int extension: 1; /* always zero */ + unsigned int kind: 10; /* K_DOC_FUNCTION or */ + /* K_DOC_MEMFUNC */ + unsigned int global: 1; /* 1 => globally visible */ + unsigned int language: 4; /* type of language */ + unsigned int level: 5; /* nesting level (top level = 0)*/ + unsigned int optimize: 2; /* level of optimization */ + unsigned int varargs: 1; /* ellipses. Pascal/800 later */ + unsigned int info: 4; /* lang-specific stuff; F_xxxx */ + unsigned int inlined: 1; + unsigned int localloc: 1; /* 0 at top, 1 at end of block */ + unsigned int expansion: 1; /* 1 = function expansion */ + unsigned int doc_clone: 1; + vtpointer name; /* name of function */ + vtpointer alias; /* alternate name, if any */ + dnttpointer firstparam; /* first FPARAM, if any */ + sltpointer address; /* code and text locations */ + CORE_ADDR entryaddr; /* address of entry point */ + dnttpointer retval; /* return type, if any */ + CORE_ADDR lowaddr; /* lowest address of function */ + CORE_ADDR hiaddr; /* highest address of function */ + dnttpointer inline_list; /* pointer to first inline */ + ltpointer lt_offset; /* start of frag/cp line table */ + ctxtpointer ctxt_offset; /* start of context table for this routine */ +}; + +/* DNTT_TYPE_DOC_MEMFUNC is unused by GDB */ + +/* DNTT_TYPE_GENERIC and DNTT_TYPE_BLOCK are convience structures + so we can examine a DNTT entry in a generic fashion. */ +struct dntt_type_generic +{ + unsigned int word[9]; +}; + +struct dntt_type_block +{ + unsigned int extension: 1; + unsigned int kind: 10; + unsigned int unused: 21; + unsigned int word[2]; +}; + +/* One entry in a DNTT (either the LNTT or GNTT). + This is a union of the above 60 or so structure definitions. */ + +union dnttentry +{ + struct dntt_type_srcfile dsfile; + struct dntt_type_module dmodule; + struct dntt_type_function dfunc; + struct dntt_type_function dentry; + struct dntt_type_begin dbegin; + struct dntt_type_end dend; + struct dntt_type_fparam dfparam; + struct dntt_type_svar dsvar; + struct dntt_type_dvar ddvar; + struct dntt_type_const dconst; + struct dntt_type_type dtype; + struct dntt_type_type dtag; + struct dntt_type_pointer dptr; + struct dntt_type_enum denum; + struct dntt_type_memenum dmember; + struct dntt_type_set dset; + struct dntt_type_subrange dsubr; + struct dntt_type_array darray; + struct dntt_type_struct dstruct; + struct dntt_type_union dunion; + struct dntt_type_field dfield; + struct dntt_type_functype dfunctype; + struct dntt_type_with dwith; + struct dntt_type_function dblockdata; + struct dntt_type_class_scope dclass_scope; + struct dntt_type_pointer dreference; + struct dntt_type_ptrmem dptrmem; + struct dntt_type_ptrmemfunc dptrmemfunc; + struct dntt_type_class dclass; + struct dntt_type_genfield dgenfield; + struct dntt_type_vfunc dvfunc; + struct dntt_type_memaccess dmemaccess; + struct dntt_type_inheritance dinheritance; + struct dntt_type_friend_class dfriend_class; + struct dntt_type_friend_func dfriend_func; + struct dntt_type_modifier dmodifier; + struct dntt_type_object_id dobject_id; + struct dntt_type_template dtemplate; + struct dntt_type_templ_arg dtempl_arg; + struct dntt_type_func_template dfunc_template; + struct dntt_type_link dlink; + struct dntt_type_doc_function ddocfunc; + struct dntt_type_generic dgeneric; + struct dntt_type_block dblock; +}; + +/* Source line entry types. */ +enum slttype +{ + SLT_NORMAL, + SLT_SRCFILE, + SLT_MODULE, + SLT_FUNCTION, + SLT_ENTRY, + SLT_BEGIN, + SLT_END, + SLT_WITH, + SLT_EXIT, + SLT_ASSIST, + SLT_MARKER, + SLT_CLASS_SCOPE, + SLT_INLN, + SLT_NORMAL_OFFSET, +}; + +/* A normal source line entry. Simply provides a mapping of a source + line number to a code address. + + SLTDESC will always be SLT_NORMAL or SLT_EXIT. */ + +struct slt_normal +{ + unsigned int sltdesc: 4; + unsigned int line: 28; + CORE_ADDR address; +}; + +struct slt_normal_off +{ + unsigned int sltdesc: 4; + unsigned int offset: 6; + unsigned int line: 22; + CORE_ADDR address; +}; + +/* A special source line entry. Provides a mapping of a declaration + to a line number. These entries point back into the DNTT which + references them. */ + +struct slt_special +{ + unsigned int sltdesc: 4; + unsigned int line: 28; + dnttpointer backptr; +}; + +/* Used to describe nesting. + + For nested languages, an slt_assist entry must follow each SLT_FUNC + entry in the SLT. The address field will point forward to the + first slt_normal entry within the function's scope. */ + +struct slt_assist +{ + unsigned int sltdesc: 4; + unsigned int unused: 28; + sltpointer address; +}; + +struct slt_generic +{ + unsigned int word[2]; +}; + +union sltentry +{ + struct slt_normal snorm; + struct slt_normal_off snormoff; + struct slt_special sspec; + struct slt_assist sasst; + struct slt_generic sgeneric; +}; + +/* $LINES$ declarations + This is the line table used for optimized code, which is only present + in the new $PROGRAM_INFO$ debug space. */ + +#define DST_LN_ESCAPE_FLAG1 15 +#define DST_LN_ESCAPE_FLAG2 14 +#define DST_LN_CTX_SPEC1 13 +#define DST_LN_CTX_SPEC2 12 + +/* Escape function codes: */ + +typedef enum +{ + dst_ln_pad, /* pad byte */ + dst_ln_escape_1, /* reserved */ + dst_ln_dpc1_dln1, /* 1 byte line delta, 1 byte pc delta */ + dst_ln_dpc2_dln2, /* 2 bytes line delta, 2 bytes pc delta */ + dst_ln_pc4_ln4, /* 4 bytes ABSOLUTE line number, 4 bytes ABSOLUTE pc */ + dst_ln_dpc0_dln1, /* 1 byte line delta, pc delta = 0 */ + dst_ln_ln_off_1, /* statement escape, stmt # = 1 (2nd stmt on line) */ + dst_ln_ln_off, /* statement escape, stmt # = next byte */ + dst_ln_entry, /* entry escape, next byte is entry number */ + dst_ln_exit, /* exit escape */ + dst_ln_stmt_end, /* gap escape, 4 bytes pc delta */ + dst_ln_stmt_cp, /* current stmt is a critical point */ + dst_ln_escape_12, /* reserved */ + dst_ln_escape_13, /* this is an exception site record */ + dst_ln_nxt_byte, /* next byte contains the real escape code */ + dst_ln_end, /* end escape, final entry follows */ + dst_ln_escape1_END_OF_ENUM +} +dst_ln_escape1_t; + +typedef enum +{ + dst_ln_ctx_1, /* next byte describes context switch with 5-bit */ + /* index into the image table and 3-bit run length. */ + /* If run length is 0, end with another cxt specifier or ctx_end */ + dst_ln_ctx_2, /* next 2 bytes switch context: 13 bit index, 3 bit run length */ + dst_ln_ctx_4, /* next 4 bytes switch context: 29 bit index, 3 bit run length */ + dst_ln_ctx_end, /* end current context */ + dst_ln_col_run_1, /* next byte is column position of start of next statement, */ + /* following byte is length of statement */ + dst_ln_col_run_2, /* next 2 bytes is column position of start of next statement, */ + /* following 2 bytes is length of statement */ + dst_ln_init_base1, /* next 4 bytes are absolute PC, followed by 1 byte of line number */ + dst_ln_init_base2, /* next 4 bytes are absolute PC, followed by 2 bytes of line number */ + dst_ln_init_base3, /* next 4 bytes are absolute PC, followed by 3 bytes of line number */ + dst_ln_escape2_END_OF_ENUM +} +dst_ln_escape2_t; + +typedef union +{ + struct + { + unsigned int pc_delta : 4; /* 4 bit pc delta */ + int ln_delta : 4; /* 4 bit line number delta */ + } + delta; + + struct + { + unsigned int esc_flag : 4; /* alias for pc_delta */ + unsigned int esc_code : 4; /* escape function code (dst_ln_escape1_t, or ...2_t */ + } + esc; + + struct + { + unsigned int esc_flag : 4; /* dst_ln_ctx_spec1, or dst_ln_ctx_spec2 */ + unsigned int run_length : 2; + unsigned int ctx_index : 2; /* ...spec2 contains index; ...spec1, index - 4 */ + } + ctx_spec; + + char sdata; /* signed data byte */ + unsigned char udata; /* unsigned data byte */ +} +dst_ln_entry_t, + * dst_ln_entry_ptr_t; + +/* Warning: although the above union occupies only 1 byte the compiler treats + it as having size 2 (the minimum size of a struct). Therefore a sequence of + dst_ln_entry_t's cannot be described as an array, and walking through such a + sequence requires convoluted code such as + ln_ptr = (dst_ln_entry_ptr_t) (char*) ln_ptr + 1 + We regret the inconvenience. */ + +/* Structure for interpreting the byte following a dst_ln_ctx1 entry. */ +typedef struct +{ + unsigned int ctx1_index : 5; /* 5 bit index into context table */ + unsigned int ctx1_run_length : 3; /* 3 bit run length */ +} dst_ln_ctx1_t, + *dst_ln_ctx1_ptr_t; + +/* Structure for interpreting the bytes following a dst_ln_ctx2 entry. */ +typedef struct +{ + unsigned int ctx2_index : 13; /* 13 bit index into context table */ + unsigned int ctx2_run_length : 3; /* 3 bit run length */ +} dst_ln_ctx2_t, + *dst_ln_ctx2_ptr_t; + +/* Structure for interpreting the bytes following a dst_ln_ctx4 entry. */ +typedef struct +{ + unsigned int ctx4_index : 29; /* 29 bit index into context table */ + unsigned int ctx4_run_length : 3; /* 3 bit run length */ +} dst_ln_ctx4_t, + *dst_ln_ctx4_ptr_t; + + +/* PXDB definitions. + + PXDB is a post-processor which takes the executable file + and massages the debug information so that the debugger may + start up and run more efficiently. Some of the tasks + performed by PXDB are: + + o Remove duplicate global type and variable information + from the GNTT, + + o Append the GNTT onto the end of the LNTT and place both + back in the LNTT section, + + o Build quick look-up tables (description follows) for + files, procedures, modules, and paragraphs (for Cobol), + placing these in the GNTT section, + + o Reconstruct the header appearing in the header section + to access this information. + + The "quick look-up" tables are in the $GNTT$ sub-space, in + the following order: + + Procedures -sorted by address + Source files -sorted by address (of the + generated code from routines) + Modules -sorted by address + Classes -<unsorted?> + Address Alias -sorted by index <?> + Object IDs -sorted by object identifier + + Most quick entries have (0-based) indices into the LNTT tables to + the full entries for the item it describes. + + The post-PXDB header is in the $HEADER$ sub-space. Alas, it + occurs in different forms, depending on the optimization level + in the compilation step and whether PXDB was run or not. The + worst part is the forms aren't self-describing, so we'll have + to grovel in the bits to figure out what kind we're looking at + (see hp_get_header in hp-psymtab-read.c). */ + +/* PXDB versions. */ + +#define PXDB_VERSION_CPLUSPLUS 1 +#define PXDB_VERSION_7_4 2 +#define PXDB_VERSION_CPP_30 3 +#define PXDB_VERSION_DDE_3_2A 4 +#define PXDB_VERSION_DDE_3_2 5 +#define PXDB_VERSION_DDE_4_0 6 + +#define PXDB_VERSION_2_1 1 + +/* Header version for the case that there is no DOC info + but the executable has been processed by pxdb (the easy + case, from "cc -g"). */ + +typedef struct PXDB_struct +{ + int pd_entries; /* # of entries in function look-up table */ + int fd_entries; /* # of entries in file look-up table */ + int md_entries; /* # of entries in module look-up table */ + unsigned int pxdbed : 1; /* 1 => file has been preprocessed */ + unsigned int bighdr : 1; /* 1 => this header contains 'time' word */ + unsigned int sa_header : 1;/* 1 => created by SA version of pxdb */ + /* used for version check in xdb */ + unsigned int inlined: 1; /* one or more functions have been inlined */ + unsigned int spare:12; + short version; /* pxdb header version */ + int globals; /* index into the DNTT where GNTT begins */ + unsigned int time; /* modify time of file before being pxdbed */ + int pg_entries; /* # of entries in label look-up table */ + int functions; /* actual number of functions */ + int files; /* actual number of files */ + int cd_entries; /* # of entries in class look-up table */ + int aa_entries; /* # of entries in addr alias look-up table */ + int oi_entries; /* # of entries in object id look-up table */ +} PXDB_header, *PXDB_header_ptr; + +/* Header version for the case that there is no DOC info and the + executable has NOT been processed by pxdb. */ + +typedef struct XDB_header_struct +{ + long gntt_length; + long lntt_length; + long slt_length; + long vt_length; + long xt_length; +} XDB_header; + +/* Header version for the case that there is DOC info and the + executable has been processed by pxdb. */ + +typedef struct DOC_info_PXDB_header_struct +{ + unsigned int xdb_header: 1; /* bit set if this is post-3.1 xdb */ + unsigned int doc_header: 1; /* bit set if this is doc-style header */ + unsigned int version: 8; /* version of pxdb see defines + PXDB_VERSION_* in this file. */ + unsigned int reserved_for_flags: 16;/* for future use; -- must be + set to zero. */ + unsigned int has_aux_pd_table: 1; /* $GNTT$ has aux PD table */ + unsigned int has_expr_table: 1; /* space has $EXPR$ */ + unsigned int has_range_table: 1; /* space has $RANGE$ */ + unsigned int has_context_table: 1; /* space has $SRC_CTXT$ */ + unsigned int has_lines_table: 1; /* space contains a $LINES$ + subspace for line tables. */ + unsigned int has_lt_offset_map: 1; /* space contains an lt_offset + subspace for line table mapping. */ + /* The following fields are the same as those in the PXDB_header in $DEBUG$ */ + int pd_entries; /* # of entries in function look-up table */ + int fd_entries; /* # of entries in file look-up table */ + int md_entries; /* # of entries in module look-up table */ + unsigned int pxdbed : 1; /* 1 => file has been preprocessed */ + unsigned int bighdr : 1; /* 1 => this header contains 'time' word */ + unsigned int sa_header : 1;/* 1 => created by SA version of pxdb */ + /* used for version check in xdb */ + unsigned int inlined: 1; /* one or more functions have been inlined */ + unsigned int spare : 28; + int globals; /* index into the DNTT where GNTT begins */ + unsigned int time; /* modify time of file before being pxdbed */ + int pg_entries; /* # of entries in label look-up table */ + int functions; /* actual number of functions */ + int files; /* actual number of files */ + int cd_entries; /* # of entries in class look-up table */ + int aa_entries; /* # of entries in addr alias look-up table */ + int oi_entries; /* # of entries in object id look-up table */ +} DOC_info_PXDB_header; + +/* Header version for the case that there is DOC info and the + executable has NOT been processed by pxdb. */ + +typedef struct DOC_info_header_struct +{ + unsigned int xdb_header: 1; /* bit set if this is post-3.1 xdb */ + unsigned int doc_header: 1; /* bit set if this is doc-style header*/ + unsigned int version: 8; /* version of debug/header + format. For 10.0 the value + will be 1. For "Davis" the value is 2. */ + unsigned int reserved_for_flags: 18; /* for future use; -- must be set to zero. */ + unsigned int has_range_table: 1; /* space contains a $RANGE$ subspace for variable ranges. */ + unsigned int has_context_table: 1; /* space contains a $CTXT$ subspace for context/inline table. */ + unsigned int has_lines_table: 1; /* space contains a $LINES$ subspace for line tables. */ + unsigned int has_lt_offset_map: 1; /* space contains an lt_offset subspace for line table mapping. */ + + long gntt_length; /* same as old header */ + long lntt_length; /* same as old header */ + long slt_length; /* same as old header */ + long vt_length; /* same as old header */ + long xt_length; /* same as old header */ + long ctxt_length; /* present only if version >= 2 */ + long range_length; /* present only if version >= 2 */ + long expr_length; /* present only if version >= 2 */ + +} DOC_info_header; + +typedef union GenericDebugHeader_union +{ + PXDB_header no_doc; + DOC_info_PXDB_header doc; + XDB_header no_pxdb_no_doc; + DOC_info_header no_pxdb_doc; +} GenericDebugHeader; + + +/* Procedure Descriptor: + An element of the procedure quick look-up table. */ + +typedef struct quick_procedure +{ + long isym; /* 0-based index of first symbol + for procedure in $LNTT$, + i.e. the procedure itself. */ + CORE_ADDR adrStart; /* memory adr of start of proc */ + CORE_ADDR adrEnd; /* memory adr of end of proc */ + char *sbAlias; /* alias name of procedure */ + char *sbProc; /* real name of procedure */ + CORE_ADDR adrBp; /* address of entry breakpoint */ + CORE_ADDR adrExitBp; /* address of exit breakpoint */ + int icd; /* member of this class (index) */ + unsigned int ipd; /* index of template for this */ + /* function (index) */ + unsigned int unused: 5; + unsigned int no_lt_offset: 1;/* no entry in lt_offset table */ + unsigned int fTemplate: 1; /* function template */ + unsigned int fExpansion: 1; /* function expansion */ + unsigned int linked : 1; /* linked with other expansions */ + unsigned int duplicate: 1; /* clone of another procedure */ + unsigned int overloaded:1; /* overloaded function */ + unsigned int member: 1; /* class member function */ + unsigned int constructor:1; /* constructor function */ + unsigned int destructor:1; /* destructor function */ + unsigned int Static: 1; /* static function */ + unsigned int Virtual: 1; /* virtual function */ + unsigned int constant: 1; /* constant function */ + unsigned int pure: 1; /* pure (virtual) function */ + unsigned int language: 4; /* procedure's language */ + unsigned int inlined: 1; /* function has been inlined */ + unsigned int Operator: 1; /* operator function */ + unsigned int stub: 1; /* bodyless function */ + unsigned int optimize: 2; /* optimization level */ + unsigned int level: 5; /* nesting level (top=0) */ +} quick_procedure_entry, *quick_procedure_entry_ptr; + +/* Source File Descriptor: + An element of the source file quick look-up table. */ + +typedef struct quick_source +{ + long isym; /* 0-based index in $LNTT$ of + first symbol for this file. */ + CORE_ADDR adrStart; /* mem adr of start of file's code */ + CORE_ADDR adrEnd; /* mem adr of end of file's code */ + char *sbFile; /* name of source file */ + unsigned int fHasDecl: 1; /* do we have a .d file? */ + unsigned int fWarned: 1; /* have warned about age problems? */ + unsigned int fSrcfile: 1; /* 0 => include 1=> source */ + unsigned short ilnMac; /* lines in file (0 if don't know) */ + int ipd; /* 0-based index of first procedure + in this file, in the quick + look-up table of procedures. */ + unsigned int *rgLn; /* line pointer array, if any */ +} quick_file_entry, *quick_file_entry_ptr; + +/* Module Descriptor: + An element of the module quick reference table. */ + +typedef struct quick_module +{ + long isym; /* 0-based index of first + symbol for module. */ + CORE_ADDR adrStart; /* adr of start of mod. */ + CORE_ADDR adrEnd; /* adr of end of mod. */ + char *sbAlias; /* alias name of module */ + char *sbMod; /* real name of module */ + unsigned int imports: 1; /* module have any imports? */ + unsigned int vars_in_front: 1; /* module globals in front? */ + unsigned int vars_in_gaps: 1; /* module globals in gaps? */ + unsigned int language: 4; /* type of language */ + unsigned int unused : 25; + unsigned int unused2; /* space for future stuff */ +} quick_module_entry, *quick_module_entry_ptr; + +/* Auxiliary Procedure Descriptor: + An element of the auxiliary procedure quick look-up table. */ + +typedef struct quick_aux_procedure +{ + long isym_inln; /* start on inline list for proc */ + long spare; +} quick_aux_procedure_entry, *quick_aux_procedure_entry_ptr; + +/* Paragraph Descriptor: + An element of the paragraph quick look-up table. */ + +typedef struct quick_paragraph +{ + long isym; /* first symbol for label (index) */ + CORE_ADDR adrStart; /* memory adr of start of label */ + CORE_ADDR adrEnd; /* memory adr of end of label */ + char *sbLab; /* name of label */ + unsigned int inst; /* Used in xdb to store inst @ bp */ + unsigned int sect: 1; /* true = section, false = parag. */ + unsigned int unused: 31; /* future use */ +} quick_paragraph_entry, *quick_paragraph_entry_ptr; + +/* Class Descriptor: + An element of the class quick look-up table. */ + +typedef struct quick_class +{ + char *sbClass; /* name of class */ + long isym; /* class symbol (tag) */ + unsigned int type : 2; /* 0=class, 1=union, 2=struct */ + unsigned int fTemplate : 1;/* class template */ + unsigned int expansion : 1;/* template expansion */ + unsigned int unused :28; + sltpointer lowscope; /* beginning of defined scope */ + sltpointer hiscope; /* end of defined scope */ +} quick_class_entry, *quick_class_entry_ptr; + +/* Address Alias Entry + An element of the address alias quick look-up table. */ + +typedef struct quick_alias +{ + CORE_ADDR low; + CORE_ADDR high; + int index; + unsigned int unused : 31; + unsigned int alternate : 1; /* alternate unnamed aliases? */ +} quick_alias_entry, *quick_alias_entry_ptr; + +/* Object Identification Entry + An element of the object identification quick look-up table. */ + +typedef struct quick_obj_ID +{ + CORE_ADDR obj_ident; /* class identifier */ + long isym; /* class symbol */ + long offset; /* offset to object start */ +} quick_obj_ID_entry, *quick_obj_ID_entry_ptr; + +#endif /* HP_SYMTAB_INCLUDED */ diff --git a/include/mpw/ChangeLog b/include/mpw/ChangeLog new file mode 100644 index 000000000000..8dbad87eab47 --- /dev/null +++ b/include/mpw/ChangeLog @@ -0,0 +1,61 @@ +Tue Feb 27 12:23:04 1996 Raymond Jou <rjou@mexican.cygnus.com> + + * mpw.h (HAVE_VPRINTF): Add and define to have the value 1. + +Fri Dec 29 14:40:46 1995 Stan Shebs <shebs@andros.cygnus.com> + + * mpw.h (HAVE_STDLIB_H, etc): Define to have the value 1. + (HAVE_FCNTL_H): Define. + +Mon Dec 11 15:39:06 1995 Stan Shebs <shebs@andros.cygnus.com> + + * mpw.h (open, access): Define as mpw_open and mpw_access. + +Thu Nov 9 15:38:37 1995 Stan Shebs <shebs@andros.cygnus.com> + + * mpw.h: Include unix.h if USE_MW_HEADERS, otherwise include + various original MPW include files (ioctl.h, etc). + (EIO): Define if not defined. + * sys/ioctl.h: Remove, not needed. + +Wed Oct 25 12:30:44 1995 Stan Shebs <shebs@andros.cygnus.com> + + * mpw.h: Don't include errno.h or ioctl.h. + (ENOENT, EACCES, ENOSYS): Define if not defined. + (fdopen): Declare if __STDC__. + (R_OK, W_OK, X_OK): Define if not defined. + +Tue Sep 26 14:57:21 1995 Stan Shebs <shebs@andros.cygnus.com> + + * mpw.h: New file, universally useful MPW host definitions. + Many of these used to live in bfd/hosts/mpw.h. + * grp.h: Remove RCS comment. + * sys/ioctl.h: Add a comment line. + +Wed Dec 14 13:12:14 1994 Stan Shebs <shebs@andros.cygnus.com> + + * spin.h: New file, cursor spinning for progress. + +Thu Jun 30 15:32:07 1994 Stan Shebs (shebs@andros.cygnus.com) + + * fcntl.h (open): Allow optional third arg. + +Thu Apr 14 12:54:51 1994 Stan Shebs (shebs@andros.cygnus.com) + + * dir.h, dirent.h, fcntl.h, grp.h, pwd.h, stat.h: New files. + * sys/ioctl.h: New file. + +Mon Feb 21 09:44:45 1994 Stan Shebs (shebs@andros.cygnus.com) + + * sys/stat.h (struct stat): New field st_rsize. + (S_IFMT, etc): Use different bit positions. + (fstat): Add parameter names to prototype. + +Mon Jan 31 19:30:16 1994 Stan Shebs (shebs@andros.cygnus.com) + + * README: New file. + * utime.h, varargs.h: New files, simulated Posix. + * sys/{file,param,resource,stat,time,types}.h: New files, more + simulated Posix. + + diff --git a/include/mpw/README b/include/mpw/README new file mode 100644 index 000000000000..10e92de79f68 --- /dev/null +++ b/include/mpw/README @@ -0,0 +1 @@ +This is a collection of include files that help imitate Posix in MPW. diff --git a/include/mpw/dir.h b/include/mpw/dir.h new file mode 100644 index 000000000000..e6ccd2d59227 --- /dev/null +++ b/include/mpw/dir.h @@ -0,0 +1,23 @@ +/* The <dir.h> header gives the layout of a directory. */ + +#pragma once + +#ifndef _DIR_H +#define _DIR_H + +#ifndef _TYPES_H /* not quite right */ +#include <sys/types.h> +#endif + +#define DIRBLKSIZ 512 /* size of directory block */ + +#ifndef DIRSIZ +#define DIRSIZ 14 +#endif + +struct direct { + ino_t d_ino; + char d_name[DIRSIZ]; +}; + +#endif /* _DIR_H */ diff --git a/include/mpw/dirent.h b/include/mpw/dirent.h new file mode 100644 index 000000000000..38000b2c5f36 --- /dev/null +++ b/include/mpw/dirent.h @@ -0,0 +1,31 @@ +#ifndef __dirent_h +#define __dirent_h + +#include "sys/dir.h" + +struct dirent { + long d_ino; /* inode number of entry */ + off_t d_off; /* offset of disk directory entry */ + unsigned short d_reclen; /* length of this record */ + char d_name[1]; /* name of file */ +}; + +/* +#define DIRENTBASESIZE \ + (((struct dirent *) 0)->d_name - (char *) 0) +#define DIRENTSIZE(namelen) \ + ((DIRENTBASESIZE + (namelen) + NBPW) & ~(NBPW - 1)) +*/ + +/* from Mips posix/dirent.h */ + +/* +#undef rewinddir +*/ + +extern DIR *opendir(); +extern struct dirent *readdir(); +extern void rewinddir(); +extern int closedir(); + +#endif /* ! __dirent_h */ diff --git a/include/mpw/fcntl.h b/include/mpw/fcntl.h new file mode 100644 index 000000000000..30999b4b17df --- /dev/null +++ b/include/mpw/fcntl.h @@ -0,0 +1,124 @@ +/* + * FCntl.h -- faccess(), fcntl(), and open() mode flags + * + * Portions copyright American Telephone & Telegraph + * Used with permission, Apple Computer Inc. (1985,1988,1990,1992) + * All rights reserved. + */ + +#ifndef __FCNTL__ +#define __FCNTL__ + +#ifndef __TYPES__ +#include <Types.h> +#endif + +/* + * For use by lseek(): + */ + +#ifndef __STDIO__ /* these defns exactly paralled in StdIO.h for fseek() */ +#define SEEK_CUR 1 +#define SEEK_END 2 +#define SEEK_SET 0 +#endif + +/* + * faccess() commands; for general use + */ + /* 'd' => "directory" ops */ +#define F_DELETE (('d'<<8)|0x01) +#define F_RENAME (('d'<<8)|0x02) + +/* + * more faccess() commands; for use only by MPW tools + */ + +#define F_OPEN (('d'<<8)|0x00) /* reserved for operating system use */ + /* 'e' => "editor" ops */ +#define F_GTABINFO (('e'<<8)|0x00) /* get tab offset for file */ +#define F_STABINFO (('e'<<8)|0x01) /* set " " " " */ +#define F_GFONTINFO (('e'<<8)|0x02) /* get font number and size for file */ +#define F_SFONTINFO (('e'<<8)|0x03) /* set " " " " " " */ +#define F_GPRINTREC (('e'<<8)|0x04) /* get print record for file */ +#define F_SPRINTREC (('e'<<8)|0x05) /* set " " " " */ +#define F_GSELINFO (('e'<<8)|0x06) /* get selection information for file */ +#define F_SSELINFO (('e'<<8)|0x07) /* set " " " " */ +#define F_GWININFO (('e'<<8)|0x08) /* get current window position */ +#define F_SWININFO (('e'<<8)|0x09) /* set " " " */ +#define F_GSCROLLINFO (('e'<<8)|0x0A) /* get scroll information */ +#define F_SSCROLLINFO (('e'<<8)|0x0B) /* set " " */ +#define F_GMARKER (('e'<<8)|0x0D) /* Get Marker */ +#define F_SMARKER (('e'<<8)|0x0C) /* Set " */ +#define F_GSAVEONCLOSE (('e'<<8)|0x0F) /* Get Save on close */ +#define F_SSAVEONCLOSE (('e'<<8)|0x0E) /* Set " " " */ + +/* + * argument structures used by various faccess() commands + */ + +struct MarkElement { + int start; /* start position of mark */ + int end; /* end position */ + unsigned char charCount; /* number of chars in mark name */ + char name[64]; /* mark name */ +} ; /* note: marker names may be up to 64 characters long */ + +#ifndef __cplusplus +typedef struct MarkElement MarkElement; +#endif + +struct SelectionRecord { + long startingPos; + long endingPos; + long displayTop; +}; + +#ifndef __cplusplus +typedef struct SelectionRecord SelectionRecord; +#endif + + +/* + * Mode values accessible to open() + */ +#define O_RDONLY 0 /* Bits 0 and 1 are used internally */ +#define O_WRONLY 1 /* Values 0..2 are historical */ +#define O_RDWR 2 /* NOTE: it goes 0, 1, 2, *!* 8, 16, 32, ... */ +#define O_APPEND (1<< 3) /* append (writes guaranteed at the end) */ +#define O_RSRC (1<< 4) /* Open the resource fork */ +#define O_ALIAS (1<< 5) /* Open alias file */ +#define O_CREAT (1<< 8) /* Open with file create */ +#define O_TRUNC (1<< 9) /* Open with truncation */ +#define O_EXCL (1<<10) /* w/ O_CREAT: Exclusive "create-only" */ +#define O_BINARY (1<<11) /* Open as a binary stream */ +#define O_NRESOLVE (1<<14) /* Don't resolve any aliases */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * function prototypes + */ +int close(int); +int creat(const char*); +int dup(int filedes); /* OBSOLETE: fcntl(filedes, F_DUPFD, 0) is preferred */ +int faccess(char*, unsigned int, long*); +int fcntl(int, unsigned int, int); +long lseek(int, long, int); +int open(const char*, int, ...); +int read(int, char*, unsigned); +int unlink(char*); +int write(int, const char*, unsigned); + +#ifdef __cplusplus +} +#endif + +/* + * fcntl() commands + */ +#define F_DUPFD 0 /* Duplicate files (file descriptor) */ + +#endif __FCNTL__ diff --git a/include/mpw/grp.h b/include/mpw/grp.h new file mode 100644 index 000000000000..faf2c6a6be9b --- /dev/null +++ b/include/mpw/grp.h @@ -0,0 +1,10 @@ +#pragma once + +#include "sys/types.h" + +struct group { + char *gr_name; + gid_t gr_gid; + char *gr_passwd; + char **gr_mem; +}; diff --git a/include/mpw/mpw.h b/include/mpw/mpw.h new file mode 100644 index 000000000000..58702e725ff8 --- /dev/null +++ b/include/mpw/mpw.h @@ -0,0 +1,130 @@ +/* Mac MPW host-specific definitions. */ + +#ifndef __INCLUDE_MPW_H +#define __INCLUDE_MPW_H + +#ifndef MPW +#define MPW +#endif + +/* MPW C is basically ANSI, but doesn't actually enable __STDC__, + nor does it allow __STDC__ to be #defined. */ + +#ifndef ALMOST_STDC +#define ALMOST_STDC +#endif + +#include <stdio.h> +#include <ctype.h> +#include <errno.h> + +#define HAVE_TIME_T_IN_TIME_H 1 + +#define HAVE_STDLIB_H 1 + +#define HAVE_ERRNO_H 1 + +#define HAVE_STDDEF_H 1 + +#define HAVE_STRING_H 1 + +#define HAVE_STDARG_H 1 + +#define HAVE_VPRINTF 1 + +#ifdef USE_MW_HEADERS + +#include <unix.h> + +#else + +#include <fcntl.h> +#include <ioctl.h> +#include <sys/stat.h> + +#define HAVE_FCNTL_H 1 + +#ifndef O_ACCMODE +#define O_ACCMODE (O_RDONLY | O_WRONLY | O_RDWR) +#endif + +#ifndef fileno +#define fileno(fp) ((fp)->_file) +#endif + +/* stdio.h does not define this if __STDC__, so define here. */ + +#ifdef __STDC__ +FILE *fdopen(int fildes, const char *mode); +#endif + +#endif /* USE_MW_HEADERS */ + +/* Add ersatz definitions, for systems that lack them. */ + +#ifndef EIO +#define EIO 96 +#endif +#ifndef ENOENT +#define ENOENT 97 +#endif +#ifndef EACCES +#define EACCES 98 +#endif +#ifndef ENOSYS +#define ENOSYS 99 +#endif + +#ifndef R_OK +#define R_OK 4 +#define W_OK 2 +#define X_OK 1 +#endif + +/* Binary files have different characteristics; for instance, no cr/nl + translation. */ + +#define USE_BINARY_FOPEN + +#include <spin.h> + +#ifdef MPW_C +#undef __PTR_TO_INT +#define __PTR_TO_INT(P) ((int)(P)) +#undef __INT_TO_PTR +#define __INT_TO_PTR(P) ((char *)(P)) +#endif /* MPW_C */ + +#define NO_FCNTL + +int fstat (); + +FILE *mpw_fopen (); +int mpw_fseek (); +int mpw_fread (); +int mpw_fwrite (); +int mpw_access (); +int mpw_open (); +int mpw_creat (); +void mpw_abort (void); + +/* Map these standard functions to improved versions in libiberty. */ + +#define fopen mpw_fopen +#define fseek mpw_fseek +#define fread mpw_fread +#define fwrite mpw_fwrite +#define open mpw_open +#define access mpw_access +#define creat mpw_creat +#define abort mpw_abort + +#define POSIX_UTIME + +#define LOSING_TOTALLY + +/* Define this so that files will be closed before being unlinked. */ + +#define CLOSE_BEFORE_UNLINK + +#endif /* __INCLUDE_MPW_H */ diff --git a/include/mpw/pwd.h b/include/mpw/pwd.h new file mode 100644 index 000000000000..2d4fb70401aa --- /dev/null +++ b/include/mpw/pwd.h @@ -0,0 +1,15 @@ +#ifndef __pwd_h +#define __pwd_h + +#include <sys/types.h> + +struct passwd { + char *pw_name; + uid_t pw_uid; + gid_t pw_gid; + char *pw_dir; + char *pw_shell; + char *pw_passwd; +}; + +#endif /* ! __pwd_h */ diff --git a/include/mpw/spin.h b/include/mpw/spin.h new file mode 100644 index 000000000000..674b00ac60be --- /dev/null +++ b/include/mpw/spin.h @@ -0,0 +1,64 @@ +/* Progress macros that use SpinCursor in MPW. + Copyright 1994 Free Software Foundation, Inc. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _SPIN_H +#define _SPIN_H + +/* For MPW, progress macros just need to "spin the cursor" frequently, + preferably several times per second on a 68K Mac. */ + +/* In order to determine if we're meeting the goal, define this macro + and information about frequency of spinning will be collected and + displayed. */ + +#define SPIN_MEASUREMENT + +#include <CursorCtl.h> + +/* Programs use this macro to indicate the start of a lengthy + activity. STR identifies the particular activity, while N + indicates the expected duration, in unspecified units. If N is + zero, then the expected time to completion is unknown. */ + +#undef START_PROGRESS +#define START_PROGRESS(STR,N) mpw_start_progress (STR, N, __FILE__, __LINE__); + +/* Programs use this macro to indicate that progress has been made on a + lengthy activity. */ + +#undef PROGRESS +#ifdef SPIN_MEASUREMENT +#define PROGRESS(X) mpw_progress_measured (X, __FILE__, __LINE__); +#else +#define PROGRESS(X) mpw_progress (X); +#endif + +/* Programs use this macro to indicate the end of a lengthy activity. + STR must match a STR passed to START_PROGRESS previously. */ + +#undef END_PROGRESS +#define END_PROGRESS(STR) mpw_end_progress (STR, __FILE__, __LINE__); + +extern void mpw_start_progress (char *, int, char *, int); + +extern void mpw_progress (int); + +extern void mpw_progress_measured (int, char *, int); + +extern void mpw_end_progress (char *, char *, int); + +#endif /* _SPIN_H */ diff --git a/include/mpw/stat.h b/include/mpw/stat.h new file mode 100644 index 000000000000..057b8d531139 --- /dev/null +++ b/include/mpw/stat.h @@ -0,0 +1,75 @@ +/* The <sys/stat.h> header defines a struct that is used in the stat() and + * fstat functions. The information in this struct comes from the i-node of + * some file. These calls are the only approved way to inspect i-nodes. + */ + +#ifndef _STAT_H +#define _STAT_H + +#ifndef _TYPES_H /* not quite right */ +#include <sys/types.h> +#endif + +struct stat { + dev_t st_dev; /* major/minor device number */ + ino_t st_ino; /* i-node number */ + mode_t st_mode; /* file mode, protection bits, etc. */ + short int st_nlink; /* # links; TEMPORARY HACK: should be nlink_t*/ + uid_t st_uid; /* uid of the file's owner */ + short int st_gid; /* gid; TEMPORARY HACK: should be gid_t */ + dev_t st_rdev; + off_t st_size; /* file size */ + time_t st_atime; /* time of last access */ + time_t st_mtime; /* time of last data modification */ + time_t st_ctime; /* time of last file status change */ +}; + +/* Traditional mask definitions for st_mode. */ +#define S_IFMT 0170000 /* type of file */ +#define S_IFREG 0100000 /* regular */ +#define S_IFBLK 0060000 /* block special */ +#define S_IFDIR 0040000 /* directory */ +#define S_IFCHR 0020000 /* character special */ +#define S_IFIFO 0010000 /* this is a FIFO */ +#define S_ISUID 0004000 /* set user id on execution */ +#define S_ISGID 0002000 /* set group id on execution */ + /* next is reserved for future use */ +#define S_ISVTX 01000 /* save swapped text even after use */ + +/* POSIX masks for st_mode. */ +#define S_IRWXU 00700 /* owner: rwx------ */ +#define S_IRUSR 00400 /* owner: r-------- */ +#define S_IWUSR 00200 /* owner: -w------- */ +#define S_IXUSR 00100 /* owner: --x------ */ + +#define S_IRWXG 00070 /* group: ---rwx--- */ +#define S_IRGRP 00040 /* group: ---r----- */ +#define S_IWGRP 00020 /* group: ----w---- */ +#define S_IXGRP 00010 /* group: -----x--- */ + +#define S_IRWXO 00007 /* others: ------rwx */ +#define S_IROTH 00004 /* others: ------r-- */ +#define S_IWOTH 00002 /* others: -------w- */ +#define S_IXOTH 00001 /* others: --------x */ + +/* The following macros test st_mode (from POSIX Sec. 5.6.1.1. */ +#define S_ISREG(m) ((m & S_IFMT) == S_IFREG) /* is a reg file */ +#define S_ISDIR(m) ((m & S_IFMT) == S_IFDIR) /* is a directory */ +#define S_ISCHR(m) ((m & S_IFMT) == S_IFCHR) /* is a char spec */ +#define S_ISBLK(m) ((m & S_IFMT) == S_IFBLK) /* is a block spec */ +#define S_ISFIFO(m) ((m & S_IFMT) == S_IFIFO) /* is a pipe/FIFO */ + + +/* Function Prototypes. */ +#ifndef _ANSI_H +#include <ansi.h> +#endif + +_PROTOTYPE( int chmod, (const char *_path, int _mode) ); +_PROTOTYPE( int fstat, (int _fildes, struct stat *_buf) ); +_PROTOTYPE( int mkdir, (const char *_path, int _mode) ); +_PROTOTYPE( int mkfifo, (const char *_path, int _mode) ); +_PROTOTYPE( int stat , (const char *_path, struct stat *_buf) ); +_PROTOTYPE( mode_t umask, (int _cmask) ); + +#endif /* _STAT_H */ diff --git a/include/mpw/sys/file.h b/include/mpw/sys/file.h new file mode 100644 index 000000000000..40a8c178f10d --- /dev/null +++ b/include/mpw/sys/file.h @@ -0,0 +1 @@ +/* empty */ diff --git a/include/mpw/sys/param.h b/include/mpw/sys/param.h new file mode 100644 index 000000000000..40a8c178f10d --- /dev/null +++ b/include/mpw/sys/param.h @@ -0,0 +1 @@ +/* empty */ diff --git a/include/mpw/sys/resource.h b/include/mpw/sys/resource.h new file mode 100644 index 000000000000..d39439d61d52 --- /dev/null +++ b/include/mpw/sys/resource.h @@ -0,0 +1,9 @@ +#ifndef __SYS_RESOURCE_H__ +#define __SYS_RESOURCE_H__ + +struct rusage { + struct timeval ru_utime; + struct timeval ru_stime; +}; + +#endif /* __SYS_RESOURCE_H__ */ diff --git a/include/mpw/sys/stat.h b/include/mpw/sys/stat.h new file mode 100644 index 000000000000..b65c72e10c6a --- /dev/null +++ b/include/mpw/sys/stat.h @@ -0,0 +1,44 @@ +/* Imitation sys/stat.h. */ + +#ifndef __SYS_STAT_H__ +#define __SYS_STAT_H__ + +#include <sys/types.h> +#include <time.h> + +struct stat { + dev_t st_dev; + ino_t st_ino; + mode_t st_mode; + short st_nlink; + uid_t st_uid; + gid_t st_gid; + dev_t st_rdev; + off_t st_size; + off_t st_rsize; + time_t st_atime; + int st_spare1; + time_t st_mtime; + int st_spare2; + time_t st_ctime; + int st_spare3; + long st_blksize; + long st_blocks; + long st_spare4[2]; +}; + +#define S_IFMT 0170000L +#define S_IFDIR 0040000L +#define S_IFREG 0100000L +#define S_IREAD 0400 +#define S_IWRITE 0200 +#define S_IEXEC 0100 + +#define S_IFIFO 010000 /* FIFO special */ +#define S_IFCHR 020000 /* character special */ +#define S_IFBLK 030000 /* block special */ + +int stat (char *path, struct stat *buf); +int fstat (int fd, struct stat *buf); + +#endif /* __SYS_STAT_H___ */ diff --git a/include/mpw/sys/time.h b/include/mpw/sys/time.h new file mode 100644 index 000000000000..f9e485232a21 --- /dev/null +++ b/include/mpw/sys/time.h @@ -0,0 +1,13 @@ +/* Imitation sys/time.h. */ + +#ifndef __SYS_TIME_H__ +#define __SYS_TIME_H__ + +#include <time.h> + +struct timeval { + long tv_sec; + long tv_usec; +}; + +#endif /* __SYS_TIME_H__ */ diff --git a/include/mpw/sys/types.h b/include/mpw/sys/types.h new file mode 100644 index 000000000000..d7d9c9f44ba0 --- /dev/null +++ b/include/mpw/sys/types.h @@ -0,0 +1,15 @@ +/* Imitation sys/types.h. */ + +#ifndef __SYS_TYPES_H__ +#define __SYS_TYPES_H__ + +#include <Types.h> + +typedef short dev_t; +typedef short ino_t; +typedef unsigned short mode_t; +typedef unsigned short uid_t; +typedef unsigned short gid_t; +typedef long off_t; + +#endif /* __SYS_TYPES_H__ */ diff --git a/include/mpw/utime.h b/include/mpw/utime.h new file mode 100644 index 000000000000..e8bf66f2ba5c --- /dev/null +++ b/include/mpw/utime.h @@ -0,0 +1,7 @@ + +struct utimbuf { + time_t actime; + time_t modtime; +}; + +int utime (char *, struct utimbuf *); diff --git a/include/mpw/varargs.h b/include/mpw/varargs.h new file mode 100644 index 000000000000..acb9e4504a2d --- /dev/null +++ b/include/mpw/varargs.h @@ -0,0 +1,9 @@ +/* varargs.h. */ +#ifndef __va_list__ +#define __va_list__ +typedef char *va_list; +#endif +#define va_dcl int va_alist; +#define va_start(list) list = (char *) &va_alist +#define va_end(list) +#define va_arg(list,mode) ((mode *)(list += sizeof(mode)))[-1] diff --git a/include/nlm/ChangeLog b/include/nlm/ChangeLog new file mode 100644 index 000000000000..b3c9529b8060 --- /dev/null +++ b/include/nlm/ChangeLog @@ -0,0 +1,93 @@ +2003-08-07 Alan Modra <amodra@bigpond.net.au> + + * internal.h (Nlm_Internal_Custom_Header): Replace PTR with void *. + +2001-10-02 Alan Modra <amodra@bigpond.net.au> + + * common.h (NLM_CAT, NLM_CAT3): Don't define. + (NLM_CAT4): Update conditions under which this is defined. Document + why CONCAT4 can't be used. + +Fri May 6 13:31:04 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * external.h (nlmNAME(External_Custom_Header)): Add length, + dataOffset, and dataStamp field. + (nlmNAME(External_Cygnus_Ext_Header)): Remove. + * internal.h (Nlm_Internal_Custom_Header): Add hdrLength, + dataOffset, dataStamp and hdr fields. + +Fri Apr 22 11:12:39 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * external.h (struct nlmNAME(external_cygnus_ext_header)): Rename + from nlmNAME(external_cygnus_section_header). Change stamp field + to 8 bytes. Add bytes field. + * internal.h (nlm_internal_cygnus_ext_header): Rename from + nlm_internal_cygnus_section_header. Change stamp field to 8 + bytes. + +Thu Apr 21 11:57:09 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (struct nlm_internal_cygnus_section_header): Define. + * external.h (struct nlmNAME(external_cygnus_section_header): + Define. + +Wed Apr 20 14:27:43 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (struct nlm_internal_custom_header): Remove + debugRecOffset and debugRecLength fields. Add data field. + * external.h (struct nlmNAME(external_custom_header)): Remove + debugRecOffset and debugRecLength fields. + +Mon Feb 7 08:28:40 1994 Jim Kingdon (kingdon@lioth.cygnus.com) + + * internal.h: Change HOST_64_BIT to BFD_HOST_64_BIT. + +Thu Dec 2 14:14:48 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * alpha-ext.h: New file describing formats of information in Alpha + NetWare files. + * common.h: Define some non-external Alpha information. + +Wed Nov 17 17:38:58 1993 Sean Eric Fagan (sef@cygnus.com) + + * external.h: Don't define external_fixed_header here. + * i386-ext.h, sparc32-ext.h: New header files to define + external_fixed_header for particular CPU's. + +Wed Oct 27 11:45:56 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h (Nlm_Internal_Extended_Header): Added fields + sharedDebugRecordOffset and sharedDebugRecordCount. + * external.h (NlmNAME(External_Extended_Header)): Likewise. + + * common.h (NLM_SIGNATURE): Do not define (it's different for each + backend). + +Tue Aug 31 13:24:15 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * internal.h: Change length fields of type char to type unsigned + char. + +Sat Jul 31 02:12:14 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) + + * common.h (NLM_HIBIT, NLM_HEADER_VERSION): Define. + +Thu Jul 22 16:09:47 1993 Fred Fish (fnf@deneb.cygnus.com) + + * common.h (NLM_CAT*, NLM_ARCH_SIZE, NLM_TARGET_LONG_SIZE, + NLM_TARGET_ADDRESS_SIZE, NLM_NAME, NlmNAME, nlmNAME): New + macros. + * external.h (TARGET_LONG_SIZE, TARGET_ADDRESS_SIZE): Remove + macros, convert usages to NLM_ equivalents. + * external.h: Use nlmNAME and NlmNAME macros to derive both + 32 and 64 bit versions. + +Mon Jul 19 22:12:40 1993 Fred Fish (fnf@deneb.cygnus.com) + + * (common.h, external.h, internal.h): New files for NLM/NetWare + support. + + +Local Variables: +version-control: never +End: diff --git a/include/nlm/alpha-ext.h b/include/nlm/alpha-ext.h new file mode 100644 index 000000000000..ae6752402e8e --- /dev/null +++ b/include/nlm/alpha-ext.h @@ -0,0 +1,166 @@ +/* Alpha NLM (NetWare Loadable Module) support for BFD. + Copyright 1993 Free Software Foundation, Inc. + By Ian Lance Taylor, Cygnus Support + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* An Alpha NLM starts with an instance of this structure. */ + +struct nlm32_alpha_external_prefix_header +{ + /* Magic number. Must be NLM32_ALPHA_MAGIC. */ + unsigned char magic[4]; + /* Format descriptor. Current value is 2. */ + unsigned char format[4]; + /* Size of prefix header. */ + unsigned char size[4]; + /* Padding. */ + unsigned char pad1[4]; + /* More fields may be added later, supposedly. */ +}; + +/* The external format of an Alpha NLM reloc. This is the same as an + Alpha ECOFF reloc. */ + +struct nlm32_alpha_external_reloc +{ + unsigned char r_vaddr[8]; + unsigned char r_symndx[4]; + unsigned char r_bits[4]; +}; + +/* Constants to unpack the r_bits field of a reloc. */ + +#define RELOC_BITS0_TYPE_LITTLE 0xff +#define RELOC_BITS0_TYPE_SH_LITTLE 0 + +#define RELOC_BITS1_EXTERN_LITTLE 0x01 + +#define RELOC_BITS1_OFFSET_LITTLE 0x7e +#define RELOC_BITS1_OFFSET_SH_LITTLE 1 + +#define RELOC_BITS1_RESERVED_LITTLE 0x80 +#define RELOC_BITS1_RESERVED_SH_LITTLE 7 +#define RELOC_BITS2_RESERVED_LITTLE 0xff +#define RELOC_BITS2_RESERVED_SH_LEFT_LITTLE 1 +#define RELOC_BITS3_RESERVED_LITTLE 0x03 +#define RELOC_BITS3_RESERVED_SH_LEFT_LITTLE 9 + +#define RELOC_BITS3_SIZE_LITTLE 0xfc +#define RELOC_BITS3_SIZE_SH_LITTLE 2 + +/* The external format of the fixed header. */ + +typedef struct nlm32_alpha_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* Padding to make it come out correct. */ + + unsigned char pad1[2]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_alpha_External_Fixed_Header; diff --git a/include/nlm/common.h b/include/nlm/common.h new file mode 100644 index 000000000000..208f4cfa7f25 --- /dev/null +++ b/include/nlm/common.h @@ -0,0 +1,123 @@ +/* NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 2001 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* This file is part of NLM support for BFD, and contains the portions + that are common to both the internal and external representations. */ + +/* If NLM_ARCH_SIZE is not defined, default to 32. NLM_ARCH_SIZE is + optionally defined by the application. */ + +#ifndef NLM_ARCH_SIZE +# define NLM_ARCH_SIZE 32 +#endif + +/* Due to horrible details of ANSI macro expansion, we can't use CONCAT4 + for NLM_NAME. CONCAT2 is used in BFD_JUMP_TABLE macros, and some of + them will expand to tokens that themselves are macros defined in terms + of NLM_NAME. If NLM_NAME were defined using CONCAT4 (which is itself + defined in bfd-in.h using CONCAT2), ANSI preprocessor rules say that + the CONCAT2 within NLM_NAME should not be expanded. + So use another name. */ +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) +#ifdef SABER +#define NLM_CAT4(a,b,c,d) a##b##c##d +#else +/* This hack is to avoid a problem with some strict ANSI C preprocessors. + The problem is, "32_" is not a valid preprocessing token, and we don't + want extra underscores (e.g., "nlm_32_"). The NLM_XCAT2 macro will + cause the inner CAT2 macros to be evaluated first, producing + still-valid pp-tokens. Then the final concatenation can be done. */ +#define NLM_CAT2(a,b) a##b +#define NLM_XCAT2(a,b) NLM_CAT2(a,b) +#define NLM_CAT4(a,b,c,d) NLM_XCAT2(NLM_CAT2(a,b),NLM_CAT2(c,d)) +#endif +#else +#define NLM_CAT4(a,b,c,d) a/**/b/**/c/**/d +#endif + +#if NLM_ARCH_SIZE == 32 +# define NLM_TARGET_LONG_SIZE 4 +# define NLM_TARGET_ADDRESS_SIZE 4 +# define NLM_NAME(x,y) NLM_CAT4(x,32,_,y) +# define NLM_HIBIT (((bfd_vma) 1) << 31) +#endif +#if NLM_ARCH_SIZE == 64 +# define NLM_TARGET_LONG_SIZE 8 +# define NLM_TARGET_ADDRESS_SIZE 8 +# define NLM_NAME(x,y) NLM_CAT4(x,64,_,y) +# define NLM_HIBIT (((bfd_vma) 1) << 63) +#endif + +#define NlmNAME(X) NLM_NAME(Nlm,X) +#define nlmNAME(X) NLM_NAME(nlm,X) + +/* Give names to things that should not change. */ + +#define NLM_MAX_DESCRIPTION_LENGTH 127 +#define NLM_MAX_SCREEN_NAME_LENGTH 71 +#define NLM_MAX_THREAD_NAME_LENGTH 71 +#define NLM_MAX_COPYRIGHT_MESSAGE_LENGTH 255 +#define NLM_OTHER_DATA_LENGTH 400 /* FIXME */ +#define NLM_OLD_THREAD_NAME_LENGTH 5 +#define NLM_SIGNATURE_SIZE 24 +#define NLM_HEADER_VERSION 4 +#define NLM_MODULE_NAME_SIZE 14 +#define NLM_DEFAULT_STACKSIZE (8 * 1024) + +/* Alpha information. This should probably be in a separate Alpha + header file, but it can't go in alpha-ext.h because some of it is + needed by nlmconv.c. */ + +/* Magic number in Alpha prefix header. */ +#define NLM32_ALPHA_MAGIC (0x83561840) + +/* The r_type field in an Alpha reloc is one of the following values. */ +#define ALPHA_R_IGNORE 0 +#define ALPHA_R_REFLONG 1 +#define ALPHA_R_REFQUAD 2 +#define ALPHA_R_GPREL32 3 +#define ALPHA_R_LITERAL 4 +#define ALPHA_R_LITUSE 5 +#define ALPHA_R_GPDISP 6 +#define ALPHA_R_BRADDR 7 +#define ALPHA_R_HINT 8 +#define ALPHA_R_SREL16 9 +#define ALPHA_R_SREL32 10 +#define ALPHA_R_SREL64 11 +#define ALPHA_R_OP_PUSH 12 +#define ALPHA_R_OP_STORE 13 +#define ALPHA_R_OP_PSUB 14 +#define ALPHA_R_OP_PRSHIFT 15 +#define ALPHA_R_GPVALUE 16 +#define ALPHA_R_NW_RELOC 250 + +/* A local reloc, other than ALPHA_R_GPDISP or ALPHA_R_IGNORE, must be + against one of these symbol indices. */ +#define ALPHA_RELOC_SECTION_TEXT 1 +#define ALPHA_RELOC_SECTION_DATA 3 + +/* An ALPHA_R_NW_RELOC has one of these values in the size field. If + it is SETGP, the r_vaddr field holds the GP value to use. If it is + LITA, the r_vaddr field holds the address of the .lita section and + the r_symndx field holds the size of the .lita section. */ +#define ALPHA_R_NW_RELOC_SETGP 1 +#define ALPHA_R_NW_RELOC_LITA 2 diff --git a/include/nlm/external.h b/include/nlm/external.h new file mode 100644 index 000000000000..12a486fd48fb --- /dev/null +++ b/include/nlm/external.h @@ -0,0 +1,174 @@ +/* NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 1994 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* This file is part of NLM support for BFD, and contains the portions + that describe how NLM is represented externally by the BFD library. + I.E. it describes the in-file representation of NLM. It requires + the nlm/common.h file which contains the portions that are common to + both the internal and external representations. + + Note that an NLM header consists of three parts: + + (1) A fixed length header that has specific fields of known length, + at specific offsets in the file. + + (2) A variable length header that has specific fields in a specific + order, but some fields may be variable length. + + (3) A auxiliary header that has various optional fields in no specific + order. There is no way to identify the end of the auxiliary headers + except by finding a header without a recognized 'stamp'. + + The exact format of the fixed length header unfortunately varies + from one NLM target to another, due to padding. Each target + defines the correct external format in a separate header file. + +*/ + +/* NLM Header */ + +/* The version header is one of the optional auxiliary headers and + follows the fixed length and variable length NLM headers. */ + +typedef struct nlmNAME(external_version_header) +{ + + /* The header is recognized by "VeRsIoN#" in the stamp field. */ + char stamp[8]; + + unsigned char majorVersion[NLM_TARGET_LONG_SIZE]; + + unsigned char minorVersion[NLM_TARGET_LONG_SIZE]; + + unsigned char revision[NLM_TARGET_LONG_SIZE]; + + unsigned char year[NLM_TARGET_LONG_SIZE]; + + unsigned char month[NLM_TARGET_LONG_SIZE]; + + unsigned char day[NLM_TARGET_LONG_SIZE]; + +} NlmNAME(External_Version_Header); + + +typedef struct nlmNAME(external_copyright_header) +{ + + /* The header is recognized by "CoPyRiGhT=" in the stamp field. */ + + char stamp[10]; + + unsigned char copyrightMessageLength[1]; + + /* There is a variable length field here called 'copyrightMessage' + that is the length specified by copyrightMessageLength. */ + +} NlmNAME(External_Copyright_Header); + + +typedef struct nlmNAME(external_extended_header) +{ + + /* The header is recognized by "MeSsAgEs" in the stamp field. */ + + char stamp[8]; + + unsigned char languageID[NLM_TARGET_LONG_SIZE]; + + unsigned char messageFileOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char messageFileLength[NLM_TARGET_LONG_SIZE]; + + unsigned char messageCount[NLM_TARGET_LONG_SIZE]; + + unsigned char helpFileOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char helpFileLength[NLM_TARGET_LONG_SIZE]; + + unsigned char RPCDataOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char RPCDataLength[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedCodeOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedCodeLength[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDataOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDataLength[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedRelocationFixupOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedRelocationFixupCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedExternalReferenceOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedExternalReferenceCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedPublicsOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedPublicsCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDebugRecordOffset[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedDebugRecordCount[NLM_TARGET_LONG_SIZE]; + + unsigned char sharedInitializationOffset[NLM_TARGET_ADDRESS_SIZE]; + + unsigned char SharedExitProcedureOffset[NLM_TARGET_ADDRESS_SIZE]; + + unsigned char productID[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved0[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved1[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved2[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved3[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved4[NLM_TARGET_LONG_SIZE]; + + unsigned char reserved5[NLM_TARGET_LONG_SIZE]; + +} NlmNAME(External_Extended_Header); + + +typedef struct nlmNAME(external_custom_header) +{ + + /* The header is recognized by "CuStHeAd" in the stamp field. */ + char stamp[8]; + + /* Length of this header. */ + unsigned char length[NLM_TARGET_LONG_SIZE]; + + /* Offset to data. */ + unsigned char dataOffset[NLM_TARGET_LONG_SIZE]; + + /* Length of data. */ + unsigned char dataLength[NLM_TARGET_LONG_SIZE]; + + /* Stamp for this customer header--we recognize "CyGnUsEx". */ + char dataStamp[8]; + +} NlmNAME(External_Custom_Header); diff --git a/include/nlm/i386-ext.h b/include/nlm/i386-ext.h new file mode 100644 index 000000000000..c7380120e2d0 --- /dev/null +++ b/include/nlm/i386-ext.h @@ -0,0 +1,116 @@ +/* i386 NLM (NetWare Loadable Module) support for BFD. + Copyright 1993 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* The external format of the fixed header. */ + +typedef struct nlm32_i386_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_i386_External_Fixed_Header; diff --git a/include/nlm/internal.h b/include/nlm/internal.h new file mode 100644 index 000000000000..f61c42db8e77 --- /dev/null +++ b/include/nlm/internal.h @@ -0,0 +1,309 @@ +/* NLM (NetWare Loadable Module) support for BFD. + Copyright 1993, 1994, 2003 Free Software Foundation, Inc. + + Written by Fred Fish @ Cygnus Support. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* This file is part of NLM support for BFD, and contains the portions + that describe how NLM is represented internally in the BFD library. + I.E. it describes the in-memory representation of NLM. It requires + the nlm/common.h file which contains the portions that are common to + both the internal and external representations. */ + +#if 0 + +/* Types used by various structures, functions, etc. */ + +typedef unsigned long Nlm32_Addr; /* Unsigned program address */ +typedef unsigned long Nlm32_Off; /* Unsigned file offset */ +typedef long Nlm32_Sword; /* Signed large integer */ +typedef unsigned long Nlm32_Word; /* Unsigned large integer */ +typedef unsigned short Nlm32_Half; /* Unsigned medium integer */ +typedef unsigned char Nlm32_Char; /* Unsigned tiny integer */ + +#ifdef BFD_HOST_64_BIT +typedef unsigned BFD_HOST_64_BIT Nlm64_Addr; +typedef unsigned BFD_HOST_64_BIT Nlm64_Off; +typedef BFD_HOST_64_BIT Nlm64_Sxword; +typedef unsigned BFD_HOST_64_BIT Nlm64_Xword; +#endif +typedef long Nlm64_Sword; +typedef unsigned long Nlm64_Word; +typedef unsigned short Nlm64_Half; + +#endif /* 0 */ + +/* This structure contains the internal form of the portion of the NLM + header that is fixed length. */ + +typedef struct nlm_internal_fixed_header +{ + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + char signature[NLM_SIGNATURE_SIZE]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + long version; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension. The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + char moduleName[NLM_MODULE_NAME_SIZE]; + + /* The byte offset of the code image from the start of the file. */ + + file_ptr codeImageOffset; + + /* The size of the code image, in bytes. */ + + bfd_size_type codeImageSize; + + /* The byte offset of the data image from the start of the file. */ + + file_ptr dataImageOffset; + + /* The size of the data image, in bytes. */ + + bfd_size_type dataImageSize; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + bfd_size_type uninitializedDataSize; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. */ + + file_ptr customDataOffset; + + /* The size of the custom data, in bytes. */ + + bfd_size_type customDataSize; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + file_ptr moduleDependencyOffset; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + long numberOfModuleDependencies; + + /* The byte offset of the relocation fixup data from the start of the file */ + + file_ptr relocationFixupOffset; + long numberOfRelocationFixups; + file_ptr externalReferencesOffset; + long numberOfExternalReferences; + file_ptr publicsOffset; + long numberOfPublics; + file_ptr debugInfoOffset; + long numberOfDebugRecords; + file_ptr codeStartOffset; + file_ptr exitProcedureOffset; + file_ptr checkUnloadProcedureOffset; + long moduleType; + long flags; +} Nlm_Internal_Fixed_Header; + +#define nlm32_internal_fixed_header nlm_internal_fixed_header +#define Nlm32_Internal_Fixed_Header Nlm_Internal_Fixed_Header +#define nlm64_internal_fixed_header nlm_internal_fixed_header +#define Nlm64_Internal_Fixed_Header Nlm_Internal_Fixed_Header + +/* This structure contains the portions of the NLM header that are either + variable in size in the external representation, or else are not at a + fixed offset relative to the start of the NLM header due to preceding + variable sized fields. + + Note that all the fields must exist in the external header, and in + the order used here (the same order is used in the internal form + for consistency, not out of necessity). */ + +typedef struct nlm_internal_variable_header +{ + + /* The descriptionLength field contains the length of the text in + descriptionText, excluding the null terminator. The descriptionText + field contains the NLM description obtained from the DESCRIPTION + keyword in NLMLINK plus the null byte terminator. The descriptionText + can be up to NLM_MAX_DESCRIPTION_LENGTH characters. */ + + unsigned char descriptionLength; + char descriptionText[NLM_MAX_DESCRIPTION_LENGTH + 1]; + + /* The stackSize field contains the size of the stack in bytes, as + specified by the STACK or STACKSIZE keyword in NLMLINK. If no size + is specified, the default is NLM_DEFAULT_STACKSIZE. */ + + long stackSize; + + /* The reserved field is included only for completeness. It should contain + zero. */ + + long reserved; + + /* This field is fixed length, should contain " LONG" (note leading + space), and is unused. */ + + char oldThreadName[NLM_OLD_THREAD_NAME_LENGTH]; + + /* The screenNameLength field contains the length of the actual text stored + in the screenName field, excluding the null byte terminator. The + screenName field contains the screen name as specified by the SCREENNAME + keyword in NLMLINK, and can be up to NLM_MAX_SCREEN_NAME_LENGTH + characters. */ + + unsigned char screenNameLength; + char screenName[NLM_MAX_SCREEN_NAME_LENGTH + 1]; + + /* The threadNameLength field contains the length of the actual text stored + in the threadName field, excluding the null byte terminator. The + threadName field contains the thread name as specified by the THREADNAME + keyword in NLMLINK, and can be up to NLM_MAX_THREAD_NAME_LENGTH + characters. */ + + unsigned char threadNameLength; + char threadName[NLM_MAX_THREAD_NAME_LENGTH + 1]; + +} Nlm_Internal_Variable_Header; + +#define nlm32_internal_variable_header nlm_internal_variable_header +#define Nlm32_Internal_Variable_Header Nlm_Internal_Variable_Header +#define nlm64_internal_variable_header nlm_internal_variable_header +#define Nlm64_Internal_Variable_Header Nlm_Internal_Variable_Header + +/* The version header is one of the optional auxiliary headers and + follows the fixed length and variable length NLM headers. */ + +typedef struct nlm_internal_version_header +{ + /* The header is recognized by "VeRsIoN#" in the stamp field. */ + char stamp[8]; + long majorVersion; + long minorVersion; + long revision; + long year; + long month; + long day; +} Nlm_Internal_Version_Header; + +#define nlm32_internal_version_header nlm_internal_version_header +#define Nlm32_Internal_Version_Header Nlm_Internal_Version_Header +#define nlm64_internal_version_header nlm_internal_version_header +#define Nlm64_Internal_Version_Header Nlm_Internal_Version_Header + +typedef struct nlm_internal_copyright_header +{ + /* The header is recognized by "CoPyRiGhT=" in the stamp field. */ + char stamp[10]; + unsigned char copyrightMessageLength; + char copyrightMessage[NLM_MAX_COPYRIGHT_MESSAGE_LENGTH]; +} Nlm_Internal_Copyright_Header; + +#define nlm32_internal_copyright_header nlm_internal_copyright_header +#define Nlm32_Internal_Copyright_Header Nlm_Internal_Copyright_Header +#define nlm64_internal_copyright_header nlm_internal_copyright_header +#define Nlm64_Internal_Copyright_Header Nlm_Internal_Copyright_Header + +typedef struct nlm_internal_extended_header +{ + /* The header is recognized by "MeSsAgEs" in the stamp field. */ + char stamp[8]; + long languageID; + file_ptr messageFileOffset; + bfd_size_type messageFileLength; + long messageCount; + file_ptr helpFileOffset; + bfd_size_type helpFileLength; + file_ptr RPCDataOffset; + bfd_size_type RPCDataLength; + file_ptr sharedCodeOffset; + bfd_size_type sharedCodeLength; + file_ptr sharedDataOffset; + bfd_size_type sharedDataLength; + file_ptr sharedRelocationFixupOffset; + long sharedRelocationFixupCount; + file_ptr sharedExternalReferenceOffset; + long sharedExternalReferenceCount; + file_ptr sharedPublicsOffset; + long sharedPublicsCount; + file_ptr sharedDebugRecordOffset; + long sharedDebugRecordCount; + bfd_vma SharedInitializationOffset; + bfd_vma SharedExitProcedureOffset; + long productID; + long reserved0; + long reserved1; + long reserved2; + long reserved3; + long reserved4; + long reserved5; +} Nlm_Internal_Extended_Header; + +#define nlm32_internal_extended_header nlm_internal_extended_header +#define Nlm32_Internal_Extended_Header Nlm_Internal_Extended_Header +#define nlm64_internal_extended_header nlm_internal_extended_header +#define Nlm64_Internal_Extended_Header Nlm_Internal_Extended_Header + +/* The format of a custom header as stored internally is different + from the external format. This is how we store a custom header + which we do not recognize. */ + +typedef struct nlm_internal_custom_header +{ + /* The header is recognized by "CuStHeAd" in the stamp field. */ + char stamp[8]; + bfd_size_type hdrLength; + file_ptr dataOffset; + bfd_size_type dataLength; + char dataStamp[8]; + void *hdr; +} Nlm_Internal_Custom_Header; + +#define nlm32_internal_custom_header nlm_internal_custom_header +#define Nlm32_Internal_Custom_Header Nlm_Internal_Custom_Header +#define nlm64_internal_custom_header nlm_internal_custom_header +#define Nlm64_Internal_Custom_Header Nlm_Internal_Custom_Header + +/* The internal Cygnus header is written out externally as a custom + header. We don't try to replicate that structure here. */ + +typedef struct nlm_internal_cygnus_ext_header +{ + /* The header is recognized by "CyGnUsEx" in the stamp field. */ + char stamp[8]; + /* File location of debugging information. */ + file_ptr offset; + /* Length of debugging information. */ + bfd_size_type length; +} Nlm_Internal_Cygnus_Ext_Header; + +#define nlm32_internal_cygnus_ext_header nlm_internal_cygnus_ext_header +#define Nlm32_Internal_Cygnus_Ext_Header Nlm_Internal_Cygnus_Ext_Header +#define nlm64_internal_cygnus_ext_header nlm_internal_cygnus_ext_header +#define Nlm64_Internal_Cygnus_Ext_Header Nlm_Internal_Cygnus_Ext_Header diff --git a/include/nlm/ppc-ext.h b/include/nlm/ppc-ext.h new file mode 100644 index 000000000000..0aae10772f56 --- /dev/null +++ b/include/nlm/ppc-ext.h @@ -0,0 +1,163 @@ +/* PowerPC NLM (NetWare Loadable Module) support for BFD. + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifdef OLDFORMAT + +/* The format of a PowerPC NLM changed. These structures are only + used in the old format. */ + +/* A PowerPC NLM starts with an instance of this structure. */ + +struct nlm32_powerpc_external_prefix_header +{ + /* Signature. Must be "AppleNLM". */ + char signature[8]; + /* Version number. Current value is 1. */ + unsigned char headerVersion[4]; + /* ??. Should be set to 0. */ + unsigned char origins[4]; + /* File creation date in standard Unix time format (seconds since + 1/1/70). */ + unsigned char date[4]; +}; + +#define NLM32_POWERPC_SIGNATURE "AppleNLM" +#define NLM32_POWERPC_HEADER_VERSION 1 + +/* The external format of a PowerPC NLM reloc. This is the same as an + XCOFF dynamic reloc. */ + +struct nlm32_powerpc_external_reloc +{ + /* Address. */ + unsigned char l_vaddr[4]; + /* Symbol table index. This is 0 for .text and 1 for .data. 2 + means .bss, but I don't know if it is used. In XCOFF, larger + numbers are indices into the dynamic symbol table, but they are + presumably not used in an NLM. */ + unsigned char l_symndx[4]; + /* Relocation type. */ + unsigned char l_rtype[2]; + /* Section number being relocated. */ + unsigned char l_rsecnm[2]; +}; + +#endif /* OLDFORMAT */ + +/* The external format of the fixed header. */ + +typedef struct nlm32_powerpc_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* Padding to make it come out correct. */ + + unsigned char pad1[2]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_powerpc_External_Fixed_Header; diff --git a/include/nlm/sparc32-ext.h b/include/nlm/sparc32-ext.h new file mode 100644 index 000000000000..d73b644b4b86 --- /dev/null +++ b/include/nlm/sparc32-ext.h @@ -0,0 +1,120 @@ +/* SPARC NLM (NetWare Loadable Module) support for BFD. + Copyright 1993 Free Software Foundation, Inc. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* The external format of the fixed header. */ + +typedef struct nlm32_sparc_external_fixed_header +{ + + /* The signature field identifies the file as an NLM. It must contain + the signature string, which depends upon the NLM target. */ + + unsigned char signature[24]; + + /* The version of the header. At this time, the highest version number + is 4. */ + + unsigned char version[4]; + + /* The name of the module, which must be a DOS name (1-8 characters followed + by a period and a 1-3 character extension). The first byte is the byte + length of the name and the last byte is a null terminator byte. This + field is fixed length, and any unused bytes should be null bytes. The + value is set by the OUTPUT keyword to NLMLINK. */ + + unsigned char moduleName[14]; + + /* Padding to make it come out correct. */ + + unsigned char pad1[2]; + + /* The byte offset of the code image from the start of the file. */ + + unsigned char codeImageOffset[4]; + + /* The size of the code image, in bytes. */ + + unsigned char codeImageSize[4]; + + /* The byte offset of the data image from the start of the file. */ + + unsigned char dataImageOffset[4]; + + /* The size of the data image, in bytes. */ + + unsigned char dataImageSize[4]; + + /* The size of the uninitialized data region that the loader is to be + allocated at load time. Uninitialized data follows the initialized + data in the NLM address space. */ + + unsigned char uninitializedDataSize[4]; + + /* The byte offset of the custom data from the start of the file. The + custom data is set by the CUSTOM keyword to NLMLINK. It is possible + for this to be EOF if there is no custom data. */ + + unsigned char customDataOffset[4]; + + /* The size of the custom data, in bytes. */ + + unsigned char customDataSize[4]; + + /* The byte offset of the module dependencies from the start of the file. + The module dependencies are determined by the MODULE keyword in + NLMLINK. */ + + unsigned char moduleDependencyOffset[4]; + + /* The number of module dependencies at the moduleDependencyOffset. */ + + unsigned char numberOfModuleDependencies[4]; + + /* The byte offset of the relocation fixup data from the start of the file */ + + unsigned char relocationFixupOffset[4]; + + unsigned char numberOfRelocationFixups[4]; + + unsigned char externalReferencesOffset[4]; + + unsigned char numberOfExternalReferences[4]; + + unsigned char publicsOffset[4]; + + unsigned char numberOfPublics[4]; + + /* The byte offset of the internal debug info from the start of the file. + It is possible for this to be EOF if there is no debug info. */ + + unsigned char debugInfoOffset[4]; + + unsigned char numberOfDebugRecords[4]; + + unsigned char codeStartOffset[4]; + + unsigned char exitProcedureOffset[4]; + + unsigned char checkUnloadProcedureOffset[4]; + + unsigned char moduleType[4]; + + unsigned char flags[4]; + +} Nlm32_sparc_External_Fixed_Header; diff --git a/include/oasys.h b/include/oasys.h new file mode 100644 index 000000000000..c8f737a455b9 --- /dev/null +++ b/include/oasys.h @@ -0,0 +1,192 @@ +/* Oasys object format header file for BFD. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + Contributed by Cygnus Support. */ + +#define OASYS_MAX_SEC_COUNT 16 +/* **** */ + +typedef struct oasys_archive_header + { + unsigned int version; + char create_date[12]; + char revision_date[12]; + unsigned int mod_count; + file_ptr mod_tbl_offset; + unsigned int sym_tbl_size; + unsigned int sym_count; + file_ptr sym_tbl_offset; + unsigned int xref_count; + file_ptr xref_lst_offset; + } +oasys_archive_header_type; + +typedef struct oasys_extarchive_header + { + bfd_byte version[4]; + bfd_byte create_date[12]; + bfd_byte revision_date[12]; + bfd_byte mod_count[4]; + bfd_byte mod_tbl_offset[4]; + bfd_byte sym_tbl_size[4]; + bfd_byte sym_count[4]; + bfd_byte sym_tbl_offset[4]; + bfd_byte xref_count[4]; + bfd_byte xref_lst_offset[4]; + } +oasys_extarchive_header_type; + +typedef struct oasys_module_table + { + int mod_number; + char mod_date[12]; + unsigned int mod_size; + unsigned int dep_count; + unsigned int depee_count; + file_ptr file_offset; + unsigned int sect_count; + char *module_name; + unsigned int module_name_size; + } +oasys_module_table_type; + +typedef struct oasys_extmodule_table_a + { + bfd_byte mod_number[4]; + bfd_byte mod_date[12]; + bfd_byte mod_size[4]; + bfd_byte dep_count[4]; + bfd_byte depee_count[4]; + bfd_byte sect_count[4]; + bfd_byte file_offset[4]; + bfd_byte mod_name[32]; + } +oasys_extmodule_table_type_a_type; + +typedef struct oasys_extmodule_table_b + { + bfd_byte mod_number[4]; + bfd_byte mod_date[12]; + bfd_byte mod_size[4]; + bfd_byte dep_count[4]; + bfd_byte depee_count[4]; + bfd_byte sect_count[4]; + bfd_byte file_offset[4]; + bfd_byte mod_name_length[4]; + } +oasys_extmodule_table_type_b_type; + +typedef enum oasys_record + { + oasys_record_is_end_enum = 0, + oasys_record_is_data_enum = 1, + oasys_record_is_symbol_enum = 2, + oasys_record_is_header_enum = 3, + oasys_record_is_named_section_enum = 4, + oasys_record_is_com_enum = 5, + oasys_record_is_debug_enum = 6, + oasys_record_is_section_enum = 7, + oasys_record_is_debug_file_enum = 8, + oasys_record_is_module_enum = 9, + oasys_record_is_local_enum = 10 + } +oasys_record_enum_type; + +typedef struct oasys_record_header + { + unsigned char length; + unsigned char check_sum; + unsigned char type; + unsigned char fill; + } +oasys_record_header_type; + +typedef struct oasys_data_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte addr[4]; + /* maximum total size of data record is 255 bytes */ + bfd_byte data[246]; + } +oasys_data_record_type; + +typedef struct oasys_header_record + { + oasys_record_header_type header; + unsigned char version_number; + unsigned char rev_number; + char module_name[26-6]; + char description[64-26]; + } +oasys_header_record_type; + +#define OASYS_VERSION_NUMBER 0 +#define OASYS_REV_NUMBER 0 + +typedef struct oasys_symbol_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte value[4]; + bfd_byte refno[2]; + char name[64]; + } +oasys_symbol_record_type; + +#define RELOCATION_PCREL_BIT 0x80 +#define RELOCATION_32BIT_BIT 0x40 +#define RELOCATION_TYPE_BITS 0x30 +#define RELOCATION_TYPE_ABS 0x00 +#define RELOCATION_TYPE_REL 0x10 +#define RELOCATION_TYPE_UND 0x20 +#define RELOCATION_TYPE_COM 0x30 +#define RELOCATION_SECT_BITS 0x0f + +typedef struct oasys_section_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte value[4]; + bfd_byte vma[4]; + bfd_byte fill[3]; + } +oasys_section_record_type; + +typedef struct oasys_end_record + { + oasys_record_header_type header; + unsigned char relb; + bfd_byte entry[4]; + bfd_byte fill[2]; + bfd_byte zero; + } +oasys_end_record_type; + +typedef union oasys_record_union + { + oasys_record_header_type header; + oasys_data_record_type data; + oasys_section_record_type section; + oasys_symbol_record_type symbol; + oasys_header_record_type first; + oasys_end_record_type end; + bfd_byte pad[256]; + } +oasys_record_union_type; diff --git a/include/opcode/a29k.h b/include/opcode/a29k.h new file mode 100644 index 000000000000..c6c8c3700036 --- /dev/null +++ b/include/opcode/a29k.h @@ -0,0 +1,281 @@ +/* Table of opcodes for the AMD 29000 family. + Copyright 1990, 1991, 1993, 1994, 2002 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +struct a29k_opcode { + /* Name of the instruction. */ + char *name; + + /* Opcode word */ + unsigned long opcode; + + /* A string of characters which describe the operands. + Valid characters are: + , Itself. The character appears in the assembly code. + a RA. The register number is in bits 8-15 of the instruction. + b RB. The register number is in bits 0-7 of the instruction. + c RC. The register number is in bits 16-23 of the instruction. + i An immediate operand is in bits 0-7 of the instruction. + x Bits 0-7 and 16-23 of the instruction are bits 0-7 and 8-15 + (respectively) of the immediate operand. + h Same as x but the instruction contains bits 16-31 of the + immediate operand. + X Same as x but bits 16-31 of the signed immediate operand + are set to 1 (thus the operand is always negative). + P,A Bits 0-7 and 16-23 of the instruction are bits 2-9 and 10-17 + (respectively) of the immediate operand. + P=PC-relative, sign-extended to 32 bits. + A=Absolute, zero-extended to 32 bits. + e CE bit (bit 23) for a load/store instruction. + n Control field (bits 16-22) for a load/store instruction. + v Immediate operand in bits 16-23 of the instruction. + (used for trap numbers). + s SA. Special-purpose register number in bits 8-15 + of the instruction. + u UI--bit 7 of the instruction. + r RND--bits 4-6 of the instruction. + d FD--bits 2-3 of the instruction. + f FS--bits 0-1 of the instruction. + I ID--bits 16-17 of the instruction. + + Extensions for 29050: + + d FMT--bits 2-3 of the instruction (not really new). + f ACN--bits 0-1 of the instruction (not really new). + F FUNC--Special function in bits 18-21 of the instruction. + C ACN--bits 16-17 specifying the accumlator register. */ + char *args; +}; + +static const struct a29k_opcode a29k_opcodes[] = +{ + +{ "add", 0x14000000, "c,a,b" }, +{ "add", 0x15000000, "c,a,i" }, +{ "addc", 0x1c000000, "c,a,b" }, +{ "addc", 0x1d000000, "c,a,i" }, +{ "addcs", 0x18000000, "c,a,b" }, +{ "addcs", 0x19000000, "c,a,i" }, +{ "addcu", 0x1a000000, "c,a,b" }, +{ "addcu", 0x1b000000, "c,a,i" }, +{ "adds", 0x10000000, "c,a,b" }, +{ "adds", 0x11000000, "c,a,i" }, +{ "addu", 0x12000000, "c,a,b" }, +{ "addu", 0x13000000, "c,a,i" }, +{ "and", 0x90000000, "c,a,b" }, +{ "and", 0x91000000, "c,a,i" }, +{ "andn", 0x9c000000, "c,a,b" }, +{ "andn", 0x9d000000, "c,a,i" }, +{ "aseq", 0x70000000, "v,a,b" }, +{ "aseq", 0x71000000, "v,a,i" }, +{ "asge", 0x5c000000, "v,a,b" }, +{ "asge", 0x5d000000, "v,a,i" }, +{ "asgeu", 0x5e000000, "v,a,b" }, +{ "asgeu", 0x5f000000, "v,a,i" }, +{ "asgt", 0x58000000, "v,a,b" }, +{ "asgt", 0x59000000, "v,a,i" }, +{ "asgtu", 0x5a000000, "v,a,b" }, +{ "asgtu", 0x5b000000, "v,a,i" }, +{ "asle", 0x54000000, "v,a,b" }, +{ "asle", 0x55000000, "v,a,i" }, +{ "asleu", 0x56000000, "v,a,b" }, +{ "asleu", 0x57000000, "v,a,i" }, +{ "aslt", 0x50000000, "v,a,b" }, +{ "aslt", 0x51000000, "v,a,i" }, +{ "asltu", 0x52000000, "v,a,b" }, +{ "asltu", 0x53000000, "v,a,i" }, +{ "asneq", 0x72000000, "v,a,b" }, +{ "asneq", 0x73000000, "v,a,i" }, +{ "call", 0xa8000000, "a,P" }, +{ "call", 0xa9000000, "a,A" }, +{ "calli", 0xc8000000, "a,b" }, +{ "class", 0xe6000000, "c,a,f" }, +{ "clz", 0x08000000, "c,b" }, +{ "clz", 0x09000000, "c,i" }, +{ "const", 0x03000000, "a,x" }, +{ "consth", 0x02000000, "a,h" }, +{ "consthz", 0x05000000, "a,h" }, +{ "constn", 0x01000000, "a,X" }, +{ "convert", 0xe4000000, "c,a,u,r,d,f" }, +{ "cpbyte", 0x2e000000, "c,a,b" }, +{ "cpbyte", 0x2f000000, "c,a,i" }, +{ "cpeq", 0x60000000, "c,a,b" }, +{ "cpeq", 0x61000000, "c,a,i" }, +{ "cpge", 0x4c000000, "c,a,b" }, +{ "cpge", 0x4d000000, "c,a,i" }, +{ "cpgeu", 0x4e000000, "c,a,b" }, +{ "cpgeu", 0x4f000000, "c,a,i" }, +{ "cpgt", 0x48000000, "c,a,b" }, +{ "cpgt", 0x49000000, "c,a,i" }, +{ "cpgtu", 0x4a000000, "c,a,b" }, +{ "cpgtu", 0x4b000000, "c,a,i" }, +{ "cple", 0x44000000, "c,a,b" }, +{ "cple", 0x45000000, "c,a,i" }, +{ "cpleu", 0x46000000, "c,a,b" }, +{ "cpleu", 0x47000000, "c,a,i" }, +{ "cplt", 0x40000000, "c,a,b" }, +{ "cplt", 0x41000000, "c,a,i" }, +{ "cpltu", 0x42000000, "c,a,b" }, +{ "cpltu", 0x43000000, "c,a,i" }, +{ "cpneq", 0x62000000, "c,a,b" }, +{ "cpneq", 0x63000000, "c,a,i" }, +{ "dadd", 0xf1000000, "c,a,b" }, +{ "ddiv", 0xf7000000, "c,a,b" }, +{ "deq", 0xeb000000, "c,a,b" }, +{ "dge", 0xef000000, "c,a,b" }, +{ "dgt", 0xed000000, "c,a,b" }, +{ "div", 0x6a000000, "c,a,b" }, +{ "div", 0x6b000000, "c,a,i" }, +{ "div0", 0x68000000, "c,b" }, +{ "div0", 0x69000000, "c,i" }, +{ "divide", 0xe1000000, "c,a,b" }, +{ "dividu", 0xe3000000, "c,a,b" }, +{ "divl", 0x6c000000, "c,a,b" }, +{ "divl", 0x6d000000, "c,a,i" }, +{ "divrem", 0x6e000000, "c,a,b" }, +{ "divrem", 0x6f000000, "c,a,i" }, +{ "dmac", 0xd9000000, "F,C,a,b" }, +{ "dmsm", 0xdb000000, "c,a,b" }, +{ "dmul", 0xf5000000, "c,a,b" }, +{ "dsub", 0xf3000000, "c,a,b" }, +{ "emulate", 0xd7000000, "v,a,b" }, +{ "exbyte", 0x0a000000, "c,a,b" }, +{ "exbyte", 0x0b000000, "c,a,i" }, +{ "exhw", 0x7c000000, "c,a,b" }, +{ "exhw", 0x7d000000, "c,a,i" }, +{ "exhws", 0x7e000000, "c,a" }, +{ "extract", 0x7a000000, "c,a,b" }, +{ "extract", 0x7b000000, "c,a,i" }, +{ "fadd", 0xf0000000, "c,a,b" }, +{ "fdiv", 0xf6000000, "c,a,b" }, +{ "fdmul", 0xf9000000, "c,a,b" }, +{ "feq", 0xea000000, "c,a,b" }, +{ "fge", 0xee000000, "c,a,b" }, +{ "fgt", 0xec000000, "c,a,b" }, +{ "fmac", 0xd8000000, "F,C,a,b" }, +{ "fmsm", 0xda000000, "c,a,b" }, +{ "fmul", 0xf4000000, "c,a,b" }, +{ "fsub", 0xf2000000, "c,a,b" }, +{ "halt", 0x89000000, "" }, +{ "inbyte", 0x0c000000, "c,a,b" }, +{ "inbyte", 0x0d000000, "c,a,i" }, +{ "inhw", 0x78000000, "c,a,b" }, +{ "inhw", 0x79000000, "c,a,i" }, +{ "inv", 0x9f000000, "I" }, +{ "iret", 0x88000000, "" }, +{ "iretinv", 0x8c000000, "I" }, +{ "jmp", 0xa0000000, "P" }, +{ "jmp", 0xa1000000, "A" }, +{ "jmpf", 0xa4000000, "a,P" }, +{ "jmpf", 0xa5000000, "a,A" }, +{ "jmpfdec", 0xb4000000, "a,P" }, +{ "jmpfdec", 0xb5000000, "a,A" }, +{ "jmpfi", 0xc4000000, "a,b" }, +{ "jmpi", 0xc0000000, "b" }, +{ "jmpt", 0xac000000, "a,P" }, +{ "jmpt", 0xad000000, "a,A" }, +{ "jmpti", 0xcc000000, "a,b" }, +{ "load", 0x16000000, "e,n,a,b" }, +{ "load", 0x17000000, "e,n,a,i" }, +{ "loadl", 0x06000000, "e,n,a,b" }, +{ "loadl", 0x07000000, "e,n,a,i" }, +{ "loadm", 0x36000000, "e,n,a,b" }, +{ "loadm", 0x37000000, "e,n,a,i" }, +{ "loadset", 0x26000000, "e,n,a,b" }, +{ "loadset", 0x27000000, "e,n,a,i" }, +{ "mfacc", 0xe9000100, "c,d,f" }, +{ "mfsr", 0xc6000000, "c,s" }, +{ "mftlb", 0xb6000000, "c,a" }, +{ "mtacc", 0xe8010000, "a,d,f" }, +{ "mtsr", 0xce000000, "s,b" }, +{ "mtsrim", 0x04000000, "s,x" }, +{ "mttlb", 0xbe000000, "a,b" }, +{ "mul", 0x64000000, "c,a,b" }, +{ "mul", 0x65000000, "c,a,i" }, +{ "mull", 0x66000000, "c,a,b" }, +{ "mull", 0x67000000, "c,a,i" }, +{ "multiplu", 0xe2000000, "c,a,b" }, +{ "multiply", 0xe0000000, "c,a,b" }, +{ "multm", 0xde000000, "c,a,b" }, +{ "multmu", 0xdf000000, "c,a,b" }, +{ "mulu", 0x74000000, "c,a,b" }, +{ "mulu", 0x75000000, "c,a,i" }, +{ "nand", 0x9a000000, "c,a,b" }, +{ "nand", 0x9b000000, "c,a,i" }, +{ "nop", 0x70400101, "" }, +{ "nor", 0x98000000, "c,a,b" }, +{ "nor", 0x99000000, "c,a,i" }, +{ "or", 0x92000000, "c,a,b" }, +{ "or", 0x93000000, "c,a,i" }, +{ "orn", 0xaa000000, "c,a,b" }, +{ "orn", 0xab000000, "c,a,i" }, + +/* The description of "setip" in Chapter 8 ("instruction set") of the user's + manual claims that these are absolute register numbers. But section + 7.2.1 explains that they are not. The latter is correct, so print + these normally ("lr0", "lr5", etc.). */ +{ "setip", 0x9e000000, "c,a,b" }, + +{ "sll", 0x80000000, "c,a,b" }, +{ "sll", 0x81000000, "c,a,i" }, +{ "sqrt", 0xe5000000, "c,a,f" }, +{ "sra", 0x86000000, "c,a,b" }, +{ "sra", 0x87000000, "c,a,i" }, +{ "srl", 0x82000000, "c,a,b" }, +{ "srl", 0x83000000, "c,a,i" }, +{ "store", 0x1e000000, "e,n,a,b" }, +{ "store", 0x1f000000, "e,n,a,i" }, +{ "storel", 0x0e000000, "e,n,a,b" }, +{ "storel", 0x0f000000, "e,n,a,i" }, +{ "storem", 0x3e000000, "e,n,a,b" }, +{ "storem", 0x3f000000, "e,n,a,i" }, +{ "sub", 0x24000000, "c,a,b" }, +{ "sub", 0x25000000, "c,a,i" }, +{ "subc", 0x2c000000, "c,a,b" }, +{ "subc", 0x2d000000, "c,a,i" }, +{ "subcs", 0x28000000, "c,a,b" }, +{ "subcs", 0x29000000, "c,a,i" }, +{ "subcu", 0x2a000000, "c,a,b" }, +{ "subcu", 0x2b000000, "c,a,i" }, +{ "subr", 0x34000000, "c,a,b" }, +{ "subr", 0x35000000, "c,a,i" }, +{ "subrc", 0x3c000000, "c,a,b" }, +{ "subrc", 0x3d000000, "c,a,i" }, +{ "subrcs", 0x38000000, "c,a,b" }, +{ "subrcs", 0x39000000, "c,a,i" }, +{ "subrcu", 0x3a000000, "c,a,b" }, +{ "subrcu", 0x3b000000, "c,a,i" }, +{ "subrs", 0x30000000, "c,a,b" }, +{ "subrs", 0x31000000, "c,a,i" }, +{ "subru", 0x32000000, "c,a,b" }, +{ "subru", 0x33000000, "c,a,i" }, +{ "subs", 0x20000000, "c,a,b" }, +{ "subs", 0x21000000, "c,a,i" }, +{ "subu", 0x22000000, "c,a,b" }, +{ "subu", 0x23000000, "c,a,i" }, +{ "xnor", 0x96000000, "c,a,b" }, +{ "xnor", 0x97000000, "c,a,i" }, +{ "xor", 0x94000000, "c,a,b" }, +{ "xor", 0x95000000, "c,a,i" }, + +{ "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ +}; + +const unsigned int num_opcodes = (((sizeof a29k_opcodes) / (sizeof a29k_opcodes[0])) - 1); diff --git a/include/opcode/avr.h b/include/opcode/avr.h new file mode 100644 index 000000000000..bcc093d302b3 --- /dev/null +++ b/include/opcode/avr.h @@ -0,0 +1,260 @@ +/* Opcode table for the Atmel AVR micro controllers. + + Copyright 2000 Free Software Foundation, Inc. + Contributed by Denis Chertykov <denisc@overta.ru> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define AVR_ISA_1200 0x0001 /* in the beginning there was ... */ +#define AVR_ISA_LPM 0x0002 /* device has LPM */ +#define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */ +#define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */ +#define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL + supported, no 8K wrap on RJMP and RCALL) */ +#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, MOVW, ...) */ +#define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */ +#define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */ +#define AVR_ISA_SPM 0x0200 /* device can program itself */ +#define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */ +#define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */ + +#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) +#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) +#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM) +#define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA) +#define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM) +#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM) +#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX) +#define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) +#define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) + +#define AVR_ISA_ALL 0xFFFF + +#define REGISTER_P(x) ((x) == 'r' \ + || (x) == 'd' \ + || (x) == 'w' \ + || (x) == 'a' \ + || (x) == 'v') + +/* Undefined combination of operands - does the register + operand overlap with pre-decremented or post-incremented + pointer register (like ld r31,Z+)? */ +#define AVR_UNDEF_P(x) (((x) & 0xFFED) == 0x91E5 || \ + ((x) & 0xFDEF) == 0x91AD || ((x) & 0xFDEF) == 0x91AE || \ + ((x) & 0xFDEF) == 0x91C9 || ((x) & 0xFDEF) == 0x91CA || \ + ((x) & 0xFDEF) == 0x91E1 || ((x) & 0xFDEF) == 0x91E2) + +/* Is this a skip instruction {cpse,sbic,sbis,sbrc,sbrs}? */ +#define AVR_SKIP_P(x) (((x) & 0xFC00) == 0x1000 || \ + ((x) & 0xFD00) == 0x9900 || ((x) & 0xFC08) == 0xFC00) + +/* Is this `ldd r,b+0' or `std b+0,r' (b={Y,Z}, disassembled as + `ld r,b' or `st b,r' respectively - next opcode entry)? */ +#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000) + +/* constraint letters + r - any register + d - `ldi' register (r16-r31) + v - `movw' even register (r0, r2, ..., r28, r30) + a - `fmul' register (r16-r23) + w - `adiw' register (r24,r26,r28,r30) + e - pointer registers (X,Y,Z) + b - base pointer register and displacement ([YZ]+disp) + z - Z pointer register (for [e]lpm Rd,Z[+]) + M - immediate value from 0 to 255 + n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible + s - immediate value from 0 to 7 + P - Port address value from 0 to 63. (in, out) + p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis) + K - immediate value from 0 to 63 (used in `adiw', `sbiw') + i - immediate value + l - signed pc relative offset from -64 to 63 + L - signed pc relative offset from -2048 to 2047 + h - absolute code address (call, jmp) + S - immediate value from 0 to 7 (S = s << 4) + ? - use this opcode entry if no parameters, else use next opcode entry + + Order is important - some binary opcodes have more than one name, + the disassembler will only see the first match. + + Remaining undefined opcodes (1699 total - some of them might work + as normal instructions if not all of the bits are decoded): + + 0x0001...0x00ff (255) (known to be decoded as `nop' by the old core) + "100100xxxxxxx011" (128) 0x9[0-3][0-9a-f][3b] + "100100xxxxxx1000" (64) 0x9[0-3][0-9a-f]8 + "1001001xxxxx01xx" (128) 0x9[23][0-9a-f][4-7] + "1001010xxxxx0100" (32) 0x9[45][0-9a-f]4 + "1001010x001x1001" (4) 0x9[45][23]9 + "1001010x01xx1001" (8) 0x9[45][4-7]9 + "1001010x1xxx1001" (16) 0x9[45][8-9a-f]9 + "1001010xxxxx1011" (32) 0x9[45][0-9a-f]b + "10010101001x1000" (2) 0x95[23]8 + "1001010101xx1000" (4) 0x95[4-7]8 + "1001010110111000" (1) 0x95b8 + "1001010111111000" (1) 0x95f8 (`espm' removed in databook update) + "11111xxxxxxx1xxx" (1024) 0xf[8-9a-f][0-9a-f][8-9a-f] + */ + +AVR_INSN (clc, "", "1001010010001000", 1, AVR_ISA_1200, 0x9488) +AVR_INSN (clh, "", "1001010011011000", 1, AVR_ISA_1200, 0x94d8) +AVR_INSN (cli, "", "1001010011111000", 1, AVR_ISA_1200, 0x94f8) +AVR_INSN (cln, "", "1001010010101000", 1, AVR_ISA_1200, 0x94a8) +AVR_INSN (cls, "", "1001010011001000", 1, AVR_ISA_1200, 0x94c8) +AVR_INSN (clt, "", "1001010011101000", 1, AVR_ISA_1200, 0x94e8) +AVR_INSN (clv, "", "1001010010111000", 1, AVR_ISA_1200, 0x94b8) +AVR_INSN (clz, "", "1001010010011000", 1, AVR_ISA_1200, 0x9498) + +AVR_INSN (sec, "", "1001010000001000", 1, AVR_ISA_1200, 0x9408) +AVR_INSN (seh, "", "1001010001011000", 1, AVR_ISA_1200, 0x9458) +AVR_INSN (sei, "", "1001010001111000", 1, AVR_ISA_1200, 0x9478) +AVR_INSN (sen, "", "1001010000101000", 1, AVR_ISA_1200, 0x9428) +AVR_INSN (ses, "", "1001010001001000", 1, AVR_ISA_1200, 0x9448) +AVR_INSN (set, "", "1001010001101000", 1, AVR_ISA_1200, 0x9468) +AVR_INSN (sev, "", "1001010000111000", 1, AVR_ISA_1200, 0x9438) +AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418) + + /* Same as {cl,se}[chinstvz] above. */ +AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488) +AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408) + +AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509) +AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409) + +AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8) +AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004) +AVR_INSN (elpm, "?", "1001010111011000", 1, AVR_ISA_ELPM, 0x95d8) +AVR_INSN (elpm, "r,z", "1001000ddddd011+", 1, AVR_ISA_ELPMX,0x9006) + +AVR_INSN (nop, "", "0000000000000000", 1, AVR_ISA_1200, 0x0000) +AVR_INSN (ret, "", "1001010100001000", 1, AVR_ISA_1200, 0x9508) +AVR_INSN (reti, "", "1001010100011000", 1, AVR_ISA_1200, 0x9518) +AVR_INSN (sleep,"", "1001010110001000", 1, AVR_ISA_1200, 0x9588) +AVR_INSN (break,"", "1001010110011000", 1, AVR_ISA_BRK, 0x9598) +AVR_INSN (wdr, "", "1001010110101000", 1, AVR_ISA_1200, 0x95a8) +AVR_INSN (spm, "", "1001010111101000", 1, AVR_ISA_SPM, 0x95e8) + +AVR_INSN (adc, "r,r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) +AVR_INSN (add, "r,r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) +AVR_INSN (and, "r,r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) +AVR_INSN (cp, "r,r", "000101rdddddrrrr", 1, AVR_ISA_1200, 0x1400) +AVR_INSN (cpc, "r,r", "000001rdddddrrrr", 1, AVR_ISA_1200, 0x0400) +AVR_INSN (cpse, "r,r", "000100rdddddrrrr", 1, AVR_ISA_1200, 0x1000) +AVR_INSN (eor, "r,r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) +AVR_INSN (mov, "r,r", "001011rdddddrrrr", 1, AVR_ISA_1200, 0x2c00) +AVR_INSN (mul, "r,r", "100111rdddddrrrr", 1, AVR_ISA_MUL, 0x9c00) +AVR_INSN (or, "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800) +AVR_INSN (sbc, "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800) +AVR_INSN (sub, "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800) + + /* Shorthand for {eor,add,adc,and} r,r above. */ +AVR_INSN (clr, "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) +AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) +AVR_INSN (rol, "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) +AVR_INSN (tst, "r=r", "001000rdddddrrrr", 1, AVR_ISA_1200, 0x2000) + +AVR_INSN (andi, "d,M", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) + /*XXX special case*/ +AVR_INSN (cbr, "d,n", "0111KKKKddddKKKK", 1, AVR_ISA_1200, 0x7000) + +AVR_INSN (ldi, "d,M", "1110KKKKddddKKKK", 1, AVR_ISA_1200, 0xe000) +AVR_INSN (ser, "d", "11101111dddd1111", 1, AVR_ISA_1200, 0xef0f) + +AVR_INSN (ori, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) +AVR_INSN (sbr, "d,M", "0110KKKKddddKKKK", 1, AVR_ISA_1200, 0x6000) + +AVR_INSN (cpi, "d,M", "0011KKKKddddKKKK", 1, AVR_ISA_1200, 0x3000) +AVR_INSN (sbci, "d,M", "0100KKKKddddKKKK", 1, AVR_ISA_1200, 0x4000) +AVR_INSN (subi, "d,M", "0101KKKKddddKKKK", 1, AVR_ISA_1200, 0x5000) + +AVR_INSN (sbrc, "r,s", "1111110rrrrr0sss", 1, AVR_ISA_1200, 0xfc00) +AVR_INSN (sbrs, "r,s", "1111111rrrrr0sss", 1, AVR_ISA_1200, 0xfe00) +AVR_INSN (bld, "r,s", "1111100ddddd0sss", 1, AVR_ISA_1200, 0xf800) +AVR_INSN (bst, "r,s", "1111101ddddd0sss", 1, AVR_ISA_1200, 0xfa00) + +AVR_INSN (in, "r,P", "10110PPdddddPPPP", 1, AVR_ISA_1200, 0xb000) +AVR_INSN (out, "P,r", "10111PPrrrrrPPPP", 1, AVR_ISA_1200, 0xb800) + +AVR_INSN (adiw, "w,K", "10010110KKddKKKK", 1, AVR_ISA_2xxx, 0x9600) +AVR_INSN (sbiw, "w,K", "10010111KKddKKKK", 1, AVR_ISA_2xxx, 0x9700) + +AVR_INSN (cbi, "p,s", "10011000pppppsss", 1, AVR_ISA_1200, 0x9800) +AVR_INSN (sbi, "p,s", "10011010pppppsss", 1, AVR_ISA_1200, 0x9a00) +AVR_INSN (sbic, "p,s", "10011001pppppsss", 1, AVR_ISA_1200, 0x9900) +AVR_INSN (sbis, "p,s", "10011011pppppsss", 1, AVR_ISA_1200, 0x9b00) + +AVR_INSN (brcc, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) +AVR_INSN (brcs, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) +AVR_INSN (breq, "l", "111100lllllll001", 1, AVR_ISA_1200, 0xf001) +AVR_INSN (brge, "l", "111101lllllll100", 1, AVR_ISA_1200, 0xf404) +AVR_INSN (brhc, "l", "111101lllllll101", 1, AVR_ISA_1200, 0xf405) +AVR_INSN (brhs, "l", "111100lllllll101", 1, AVR_ISA_1200, 0xf005) +AVR_INSN (brid, "l", "111101lllllll111", 1, AVR_ISA_1200, 0xf407) +AVR_INSN (brie, "l", "111100lllllll111", 1, AVR_ISA_1200, 0xf007) +AVR_INSN (brlo, "l", "111100lllllll000", 1, AVR_ISA_1200, 0xf000) +AVR_INSN (brlt, "l", "111100lllllll100", 1, AVR_ISA_1200, 0xf004) +AVR_INSN (brmi, "l", "111100lllllll010", 1, AVR_ISA_1200, 0xf002) +AVR_INSN (brne, "l", "111101lllllll001", 1, AVR_ISA_1200, 0xf401) +AVR_INSN (brpl, "l", "111101lllllll010", 1, AVR_ISA_1200, 0xf402) +AVR_INSN (brsh, "l", "111101lllllll000", 1, AVR_ISA_1200, 0xf400) +AVR_INSN (brtc, "l", "111101lllllll110", 1, AVR_ISA_1200, 0xf406) +AVR_INSN (brts, "l", "111100lllllll110", 1, AVR_ISA_1200, 0xf006) +AVR_INSN (brvc, "l", "111101lllllll011", 1, AVR_ISA_1200, 0xf403) +AVR_INSN (brvs, "l", "111100lllllll011", 1, AVR_ISA_1200, 0xf003) + + /* Same as br?? above. */ +AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400) +AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000) + +AVR_INSN (rcall, "L", "1101LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xd000) +AVR_INSN (rjmp, "L", "1100LLLLLLLLLLLL", 1, AVR_ISA_1200, 0xc000) + +AVR_INSN (call, "h", "1001010hhhhh111h", 2, AVR_ISA_MEGA, 0x940e) +AVR_INSN (jmp, "h", "1001010hhhhh110h", 2, AVR_ISA_MEGA, 0x940c) + +AVR_INSN (asr, "r", "1001010rrrrr0101", 1, AVR_ISA_1200, 0x9405) +AVR_INSN (com, "r", "1001010rrrrr0000", 1, AVR_ISA_1200, 0x9400) +AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a) +AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403) +AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406) +AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401) +AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f) +AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f) +AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) +AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) + + /* Known to be decoded as `nop' by the old core. */ +AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MUL, 0x0100) +AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200) +AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300) +AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308) +AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380) +AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388) + +AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200) +AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000) + + /* Special case for b+0, `e' must be next entry after `b', + b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ +AVR_INSN (ldd, "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000) +AVR_INSN (ld, "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000) +AVR_INSN (std, "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200) +AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200) + + /* These are for devices that don't exist yet + (>128K program memory, PC = EIND:Z). */ +AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519) +AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419) + diff --git a/include/opcode/cris.h b/include/opcode/cris.h new file mode 100644 index 000000000000..1f10034c304d --- /dev/null +++ b/include/opcode/cris.h @@ -0,0 +1,300 @@ +/* cris.h -- Header file for CRIS opcode and register tables. + Copyright (C) 2000, 2001 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Originally written for GAS 1.38.1 by Mikael Asker. + Updated, BFDized and GNUified by Hans-Peter Nilsson. + +This file is part of GAS, GDB and the GNU binutils. + +GAS, GDB, and GNU binutils is free software; you can redistribute it +and/or modify it under the terms of the GNU General Public License as +published by the Free Software Foundation; either version 2, or (at your +option) any later version. + +GAS, GDB, and GNU binutils are distributed in the hope that they will be +useful, but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef __CRIS_H_INCLUDED_ +#define __CRIS_H_INCLUDED_ + +#if !defined(__STDC__) && !defined(const) +#define const +#endif + + +/* Registers. */ +#define MAX_REG (15) +#define REG_SP (14) +#define REG_PC (15) + +/* CPU version control of disassembly and assembly of instructions. + May affect how the instruction is assembled, at least the size of + immediate operands. */ +enum cris_insn_version_usage +{ + /* Any version. */ + cris_ver_version_all=0, + + /* Indeterminate (intended for disassembly only, or obsolete). */ + cris_ver_warning, + + /* Simulator only (reserved). */ + cris_ver_sim, + + /* Only for v0..3 (Etrax 1..4). */ + cris_ver_v0_3, + + /* Only for v3 or higher (ETRAX 4 and beyond). */ + cris_ver_v3p, + + /* Only for v8 (Etrax 100). */ + cris_ver_v8, + + /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */ + cris_ver_v8p, + + /* Only for v10 or higher (ETRAX 100 LX). + Of course some or all these of may change to cris_ver_v10p if/when + there's a new revision. */ + cris_ver_v10p +}; + + +/* Special registers. */ +struct cris_spec_reg +{ + const char *const name; + unsigned int number; + + /* The size of the register. */ + unsigned int reg_size; + + /* What CPU version the special register of that name is implemented + in. If cris_ver_warning, emit an unimplemented-warning. */ + enum cris_insn_version_usage applicable_version; + + /* There might be a specific warning for using a special register + here. */ + const char *const warning; +}; +extern const struct cris_spec_reg cris_spec_regs[]; + +/* Opcode-dependent constants. */ +#define AUTOINCR_BIT (0x04) + +/* Prefixes. */ +#define BDAP_QUICK_OPCODE (0x0100) +#define BDAP_QUICK_Z_BITS (0x0e00) + +#define BIAP_OPCODE (0x0540) +#define BIAP_Z_BITS (0x0a80) + +#define DIP_OPCODE (0x0970) +#define DIP_Z_BITS (0xf280) + +#define BDAP_INDIR_LOW (0x40) +#define BDAP_INDIR_LOW_Z (0x80) +#define BDAP_INDIR_HIGH (0x09) +#define BDAP_INDIR_HIGH_Z (0x02) + +#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW) +#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z) +#define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC) +#define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT) + +/* No prefix must have this code for its "match" bits in the + opcode-table. "BCC .+2" will do nicely. */ +#define NO_CRIS_PREFIX 0 + +/* Definitions for condition codes. */ +#define CC_CC 0x0 +#define CC_HS 0x0 +#define CC_CS 0x1 +#define CC_LO 0x1 +#define CC_NE 0x2 +#define CC_EQ 0x3 +#define CC_VC 0x4 +#define CC_VS 0x5 +#define CC_PL 0x6 +#define CC_MI 0x7 +#define CC_LS 0x8 +#define CC_HI 0x9 +#define CC_GE 0xA +#define CC_LT 0xB +#define CC_GT 0xC +#define CC_LE 0xD +#define CC_A 0xE +#define CC_EXT 0xF + +/* A table of strings "cc", "cs"... indexed with condition code + values as above. */ +extern const char *const cris_cc_strings[]; + +/* Bcc quick. */ +#define BRANCH_QUICK_LOW (0) +#define BRANCH_QUICK_HIGH (0) +#define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW) +#define BRANCH_QUICK_Z_BITS (0x0F00) + +/* BA quick. */ +#define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10) +#define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW) + +/* Bcc [PC+]. */ +#define BRANCH_PC_LOW (0xFF) +#define BRANCH_INCR_HIGH (0x0D) +#define BA_PC_INCR_OPCODE \ + ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW) + +/* Jump. */ +/* Note that old versions generated special register 8 (in high bits) + and not-that-old versions recognized it as a jump-instruction. + That opcode now belongs to JUMPU. */ +#define JUMP_INDIR_OPCODE (0x0930) +#define JUMP_INDIR_Z_BITS (0xf2c0) +#define JUMP_PC_INCR_OPCODE \ + (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC) +#define ADD_PC_INCR_OPCODE \ + (0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC) + +/* Nop. */ +#define NOP_OPCODE (0x050F) +#define NOP_Z_BITS (0xFAF0) + +/* Structure of an opcode table entry. */ +enum cris_imm_oprnd_size_type +{ + /* No size is applicable. */ + SIZE_NONE, + + /* Always 32 bits. */ + SIZE_FIX_32, + + /* Indicated by size of special register. */ + SIZE_SPEC_REG, + + /* Indicated by size field. */ + SIZE_FIELD +}; + +/* For GDB. FIXME: Is this the best way to handle opcode + interpretation? */ +enum cris_op_type +{ + cris_not_implemented_op = 0, + cris_abs_op, + cris_addi_op, + cris_asr_op, + cris_asrq_op, + cris_ax_ei_setf_op, + cris_bdap_prefix, + cris_biap_prefix, + cris_break_op, + cris_btst_nop_op, + cris_clearf_di_op, + cris_dip_prefix, + cris_dstep_logshift_mstep_neg_not_op, + cris_eight_bit_offset_branch_op, + cris_move_mem_to_reg_movem_op, + cris_move_reg_to_mem_movem_op, + cris_move_to_preg_op, + cris_muls_op, + cris_mulu_op, + cris_none_reg_mode_add_sub_cmp_and_or_move_op, + cris_none_reg_mode_clear_test_op, + cris_none_reg_mode_jump_op, + cris_none_reg_mode_move_from_preg_op, + cris_quick_mode_add_sub_op, + cris_quick_mode_and_cmp_move_or_op, + cris_quick_mode_bdap_prefix, + cris_reg_mode_add_sub_cmp_and_or_move_op, + cris_reg_mode_clear_op, + cris_reg_mode_jump_op, + cris_reg_mode_move_from_preg_op, + cris_reg_mode_test_op, + cris_scc_op, + cris_sixteen_bit_offset_branch_op, + cris_three_operand_add_sub_cmp_and_or_op, + cris_three_operand_bound_op, + cris_two_operand_bound_op, + cris_xor_op +}; + +struct cris_opcode +{ + /* The name of the insn. */ + const char *name; + + /* Bits that must be 1 for a match. */ + unsigned int match; + + /* Bits that must be 0 for a match. */ + unsigned int lose; + + /* See the table in "opcodes/cris-opc.c". */ + const char *args; + + /* Nonzero if this is a delayed branch instruction. */ + char delayed; + + /* Size of immediate operands. */ + enum cris_imm_oprnd_size_type imm_oprnd_size; + + /* Indicates which version this insn was first implemented in. */ + enum cris_insn_version_usage applicable_version; + + /* What kind of operation this is. */ + enum cris_op_type op; +}; +extern const struct cris_opcode cris_opcodes[]; + + +/* These macros are for the target-specific flags in disassemble_info + used at disassembly. */ + +/* This insn accesses memory. This flag is more trustworthy than + checking insn_type for "dis_dref" which does not work for + e.g. "JSR [foo]". */ +#define CRIS_DIS_FLAG_MEMREF (1 << 0) + +/* The "target" field holds a register number. */ +#define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1) + +/* The "target2" field holds a register number; add it to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2) + +/* Yet another add-on: the register in "target2" must be multiplied + by 2 before adding to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3) + +/* Yet another add-on: the register in "target2" must be multiplied + by 4 (mutually exclusive with .._MULT2). */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4) + +/* The register in "target2" is an indirect memory reference (of the + register there), add to "target". Assumed size is dword (mutually + exclusive with .._MULT[24]). */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5) + +/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte"; + sign-extended before adding to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6) + +/* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word"; + sign-extended before adding to "target". */ +#define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7) + +#endif /* __CRIS_H_INCLUDED_ */ + +/* + * Local variables: + * eval: (c-set-style "gnu") + * indent-tabs-mode: t + * End: + */ diff --git a/include/opcode/d10v.h b/include/opcode/d10v.h new file mode 100644 index 000000000000..74d9006f17cb --- /dev/null +++ b/include/opcode/d10v.h @@ -0,0 +1,208 @@ +/* d10v.h -- Header file for D10V opcode table + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Free Software Foundation, Inc. + Written by Martin Hunt (hunt@cygnus.com), Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef D10V_H +#define D10V_H + +/* Format Specifier */ +#define FM00 0 +#define FM01 0x40000000 +#define FM10 0x80000000 +#define FM11 0xC0000000 + +#define NOP 0x5e00 +#define OPCODE_DIVS 0x14002800 + +/* The opcode table is an array of struct d10v_opcode. */ + +struct d10v_opcode +{ + /* The opcode name. */ + const char *name; + + /* the opcode format */ + int format; + + /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ +#define SHORT_OPCODE 1 +#define LONG_OPCODE 8 +#define SHORT_2 1 /* short with 2 operands */ +#define SHORT_B 3 /* short with 8-bit branch */ +#define LONG_B 8 /* long with 16-bit branch */ +#define LONG_L 10 /* long with 3 operands */ +#define LONG_R 12 /* reserved */ + + /* just a placeholder for variable-length instructions */ + /* for example, "bra" will be a fake for "bra.s" and bra.l" */ + /* which will immediately follow in the opcode table. */ +#define OPCODE_FAKE 32 + + /* the number of cycles */ + int cycles; + + /* the execution unit(s) used */ + int unit; +#define EITHER 0 +#define IU 1 +#define MU 2 +#define BOTH 3 + + /* execution type; parallel or sequential */ + /* this field is used to decide if two instructions */ + /* can be executed in parallel */ + int exec_type; +#define PARONLY 1 /* parallel only */ +#define SEQ 2 /* must be sequential */ +#define PAR 4 /* may be parallel */ +#define BRANCH_LINK 8 /* subroutine call. must be aligned */ +#define RMEM 16 /* reads memory */ +#define WMEM 32 /* writes memory */ +#define RF0 64 /* reads f0 */ +#define WF0 128 /* modifies f0 */ +#define WCAR 256 /* write Carry */ +#define BRANCH 512 /* branch, no link */ +#define ALONE 1024 /* short but pack with a NOP if on asm line alone */ + + /* the opcode */ + long opcode; + + /* mask. if( (i & mask) == opcode ) then match */ + long mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[6]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct d10v_opcode d10v_opcodes[]; +extern const int d10v_num_opcodes; + +/* The operands table is an array of struct d10v_operand. */ +struct d10v_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the d10v_opcodes table. */ + +extern const struct d10v_operand d10v_operands[]; + +/* Values defined for the flags field of a struct d10v_operand. */ + +/* the operand must be an even number */ +#define OPERAND_EVEN (1) + +/* the operand must be an odd number */ +#define OPERAND_ODD (2) + +/* this is the destination register; it will be modified */ +/* this is used by the optimizer */ +#define OPERAND_DEST (4) + +/* number or symbol */ +#define OPERAND_NUM (8) + +/* address or label */ +#define OPERAND_ADDR (0x10) + +/* register */ +#define OPERAND_REG (0x20) + +/* postincrement + */ +#define OPERAND_PLUS (0x40) + +/* postdecrement - */ +#define OPERAND_MINUS (0x80) + +/* @ */ +#define OPERAND_ATSIGN (0x100) + +/* @( */ +#define OPERAND_ATPAR (0x200) + +/* accumulator 0 */ +#define OPERAND_ACC0 (0x400) + +/* accumulator 1 */ +#define OPERAND_ACC1 (0x800) + +/* f0 / f1 flag register */ +#define OPERAND_FFLAG (0x1000) + +/* c flag register */ +#define OPERAND_CFLAG (0x2000) + +/* control register */ +#define OPERAND_CONTROL (0x4000) + +/* predecrement mode '@-sp' */ +#define OPERAND_ATMINUS (0x8000) + +/* signed number */ +#define OPERAND_SIGNED (0x10000) + +/* special accumulator shifts need a 4-bit number */ +/* 1 <= x <= 16 */ +#define OPERAND_SHIFT (0x20000) + +/* general purpose register */ +#define OPERAND_GPR (0x40000) + +/* special imm3 values with range restricted to -2 <= imm3 <= 3 */ +/* needed for rac/rachi */ +#define RESTRICTED_NUM3 (0x80000) + +/* Pre-decrement is only supported for SP. */ +#define OPERAND_SP (0x100000) + +/* Post-decrement is not supported for SP. Like OPERAND_EVEN, and + unlike OPERAND_SP, this flag doesn't prevent the instruction from + matching, it only fails validation later on. */ +#define OPERAND_NOSP (0x200000) + +/* Structure to hold information about predefined registers. */ +struct pd_reg +{ + char *name; /* name to recognize */ + char *pname; /* name to print for this register */ + int value; +}; + +extern const struct pd_reg d10v_predefined_registers[]; +int d10v_reg_name_cnt (void); + +/* an expressionS only has one register type, so we fake it */ +/* by setting high bits to indicate type */ +#define REGISTER_MASK 0xFF + +#endif /* D10V_H */ diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h new file mode 100644 index 000000000000..809bdeb7db72 --- /dev/null +++ b/include/opcode/d30v.h @@ -0,0 +1,286 @@ +/* d30v.h -- Header file for D30V opcode table + Copyright 1997, 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc. + Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef D30V_H +#define D30V_H + +#define NOP 0x00F00000 + +/* Structure to hold information about predefined registers. */ +struct pd_reg +{ + char *name; /* name to recognize */ + char *pname; /* name to print for this register */ + int value; +}; + +extern const struct pd_reg pre_defined_registers[]; +int reg_name_cnt (void); + +/* the number of control registers */ +#define MAX_CONTROL_REG 64 + +/* define the format specifiers */ +#define FM00 0 +#define FM01 0x80000000 +#define FM10 0x8000000000000000LL +#define FM11 0x8000000080000000LL + +/* define the opcode classes */ +#define BRA 0 +#define LOGIC 1 +#define IMEM 2 +#define IALU1 4 +#define IALU2 5 + +/* define the execution condition codes */ +#define ECC_AL 0 /* ALways (default) */ +#define ECC_TX 1 /* F0=True, F1=Don't care */ +#define ECC_FX 2 /* F0=False, F1=Don't care */ +#define ECC_XT 3 /* F0=Don't care, F1=True */ +#define ECC_XF 4 /* F0=Don't care, F1=False */ +#define ECC_TT 5 /* F0=True, F1=True */ +#define ECC_TF 6 /* F0=True, F1=False */ +#define ECC_RESERVED 7 /* reserved */ +#define ECC_MAX ECC_RESERVED + +extern const char *d30v_ecc_names[]; + +/* condition code table for CMP and CMPU */ +extern const char *d30v_cc_names[]; + +/* The opcode table is an array of struct d30v_opcode. */ +struct d30v_opcode +{ + /* The opcode name. */ + const char *name; + + /* the opcode */ + int op1; /* first part, "IALU1" for example */ + int op2; /* the rest of the opcode */ + + /* opcode format(s). These numbers correspond to entries */ + /* in the d30v_format_table */ + unsigned char format[4]; + +#define SHORT_M 1 +#define SHORT_M2 5 /* for ld2w and st2w */ +#define SHORT_A 9 +#define SHORT_B1 11 +#define SHORT_B2 12 +#define SHORT_B2r 13 +#define SHORT_B3 14 +#define SHORT_B3r 16 +#define SHORT_B3b 18 +#define SHORT_B3br 20 +#define SHORT_D1r 22 +#define SHORT_D2 24 +#define SHORT_D2r 26 +#define SHORT_D2Br 28 +#define SHORT_U 30 /* unary SHORT_A. ABS for example */ +#define SHORT_F 31 /* SHORT_A with flag registers */ +#define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ +#define SHORT_T 35 /* for trap instruction */ +#define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ +#define SHORT_CMP 38 /* special form for CMPcc */ +#define SHORT_CMPU 40 /* special form for CMPUcc */ +#define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ +#define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ +#define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ +#define SHORT_MODINC 48 +#define SHORT_MODDEC 49 +#define SHORT_C1 50 +#define SHORT_C2 51 +#define SHORT_UF 52 +#define SHORT_A2 53 +#define SHORT_NONE 55 /* no operands */ +#define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ +#define LONG 57 +#define LONG_U 58 /* unary LONG */ +#define LONG_Ur 59 /* LONG pc-relative */ +#define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ +#define LONG_M 61 /* Memory long for ldb, stb */ +#define LONG_M2 62 /* Memory long for ld2w, st2w */ +#define LONG_2 63 /* LONG with 2 operands; jmptnz */ +#define LONG_2r 64 /* LONG with 2 operands; bratnz */ +#define LONG_2b 65 /* LONG_2 with modifier of 3 */ +#define LONG_2br 66 /* LONG_2r with modifier of 3 */ +#define LONG_D 67 /* for DJMPI */ +#define LONG_Dr 68 /* for DBRAI */ +#define LONG_Dbr 69 /* for repeati */ + + /* the execution unit(s) used */ + int unit; +#define EITHER 0 +#define IU 1 +#define MU 2 +#define EITHER_BUT_PREFER_MU 3 + + /* this field is used to decide if two instructions */ + /* can be executed in parallel */ + long flags_used; + long flags_set; +#define FLAG_0 (1L<<0) +#define FLAG_1 (1L<<1) +#define FLAG_2 (1L<<2) +#define FLAG_3 (1L<<3) +#define FLAG_4 (1L<<4) /* S (saturation) */ +#define FLAG_5 (1L<<5) /* V (overflow) */ +#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */ +#define FLAG_7 (1L<<7) /* C (carry/borrow) */ +#define FLAG_SM (1L<<8) /* SM (stack mode) */ +#define FLAG_RP (1L<<9) /* RP (repeat enable) */ +#define FLAG_CONTROL (1L<<10) /* control registers */ +#define FLAG_A0 (1L<<11) /* A0 */ +#define FLAG_A1 (1L<<12) /* A1 */ +#define FLAG_JMP (1L<<13) /* instruction is a branch */ +#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ +#define FLAG_MEM (1L<<15) /* reads/writes memory */ +#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation + New meaning: operation cannot be + combined in parallel with ADD/SUBppp. */ +#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ +#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ +#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ +#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */ +#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */ +#define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7) +#define FLAG_C FLAG_7 +#define FLAG_ALL (FLAG_0 | \ + FLAG_1 | \ + FLAG_2 | \ + FLAG_3 | \ + FLAG_4 | \ + FLAG_5 | \ + FLAG_6 | \ + FLAG_7 | \ + FLAG_SM | \ + FLAG_RP | \ + FLAG_CONTROL) + + int reloc_flag; +#define RELOC_PCREL 1 +#define RELOC_ABS 2 +}; + +extern const struct d30v_opcode d30v_opcode_table[]; +extern const int d30v_num_opcodes; + +/* The operands table is an array of struct d30v_operand. */ +struct d30v_operand +{ + /* the length of the field */ + int length; + + /* The number of significant bits in the operand. */ + int bits; + + /* position relative to Ra */ + int position; + + /* syntax flags. */ + long flags; +}; +extern const struct d30v_operand d30v_operand_table[]; + +/* Values defined for the flags field of a struct d30v_operand. */ + +/* this is the destination register; it will be modified */ +/* this is used by the optimizer */ +#define OPERAND_DEST (1) + +/* number or symbol */ +#define OPERAND_NUM (2) + +/* address or label */ +#define OPERAND_ADDR (4) + +/* register */ +#define OPERAND_REG (8) + +/* postincrement + */ +#define OPERAND_PLUS (0x10) + +/* postdecrement - */ +#define OPERAND_MINUS (0x20) + +/* signed number */ +#define OPERAND_SIGNED (0x40) + +/* this operand must be shifted left by 3 */ +#define OPERAND_SHIFT (0x80) + +/* flag register */ +#define OPERAND_FLAG (0x100) + +/* control register */ +#define OPERAND_CONTROL (0x200) + +/* accumulator */ +#define OPERAND_ACC (0x400) + +/* @ */ +#define OPERAND_ATSIGN (0x800) + +/* @( */ +#define OPERAND_ATPAR (0x1000) + +/* predecrement mode '@-sp' */ +#define OPERAND_ATMINUS (0x2000) + +/* this operand changes the instruction name */ +/* for example, CPMcc, CMPUcc */ +#define OPERAND_NAME (0x4000) + +/* fake operand for mvtsys and mvfsys */ +#define OPERAND_SPECIAL (0x8000) + +/* let the optimizer know that two registers are affected */ +#define OPERAND_2REG (0x10000) + +/* This operand is pc-relative. Note that repeati can have two immediate + operands, one of which is pcrel, the other (the IMM6U one) is not. */ +#define OPERAND_PCREL (0x20000) + +/* The format table is an array of struct d30v_format. */ +struct d30v_format +{ + int form; /* SHORT_A, LONG, etc */ + int modifier; /* two bit modifier following opcode */ + unsigned char operands[5]; +}; +extern const struct d30v_format d30v_format_table[]; + + +/* an instruction is defined by an opcode and a format */ +/* for example, "add" has one opcode, but three different */ +/* formats, 2 SHORT_A forms and a LONG form. */ +struct d30v_insn +{ + struct d30v_opcode *op; /* pointer to an entry in the opcode table */ + struct d30v_format *form; /* pointer to an entry in the format table */ + int ecc; /* execution condition code */ +}; + +/* an expressionS only has one register type, so we fake it */ +/* by setting high bits to indicate type */ +#define REGISTER_MASK 0xFF + +#endif /* D30V_H */ diff --git a/include/opcode/dlx.h b/include/opcode/dlx.h new file mode 100644 index 000000000000..e1b249f8523d --- /dev/null +++ b/include/opcode/dlx.h @@ -0,0 +1,282 @@ +/* Table of opcodes for the DLX microprocess. + Copyright 2002 Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + Initially created by Kuang Hwa Lin, 2002. */ + +/* Following are the function codes for the Special OP (ALU). */ +#define ALUOP 0x00000000 +#define SPECIALOP 0x00000000 + +#define NOPF 0x00000000 +#define SLLF 0x00000004 +#define SRLF 0x00000006 +#define SRAF 0x00000007 + +#define SEQUF 0x00000010 +#define SNEUF 0x00000011 +#define SLTUF 0x00000012 +#define SGTUF 0x00000013 +#define SLEUF 0x00000014 +#define SGEUF 0x00000015 + +#define ADDF 0x00000020 +#define ADDUF 0x00000021 +#define SUBF 0x00000022 +#define SUBUF 0x00000023 +#define ANDF 0x00000024 +#define ORF 0x00000025 +#define XORF 0x00000026 + +#define SEQF 0x00000028 +#define SNEF 0x00000029 +#define SLTF 0x0000002A +#define SGTF 0x0000002B +#define SLEF 0x0000002C +#define SGEF 0x0000002D + /* Following special functions was not mentioned in the + Hennessy's book but was implemented in the RTL. */ +#define MVTSF 0x00000030 +#define MVFSF 0x00000031 +#define BSWAPF 0x00000032 +#define LUTF 0x00000033 +/* Following special functions was mentioned in the + Hennessy's book but was not implemented in the RTL. */ +#define MULTF 0x00000005 +#define MULTUF 0x00000006 +#define DIVF 0x00000007 +#define DIVUF 0x00000008 + + +/* Following are the rest of the OPcodes: + JOP = (0x002 << 26), JALOP = (0x003 << 26), BEQOP = (0x004 << 26), BNEOP = (0x005 << 26) + ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP = (0x00A << 26), SUBUIOP= (0x00B << 26) + ANDIOP = (0x00C << 26), ORIOP = (0x00D << 26), XORIOP = (0x00E << 26), LHIOP = (0x00F << 26) + RFEOP = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26) + BREAKOP= (0x014 << 26) + SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26), SGTIOP = (0x01B << 26) + SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26) + LBOP = (0x020 << 26), LHOP = (0x021 << 26), LWOP = (0x023 << 26), LBUOP = (0x024 << 26) + LHUOP = (0x025 << 26), SBOP = (0x028 << 26), SHOP = (0x029 << 26), SWOP = (0x02B << 26) + LSBUOP = (0x026 << 26), LSHU = (0x027 << 26), LSW = (0x02C << 26), + SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26), SGTUIOP= (0x033 << 26) + SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26) + SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26). */ +#define JOP 0x08000000 +#define JALOP 0x0c000000 +#define BEQOP 0x10000000 +#define BNEOP 0x14000000 + +#define ADDIOP 0x20000000 +#define ADDUIOP 0x24000000 +#define SUBIOP 0x28000000 +#define SUBUIOP 0x2c000000 +#define ANDIOP 0x30000000 +#define ORIOP 0x34000000 +#define XORIOP 0x38000000 +#define LHIOP 0x3c000000 +#define RFEOP 0x40000000 +#define TRAPOP 0x44000000 +#define JROP 0x48000000 +#define JALROP 0x4c000000 +#define BREAKOP 0x50000000 + +#define SEQIOP 0x60000000 +#define SNEIOP 0x64000000 +#define SLTIOP 0x68000000 +#define SGTIOP 0x6c000000 +#define SLEIOP 0x70000000 +#define SGEIOP 0x74000000 + +#define LBOP 0x80000000 +#define LHOP 0x84000000 +#define LWOP 0x8c000000 +#define LBUOP 0x90000000 +#define LHUOP 0x94000000 +#define LDSTBU +#define LDSTHU +#define SBOP 0xa0000000 +#define SHOP 0xa4000000 +#define SWOP 0xac000000 +#define LDST + +#define SEQUIOP 0xc0000000 +#define SNEUIOP 0xc4000000 +#define SLTUIOP 0xc8000000 +#define SGTUIOP 0xcc000000 +#define SLEUIOP 0xd0000000 +#define SGEUIOP 0xd4000000 + +#define SLLIOP 0xd8000000 +#define SRLIOP 0xdc000000 +#define SRAIOP 0xe0000000 + +/* Following 3 ops was added to provide the MP atonmic operation. */ +#define LSBUOP 0x98000000 +#define LSHUOP 0x9c000000 +#define LSWOP 0xb0000000 + +/* Following opcode was defined in the Hennessy's book as + "normal" opcode but was implemented in the RTL as special + functions. */ +#if 0 +#define MVTSOP 0x50000000 +#define MVFSOP 0x54000000 +#endif + +struct dlx_opcode +{ + /* Name of the instruction. */ + char *name; + + /* Opcode word. */ + unsigned long opcode; + + /* A string of characters which describe the operands. + Valid characters are: + , Itself. The character appears in the assembly code. + a rs1 The register number is in bits 21-25 of the instruction. + b rs2/rd The register number is in bits 16-20 of the instruction. + c rd. The register number is in bits 11-15 of the instruction. + f FUNC bits 0-10 of the instruction. + i An immediate operand is in bits 0-16 of the instruction. 0 extended + I An immediate operand is in bits 0-16 of the instruction. sign extended + d An 16 bit PC relative displacement. + D An immediate operand is in bits 0-25 of the instruction. + N No opperands needed, for nops. + P it can be a register or a 16 bit operand. */ + char *args; +}; + +static const struct dlx_opcode dlx_opcodes[] = + { + /* Arithmetic and Logic R-TYPE instructions. */ + { "nop", (ALUOP|NOPF), "N" }, /* NOP */ + { "add", (ALUOP|ADDF), "c,a,b" }, /* Add */ + { "addu", (ALUOP|ADDUF), "c,a,b" }, /* Add Unsigned */ + { "sub", (ALUOP|SUBF), "c,a,b" }, /* SUB */ + { "subu", (ALUOP|SUBUF), "c,a,b" }, /* Sub Unsigned */ + { "mult", (ALUOP|MULTF), "c,a,b" }, /* MULTIPLY */ + { "multu", (ALUOP|MULTUF), "c,a,b" }, /* MULTIPLY Unsigned */ + { "div", (ALUOP|DIVF), "c,a,b" }, /* DIVIDE */ + { "divu", (ALUOP|DIVUF), "c,a,b" }, /* DIVIDE Unsigned */ + { "and", (ALUOP|ANDF), "c,a,b" }, /* AND */ + { "or", (ALUOP|ORF), "c,a,b" }, /* OR */ + { "xor", (ALUOP|XORF), "c,a,b" }, /* Exclusive OR */ + { "sll", (ALUOP|SLLF), "c,a,b" }, /* SHIFT LEFT LOGICAL */ + { "sra", (ALUOP|SRAF), "c,a,b" }, /* SHIFT RIGHT ARITHMETIC */ + { "srl", (ALUOP|SRLF), "c,a,b" }, /* SHIFT RIGHT LOGICAL */ + { "seq", (ALUOP|SEQF), "c,a,b" }, /* Set if equal */ + { "sne", (ALUOP|SNEF), "c,a,b" }, /* Set if not equal */ + { "slt", (ALUOP|SLTF), "c,a,b" }, /* Set if less */ + { "sgt", (ALUOP|SGTF), "c,a,b" }, /* Set if greater */ + { "sle", (ALUOP|SLEF), "c,a,b" }, /* Set if less or equal */ + { "sge", (ALUOP|SGEF), "c,a,b" }, /* Set if greater or equal */ + { "sequ", (ALUOP|SEQUF), "c,a,b" }, /* Set if equal unsigned */ + { "sneu", (ALUOP|SNEUF), "c,a,b" }, /* Set if not equal unsigned */ + { "sltu", (ALUOP|SLTUF), "c,a,b" }, /* Set if less unsigned */ + { "sgtu", (ALUOP|SGTUF), "c,a,b" }, /* Set if greater unsigned */ + { "sleu", (ALUOP|SLEUF), "c,a,b" }, /* Set if less or equal unsigned*/ + { "sgeu", (ALUOP|SGEUF), "c,a,b" }, /* Set if greater or equal */ + { "mvts", (ALUOP|MVTSF), "c,a" }, /* Move to special register */ + { "mvfs", (ALUOP|MVFSF), "c,a" }, /* Move from special register */ + { "bswap", (ALUOP|BSWAPF), "c,a,b" }, /* ??? Was not documented */ + { "lut", (ALUOP|LUTF), "c,a,b" }, /* ????? same as above */ + + /* Arithmetic and Logical Immediate I-TYPE instructions. */ + { "addi", ADDIOP, "b,a,I" }, /* Add Immediate */ + { "addui", ADDUIOP, "b,a,i" }, /* Add Usigned Immediate */ + { "subi", SUBIOP, "b,a,I" }, /* Sub Immediate */ + { "subui", SUBUIOP, "b,a,i" }, /* Sub Unsigned Immedated */ + { "andi", ANDIOP, "b,a,i" }, /* AND Immediate */ + { "ori", ORIOP, "b,a,i" }, /* OR Immediate */ + { "xori", XORIOP, "b,a,i" }, /* Exclusive OR Immediate */ + { "slli", SLLIOP, "b,a,i" }, /* SHIFT LEFT LOCICAL Immediate */ + { "srai", SRAIOP, "b,a,i" }, /* SHIFT RIGHT ARITH. Immediate */ + { "srli", SRLIOP, "b,a,i" }, /* SHIFT RIGHT LOGICAL Immediate*/ + { "seqi", SEQIOP, "b,a,i" }, /* Set if equal */ + { "snei", SNEIOP, "b,a,i" }, /* Set if not equal */ + { "slti", SLTIOP, "b,a,i" }, /* Set if less */ + { "sgti", SGTIOP, "b,a,i" }, /* Set if greater */ + { "slei", SLEIOP, "b,a,i" }, /* Set if less or equal */ + { "sgei", SGEIOP, "b,a,i" }, /* Set if greater or equal */ + { "sequi", SEQUIOP, "b,a,i" }, /* Set if equal */ + { "sneui", SNEUIOP, "b,a,i" }, /* Set if not equal */ + { "sltui", SLTUIOP, "b,a,i" }, /* Set if less */ + { "sgtui", SGTUIOP, "b,a,i" }, /* Set if greater */ + { "sleui", SLEUIOP, "b,a,i" }, /* Set if less or equal */ + { "sgeui", SGEUIOP, "b,a,i" }, /* Set if greater or equal */ + /* Macros for I type instructions. */ + { "mov", ADDIOP, "b,P" }, /* a move macro */ + { "movu", ADDUIOP, "b,P" }, /* a move macro, unsigned */ + +#if 0 + /* Move special. */ + { "mvts", MVTSOP, "b,a" }, /* Move From Integer to Special */ + { "mvfs", MVFSOP, "b,a" }, /* Move From Special to Integer */ +#endif + + /* Load high Immediate I-TYPE instruction. */ + { "lhi", LHIOP, "b,i" }, /* Load High Immediate */ + { "lui", LHIOP, "b,i" }, /* Load High Immediate */ + { "sethi", LHIOP, "b,i" }, /* Load High Immediate */ + + /* LOAD/STORE BYTE 8 bits I-TYPE. */ + { "lb", LBOP, "b,a,I" }, /* Load Byte */ + { "lbu", LBUOP, "b,a,I" }, /* Load Byte Unsigned */ + { "ldstbu", LSBUOP, "b,a,I" }, /* Load store Byte Unsigned */ + { "sb", SBOP, "b,a,I" }, /* Store Byte */ + + /* LOAD/STORE HALFWORD 16 bits. */ + { "lh", LHOP, "b,a,I" }, /* Load Halfword */ + { "lhu", LHUOP, "b,a,I" }, /* Load Halfword Unsigned */ + { "ldsthu", LSHUOP, "b,a,I" }, /* Load Store Halfword Unsigned */ + { "sh", SHOP, "b,a,I" }, /* Store Halfword */ + + /* LOAD/STORE WORD 32 bits. */ + { "lw", LWOP, "b,a,I" }, /* Load Word */ + { "sw", SWOP, "b,a,I" }, /* Store Word */ + { "ldstw", LSWOP, "b,a,I" }, /* Load Store Word */ + + /* Branch PC-relative, 16 bits offset. */ + { "beqz", BEQOP, "a,d" }, /* Branch if a == 0 */ + { "bnez", BNEOP, "a,d" }, /* Branch if a != 0 */ + { "beq", BEQOP, "a,d" }, /* Branch if a == 0 */ + { "bne", BNEOP, "a,d" }, /* Branch if a != 0 */ + + /* Jumps Trap and RFE J-TYPE. */ + { "j", JOP, "D" }, /* Jump, PC-relative 26 bits */ + { "jal", JALOP, "D" }, /* JAL, PC-relative 26 bits */ + { "break", BREAKOP, "D" }, /* break to OS */ + { "trap" , TRAPOP, "D" }, /* TRAP to OS */ + { "rfe", RFEOP, "N" }, /* Return From Exception */ + /* Macros. */ + { "call", JOP, "D" }, /* Jump, PC-relative 26 bits */ + + /* Jumps Trap and RFE I-TYPE. */ + { "jr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ + { "jalr", JALROP, "a" }, /* JALR, Abs (32 bits) */ + /* Macros. */ + { "retr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ + + { "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. + This lets code examine entry i + 1 without + checking if we've run off the end of the table. */ + }; + +const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1); diff --git a/include/opcode/h8300.h b/include/opcode/h8300.h new file mode 100644 index 000000000000..29374df5b4fe --- /dev/null +++ b/include/opcode/h8300.h @@ -0,0 +1,1892 @@ +/* Opcode table for the H8/300 + Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002, 2003, 2004 + Free Software Foundation, Inc. + Written by Steve Chamberlain <sac@cygnus.com>. + + This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* Instructions are stored as a sequence of nibbles. + If the nibble has value 15 or less than the representation is complete. + Otherwise, we record what it contains with several flags. */ + +typedef int op_type; + +enum h8_flags +{ + L_2 = 0x10, + L_3 = 0x20, + /* 3 bit constant, zero not accepted. */ + L_3NZ = 0x30, + L_4 = 0x40, + L_5 = 0x50, + L_8 = 0x60, + L_8U = 0x70, + L_16 = 0x80, + L_16U = 0x90, + L_24 = 0xA0, + L_32 = 0xB0, + L_P = 0xC0, + + /* Mask to isolate the L_x size bits. */ + SIZE = 0xF0, + + REG = 0x0100, + ABS = 0x0200, + MEMIND = 0x0300, + IMM = 0x0400, + DISP = 0x0500, + IND = 0x0600, + POSTINC = 0x0700, + POSTDEC = 0x0800, + PREINC = 0x0900, + PREDEC = 0x0A00, + PCREL = 0x0B00, + KBIT = 0x0C00, + DBIT = 0x0D00, + CONST_2 = 0x0E00, + CONST_4 = 0x0F00, + CONST_8 = 0x1000, + CONST_16 = 0x1100, + INDEXB = 0x1200, + INDEXW = 0x1300, + INDEXL = 0x1400, + PCIDXB = 0x1500, + PCIDXW = 0x1600, + PCIDXL = 0x1700, + VECIND = 0x1800, + LOWREG = 0x1900, + DATA = 0x2000, + + /* Synonyms. */ + INC = POSTINC, + DEC = PREDEC, + /* Control Registers. */ + CCR = 0x4000, + EXR = 0x4100, + MACH = 0x4200, + MACL = 0x4300, + RESERV1 = 0x4400, + RESERV2 = 0x4500, + VBR = 0x4600, + SBR = 0x4700, + MACREG = 0x4800, + CCR_EXR = 0x4900, + VBR_SBR = 0x4A00, + CC_EX_VB_SB = 0x4B00, + RESERV3 = 0x4C00, + RESERV4 = 0x4D00, + RESERV5 = 0x4E00, + RESERV6 = 0x4F00, + + /* Mask to isolate the addressing mode bits (REG .. PREDEC). */ + MODE = 0x7F00, + + CTRL = 0x4000, + + NO_SYMBOLS = 0x8000, + SRC = 0x10000, + DST = 0x20000, + OP3 = 0x40000, + MEMRELAX = 0x80000, /* Move insn which may relax. */ + + DISPREG = 0x100000, + IGNORE = 0x200000, + ABSJMP = 0x400000, + + B00 = 0x800000, /* Bit 0 must be low. */ + B01 = 0x1000000, /* Bit 0 must be high. */ + B10 = 0x2000000, /* Bit 1 must be low. */ + B11 = 0x4000000, /* Bit 1 must be high. */ + B20 = 0x8000000, /* Bit 2 must be low. */ + B21 = 0x10000000, /* Bit 2 must be high. */ + B30 = 0x20000000, /* Bit 3 must be low. */ + B31 = 0x40000000, /* Bit 3 must be high. */ + E = 0x80000000, /* End of nibble sequence. */ + + /* Immediates smaller than 8 bits are always unsigned. */ + IMM3 = IMM | L_3, + IMM4 = IMM | L_4, + IMM5 = IMM | L_5, + IMM3NZ = IMM | L_3NZ, + IMM2 = IMM | L_2, + + IMM8 = IMM | SRC | L_8, + IMM8U = IMM | SRC | L_8U, + IMM16 = IMM | SRC | L_16, + IMM16U = IMM | SRC | L_16U, + IMM32 = IMM | SRC | L_32, + + IMM3NZ_NS = IMM3NZ | NO_SYMBOLS, + IMM4_NS = IMM4 | NO_SYMBOLS, + IMM8U_NS = IMM8U | NO_SYMBOLS, + IMM16U_NS = IMM16U | NO_SYMBOLS, + + RD8 = DST | L_8 | REG, + RD16 = DST | L_16 | REG, + RD32 = DST | L_32 | REG, + R3_8 = OP3 | L_8 | REG, + R3_16 = OP3 | L_16 | REG, + R3_32 = OP3 | L_32 | REG, + RS8 = SRC | L_8 | REG, + RS16 = SRC | L_16 | REG, + RS32 = SRC | L_32 | REG, + + RSP = SRC | L_P | REG, + RDP = DST | L_P | REG, + + PCREL8 = PCREL | L_8, + PCREL16 = PCREL | L_16, + + OP3PCREL8 = OP3 | PCREL | L_8, + OP3PCREL16 = OP3 | PCREL | L_16, + + INDEXB16 = INDEXB | L_16, + INDEXW16 = INDEXW | L_16, + INDEXL16 = INDEXL | L_16, + INDEXB16D = INDEXB | L_16 | DST, + INDEXW16D = INDEXW | L_16 | DST, + INDEXL16D = INDEXL | L_16 | DST, + + INDEXB32 = INDEXB | L_32, + INDEXW32 = INDEXW | L_32, + INDEXL32 = INDEXL | L_32, + INDEXB32D = INDEXB | L_32 | DST, + INDEXW32D = INDEXW | L_32 | DST, + INDEXL32D = INDEXL | L_32 | DST, + + DISP2SRC = DISP | L_2 | SRC, + DISP16SRC = DISP | L_16 | SRC, + DISP32SRC = DISP | L_32 | SRC, + + DISP2DST = DISP | L_2 | DST, + DISP16DST = DISP | L_16 | DST, + DISP32DST = DISP | L_32 | DST, + + DSTDISPREG = DST | DISPREG, + SRCDISPREG = SRC | DISPREG, + + ABS8SRC = SRC | ABS | L_8, + ABS16SRC = SRC | ABS | L_16U, + ABS24SRC = SRC | ABS | L_24, + ABS32SRC = SRC | ABS | L_32, + + ABS8DST = DST | ABS | L_8, + ABS16DST = DST | ABS | L_16U, + ABS24DST = DST | ABS | L_24, + ABS32DST = DST | ABS | L_32, + + ABS8OP3 = OP3 | ABS | L_8, + ABS16OP3 = OP3 | ABS | L_16U, + ABS24OP3 = OP3 | ABS | L_24, + ABS32OP3 = OP3 | ABS | L_32, + + RDDEC = DST | DEC, + RSINC = SRC | INC, + RDINC = DST | INC, + + RSPOSTINC = SRC | POSTINC, + RDPOSTINC = DST | POSTINC, + RSPREINC = SRC | PREINC, + RDPREINC = DST | PREINC, + RSPOSTDEC = SRC | POSTDEC, + RDPOSTDEC = DST | POSTDEC, + RSPREDEC = SRC | PREDEC, + RDPREDEC = DST | PREDEC, + + RSIND = SRC | IND, + RDIND = DST | IND, + R3_IND = OP3 | IND, + +#define MS32 (SRC | L_32 | MACREG) +#define MD32 (DST | L_32 | MACREG) + +#if 1 + OR8 = RS8, /* ??? OR as in One Register. */ + OR16 = RS16, + OR32 = RS32, +#else + OR8 = RD8, + OR16 = RD16, + OR32 = RD32 +#endif +}; + +enum ctrlreg +{ + C_CCR = 0, + C_EXR = 1, + C_MACH = 2, + C_MACL = 3, + C_VBR = 6, + C_SBR = 7 +}; + +enum {MAX_CODE_NIBBLES = 33}; + +struct code +{ + op_type nib[MAX_CODE_NIBBLES]; +}; + +struct arg +{ + op_type nib[3]; +}; + +/* Availability of instructions on processor models. */ +enum h8_model +{ + AV_H8, + AV_H8H, + AV_H8S, + AV_H8SX +}; + +struct h8_opcode +{ + int how; + enum h8_model available; + int time; + char *name; + struct arg args; + struct code data; +}; + +#ifdef DEFINE_TABLE + +#define DATA2 DATA, DATA +#define DATA3 DATA, DATA, DATA +#define DATA5 DATA, DATA, DATA, DATA, DATA +#define DATA7 DATA, DATA, DATA, DATA, DATA, DATA, DATA + +#define IMM8LIST IMM8, DATA +#define IMM16LIST IMM16, DATA3 +#define IMM16ULIST IMM16U, DATA3 +#define IMM24LIST IMM24, DATA5 +#define IMM32LIST IMM32, DATA7 + +#define DISP16LIST DISP | L_16, DATA3 +#define DISP24LIST DISP | L_24, DATA5 +#define DISP32LIST DISP | L_32, DATA7 + +#define ABS8LIST ABS | L_8, DATA +#define ABS16LIST ABS | L_16U, DATA3 +#define ABS24LIST ABS | L_24, DATA5 +#define ABS32LIST ABS | L_32, DATA7 + +#define DSTABS8LIST DST | ABS | L_8, DATA +#define DSTABS16LIST DST | ABS | L_16U, DATA3 +#define DSTABS24LIST DST | ABS | L_24, DATA5 +#define DSTABS32LIST DST | ABS | L_32, DATA7 + +#define OP3ABS8LIST OP3 | ABS | L_8, DATA +#define OP3ABS16LIST OP3 | ABS | L_16, DATA3 +#define OP3ABS24LIST OP3 | ABS | L_24, DATA5 +#define OP3ABS32LIST OP3 | ABS | L_32, DATA7 + +#define DSTDISP16LIST DST | DISP | L_16, DATA3 +#define DSTDISP24LIST DST | DISP | L_24, DATA5 +#define DSTDISP32LIST DST | DISP | L_32, DATA7 + +#define A16LIST L_16, DATA3 +#define A24LIST L_24, DATA5 +#define A32LIST L_32, DATA7 + +/* Extended Operand Prefixes: */ + +#define PREFIX_010 0x0, 0x1, 0x0 +#define PREFIX_015 0x0, 0x1, 0x5 +#define PREFIX_017 0x0, 0x1, 0x7 + +#define PREFIX_0100 0x0, 0x1, 0x0, 0x0 +#define PREFIX_010_D2 0x0, 0x1, 0x0, B30 | B21 | DISP2SRC +#define PREFIX_0101 0x0, 0x1, 0x0, 0x1 +#define PREFIX_0102 0x0, 0x1, 0x0, 0x2 +#define PREFIX_0103 0x0, 0x1, 0x0, 0x3 +#define PREFIX_0104 0x0, 0x1, 0x0, 0x4 +#define PREFIX_0105 0x0, 0x1, 0x0, 0x5 +#define PREFIX_0106 0x0, 0x1, 0x0, 0x6 +#define PREFIX_0107 0x0, 0x1, 0x0, 0x7 +#define PREFIX_0108 0x0, 0x1, 0x0, 0x8 +#define PREFIX_0109 0x0, 0x1, 0x0, 0x9 +#define PREFIX_010A 0x0, 0x1, 0x0, 0xa +#define PREFIX_010D 0x0, 0x1, 0x0, 0xd +#define PREFIX_010E 0x0, 0x1, 0x0, 0xe + +#define PREFIX_0150 0x0, 0x1, 0x5, 0x0 +#define PREFIX_015_D2 0x0, 0x1, 0x5, B30 | B21 | DISP2SRC +#define PREFIX_0151 0x0, 0x1, 0x5, 0x1 +#define PREFIX_0152 0x0, 0x1, 0x5, 0x2 +#define PREFIX_0153 0x0, 0x1, 0x5, 0x3 +#define PREFIX_0154 0x0, 0x1, 0x5, 0x4 +#define PREFIX_0155 0x0, 0x1, 0x5, 0x5 +#define PREFIX_0156 0x0, 0x1, 0x5, 0x6 +#define PREFIX_0157 0x0, 0x1, 0x5, 0x7 +#define PREFIX_0158 0x0, 0x1, 0x5, 0x8 +#define PREFIX_0159 0x0, 0x1, 0x5, 0x9 +#define PREFIX_015A 0x0, 0x1, 0x5, 0xa +#define PREFIX_015D 0x0, 0x1, 0x5, 0xd +#define PREFIX_015E 0x0, 0x1, 0x5, 0xe +#define PREFIX_015F 0x0, 0x1, 0x5, 0xf + +#define PREFIX_0170 0x0, 0x1, 0x7, 0x0 +#define PREFIX_017_D2S 0x0, 0x1, 0x7, B30 | B21 | DISP2SRC +#define PREFIX_017_D2D 0x0, 0x1, 0x7, B30 | B21 | DISP2DST +#define PREFIX_0171 0x0, 0x1, 0x7, 0x1 +#define PREFIX_0172 0x0, 0x1, 0x7, 0x2 +#define PREFIX_0173 0x0, 0x1, 0x7, 0x3 +#define PREFIX_0174 0x0, 0x1, 0x7, 0x4 +#define PREFIX_0175 0x0, 0x1, 0x7, 0x5 +#define PREFIX_0176 0x0, 0x1, 0x7, 0x6 +#define PREFIX_0177 0x0, 0x1, 0x7, 0x7 +#define PREFIX_0178 0x0, 0x1, 0x7, 0x8 +#define PREFIX_0179 0x0, 0x1, 0x7, 0x9 +#define PREFIX_017A 0x0, 0x1, 0x7, 0xa +#define PREFIX_017D 0x0, 0x1, 0x7, 0xd +#define PREFIX_017E 0x0, 0x1, 0x7, 0xe +#define PREFIX_017F 0x0, 0x1, 0x7, 0xf + +#define PREFIX_6A15 0x6, 0xa, 0x1, 0x5 +#define PREFIX_6A35 0x6, 0xa, 0x3, 0x5 +#define PREFIX_6B15 0x6, 0xb, 0x1, 0x5 +#define PREFIX_6B35 0x6, 0xb, 0x3, 0x5 + +#define PREFIX_78R4 0x7, 0x8, B31 | DISPREG, 0x4 +#define PREFIX_78R5 0x7, 0x8, B31 | DISPREG, 0x5 +#define PREFIX_78R6 0x7, 0x8, B31 | DISPREG, 0x6 +#define PREFIX_78R7 0x7, 0x8, B31 | DISPREG, 0x7 + +#define PREFIX_78R4W 0x7, 0x8, B30 | DISPREG, 0x4 +#define PREFIX_78R5W 0x7, 0x8, B30 | DISPREG, 0x5 +#define PREFIX_78R6W 0x7, 0x8, B30 | DISPREG, 0x6 +#define PREFIX_78R7W 0x7, 0x8, B30 | DISPREG, 0x7 + +#define PREFIX_78R4WD 0x7, 0x8, B30 | DSTDISPREG, 0x4 +#define PREFIX_78R5WD 0x7, 0x8, B30 | DSTDISPREG, 0x5 +#define PREFIX_78R6WD 0x7, 0x8, B30 | DSTDISPREG, 0x6 +#define PREFIX_78R7WD 0x7, 0x8, B30 | DSTDISPREG, 0x7 + +#define PREFIX_7974 0x7, 0x9, 0x7, 0x4 +#define PREFIX_7A74 0x7, 0xa, 0x7, 0x4 +#define PREFIX_7A7C 0x7, 0xa, 0x7, 0xc + + +/* Source standard fragment: */ +#define FROM_IND 0, RSIND +#define FROM_POSTINC 8, RSPOSTINC +#define FROM_POSTDEC 10, RSPOSTDEC +#define FROM_PREINC 9, RSPREINC +#define FROM_PREDEC 11, RSPREDEC +#define FROM_DISP2 B30 | B20 | DISP2SRC, DISPREG +#define FROM_DISP16 12, B30 | DISPREG +#define FROM_DISP32 12, B31 | DISPREG +#define FROM_DISP16B 13, B30 | DISPREG +#define FROM_DISP16W 14, B30 | DISPREG +#define FROM_DISP16L 15, B30 | DISPREG +#define FROM_DISP32B 13, B31 | DISPREG +#define FROM_DISP32W 14, B31 | DISPREG +#define FROM_DISP32L 15, B31 | DISPREG +#define FROM_ABS16 4, B30 | IGNORE +#define FROM_ABS32 4, B31 | IGNORE + +/* Destination standard fragment: */ +#define TO_IND 0, RDIND +#define TO_IND_MOV 0, RDIND | B30 +#define TO_POSTINC 8, RDPOSTINC +#define TO_POSTINC_MOV 8, RDPOSTINC | B30 +#define TO_POSTDEC 10, RDPOSTDEC +#define TO_POSTDEC_MOV 10, RDPOSTDEC | B30 +#define TO_PREINC 9, RDPREINC +#define TO_PREINC_MOV 9, RDPREINC | B30 +#define TO_PREDEC 11, RDPREDEC +#define TO_PREDEC_MOV 11, RDPREDEC | B30 +#define TO_DISP2 B30 | B20 | DISP2DST, DSTDISPREG +#define TO_DISP2_MOV B30 | B20 | DISP2DST, DSTDISPREG | B30 +#define TO_DISP16 12, B30 | DSTDISPREG +#define TO_DISP32 12, B31 | DSTDISPREG +#define TO_DISP16B 13, B30 | DSTDISPREG +#define TO_DISP16W 14, B30 | DSTDISPREG +#define TO_DISP16L 15, B30 | DSTDISPREG +#define TO_DISP32B 13, B31 | DSTDISPREG +#define TO_DISP32W 14, B31 | DSTDISPREG +#define TO_DISP32L 15, B31 | DSTDISPREG +#define TO_ABS16 4, B30 | IGNORE +#define TO_ABS32 4, B31 | IGNORE + +/* Source fragment for three-word instruction: */ +#define TFROM_IND 6, 9, B30 | RSIND, 12 +#define TFROM_DISP2 6, 9, B30 | DISPREG, 12 +#define TFROM_ABS16 6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST +#define TFROM_ABS32 6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST +#define TFROM_POSTINC 6, 13, B30 | RSPOSTINC, 12 +#define TFROM_PREINC 6, 13, B30 | RSPREINC, 12 +#define TFROM_POSTDEC 6, 13, B30 | RSPOSTDEC, 12 +#define TFROM_PREDEC 6, 13, B30 | RSPREDEC, 12 +#define TFROM_DISP16 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32 6, 11, 2, 12, DISP32LIST +#define TFROM_DISP16B 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16W 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16L 6, 15, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32B 6, 11, 2, 12, DISP32LIST +#define TFROM_DISP32W 6, 11, 2, 12, DISP32LIST +#define TFROM_DISP32L 6, 11, 2, 12, DISP32LIST +#define TFROM_ABS16W 6, 11, 1, 12, ABS16LIST +#define TFROM_ABS32W 6, 11, 3, 12, ABS32LIST + +/* Source fragment for three-word instruction: */ +#define TFROM_IND_B 6, 8, B30 | RSIND, 12 +#define TFROM_ABS16_B 6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST +#define TFROM_ABS32_B 6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST + +#define TFROM_DISP2_B 6, 8, B30 | DISPREG, 12 +#define TFROM_POSTINC_B 6, 12, B30 | RSPOSTINC, 12 +#define TFROM_PREINC_B 6, 12, B30 | RSPREINC, 12 +#define TFROM_POSTDEC_B 6, 12, B30 | RSPOSTDEC, 12 +#define TFROM_PREDEC_B 6, 12, B30 | RSPREDEC, 12 +#define TFROM_DISP16_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32_B 6, 10, 2, 12, DISP32LIST +#define TFROM_DISP16B_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16W_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP16L_B 6, 14, B30 | DISPREG, 12, DISP16LIST +#define TFROM_DISP32B_B 6, 10, 2, 12, DISP32LIST +#define TFROM_DISP32W_B 6, 10, 2, 12, DISP32LIST +#define TFROM_DISP32L_B 6, 10, 2, 12, DISP32LIST + +#define TFROM_ABS16W_B 6, 10, 1, 12, ABS16LIST +#define TFROM_ABS32W_B 6, 10, 3, 12, ABS32LIST + +/* Extended Operand Class Expanders: */ + +#define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, DSTABS32LIST, E}}} + +#define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, SRC_INFIX, TO_IND_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, SRC_INFIX, TO_PREINC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, SRC_INFIX, TO_PREDEC_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP2_MOV, SRC_SUFFIX, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP16, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, SRC_INFIX, TO_DISP32, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16B, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16W, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, SRC_INFIX, TO_DISP16L, SRC_SUFFIX, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32B, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32W, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, SRC_INFIX, TO_DISP32L, SRC_SUFFIX, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS16, SRC_SUFFIX, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, SRC_INFIX, TO_ABS32, SRC_SUFFIX, DSTABS32LIST, E}}} + +#define MOVFROM_IMM8(CODE, PREFIX, NAME, SRC) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, 0, RDIND, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 8, RDPOSTINC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 10, RDPOSTDEC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 9, RDPREINC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, 11, RDPREDEC, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, DSTDISPREG, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, 12, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, 12, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 13, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 14, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 15, B30 | DSTDISPREG, IMM8LIST, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, 13, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, 14, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, 15, B31 | DSTDISPREG, IMM8LIST, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, 4, B30 | IGNORE, IMM8LIST, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, 4, B31 | IGNORE, IMM8LIST, DSTABS32LIST, E}}} + +#define MOVFROM_IMM(CODE, PREFIX, NAME, SRC, LIST) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, LIST, 0, RDIND, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, LIST, 8, RDPOSTINC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, LIST, 10, RDPOSTDEC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, LIST, 9, RDPREINC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, LIST, 11, RDPREDEC, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, LIST, B30 | B20 | DISP2DST, DSTDISPREG, DATA2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, LIST, 12, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, LIST, 12, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, LIST, 13, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, LIST, 14, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, LIST, 15, B30 | DSTDISPREG, DATA2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, LIST, 13, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, LIST, 14, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, LIST, 15, B31 | DSTDISPREG, DATA2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, LIST, 4, B30 | IGNORE, DATA2, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, LIST, 4, B31 | IGNORE, DATA2, DSTABS32LIST, E}}} + +#define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ + {CODE, AV_H8, 4, NAME, {{SRC, RDIND, E}}, {{ 6, OP1, B31 | RDIND, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, 3, 6, OP3, B31 | RDPOSTINC, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, 1, 6, OP3, B31 | RDPOSTDEC, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, 2, 6, OP3, B31 | RDPREINC, SRC, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, RDPREDEC, E}}, {{ 6, OP3, B31 | RDPREDEC, SRC, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, DISP16DST, E}}, {{ 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 0, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, 1, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, 2, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, 3, 6, OP4, B31 | DSTDISPREG, SRC, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 1, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 2, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 3, 6, OP2, 10, SRC, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8, 4, NAME, {{SRC, ABS16DST, E}}, {{ 6, OP2, 8, SRC, RELAX16 | DSTABS16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{SRC, ABS32DST, E}}, {{ 6, OP2, 10, SRC, MEMRELAX | DSTABS32LIST, E}}} + +#define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \ + {CODE, AV_H8, 4, NAME, {{RSIND, DST, E}}, {{ 6, OP1, B30 | RSIND, DST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{RSPOSTINC, DST, E}}, {{ 6, OP3, B30 | RSPOSTINC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, 2, 6, OP3, B30 | RSPOSTDEC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, 1, 6, OP3, B30 | RSPREINC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, 3, 6, OP3, B30 | RSPREDEC, DST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG, DST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{DISP16SRC, DST, E}}, {{ 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{DISP32SRC, DST, E}}, {{7, 8, B30 | DISPREG, 0, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, 1, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, 2, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, 3, 6, OP4, B30 | DISPREG, DST, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{7, 8, B30 | DISPREG, 1, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{7, 8, B30 | DISPREG, 2, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{7, 8, B30 | DISPREG, 3, 6, OP2, 2, DST, DISP32LIST, E}}}, \ + {CODE, AV_H8, 4, NAME, {{ABS16SRC, DST, E}}, {{ 6, OP2, 0, DST, RELAX16 | ABS16LIST, E}}}, \ + {CODE, AV_H8, 6, NAME, {{ABS32SRC, DST, E}}, {{ 6, OP2, 2, DST, MEMRELAX | ABS32LIST, E}}} + +/* Expansion macros for two-word (plus data) instructions. */ + +/* Expansion from one source to "standard" destinations. */ +#define EXPAND2_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, NIB1, NIB2) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} + +/* Expansion from one destination to "standard" sources. */ +#define EXPAND2_STD_DST(CODE, WEIGHT, NAME, DST, PREFIX, NIB1, NIB2) \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, DST, E}}, {{PREFIX, FROM_POSTINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, DST, E}}, {{PREFIX, FROM_POSTDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, DST, E}}, {{PREFIX, FROM_PREINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, DST, E}}, {{PREFIX, FROM_PREDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, FROM_DISP2, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, DST, E}}, {{PREFIX, FROM_DISP16, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, DST, E}}, {{PREFIX, FROM_DISP32, NIB1, NIB2, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, DST, E}}, {{PREFIX, FROM_DISP16B, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, DST, E}}, {{PREFIX, FROM_DISP16W, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, DST, E}}, {{PREFIX, FROM_DISP16L, NIB1, NIB2, DISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, DST, E}}, {{PREFIX, FROM_DISP32B, NIB1, NIB2, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, DST, E}}, {{PREFIX, FROM_DISP32W, NIB1, NIB2, DISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, DST, E}}, {{PREFIX, FROM_DISP32L, NIB1, NIB2, DISP32LIST, E}}} + +/* Expansion from immediate source to "standard" destinations. */ +#define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, TO_DISP16W, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, TO_DISP16L, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, TO_DISP32B, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, TO_DISP32W, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, TO_DISP32L, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}} + +/* Expansion from abs/disp source to "standard" destinations. */ +#define EXPAND2_STD_ABSDISP(CODE, WEIGHT, NAME, SRC, PREFIX, DSTLIST, NIB1, NIB2) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, DSTLIST, TO_POSTINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, DSTLIST, TO_POSTDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, DSTLIST, TO_PREINC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, DSTLIST, TO_PREDEC, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, DSTLIST, TO_DISP2, NIB1, NIB2, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, DSTLIST, TO_DISP16, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, DSTLIST, TO_DISP32, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, DSTLIST, TO_DISP16B, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, DSTLIST, TO_DISP16W, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, DSTLIST, TO_DISP16L, NIB1, NIB2, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, DSTLIST, TO_DISP32B, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, DSTLIST, TO_DISP32W, NIB1, NIB2, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, DSTLIST, TO_DISP32L, NIB1, NIB2, DSTDISP32LIST, E}}} + +/* Expansion from ind source to "standard" destinations. */ +#define EXPAND2_STD_IND(CODE, WEIGHT, NAME, OPCODE, BIT) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTINC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPOSTDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_POSTDEC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREINC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREINC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDPREDEC, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_PREDEC, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP2DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP2, OPCODE, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP16DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, DISP32DST, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16B, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16W, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL16D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP16L, OPCODE, IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXB32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32B, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXW32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32W, OPCODE, IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, INDEXL32D, E}}, {{0x7, 0xc, BIT | RSIND, 0x5, TO_DISP32L, OPCODE, IGNORE, DSTDISP32LIST, E}}} + +/* Expansion macros for three word (plus data) instructions. */ + +#define EXPAND3_STD_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}} + +#define EXPAND3_L_SRC(CODE, WEIGHT, NAME, SRC, PREFIX, INFIX, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND, E}}, {{PREFIX, INFIX, 0, RDIND, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, INFIX, 8, RDPOSTINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, INFIX, 10, RDPOSTDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, INFIX, 9, RDPREINC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, INFIX, 11, RDPREDEC, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, INFIX, B30 | B20 | DISP2DST, DSTDISPREG, OPCODE, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, INFIX, 12, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, INFIX, 12, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, INFIX, 13, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}}, {{PREFIX, INFIX, 14, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}}, {{PREFIX, INFIX, 15, B30 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}}, {{PREFIX, INFIX, 13, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}}, {{PREFIX, INFIX, 14, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}}, {{PREFIX, INFIX, 15, B31 | DSTDISPREG, OPCODE, B30 | IGNORE, DSTDISP32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST, E}}, {{PREFIX, INFIX, 4, B30 | IGNORE, OPCODE, B30 | IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST, E}}, {{PREFIX, INFIX, 4, B31 | IGNORE, OPCODE, B30 | IGNORE, DSTABS32LIST, E}}} + + +#define EXPAND_STD_MATRIX_L(CODE, NAME, OPCODE) \ + EXPAND3_L_SRC (CODE, 6, NAME, RSIND, PREFIX_0104, TFROM_IND, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTINC, PREFIX_0104, TFROM_POSTINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPOSTDEC, PREFIX_0106, TFROM_POSTDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPREINC, PREFIX_0105, TFROM_PREINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, RSPREDEC, PREFIX_0107, TFROM_PREDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, DISP2SRC, PREFIX_010_D2, TFROM_DISP2, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, DISP16SRC, PREFIX_0104, TFROM_DISP16, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, DISP32SRC, PREFIX_78R4, TFROM_DISP32, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXB16, PREFIX_0105, TFROM_DISP16B, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXW16, PREFIX_0106, TFROM_DISP16W, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXL16, PREFIX_0107, TFROM_DISP16L, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXB32, PREFIX_78R5, TFROM_DISP32B, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXW32, PREFIX_78R6, TFROM_DISP32W, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, INDEXL32, PREFIX_78R7, TFROM_DISP32L, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, ABS16SRC, PREFIX_0104, TFROM_ABS16, OPCODE), \ + EXPAND3_L_SRC (CODE, 6, NAME, ABS32SRC, PREFIX_0104, TFROM_ABS32, OPCODE) + + +#define EXPAND_STD_MATRIX_W(CODE, NAME, OPCODE) \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0154, TFROM_POSTINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0156, TFROM_POSTDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0155, TFROM_PREINC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0157, TFROM_PREDEC, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_015_D2, TFROM_DISP2, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0154, TFROM_DISP16, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0155, TFROM_DISP16B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0156, TFROM_DISP16W, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0157, TFROM_DISP16L, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L, OPCODE) + +#define EXPAND_STD_MATRIX_B(CODE, NAME, OPCODE) \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTINC, PREFIX_0174, TFROM_POSTINC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPOSTDEC, PREFIX_0176, TFROM_POSTDEC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREINC, PREFIX_0175, TFROM_PREINC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, RSPREDEC, PREFIX_0177, TFROM_PREDEC_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP2SRC, PREFIX_017_D2S, TFROM_DISP2_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP16SRC, PREFIX_0174, TFROM_DISP16_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, DISP32SRC, PREFIX_78R4W, TFROM_DISP32_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB16, PREFIX_0175, TFROM_DISP16B_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW16, PREFIX_0176, TFROM_DISP16W_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL16, PREFIX_0177, TFROM_DISP16L_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXB32, PREFIX_78R5W, TFROM_DISP32B_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXW32, PREFIX_78R6W, TFROM_DISP32W_B, OPCODE), \ + EXPAND3_L_SRC (CODE, 4, NAME, INDEXL32, PREFIX_78R7W, TFROM_DISP32L_B, OPCODE) + + +/* Use the expansion macros to fill out the opcode table. */ + +#define EXPAND_FROM_REG8(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8SX, 0, NAME, {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, OP2, RS8, IGNORE, E}}}, \ + EXPAND2_STD_SRC (CODE, 2, NAME, RS8, PREFIX_0179, OP3, RS8), \ + {CODE, AV_H8SX, 0, NAME, {{RS8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, OP2, RS8, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS8, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS8, IGNORE, E}}} + +#define EXPAND_TO_REG8(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, OP1, OP2, IGNORE, RD8, E}}}, \ + EXPAND2_STD_DST (CODE, 2, NAME, RD8, PREFIX_017A, OP3, RD8), \ + {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, RD8, E}}, {{0x7, 0xe, ABS8LIST, OP1, OP2, IGNORE, RD8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD8, E}}, {{0x6, 0xa, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD8, E}}, {{0x6, 0xa, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD8, E}}} + +#define EXPAND_FROM_IND8(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B30), \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B30 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS16_B(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6A15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6A15, ABS16LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6A15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS32_B(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6A35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6A35, ABS32LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6A35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_IMM16_W(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{IMM16, RDIND, E}}, {{PREFIX_015E, TO_IND, OPCODE, IGNORE, IMM16LIST, E}}}, \ + EXPAND2_STD_IMM (CODE, 2, NAME, IMM16, PREFIX_015E, OPCODE, IGNORE, IMM16LIST), \ + {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS16DST, E}}, {{PREFIX_015E, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, IMM16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM16, ABS32DST, E}}, {{PREFIX_015E, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, IMM16LIST, E}}} + +#define EXPAND_FROM_REG16(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, OP1, OP2, RS16, IGNORE, E}}}, \ + EXPAND2_STD_SRC (CODE, 2, NAME, RS16, PREFIX_0159, OP3, RS16), \ + {CODE, AV_H8SX, 0, NAME, {{RS16, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, RS16, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS16, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, RS16, IGNORE, E}}} + +#define EXPAND_TO_REG16(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, IGNORE, OP1, OP2, IGNORE, RD16, E}}}, \ + EXPAND2_STD_DST (CODE, 2, NAME, RD16, PREFIX_015A, OP3, RD16), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD16, E}}, {{0x6, 0xb, 0x1, B30 | IGNORE, ABS16LIST, OP1, OP2, IGNORE, RD16, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD16, E}}, {{0x6, 0xb, 0x3, B30 | IGNORE, ABS32LIST, OP1, OP2, IGNORE, RD16, E}}} + +#define EXPAND_FROM_IND16(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RDIND, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_IND (CODE, 2, NAME, OPCODE, B31), \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS16DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, ABS32DST, E}}, {{0x7, 0xc, B31 | RSIND, 0x5, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS16_W(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RDIND, E}}, {{PREFIX_6B15, ABS16LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS16SRC, PREFIX_6B15, ABS16LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS16DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, ABS32DST, E}}, {{PREFIX_6B15, ABS16LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_ABS32_W(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RDIND, E}}, {{PREFIX_6B35, ABS32LIST, TO_IND, OPCODE, IGNORE, E}}}, \ + EXPAND2_STD_ABSDISP (CODE, 2, NAME, ABS32SRC, PREFIX_6B35, ABS32LIST, OPCODE, IGNORE), \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS16DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS16, OPCODE, IGNORE, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, ABS32DST, E}}, {{PREFIX_6B35, ABS32LIST, TO_ABS32, OPCODE, IGNORE, DSTABS32LIST, E}}} + +#define EXPAND_FROM_IMM16_L(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B30 | IGNORE, IMM16ULIST, E}}}, \ + EXPAND2_STD_IMM (CODE, 2, NAME, IMM16U_NS, PREFIX_010E, OPCODE, B30 | IGNORE, IMM16ULIST), \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B30 | IGNORE, DSTABS16LIST, IMM16ULIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B30 | IGNORE, DSTABS32LIST, IMM16ULIST, E}}} + +#define EXPAND_FROM_IMM32_L(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{IMM32, RDIND, E}}, {{PREFIX_010E, TO_IND, OPCODE, B31 | IGNORE, IMM32LIST, E}}}, \ + EXPAND2_STD_IMM (CODE, 2, NAME, IMM32, PREFIX_010E, OPCODE, B31 | IGNORE, IMM32LIST), \ + {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS16DST, E}}, {{PREFIX_010E, TO_ABS16, OPCODE, B31 | IGNORE, DSTABS16LIST, IMM32LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM32, ABS32DST, E}}, {{PREFIX_010E, TO_ABS32, OPCODE, B31 | IGNORE, DSTABS32LIST, IMM32LIST, E}}} + +#define EXPAND_FROM_REG32(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RS32, RDIND, E}}, {{PREFIX_0109, TO_IND, OPCODE, B30 | RS32, E}}}, \ + EXPAND2_STD_SRC (CODE, 2, NAME, RS32, PREFIX_0109, OPCODE, B30 | RS32), \ + {CODE, AV_H8SX, 0, NAME, {{RS32, ABS16DST, E}}, {{PREFIX_0109, TO_ABS16, OPCODE, B30 | RS32, DSTABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RS32, ABS32DST, E}}, {{PREFIX_0109, TO_ABS32, OPCODE, B30 | RS32, DSTABS32LIST, E}}} + +#define EXPAND_TO_REG32(CODE, NAME, OPCODE) \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, RD32, E}}, {{PREFIX_010A, FROM_IND, OPCODE, B30 | RD32, E}}}, \ + EXPAND2_STD_DST (CODE, 2, NAME, RD32, PREFIX_010A, OPCODE, B30 | RD32), \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS16, OPCODE, B30 | RD32, ABS16LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, RD32, E}}, {{PREFIX_010A, FROM_ABS32, OPCODE, B30 | RD32, ABS32LIST, E}}} + + +#define EXPAND_TWOOP_B(CODE, NAME, OP1, OP2, OP3, OP4, BIT) \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTINC, E}}, {{PREFIX_0174, 0x6, 0xc, B30 | RDPOSTINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREINC, E}}, {{PREFIX_0175, 0x6, 0xc, B30 | RDPREINC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, RDPREDEC, E}}, {{PREFIX_0177, 0x6, 0xc, B30 | RDPREDEC, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP2DST, E}}, {{PREFIX_017_D2D, 0x6, 0x8, B30 | DSTDISPREG, B31 | B20 | IGNORE, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP16DST, E}}, {{PREFIX_0174, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, DISP32DST, E}}, {{PREFIX_78R4WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB16D, E}}, {{PREFIX_0175, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW16D, E}}, {{PREFIX_0176, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL16D, E}}, {{PREFIX_0177, 0x6, 0xe, B30 | DSTDISPREG, B31 | B20 | IGNORE, DSTDISP16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXB32D, E}}, {{PREFIX_78R5WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXW32D, E}}, {{PREFIX_78R6WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, INDEXL32D, E}}, {{PREFIX_78R7WD, 0x6, 0xa, 2, B31 | B20 | IGNORE, DSTDISP32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS8DST, E}}, {{0x7, 0xf, DSTABS8LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS16DST, E}}, {{0x6, 0xa, 0x1, B31 | B20 | IGNORE, DSTABS16LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{IMM8, ABS32DST, E}}, {{0x6, 0xa, 0x3, B31 | B20 | IGNORE, DSTABS32LIST, OP1, BIT | IGNORE, IMM8LIST, E}}}, \ + {CODE, AV_H8, 2, NAME, {{RS8, RD8, E}}, {{OP2, OP3, RS8, RD8, E}}}, \ + EXPAND_FROM_REG8 (CODE, NAME, OP2, OP3, OP4), \ + EXPAND_TO_REG8 (CODE, NAME, OP2, OP3, OP4), \ + EXPAND_FROM_IND8 (CODE, NAME, OP4), \ + EXPAND_STD_MATRIX_B (CODE, NAME, OP4), \ + EXPAND_FROM_ABS16_B (CODE, NAME, OP4), \ + EXPAND_FROM_ABS32_B (CODE, NAME, OP4) + +#define EXPAND_TWOOP_W(CODE, NAME, OP1, OP2, OP3) \ + {CODE, AV_H8H, 6, NAME, {{IMM16, RD16, E}}, {{0x7, 0x9, OP3, RD16, IMM16LIST, E}}}, \ + EXPAND_FROM_IMM16_W (CODE, NAME, OP3), \ + EXPAND_FROM_REG16 (CODE, NAME, OP1, OP2, OP3), \ + EXPAND_TO_REG16 (CODE, NAME, OP1, OP2, OP3), \ + EXPAND_FROM_IND16 (CODE, NAME, OP3), \ + EXPAND_STD_MATRIX_W (CODE, NAME, OP3), \ + EXPAND_FROM_ABS16_W (CODE, NAME, OP3), \ + EXPAND_FROM_ABS32_W (CODE, NAME, OP3) + +#define EXPAND_TWOOP_L(CODE, NAME, OP1) \ + {CODE, AV_H8SX, 0, NAME, {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, OP1, B31 | RD32, IMM16ULIST, E}}}, \ + {CODE, AV_H8H, 6, NAME, {{IMM32, RD32, E}}, {{0x7, 0xa, OP1, B30 | RD32, IMM32LIST, E}}}, \ + EXPAND_FROM_IMM16_L (CODE, NAME, OP1), \ + EXPAND_FROM_IMM32_L (CODE, NAME, OP1), \ + EXPAND_FROM_REG32 (CODE, NAME, OP1), \ + EXPAND_TO_REG32 (CODE, NAME, OP1), \ + EXPAND_STD_MATRIX_L (CODE, NAME, OP1) + + +/* Old expanders: */ + +#define BITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + {code, AV_H8, 2, name, {{imm, RD8, E}}, {{op00, op01, imm, RD8, E}}}, \ + {code, AV_H8, 6, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, 0, E}}}, \ + {code, AV_H8, 6, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, 0, E}}}, \ + {code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \ + {code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}} + +#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + {code, AV_H8SX, 0, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, op4, E}}}, \ + {code, AV_H8SX, 0, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, op4, E}}}, \ + {code, AV_H8SX, 0, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \ + {code, AV_H8SX, 0, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | ABS32LIST, op00, op01, imm, op4, E}}} + +#define EBITOP(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + BITOP(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ + BITOP(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) + +#define EBITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \ + BITOP_B(code, imm, name, op00+1, op01, op10, op11, op20, op21, op30, op4), \ + BITOP_B(code, RS8, name, op00, op01, op10, op11, op20, op21, op30, op4) + +#define WTWOP(code, name, op1, op2) \ + {code, AV_H8, 2, name, {{RS16, RD16, E}}, {{op1, op2, RS16, RD16, E}}} + +#define BRANCH(code, name, op) \ + {code, AV_H8H, 6, name, {{PCREL16, E}}, {{0x5, 0x8, op, 0x0, PCREL16, DATA3 | B00, E}}}, \ + {code, AV_H8, 4, name, {{PCREL8, E}}, {{0x4, op, PCREL8, DATA | B00, E}}} + + +#define UNOP(code, name, op1, op2) \ + {code, AV_H8, 2, name, {{OR8, E}}, {{op1, op2, 0, OR8, E}}} + +#define EXPAND_UNOP_STD_B(CODE, NAME, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{OR8, E}}, {{ OP1, OP2, OP3, OR8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B30 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 8, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 14, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 10, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS8SRC, E}}, {{ 7, 15, ABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 10, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 10, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_STD_W(CODE, NAME, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8H, 2, NAME, {{OR16, E}}, {{ OP1, OP2, OP3, OR16, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{ 7, 13, B31 | RSIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B30 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B30 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B30 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B30 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{ 6, 11, 1, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{ 6, 11, 3, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_STD_L(CODE, NAME, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8H, 2, NAME, {{OR32, E}}, {{ OP1, OP2, OP3, B30 | OR32, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSIND, E}}, {{PREFIX, 4, 6, 9, B30 | RSIND, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RSPOSTINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RSPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RSPREINC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{RSPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RSPREDEC, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, E}}, {{PREFIX, B30 | B21 | DISP2SRC, 6, 9, B30 | DISPREG, B31 | IGNORE, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP16SRC, E}}, {{PREFIX, 4, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{DISP32SRC, E}}, {{7, 8, B31 | DISPREG, 4, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB16, E}}, {{PREFIX, 5, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW16, E}}, {{PREFIX, 6, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL16, E}}, {{PREFIX, 7, 6, 15, B30 | DISPREG, B31 | IGNORE, DISP16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXB32, E}}, {{7, 8, B31 | DISPREG, 5, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXW32, E}}, {{7, 8, B31 | DISPREG, 6, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{INDEXL32, E}}, {{7, 8, B31 | DISPREG, 7, 6, 11, 2, B31 | IGNORE, DISP32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS16SRC, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, ABS16LIST, OP1, OP2, OP3, B30 | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{ABS32SRC, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, ABS32LIST, OP1, OP2, OP3, B30 | IGNORE, E}}} + +#define EXPAND_UNOP_EXTENDED_B(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{CONST, RD8, E}}, {{ OP1, OP2, OP3, RD8, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B30 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 12, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 12, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 12, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 12, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 8, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 14, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 10, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS8DST, E}}, {{ 7, 15, DSTABS8LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 10, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 10, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_EXTENDED_W(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3) \ + {CODE, AV_H8, 2, NAME, {{CONST, RD16, E}}, {{ OP1, OP2, OP3, RD16, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{ 7, 13, B31 | RDIND, IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B30 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B30 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B30 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B30 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{ 6, 11, 1, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{ 6, 11, 3, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, IGNORE, E}}} + +#define EXPAND_UNOP_EXTENDED_L(CODE, NAME, CONST, PREFIX, OP1, OP2, OP3, BIT) \ + {CODE, AV_H8, 2, NAME, {{CONST, RD32, E}}, {{ OP1, OP2, OP3, BIT | RD32, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDIND, E}}, {{PREFIX, 4, 6, 9, B30 | RDIND, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTINC, E}}, {{PREFIX, 4, 6, 13, B30 | RDPOSTINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPOSTDEC, E}}, {{PREFIX, 6, 6, 13, B30 | RDPOSTDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREINC, E}}, {{PREFIX, 5, 6, 13, B30 | RDPREINC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, RDPREDEC, E}}, {{PREFIX, 7, 6, 13, B30 | RDPREDEC, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP2DST, E}}, {{PREFIX, B30 | B21 | DISP2DST, 6, 9, B30 | DSTDISPREG, B31 | IGNORE, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP16DST, E}}, {{PREFIX, 4, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, DISP32DST, E}}, {{7, 8, B31 | DSTDISPREG, 4, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB16D, E}}, {{PREFIX, 5, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW16D, E}}, {{PREFIX, 6, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL16D, E}}, {{PREFIX, 7, 6, 15, B30 | DSTDISPREG, B31 | IGNORE, DSTDISP16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXB32D, E}}, {{7, 8, B31 | DSTDISPREG, 5, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXW32D, E}}, {{7, 8, B31 | DSTDISPREG, 6, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, INDEXL32D, E}}, {{7, 8, B31 | DSTDISPREG, 7, 6, 11, 2, B31 | IGNORE, DSTDISP32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS16DST, E}}, {{PREFIX, 4, 6, 11, 0, B31 | IGNORE, DSTABS16LIST, OP1, OP2, OP3, BIT | IGNORE, E}}}, \ + {CODE, AV_H8SX, 0, NAME, {{CONST, ABS32DST, E}}, {{PREFIX, 4, 6, 11, 2, B31 | IGNORE, DSTABS32LIST, OP1, OP2, OP3, BIT | IGNORE, E}}} + +#define PREFIXLDC 0x0, 0x1, 0x4, B30 | CCR_EXR | DST +#define PREFIXSTC 0x0, 0x1, 0x4, B30 | CCR_EXR | SRC + +#define O(op, size) (op * 4 + size) +#define OP_SIZE(HOW) (HOW % 4) +#define OP_KIND(HOW) (HOW / 4) + +enum h8_asm_codes +{ + O_RECOMPILE = 0, + O_ADD, + O_ADDX, + O_AND, + O_BAND, + O_BRA, + O_BRAB, + O_BRAW, + O_BRAL, + O_BRAS, + O_BRABC, + O_BRABS, + O_BSRBC, + O_BSRBS, + O_BRN, + O_BHI, + O_BLS, + O_BCC, + O_BCS, + O_BNE, + O_BVC, + O_BVS, + O_BPL, + O_BMI, + O_BGE, + O_BLT, + O_BGT, + O_BLE, + O_ANDC, + O_BEQ, + O_BCLR, + O_BCLREQ, + O_BCLRNE, + O_BSETEQ, + O_BSETNE, + O_BFLD, + O_BFST, + O_BIAND, + O_BILD, + O_BIOR, + O_BIXOR, + O_BIST, + O_BISTZ, + O_BLD, + O_BNOT, + O_BOR, + O_BSET, + O_BSR, + O_BXOR, + O_CMP, + O_DAA, + O_DAS, + O_DEC, + O_DIVU, + O_DIVS, + O_DIVXU, + O_DIVXS, + O_INC, + O_LDC, + O_MOV, + O_MOVAB, + O_MOVAW, + O_MOVAL, + O_MOVMD, + O_MOVSD, + O_OR, + O_ROTL, + O_ROTR, + O_ROTXL, + O_ROTXR, + O_BPT, + O_SHAL, + O_SHAR, + O_SHLL, + O_SHLR, + O_SUB, + O_SUBS, + O_TRAPA, + O_XOR, + O_XORC, + O_BST, + O_BSTZ, + O_BTST, + O_EEPMOV, + O_EXTS, + O_EXTU, + O_JMP, + O_JSR, + O_MULU, + O_MULUU, + O_MULS, + O_MULSU, + O_MULXU, + O_MULXS, + O_NOP, + O_NOT, + O_ORC, + O_RTE, + O_RTEL, + O_STC, + O_SUBX, + O_NEG, + O_RTS, + O_RTSL, + O_SLEEP, + O_ILL, + O_ADDS, + O_SYSCALL, + O_TAS, + O_CLRMAC, + O_LDMAC, + O_MAC, + O_LDM, + O_STM, + O_STMAC, + O_LAST, + /* Change made for System Call processing. */ + O_SYS_CREAT, + O_SYS_OPEN, + O_SYS_READ, + O_SYS_WRITE, + O_SYS_LSEEK, + O_SYS_CLOSE, + O_SYS_STAT, + O_SYS_FSTAT, +/* Space reserved for future file I/O system calls. */ + O_SYS_CMDLINE + /* End of System Call specific Changes. */ +}; + +enum h8_size +{ + SB = 0, + SW = 1, + SL = 2, + SN = 3 +}; + + +/* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences. + Methinks the zeroes aren't necessary. Once confirmed, nuke 'em. */ + +struct h8_opcode h8_opcodes[] = +{ + {O (O_ADD, SB), AV_H8, 2, "add.b", {{IMM8, RD8, E}}, {{0x8, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_ADD, SB), "add.b", 0x8, 0x0, 0x8, 0x1, 0), + + {O (O_ADD, SW), AV_H8, 6, "add.w", {{RS16, RD16, E}}, {{0x0, 0x9, RS16, RD16, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xa, B30 | IMM3NZ, RD16, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_ADD, SW), AV_H8SX, 0, "add.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x0, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + EXPAND_TWOOP_W (O (O_ADD, SW), "add.w", 0x0, 0x9, 0x1), + + {O (O_ADD, SL), AV_H8H, 6, "add.l", {{RS32, RD32, E}}, {{0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_ADD, SL), AV_H8SX, 0, "add.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_ADD, SL), "add.l", 0x1), + + {O (O_ADDS, SL), AV_H8, 2, "adds", {{KBIT, RDP, E}}, {{0x0, 0xB,KBIT, RDP, E}}}, + + {O (O_ADDX, SB), AV_H8, 2, "addx", {{IMM8, RD8, E}}, {{0x9, RD8, IMM8LIST, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x9, IGNORE, IMM8LIST, E}}}, + {O (O_ADDX, SB), AV_H8, 2, "addx", {{RS8, RD8, E}}, {{0x0, 0xe, RS8, RD8, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x0, 0xe, RS8, IGNORE, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x0, 0xe, IGNORE, RD8, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, + {O (O_ADDX, SB), AV_H8SX, 0, "addx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, + + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x1, RD16, IMM16LIST, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x1, IGNORE, IMM16LIST, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x0, 0x9, RS16, RD16, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0x9, RS16, IGNORE, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0x9, IGNORE, RD16, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, + {O (O_ADDX, SW), AV_H8SX, 0, "addx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, + + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x1, RD32, IMM32LIST, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x1, IGNORE, IMM32LIST, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x0, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x0, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x1, IGNORE, E}}}, + {O (O_ADDX, SL), AV_H8SX, 0, "addx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x1, IGNORE, E}}}, + + {O (O_AND, SB), AV_H8, 2, "and.b", {{IMM8, RD8, E}}, {{0xe, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_AND, SB), "and.b", 0xe, 0x1, 0x6, 0x6, 0), + + {O (O_AND, SW), AV_H8, 2, "and.w", {{RS16, RD16, E}}, {{0x6, 0x6, RS16, RD16, E}}}, + EXPAND_TWOOP_W (O (O_AND, SW), "and.w", 0x6, 0x6, 0x6), + + {O (O_AND, SL), AV_H8H, 2, "and.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x6, B30 | RS32, B30 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_AND, SL), "and.l", 0x6), + + {O (O_ANDC, SB), AV_H8, 2, "andc", {{IMM8, CCR | DST, E}}, {{0x0, 0x6, IMM8LIST, E}}}, + {O (O_ANDC, SB), AV_H8S, 2, "andc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x6, IMM8LIST, E}}}, + + BRANCH (O (O_BRA, SB), "bra", 0x0), + + {O (O_BRAB, SB), AV_H8SX, 0, "bra", {{LOWREG | L_8, E}}, {{0x5, 0x9, LOWREG | L_8 | B30, 0x5, E}}}, + {O (O_BRAW, SW), AV_H8SX, 0, "bra", {{LOWREG | L_16, E}}, {{0x5, 0x9, LOWREG | L_16 | B30, 0x6, E}}}, + {O (O_BRAL, SL), AV_H8SX, 0, "bra", {{RS32, E}}, {{0x5, 0x9, RS32 | B30, 0x7, E}}}, + + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B30 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL8}}, {{0x7, 0xE, DSTABS8LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x4, B31 | IMM3, OP3PCREL8, DATA, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABC, SB), AV_H8SX, 0, "bra/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BRABS, SB), AV_H8SX, 0, "bra/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0x8, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + + {O (O_BRAS, SB), AV_H8SX, 0, "bra/s", {{PCREL8, E}}, {{0x4, 0x0, PCREL8, DATA | B01, E}}}, + + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBC, SB), AV_H8SX, 0, "bsr/bc", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B30 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, RDIND, OP3PCREL16}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS8DST, OP3PCREL16}}, {{0x7, 0xE, DSTABS8LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS16DST, OP3PCREL16}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + {O (O_BSRBS, SB), AV_H8SX, 0, "bsr/bs", {{IMM3, ABS32DST, OP3PCREL16}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0x5, 0xC, B31 | IMM3, 0x0, OP3PCREL16, DATA3, E}}}, + + BRANCH (O (O_BRA, SB), "bt", 0x0), + BRANCH (O (O_BRN, SB), "brn", 0x1), + BRANCH (O (O_BRN, SB), "bf", 0x1), + BRANCH (O (O_BHI, SB), "bhi", 0x2), + BRANCH (O (O_BLS, SB), "bls", 0x3), + BRANCH (O (O_BCC, SB), "bcc", 0x4), + BRANCH (O (O_BCC, SB), "bhs", 0x4), + BRANCH (O (O_BCS, SB), "bcs", 0x5), + BRANCH (O (O_BCS, SB), "blo", 0x5), + BRANCH (O (O_BNE, SB), "bne", 0x6), + BRANCH (O (O_BEQ, SB), "beq", 0x7), + BRANCH (O (O_BVC, SB), "bvc", 0x8), + BRANCH (O (O_BVS, SB), "bvs", 0x9), + BRANCH (O (O_BPL, SB), "bpl", 0xA), + BRANCH (O (O_BMI, SB), "bmi", 0xB), + BRANCH (O (O_BGE, SB), "bge", 0xC), + BRANCH (O (O_BLT, SB), "blt", 0xD), + BRANCH (O (O_BGT, SB), "bgt", 0xE), + BRANCH (O (O_BLE, SB), "ble", 0xF), + + EBITOP (O (O_BCLR, SB), IMM3 | B30, "bclr", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BAND, SB), IMM3 | B30, "band", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BIAND, SB), IMM3 | B31, "biand", 0x7, 0x6, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BILD, SB), IMM3 | B31, "bild", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BIOR, SB), IMM3 | B31, "bior", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BIST, SB), IMM3 | B31, "bist", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BIXOR, SB), IMM3 | B31, "bixor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BLD, SB), IMM3 | B30, "bld", 0x7, 0x7, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + EBITOP (O (O_BNOT, SB), IMM3 | B30, "bnot", 0x6, 0x1, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BOR, SB), IMM3 | B30, "bor", 0x7, 0x4, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + EBITOP (O (O_BSET, SB), IMM3 | B30, "bset", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + BITOP (O (O_BST, SB), IMM3 | B30, "bst", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0), + EBITOP (O (O_BTST, SB), IMM3 | B30, "btst", 0x6, 0x3, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + BITOP (O (O_BXOR, SB), IMM3 | B30, "bxor", 0x7, 0x5, 0x7, 0xC, 0x7, 0xE, 0x0, 0), + + EBITOP_B (O (O_BCLREQ, SB), IMM3 | B30, "bclr/eq", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + EBITOP_B (O (O_BCLRNE, SB), IMM3 | B30, "bclr/ne", 0x6, 0x2, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), + EBITOP_B (O (O_BSETEQ, SB), IMM3 | B30, "bset/eq", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + EBITOP_B (O (O_BSETNE, SB), IMM3 | B30, "bset/ne", 0x6, 0x0, 0x7, 0xD, 0x7, 0xF, 0x8, 0x6), + BITOP_B (O (O_BISTZ, SB), IMM3 | B31, "bistz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + BITOP_B (O (O_BSTZ, SB), IMM3 | B30, "bstz", 0x6, 0x7, 0x7, 0xD, 0x7, 0xF, 0x8, 0x7), + + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, RDIND, R3_8}}, {{0x7, 0xC, B30 | RDIND, 0x0, 0xF, R3_8, IMM8LIST, E}}}, + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS8DST, R3_8}}, {{0x7, 0xE, DSTABS8LIST, 0xF, R3_8, IMM8LIST, E}}}, + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS16DST, R3_8}}, {{0x6, 0xA, 0x1, 0x0, DSTABS16LIST, 0xF, R3_8, IMM8LIST, E}}}, + {O (O_BFLD, SB), AV_H8SX, 0, "bfld", {{IMM8, ABS32DST, R3_8}}, {{0x6, 0xA, 0x3, 0x0, DSTABS32LIST, 0xF, R3_8, IMM8LIST, E}}}, + + /* Because the assembler treats SRC, DST and OP3 as ordinals, + I must designate the second argument, an immediate value, as DST. + May God have mercy on my soul. */ + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, R3_IND}}, {{0x7, 0xD, B30 | R3_IND, 0x0, 0xF, RS8, DST | IMM8LIST, E}}}, + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS8OP3}}, {{0x7, 0xF, OP3ABS8LIST, 0xF, RS8, DST | IMM8LIST, E}}}, + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS16OP3}}, {{0x6, 0xA, 0x1, 0x8, OP3ABS16LIST, 0xF, RS8, DST | IMM8LIST, E}}}, + {O (O_BFST, SB), AV_H8SX, 0, "bfst", {{RS8, DST | IMM8, ABS32OP3}}, {{0x6, 0xA, 0x3, 0x8, OP3ABS32LIST, 0xF, RS8, DST | IMM8LIST, E}}}, + + {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL8, E}}, {{0x5, 0x5, PCREL8, DATA, E}}}, + {O (O_BSR, SB), AV_H8, 6, "bsr", {{PCREL16, E}}, {{0x5, 0xC, 0x0, 0x0, PCREL16, DATA3, E}}}, + {O (O_BSR, SB), AV_H8SX, 0, "bsr", {{LOWREG | L_8, E}}, {{0x5, 0xd, B30 | LOWREG | L_8, 0x5, E}}}, + {O (O_BSR, SW), AV_H8SX, 0, "bsr", {{LOWREG | L_16, E}}, {{0x5, 0xd, B30 | LOWREG | L_16, 0x6, E}}}, + {O (O_BSR, SL), AV_H8SX, 0, "bsr", {{OR32, E}}, {{0x5, 0xd, B30 | OR32, 0x7, E}}}, + + {O (O_CMP, SB), AV_H8, 2, "cmp.b", {{IMM8, RD8, E}}, {{0xa, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_CMP, SB), "cmp.b", 0xa, 0x1, 0xc, 0x2, B00), + + {O (O_CMP, SW), AV_H8, 2, "cmp.w", {{RS16, RD16, E}}, {{0x1, 0xd, RS16, RD16, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xf, B30 | IMM3NZ, RD16, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_CMP, SW), AV_H8SX, 0, "cmp.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xf, B30 | IMM3NZ, IGNORE, E}}}, + EXPAND_TWOOP_W (O (O_CMP, SW), "cmp.w", 0x1, 0xd, 0x2), + + {O (O_CMP, SL), AV_H8H, 6, "cmp.l", {{RS32, RD32, E}}, {{0x1, 0xf, B31 | RS32, B30 | RD32, E}}}, + {O (O_CMP, SL), AV_H8SX, 0, "cmp.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_CMP, SL), "cmp.l", 0x2), + + UNOP (O (O_DAA, SB), "daa", 0x0, 0xF), + UNOP (O (O_DAS, SB), "das", 0x1, 0xF), + UNOP (O (O_DEC, SB), "dec.b", 0x1, 0xA), + + {O (O_DEC, SW), AV_H8H, 2, "dec.w", {{DBIT, RD16, E}}, {{0x1, 0xB, 0x5 | DBIT, RD16, E}}}, + {O (O_DEC, SL), AV_H8H, 2, "dec.l", {{DBIT, RD32, E}}, {{0x1, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, + + {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVS, SW), AV_H8SX, 0, "divs.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x1, RS16, RD16, E}}}, + {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0x6, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVS, SL), AV_H8SX, 0, "divs.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0x2, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, + + {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVU, SW), AV_H8SX, 0, "divu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x1, RS16, RD16, E}}}, + {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xd, 0xe, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVU, SL), AV_H8SX, 0, "divu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xd, 0xa, 0x5, 0x3, B30 | RS32, B30 | RD32, E}}}, + + {O (O_DIVXS, SB), AV_H8SX, 0, "divxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVXS, SB), AV_H8H, 13, "divxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x1, RS8, RD16, E}}}, + {O (O_DIVXS, SW), AV_H8SX, 0, "divxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0x4, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVXS, SW), AV_H8H, 21, "divxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xD, 0x0, 0x5, 0x3, RS16, B30 | RD32, E}}}, + + {O (O_DIVXU, SB), AV_H8SX, 0, "divxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x1, IMM4, RD16, E}}}, + {O (O_DIVXU, SB), AV_H8, 13, "divxu.b", {{RS8, RD16, E}}, {{0x5, 0x1, RS8, RD16, E}}}, + {O (O_DIVXU, SW), AV_H8SX, 0, "divxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xD, 0xC, 0x5, 0x3, IMM4, B30 | RD32, E}}}, + {O (O_DIVXU, SW), AV_H8H, 21, "divxu.w", {{RS16, RD32, E}}, {{0x5, 0x3, RS16, B30 | RD32, E}}}, + + {O (O_EEPMOV, SB), AV_H8, 4, "eepmov.b", {{E}}, {{0x7, 0xB, 0x5, 0xC, 0x5, 0x9, 0x8, 0xF, E}}}, + {O (O_EEPMOV, SW), AV_H8H, 4, "eepmov.w", {{E}}, {{0x7, 0xB, 0xD, 0x4, 0x5, 0x9, 0x8, 0xF, E}}}, + + EXPAND_UNOP_STD_W (O (O_EXTS, SW), "exts.w", PREFIX_015, 0x1, 0x7, 0xd), + EXPAND_UNOP_STD_L (O (O_EXTS, SL), "exts.l", PREFIX_010, 0x1, 0x7, 0xf), + EXPAND_UNOP_EXTENDED_L (O (O_EXTS, SL), "exts.l", CONST_2, PREFIX_010, 0x1, 0x7, 0xe, 0), + EXPAND_UNOP_STD_W (O (O_EXTU, SW), "extu.w", PREFIX_015, 0x1, 0x7, 0x5), + EXPAND_UNOP_STD_L (O (O_EXTU, SL), "extu.l", PREFIX_010, 0x1, 0x7, 0x7), + EXPAND_UNOP_EXTENDED_L (O (O_EXTU, SL), "extu.l", CONST_2, PREFIX_010, 0x1, 0x7, 0x6, 0), + + UNOP (O (O_INC, SB), "inc", 0x0, 0xA), + + {O (O_INC, SW), AV_H8H, 2, "inc.w", {{DBIT, RD16, E}}, {{0x0, 0xB, 0x5 | DBIT, RD16, E}}}, + {O (O_INC, SL), AV_H8H, 2, "inc.l", {{DBIT, RD32, E}}, {{0x0, 0xB, 0x7 | DBIT, RD32 | B30, E}}}, + + {O (O_JMP, SN), AV_H8, 4, "jmp", {{RSIND, E}}, {{0x5, 0x9, B30 | RSIND, 0x0, E}}}, + {O (O_JMP, SN), AV_H8, 6, "jmp", {{ABSJMP | L_24, E}}, {{0x5, 0xA, SRC | ABSJMP | L_24, DATA5, E}}}, + + {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{ABSJMP | L_32, E}}, {{0x5, 0x9, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, + + {O (O_JMP, SN), AV_H8, 8, "jmp", {{MEMIND, E}}, {{0x5, 0xB, SRC | MEMIND, DATA, E}}}, + {O (O_JMP, SN), AV_H8SX, 0, "jmp", {{VECIND, E}}, {{0x5, 0x9, B31 | SRC | VECIND, DATA, E}}}, + + {O (O_JSR, SN), AV_H8, 6, "jsr", {{RSIND, E}}, {{0x5, 0xD, B30 | RSIND, 0x0, E}}}, + {O (O_JSR, SN), AV_H8, 8, "jsr", {{ABSJMP | L_24, E}}, {{0x5, 0xE, SRC | ABSJMP | L_24, DATA5, E}}}, + + {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, + + {O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}}, + {O (O_JSR, SN), AV_H8, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}}, + + {O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ 0x0, 0x7, IMM8LIST, E}}}, + {O (O_LDC, SB), AV_H8S, 2, "ldc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x7, IMM8LIST, E}}}, + {O (O_LDC, SB), AV_H8, 2, "ldc", {{RS8, CCR | DST, E}}, {{0x0, 0x3, B30 | CCR | DST, RS8, E}}}, + {O (O_LDC, SB), AV_H8S, 2, "ldc", {{RS8, EXR | DST, E}}, {{0x0, 0x3, B30 | EXR | DST, RS8, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSIND, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSIND, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0x9, B30 | RSIND, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{RSPOSTINC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{RSPOSTINC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xD, B30 | RSPOSTINC, IGNORE, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xF, B30 | DISPREG, IGNORE, SRC | DISP16LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{DISP32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}}, + {O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, + {O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}}, + + {O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}}, + + + {O (O_MOV, SB), AV_H8, 2, "mov.b", {{IMM8, RD8, E}}, {{0xF, RD8, IMM8LIST, E}}}, + {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xa, 0xd, IMM4, DSTABS16LIST, E}}}, + {O (O_MOV, SB), AV_H8SX, 0, "mov.b", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xa, 0xf, IMM4, DSTABS32LIST, E}}}, + MOVFROM_IMM8 (O (O_MOV, SB), PREFIX_017D, "mov.b", IMM8), + + {O (O_MOV, SB), AV_H8, 2, "mov.b", {{RS8, RD8, E}}, {{0x0, 0xC, RS8, RD8, E}}}, + MOVFROM_REG_BW (O (O_MOV, SB), "mov.b", RS8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), + {O (O_MOV, SB), AV_H8, 4, "mov.b", {{RS8, ABS8DST, E}}, {{0x3, RS8, DSTABS8LIST, E}}}, + MOVTO_REG_BW (O (O_MOV, SB), "mov.b", RD8, PREFIX_017, 8, 10, 12, 14, MEMRELAX), + {O (O_MOV, SB), AV_H8, 4, "mov.b", {{ABS8SRC, RD8, E}}, {{0x2, RD8, ABS8LIST, E}}}, + + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSIND, FROM_IND), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTINC, FROM_POSTINC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPOSTDEC, FROM_POSTDEC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREINC, FROM_PREINC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", RSPREDEC, FROM_PREDEC), + MOVFROM_STD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP2SRC, FROM_DISP2), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP16SRC, FROM_DISP16, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", DISP32SRC, FROM_DISP32, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB16, FROM_DISP16B, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW16, FROM_DISP16W, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL16, FROM_DISP16L, DISP16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXB32, FROM_DISP32B, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXW32, FROM_DISP32W, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", INDEXL32, FROM_DISP32L, DISP32LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS16SRC, FROM_ABS16, ABS16LIST), + MOVFROM_AD (O (O_MOV, SB), PREFIX_0178, "mov.b", ABS32SRC, FROM_ABS32, ABS32LIST), + + {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM3NZ_NS, RD16, E}}, {{0x0, 0xf, B30 | IMM3NZ, RD16, E}}}, + {O (O_MOV, SW), AV_H8, 4, "mov.w", {{IMM16, RD16, E}}, {{0x7, 0x9, 0x0, RD16, IMM16LIST, E}}}, + {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}}, + {O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}}, + + MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8U_NS), + MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST), + + {O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}}, + MOVFROM_REG_BW (O (O_MOV, SW), "mov.w", RS16, PREFIX_015, 9, 11, 13, 15, 0), + MOVTO_REG_BW (O (O_MOV, SW), "mov.w", RD16, PREFIX_015, 9, 11, 13, 15, 0), + + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSIND, FROM_IND), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTINC, FROM_POSTINC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPOSTDEC, FROM_POSTDEC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREINC, FROM_PREINC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", RSPREDEC, FROM_PREDEC), + MOVFROM_STD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP2SRC, FROM_DISP2), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP16SRC, FROM_DISP16, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", DISP32SRC, FROM_DISP32, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB16, FROM_DISP16B, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW16, FROM_DISP16W, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL16, FROM_DISP16L, DISP16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXB32, FROM_DISP32B, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXW32, FROM_DISP32W, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", INDEXL32, FROM_DISP32L, DISP32LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS16SRC, FROM_ABS16, ABS16LIST), + MOVFROM_AD (O (O_MOV, SW), PREFIX_0158, "mov.w", ABS32SRC, FROM_ABS32, ABS32LIST), + + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}}, + + MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS), + MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST), + + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}}, + {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{IMM32, RD32, E}}, {{0x7, 0xa, 0x0, B30 | RD32, IMM32LIST, E}}}, + + MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A74, "mov.l", IMM32, IMM32LIST), + + {O (O_MOV, SL), AV_H8H, 2, "mov.l", {{RS32, RD32, E}}, {{0x0, 0xf, B31 | RS32, B30 | RD32, E}}}, + + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDIND, E}}, {{PREFIX_0100, 0x6, 0x9, B31 | RDIND, B30 | RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTINC, E}}, {{PREFIX_0103, 0x6, 0xd, B31 | RDPOSTINC, RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0101, 0x6, 0xd, B31 | RDPOSTDEC, RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, RDPREINC, E}}, {{PREFIX_0102, 0x6, 0xd, B31 | RDPREINC, RS32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, RDPREDEC, E}}, {{PREFIX_0100, 0x6, 0xd, B31 | RDPREDEC, RS32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, DISP2DST, E}}, {{PREFIX_010, B30 | B20 | DISP2DST, 0x6, 0x9, B31 | DSTDISPREG, RS32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP16DST, E}}, {{PREFIX_0100, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{RS32, DISP32DST, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, DISP32DST, E}}, {{PREFIX_0100, 0x7, 0x8, B31 | DSTDISPREG, 0x0, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB16D, E}}, {{PREFIX_0101, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW16D, E}}, {{PREFIX_0102, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL16D, E}}, {{PREFIX_0103, 0x6, 0xf, B31 | DSTDISPREG, RS32, DSTDISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXB32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x1, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXW32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x2, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RS32, INDEXL32D, E}}, {{0x7, 0x8, B31 | DSTDISPREG, 0x3, 0x6, 0xb, 0xa, RS32, DSTDISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS16DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0x8, RS32, DSTABS16LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RS32, ABS32DST, E}}, {{PREFIX_0100, 0x6, 0xb, 0xa, RS32, MEMRELAX | DSTABS32LIST, E}}}, + + {O (O_MOV, SL), AV_H8H, 4, "mov.l", {{RSIND, RD32, E}}, {{PREFIX_0100, 0x6, 0x9, B30 | RSIND, RD32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{RSPOSTINC, RD32, E}}, {{PREFIX_0100, 0x6, 0xd, B30 | RSPOSTINC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0102, 0x6, 0xd, B30 | RSPOSTDEC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREINC, RD32, E}}, {{PREFIX_0101, 0x6, 0xd, B30 | RSPREINC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{RSPREDEC, RD32, E}}, {{PREFIX_0103, 0x6, 0xd, B30 | RSPREDEC, RD32, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{DISP2SRC, RD32, E}}, {{PREFIX_010, B30 | B20 | DISP2SRC, 0x6, 0x9, B30 | DISPREG, RD32, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{DISP32SRC, RD32, E}}, {{PREFIX_0100, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB16, RD32, E}}, {{PREFIX_0101, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW16, RD32, E}}, {{PREFIX_0102, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL16, RD32, E}}, {{PREFIX_0103, 0x6, 0xf, B30 | DISPREG, RD32, SRC | DISP16LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXB32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x1, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXW32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x2, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{INDEXL32, RD32, E}}, {{0x7, 0x8, B31 | DISPREG, 0x3, 0x6, 0xb, 0x2, RD32, SRC | DISP32LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS16SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x0, RD32, SRC | ABS16LIST, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "mov.l", {{ABS32SRC, RD32, E}}, {{PREFIX_0100, 0x6, 0xb, 0x2, RD32, SRC | MEMRELAX | ABS32LIST, E}}}, + + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSIND, FROM_IND), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTINC, FROM_POSTINC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPOSTDEC, FROM_POSTDEC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREINC, FROM_PREINC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", RSPREDEC, FROM_PREDEC), + MOVFROM_STD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP2SRC, FROM_DISP2), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP16SRC, FROM_DISP16, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", DISP32SRC, FROM_DISP32, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB16, FROM_DISP16B, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW16, FROM_DISP16W, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL16, FROM_DISP16L, DISP16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXB32, FROM_DISP32B, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXW32, FROM_DISP32W, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", INDEXL32, FROM_DISP32L, DISP32LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS16SRC, FROM_ABS16, ABS16LIST), + MOVFROM_AD (O (O_MOV, SL), PREFIX_0108, "mov.l", ABS32SRC, FROM_ABS32, ABS32LIST), + +#define DO_MOVA1(TYPE, OP0, OP1) \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, DISP16LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, DISP16LIST, E}}}, \ +\ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, DISP32LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, DISP32LIST, E}}} + +#define DO_MOVA2(TYPE, OP0, OP1, OP2) \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B30 | R3_32, OP2, DISP16LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B30 | R3_32, OP2, DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B30 | R3_32, OP2, DISP16LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B30 | R3_32, OP2, DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B30 | R3_32, OP2, DISP16LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B30 | R3_32, OP2, DISP16LIST, E}}}, \ +\ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0x8, B31 | R3_32, OP2, DISP32LIST, E}}}, \ + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0x9, B31 | R3_32, OP2, DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xA, B31 | R3_32, OP2, DISP32LIST, E}}}, \ + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xB, B31 | R3_32, OP2, DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, TYPE, R3_32}}, {{PREFIX_017F, OP0, OP1, 0xC, B31 | R3_32, OP2, DISP32LIST, E}}}, \ + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, TYPE, R3_32}}, {{PREFIX_015F, OP0, OP1, 0xD, B31 | R3_32, OP2, DISP32LIST, E}}} + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, E}}, {{0x7, 0xA, 0x8, B31 | DISPREG, DISP16LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, E}}, {{0x7, 0xA, 0x9, B31 | DISPREG, DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xA, B31 | DISPREG, DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xB, B31 | DISPREG, DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, E}}, {{0x7, 0xA, 0xC, B31 | DISPREG, DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, E}}, {{0x7, 0xA, 0xD, B31 | DISPREG, DISP16LIST, E}}}, + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, E}}, {{0x7, 0xA, 0x8, B30 | DISPREG, DISP32LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, E}}, {{0x7, 0xA, 0x9, B30 | DISPREG, DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xA, B30 | DISPREG, DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xB, B30 | DISPREG, DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, E}}, {{0x7, 0xA, 0xC, B30 | DISPREG, DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, E}}, {{0x7, 0xA, 0xD, B30 | DISPREG, DISP32LIST, E}}}, + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B31 | R3_32, DISP16LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B31 | R3_32, DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B31 | R3_32, DISP16LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B31 | R3_32, DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB16, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B31 | R3_32, DISP16LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW16, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B31 | R3_32, DISP16LIST, E}}}, + + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0x8, B30 | R3_32, DISP32LIST, E}}}, + {O (O_MOVAB, SL), AV_H8SX, 0, "mova/b.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0x9, B30 | R3_32, DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xA, B30 | R3_32, DISP32LIST, E}}}, + {O (O_MOVAW, SL), AV_H8SX, 0, "mova/w.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xB, B30 | R3_32, DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXB32, RD8, R3_32}}, {{0x7, 0x8, RD8, 0x8, 0x7, 0xA, 0xC, B30 | R3_32, DISP32LIST, E}}}, + {O (O_MOVAL, SL), AV_H8SX, 0, "mova/l.l", {{INDEXW32, RD16, R3_32}}, {{0x7, 0x8, RD16, 0x9, 0x7, 0xA, 0xD, B30 | R3_32, DISP32LIST, E}}}, + + DO_MOVA1 (RDIND, 0x0, B30 | RDIND), + DO_MOVA1 (RDPOSTINC, 0x8, B30 | RDPOSTINC), + DO_MOVA1 (RDPOSTDEC, 0xA, B30 | RDPOSTDEC), + DO_MOVA1 (RDPREINC, 0x9, B30 | RDPREINC), + DO_MOVA1 (RDPREDEC, 0xB, B30 | RDPREDEC), + DO_MOVA1 (DISP2DST, B30 | B20 | DISP2DST, B30 | DSTDISPREG), + DO_MOVA2 (DISP16DST, 0xC, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (DISP32DST, 0xC, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (INDEXB16D, 0xD, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (INDEXW16D, 0xE, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (INDEXL16D, 0xF, B30 | DSTDISPREG, DSTDISP16LIST), + DO_MOVA2 (INDEXB32D, 0xD, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (INDEXW32D, 0xE, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (INDEXL32D, 0xF, B31 | DSTDISPREG, DSTDISP32LIST), + DO_MOVA2 (ABS16DST, 0x4, 0x0, DSTABS16LIST), + DO_MOVA2 (ABS32DST, 0x4, 0x8, DSTABS32LIST), + + {O (O_MOV, SB), AV_H8, 10, "movfpe", {{ABS16SRC, RD8, E}}, {{0x6, 0xA, 0x4, RD8, ABS16SRC, DATA3, E}}}, + {O (O_MOV, SB), AV_H8, 10, "movtpe", {{RS8, ABS16DST, E}}, {{0x6, 0xA, 0xC, RS8, ABS16DST, DATA3, E}}}, + + {O (O_MOVMD, SB), AV_H8SX, 0, "movmd.b", {{E}}, {{0x7, 0xb, 0x9, 0x4, E}}}, + {O (O_MOVMD, SW), AV_H8SX, 0, "movmd.w", {{E}}, {{0x7, 0xb, 0xa, 0x4, E}}}, + {O (O_MOVMD, SL), AV_H8SX, 0, "movmd.l", {{E}}, {{0x7, 0xb, 0xb, 0x4, E}}}, + {O (O_MOVSD, SB), AV_H8SX, 0, "movsd.b", {{PCREL16, E}}, {{0x7, 0xb, 0x8, 0x4, PCREL16, DATA3, E}}}, + + {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULS, SW), AV_H8SX, 0, "muls.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x0, RS16, RD16, E}}}, + {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x6, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULS, SL), AV_H8SX, 0, "muls.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x2, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + + {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULU, SW), AV_H8SX, 0, "mulu.w", {{RS16, RD16, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x0, RS16, RD16, E}}}, + {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xe, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULU, SL), AV_H8SX, 0, "mulu.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xa, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + + {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x7, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULSU, SL), AV_H8SX, 0, "muls/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0x3, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xf, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULUU, SL), AV_H8SX, 0, "mulu/u.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xc, 0xb, 0x5, 0x2, B30 | RS32, B30 | RD32, E}}}, + + {O (O_MULXS, SB), AV_H8SX, 0, "mulxs.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULXS, SB), AV_H8H, 20, "mulxs.b", {{RS8, RD16, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x0, RS8, RD16, E}}}, + {O (O_MULXS, SW), AV_H8SX, 0, "mulxs.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0x4, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULXS, SW), AV_H8H, 20, "mulxs.w", {{RS16, RD32, E}}, {{0x0, 0x1, 0xc, 0x0, 0x5, 0x2, RS16, B30 | RD32, E}}}, + + {O (O_MULXU, SB), AV_H8SX, 0, "mulxu.b", {{IMM4, RD16, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x0, IMM4, RD16, E}}}, + {O (O_MULXU, SB), AV_H8, 14, "mulxu.b", {{RS8, RD16, E}}, {{0x5, 0x0, RS8, RD16, E}}}, + {O (O_MULXU, SW), AV_H8SX, 0, "mulxu.w", {{IMM4, RD32, E}}, {{0x0, 0x1, 0xc, 0xc, 0x5, 0x2, IMM4, B30 | RD32, E}}}, + {O (O_MULXU, SW), AV_H8H, 14, "mulxu.w", {{RS16, RD32, E}}, {{0x5, 0x2, RS16, B30 | RD32, E}}}, + + EXPAND_UNOP_STD_B (O (O_NEG, SB), "neg.b", PREFIX_017, 0x1, 0x7, 0x8), + EXPAND_UNOP_STD_W (O (O_NEG, SW), "neg.w", PREFIX_015, 0x1, 0x7, 0x9), + EXPAND_UNOP_STD_L (O (O_NEG, SL), "neg.l", PREFIX_010, 0x1, 0x7, 0xb), + + {O (O_NOP, SN), AV_H8, 2, "nop", {{E}}, {{0x0, 0x0, 0x0, 0x0, E}}}, + + EXPAND_UNOP_STD_B (O (O_NOT, SB), "not.b", PREFIX_017, 0x1, 0x7, 0x0), + EXPAND_UNOP_STD_W (O (O_NOT, SW), "not.w", PREFIX_015, 0x1, 0x7, 0x1), + EXPAND_UNOP_STD_L (O (O_NOT, SL), "not.l", PREFIX_010, 0x1, 0x7, 0x3), + + {O (O_OR, SB), AV_H8, 2, "or.b", {{IMM8, RD8, E}}, {{0xc, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_OR, SB), "or.b", 0xc, 0x1, 0x4, 0x4, 0), + + {O (O_OR, SW), AV_H8, 2, "or.w", {{RS16, RD16, E}}, {{0x6, 0x4, RS16, RD16, E}}}, + EXPAND_TWOOP_W (O (O_OR, SW), "or.w", 0x6, 0x4, 0x4), + + {O (O_OR, SL), AV_H8H, 2, "or.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x4, B30 | RS32, B30 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_OR, SL), "or.l", 0x4), + + {O (O_ORC, SB), AV_H8, 2, "orc", {{IMM8, CCR | DST, E}}, {{0x0, 0x4, IMM8LIST, E}}}, + {O (O_ORC, SB), AV_H8S, 2, "orc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x4, IMM8LIST, E}}}, + + {O (O_MOV, SW), AV_H8, 6, "pop.w", {{OR16, E}}, {{0x6, 0xD, 0x7, OR16, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "pop.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0x7, OR32 | B30, E}}}, + {O (O_MOV, SW), AV_H8, 6, "push.w", {{OR16, E}}, {{0x6, 0xD, 0xF, OR16, E}}}, + {O (O_MOV, SL), AV_H8H, 6, "push.l", {{OR32, E}}, {{PREFIX_0100, 0x6, 0xD, 0xF, OR32 | B30, E}}}, + + EXPAND_UNOP_STD_B (O (O_ROTL, SB), "rotl.b", PREFIX_017, 0x1, 0x2, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_ROTL, SB), "rotl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0xc), + EXPAND_UNOP_STD_W (O (O_ROTL, SW), "rotl.w", PREFIX_015, 0x1, 0x2, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_ROTL, SW), "rotl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0xd), + EXPAND_UNOP_STD_L (O (O_ROTL, SL), "rotl.l", PREFIX_010, 0x1, 0x2, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_ROTL, SL), "rotl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0xf, B30), + EXPAND_UNOP_STD_B (O (O_ROTR, SB), "rotr.b", PREFIX_017, 0x1, 0x3, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_ROTR, SB), "rotr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0xc), + EXPAND_UNOP_STD_W (O (O_ROTR, SW), "rotr.w", PREFIX_015, 0x1, 0x3, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_ROTR, SW), "rotr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0xd), + EXPAND_UNOP_STD_L (O (O_ROTR, SL), "rotr.l", PREFIX_010, 0x1, 0x3, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_ROTR, SL), "rotr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0xf, B30), + EXPAND_UNOP_STD_B (O (O_ROTXL, SB), "rotxl.b", PREFIX_017, 0x1, 0x2, 0x0), + EXPAND_UNOP_EXTENDED_B (O (O_ROTXL, SB), "rotxl.b", CONST_2, PREFIX_017, 0x1, 0x2, 0x4), + EXPAND_UNOP_STD_W (O (O_ROTXL, SW), "rotxl.w", PREFIX_015, 0x1, 0x2, 0x1), + EXPAND_UNOP_EXTENDED_W (O (O_ROTXL, SW), "rotxl.w", CONST_2, PREFIX_015, 0x1, 0x2, 0x5), + EXPAND_UNOP_STD_L (O (O_ROTXL, SL), "rotxl.l", PREFIX_010, 0x1, 0x2, 0x3), + EXPAND_UNOP_EXTENDED_L (O (O_ROTXL, SL), "rotxl.l", CONST_2, PREFIX_010, 0x1, 0x2, 0x7, B30), + EXPAND_UNOP_STD_B (O (O_ROTXR, SB), "rotxr.b", PREFIX_017, 0x1, 0x3, 0x0), + EXPAND_UNOP_EXTENDED_B (O (O_ROTXR, SB), "rotxr.b", CONST_2, PREFIX_017, 0x1, 0x3, 0x4), + EXPAND_UNOP_STD_W (O (O_ROTXR, SW), "rotxr.w", PREFIX_015, 0x1, 0x3, 0x1), + EXPAND_UNOP_EXTENDED_W (O (O_ROTXR, SW), "rotxr.w", CONST_2, PREFIX_015, 0x1, 0x3, 0x5), + EXPAND_UNOP_STD_L (O (O_ROTXR, SL), "rotxr.l", PREFIX_010, 0x1, 0x3, 0x3), + EXPAND_UNOP_EXTENDED_L (O (O_ROTXR, SL), "rotxr.l", CONST_2, PREFIX_010, 0x1, 0x3, 0x7, B30), + + + {O (O_BPT, SN), AV_H8, 10, "bpt", {{E}}, {{0x7, 0xA, 0xF, 0xF, E}}}, + {O (O_RTE, SN), AV_H8, 10, "rte", {{E}}, {{0x5, 0x6, 0x7, 0x0, E}}}, + {O (O_RTS, SN), AV_H8, 8, "rts", {{E}}, {{0x5, 0x4, 0x7, 0x0, E}}}, + {O (O_RTEL, SN), AV_H8SX, 0, "rte/l", {{RS32, RD32, E}}, {{0x5, 0x6, RS32 | B30, RD32 | B30, E}}}, + {O (O_RTSL, SN), AV_H8SX, 0, "rts/l", {{RS32, RD32, E}}, {{0x5, 0x4, RS32 | B30, RD32 | B30, E}}}, + + EXPAND_UNOP_STD_B (O (O_SHAL, SB), "shal.b", PREFIX_017, 0x1, 0x0, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_SHAL, SB), "shal.b", CONST_2, PREFIX_017, 0x1, 0x0, 0xc), + EXPAND_UNOP_STD_W (O (O_SHAL, SW), "shal.w", PREFIX_015, 0x1, 0x0, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_SHAL, SW), "shal.w", CONST_2, PREFIX_015, 0x1, 0x0, 0xd), + EXPAND_UNOP_STD_L (O (O_SHAL, SL), "shal.l", PREFIX_010, 0x1, 0x0, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_SHAL, SL), "shal.l", CONST_2, PREFIX_010, 0x1, 0x0, 0xf, B30), + EXPAND_UNOP_STD_B (O (O_SHAR, SB), "shar.b", PREFIX_017, 0x1, 0x1, 0x8), + EXPAND_UNOP_EXTENDED_B (O (O_SHAR, SB), "shar.b", CONST_2, PREFIX_017, 0x1, 0x1, 0xc), + EXPAND_UNOP_STD_W (O (O_SHAR, SW), "shar.w", PREFIX_015, 0x1, 0x1, 0x9), + EXPAND_UNOP_EXTENDED_W (O (O_SHAR, SW), "shar.w", CONST_2, PREFIX_015, 0x1, 0x1, 0xd), + EXPAND_UNOP_STD_L (O (O_SHAR, SL), "shar.l", PREFIX_010, 0x1, 0x1, 0xb), + EXPAND_UNOP_EXTENDED_L (O (O_SHAR, SL), "shar.l", CONST_2, PREFIX_010, 0x1, 0x1, 0xf, B30), + + EXPAND_UNOP_STD_B (O (O_SHLL, SB), "shll.b", PREFIX_017, 0x1, 0x0, 0x0), + + {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x0, RD8, E}}}, + + EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_2, PREFIX_017, 0x1, 0x0, 0x4), + EXPAND_UNOP_EXTENDED_B (O (O_SHLL, SB), "shll.b", CONST_4, PREFIX_017, 0x1, 0x0, 0xa), + {O (O_SHLL, SB), AV_H8SX, 0, "shll.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x0, RD8, E}}}, + + EXPAND_UNOP_STD_W (O (O_SHLL, SW), "shll.w", PREFIX_015, 0x1, 0x0, 0x1), + + {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x1, RD16, E}}}, + + EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_2, PREFIX_015, 0x1, 0x0, 0x5), + EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_4, PREFIX_015, 0x1, 0x0, 0x2), + EXPAND_UNOP_EXTENDED_W (O (O_SHLL, SW), "shll.w", CONST_8, PREFIX_015, 0x1, 0x0, 0x6), + {O (O_SHLL, SW), AV_H8SX, 0, "shll.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x1, RD16, E}}}, + + EXPAND_UNOP_STD_L (O (O_SHLL, SL), "shll.l", PREFIX_010, 0x1, 0x0, 0x3), + + {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x0, 0x3, B30 | RD32, E}}}, + + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_2, PREFIX_010, 0x1, 0x0, 0x7, B30), + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_4, PREFIX_010, 0x1, 0x0, 0x3, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_8, PREFIX_010, 0x1, 0x0, 0x7, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLL, SL), "shll.l", CONST_16, PREFIX_010, 0x1, 0x0, 0xf, B31), + {O (O_SHLL, SL), AV_H8SX, 0, "shll.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x0, 0x3, B30 | RD32, E}}}, + + EXPAND_UNOP_STD_B (O (O_SHLR, SB), "shlr.b", PREFIX_017, 0x1, 0x1, 0x0), + + {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{RS8, RD8, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x0, RD8, E}}}, + + EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_2, PREFIX_017, 0x1, 0x1, 0x4), + EXPAND_UNOP_EXTENDED_B (O (O_SHLR, SB), "shlr.b", CONST_4, PREFIX_017, 0x1, 0x1, 0xa), + {O (O_SHLR, SB), AV_H8SX, 0, "shlr.b", {{IMM5, RD8, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x0, RD8, E}}}, + + EXPAND_UNOP_STD_W (O (O_SHLR, SW), "shlr.w", PREFIX_015, 0x1, 0x1, 0x1), + + {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{RS8, RD16, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x1, RD16, E}}}, + + EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_2, PREFIX_015, 0x1, 0x1, 0x5), + EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_4, PREFIX_015, 0x1, 0x1, 0x2), + EXPAND_UNOP_EXTENDED_W (O (O_SHLR, SW), "shlr.w", CONST_8, PREFIX_015, 0x1, 0x1, 0x6), + {O (O_SHLR, SW), AV_H8SX, 0, "shlr.w", {{IMM5, RD16, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x1, RD16, E}}}, + + EXPAND_UNOP_STD_L (O (O_SHLR, SL), "shlr.l", PREFIX_010, 0x1, 0x1, 0x3), + + {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{RS8, RD32, E}}, {{0x7, 0x8, RS8, 0x8, 0x1, 0x1, 0x3, B30 | RD32, E}}}, + + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_2, PREFIX_010, 0x1, 0x1, 0x7, B30), + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_4, PREFIX_010, 0x1, 0x1, 0x3, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_8, PREFIX_010, 0x1, 0x1, 0x7, B31), + EXPAND_UNOP_EXTENDED_L (O (O_SHLR, SL), "shlr.l", CONST_16, PREFIX_010, 0x1, 0x1, 0xf, B31), + {O (O_SHLR, SL), AV_H8SX, 0, "shlr.l", {{IMM5, RD32, E}}, {{0x0, 0x3, B31 | IMM5, DATA, 0x1, 0x1, 0x3, B30 | RD32, E}}}, + + {O (O_SLEEP, SN), AV_H8, 2, "sleep", {{E}}, {{0x0, 0x1, 0x8, 0x0, E}}}, + + {O (O_STC, SB), AV_H8, 2, "stc", {{CCR | SRC, RD8, E}}, {{0x0, 0x2, B30 | CCR | SRC, RD8, E}}}, + {O (O_STC, SB), AV_H8S, 2, "stc", {{EXR | SRC, RD8, E}}, {{0x0, 0x2, B30 | EXR | SRC, RD8, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDIND, E}}, {{PREFIXSTC, 0x6, 0x9, B31 | RDIND, IGNORE, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, RDPREDEC, E}}, {{PREFIXSTC, 0x6, 0xD, B31 | RDPREDEC, IGNORE, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP16DST, E}}, {{PREFIXSTC, 0x6, 0xF, B31 | DSTDISPREG, IGNORE, DSTDISP16LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}}, + {O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, + {O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}}, + {O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}}, + + + EXPAND_TWOOP_B (O (O_SUB, SB), "sub.b", 0xa, 0x1, 0x8, 0x3, B01), + + {O (O_SUB, SW), AV_H8, 2, "sub.w", {{RS16, RD16, E}}, {{0x1, 0x9, RS16, RD16, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RD16, E}}, {{0x1, 0xa, B30 | IMM3NZ, RD16, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, IGNORE, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS16DST, E}}, {{0x6, 0xb, 0x1, B31 | IGNORE, DSTABS16LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + {O (O_SUB, SW), AV_H8SX, 0, "sub.w", {{IMM3NZ_NS, ABS32DST, E}}, {{0x6, 0xb, 0x3, B31 | IGNORE, DSTABS32LIST, 0x1, 0xa, B30 | IMM3NZ, IGNORE, E}}}, + EXPAND_TWOOP_W (O (O_SUB, SW), "sub.w", 0x1, 0x9, 0x3), + + {O (O_SUB, SL), AV_H8H, 6, "sub.l", {{RS32, RD32, E}}, {{0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_SUB, SL), AV_H8SX, 0, "sub.l", {{IMM3NZ_NS, RD32, E}}, {{0x1, 0xa, B31 | IMM3NZ, B31 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_SUB, SL), "sub.l", 0x3), + + {O (O_SUBS, SL), AV_H8, 2, "subs", {{KBIT, RDP, E}}, {{0x1, 0xB,KBIT, RDP, E}}}, + + {O (O_SUBX, SB), AV_H8, 2, "subx", {{IMM8, RD8, E}}, {{0xb, RD8, IMM8LIST, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{IMM8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0xb, IGNORE, IMM8LIST, E}}}, + {O (O_SUBX, SB), AV_H8, 2, "subx", {{RS8, RD8, E}}, {{0x1, 0xe, RS8, RD8, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDIND, E}}, {{0x7, 0xd, B30 | RDIND, IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RS8, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RDPOSTDEC, B31 | IGNORE, 0x1, 0xe, RS8, IGNORE, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RD8, E}}, {{0x7, 0xc, B30 | RSIND, IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RD8, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, B30 | B20 | IGNORE, 0x1, 0xe, IGNORE, RD8, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSIND, RDIND, E}}, {{PREFIX_0174, 0x6, 0x8, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, + {O (O_SUBX, SB), AV_H8SX, 0, "subx.b", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0176, 0x6, 0xc, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, + + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RD16, E}}, {{PREFIX_0151, 0x7, 0x9, 0x3, RD16, IMM16LIST, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{IMM16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0x9, 0x3, IGNORE, IMM16LIST, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RD16, E}}, {{PREFIX_0151, 0x1, 0x9, RS16, RD16, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDIND, E}}, {{0x7, 0xd, B31 | RDIND, B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RS16, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0x9, RS16, IGNORE, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RD16, E}}, {{0x7, 0xc, B31 | RSIND, B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RD16, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0x9, IGNORE, RD16, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSIND, RDIND, E}}, {{PREFIX_0154, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, + {O (O_SUBX, SW), AV_H8SX, 0, "subx.w", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0156, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, + + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RD32, E}}, {{PREFIX_0101, 0x7, 0xa, 0x3, RD32, IMM32LIST, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{IMM32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x7, 0xa, 0x3, IGNORE, IMM32LIST, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RD32, E}}, {{PREFIX_0101, 0x1, 0xa, B31 | RS32, B30 | RD32, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RDIND, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RS32, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RDPOSTDEC, B31 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | RS32, B30 | IGNORE, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RD32, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RD32, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, B30 | B20 | B01 | IGNORE, 0x1, 0xa, B31 | IGNORE, B30 | RD32, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSIND, RDIND, E}}, {{PREFIX_0104, 0x6, 0x9, B30 | RSIND, 0xd, 0x0, RDIND, 0x3, IGNORE, E}}}, + {O (O_SUBX, SL), AV_H8SX, 0, "subx.l", {{RSPOSTDEC, RDPOSTDEC, E}}, {{PREFIX_0106, 0x6, 0xd, B30 | RSPOSTDEC, 0xd, 0xa, RDPOSTDEC, 0x3, IGNORE, E}}}, + + {O (O_TRAPA, SB), AV_H8H, 2, "trapa", {{IMM2, E}}, {{0x5, 0x7, IMM2, IGNORE, E}}}, + {O (O_TAS, SB), AV_H8H, 2, "tas", {{RSIND, E}}, {{0x0, 0x1, 0xe, 0x0, 0x7, 0xb, B30 | RSIND, 0xc, E}}}, + + {O (O_XOR, SB), AV_H8, 2, "xor.b", {{IMM8, RD8, E}}, {{0xd, RD8, IMM8LIST, E}}}, + EXPAND_TWOOP_B (O (O_XOR, SB), "xor.b", 0xd, 0x1, 0x5, 0x5, 0), + + {O (O_XOR, SW), AV_H8, 2, "xor.w", {{RS16, RD16, E}}, {{0x6, 0x5, RS16, RD16, E}}}, + EXPAND_TWOOP_W (O (O_XOR, SW), "xor.w", 0x6, 0x5, 0x5), + + {O (O_XOR, SL), AV_H8H, 2, "xor.l", {{RS32, RD32, E}}, {{0x0, 0x1, 0xF, 0x0, 0x6, 0x5, B30 | RS32, B30 | RD32, E}}}, + EXPAND_TWOOP_L (O (O_XOR, SL), "xor.l", 0x5), + + {O (O_XORC, SB), AV_H8, 2, "xorc", {{IMM8, CCR | DST, E}}, {{0x0, 0x5, IMM8LIST, E}}}, + {O (O_XORC, SB), AV_H8S, 2, "xorc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x5, IMM8LIST, E}}}, + + {O (O_CLRMAC, SN), AV_H8S, 2, "clrmac", {{E}}, {{0x0, 0x1, 0xa, 0x0, E}}}, + {O (O_MAC, SW), AV_H8S, 2, "mac", {{RSPOSTINC, RDPOSTINC, E}}, {{0x0, 0x1, 0x6, 0x0, 0x6, 0xd, B30 | RSPOSTINC, B30 | RDPOSTINC, E}}}, + {O (O_LDMAC, SL), AV_H8S, 2, "ldmac", {{RS32, MD32, E}}, {{0x0, 0x3, MD32, RS32, E}}}, + {O (O_STMAC, SL), AV_H8S, 2, "stmac", {{MS32, RD32, E}}, {{0x0, 0x2, MS32, RD32, E}}}, + {O (O_LDM, SL), AV_H8H, 6, "ldm.l", {{RSPOSTINC, RD32, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0x7, B30 | RD32, E}}}, + {O (O_STM, SL), AV_H8H, 6, "stm.l", {{RS32, RDPREDEC, E}}, {{0x0, 0x1, DATA, 0x0, 0x6, 0xD, 0xF, B30 | RS32, E}}}, + {0, 0, 0, NULL, {{0, 0, 0}}, {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}} +}; +#else +extern const struct h8_opcode h8_opcodes[]; +#endif + diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h new file mode 100644 index 000000000000..8234664a6261 --- /dev/null +++ b/include/opcode/hppa.h @@ -0,0 +1,874 @@ +/* Table of opcodes for the PA-RISC. + Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, + 2001, 2002 + Free Software Foundation, Inc. + + Contributed by the Center for Software Science at the + University of Utah (pa-gdb-bugs@cs.utah.edu). + +This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + +GAS/GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GAS/GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS or GDB; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#if !defined(__STDC__) && !defined(const) +#define const +#endif + +/* + * Structure of an opcode table entry. + */ + +/* There are two kinds of delay slot nullification: normal which is + * controled by the nullification bit, and conditional, which depends + * on the direction of the branch and its success or failure. + * + * NONE is unfortunately #defined in the hiux system include files. + * #undef it away. + */ +#undef NONE +struct pa_opcode +{ + const char *name; + unsigned long int match; /* Bits that must be set... */ + unsigned long int mask; /* ... in these bits. */ + char *args; + enum pa_arch arch; + char flags; +}; + +/* Enable/disable strict syntax checking. Not currently used, but will + be necessary for PA2.0 support in the future. */ +#define FLAG_STRICT 0x1 + +/* + All hppa opcodes are 32 bits. + + The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing one character for each operand of + the instruction. Characters used as a prefix allow any second character to + be used without conflicting with the main operand characters. + + Bit positions in this description follow HP usage of lsb = 31, + "at" is lsb of field. + + In the args field, the following characters must match exactly: + + '+,() ' + + In the args field, the following characters are unused: + + ' " - / 34 6789:; ' + '@ C M [\] ' + '` e g } ' + + Here are all the characters: + + ' !"#$%&'()*+-,./0123456789:;<=>?' + '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_' + '`abcdefghijklmnopqrstuvwxyz{|}~ ' + +Kinds of operands: + x integer register field at 15. + b integer register field at 10. + t integer register field at 31. + a integer register field at 10 and 15 (for PERMH) + 5 5 bit immediate at 15. + s 2 bit space specifier at 17. + S 3 bit space specifier at 18. + V 5 bit immediate value at 31 + i 11 bit immediate value at 31 + j 14 bit immediate value at 31 + k 21 bit immediate value at 31 + l 16 bit immediate value at 31 (wide mode only, unusual encoding). + n nullification for branch instructions + N nullification for spop and copr instructions + w 12 bit branch displacement + W 17 bit branch displacement (PC relative) + X 22 bit branch displacement (PC relative) + z 17 bit branch displacement (just a number, not an address) + +Also these: + + . 2 bit shift amount at 25 + * 4 bit shift amount at 25 + p 5 bit shift count at 26 (to support the SHD instruction) encoded as + 31-p + ~ 6 bit shift count at 20,22:26 encoded as 63-~. + P 5 bit bit position at 26 + q 6 bit bit position at 20,22:26 + T 5 bit field length at 31 (encoded as 32-T) + % 6 bit field length at 23,27:31 (variable extract/deposit) + | 6 bit field length at 19,27:31 (fixed extract/deposit) + A 13 bit immediate at 18 (to support the BREAK instruction) + ^ like b, but describes a control register + ! sar (cr11) register + D 26 bit immediate at 31 (to support the DIAG instruction) + $ 9 bit immediate at 28 (to support POPBTS) + + v 3 bit Special Function Unit identifier at 25 + O 20 bit Special Function Unit operation split between 15 bits at 20 + and 5 bits at 31 + o 15 bit Special Function Unit operation at 20 + 2 22 bit Special Function Unit operation split between 17 bits at 20 + and 5 bits at 31 + 1 15 bit Special Function Unit operation split between 10 bits at 20 + and 5 bits at 31 + 0 10 bit Special Function Unit operation split between 5 bits at 20 + and 5 bits at 31 + u 3 bit coprocessor unit identifier at 25 + F Source Floating Point Operand Format Completer encoded 2 bits at 20 + I Source Floating Point Operand Format Completer encoded 1 bits at 20 + (for 0xe format FP instructions) + G Destination Floating Point Operand Format Completer encoded 2 bits at 18 + H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' + (very similar to 'F') + + r 5 bit immediate value at 31 (for the break instruction) + (very similar to V above, except the value is unsigned instead of + low_sign_ext) + R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions) + (same as r above, except the value is in a different location) + U 10 bit immediate value at 15 (for SSM, RSM on pa2.0) + Q 5 bit immediate value at 10 (a bit position specified in + the bb instruction. It's the same as r above, except the + value is in a different location) + B 5 bit immediate value at 10 (a bit position specified in + the bb instruction. Similar to Q, but 64 bit handling is + different. + Z %r1 -- implicit target of addil instruction. + L ,%r2 completer for new syntax branch + { Source format completer for fcnv + _ Destination format completer for fcnv + h cbit for fcmp + = gfx tests for ftest + d 14 bit offset for single precision FP long load/store. + # 14 bit offset for double precision FP load long/store. + J Yet another 14 bit offset for load/store with ma,mb completers. + K Yet another 14 bit offset for load/store with ma,mb completers. + y 16 bit offset for word aligned load/store (PA2.0 wide). + & 16 bit offset for dword aligned load/store (PA2.0 wide). + < 16 bit offset for load/store with ma,mb completers (PA2.0 wide). + > 16 bit offset for load/store with ma,mb completers (PA2.0 wide). + Y %sr0,%r31 -- implicit target of be,l instruction. + @ implicit immediate value of 0 + +Completer operands all have 'c' as the prefix: + + cx indexed load completer. + cX indexed load completer. Like cx, but emits a space after + in disassembler. + cm short load and store completer. + cM short load and store completer. Like cm, but emits a space + after in disassembler. + cq long load and store completer (like cm, but inserted into a + different location in the target instruction). + cs store bytes short completer. + cA store bytes short completer. Like cs, but emits a space + after in disassembler. + ce long load/store completer for LDW/STW with a different encoding than the + others + cc load cache control hint + cd load and clear cache control hint + cC store cache control hint + co ordered access + + cp branch link and push completer + cP branch pop completer + cl branch link completer + cg branch gate completer + + cw read/write completer for PROBE + cW wide completer for MFCTL + cL local processor completer for cache control + cZ System Control Completer (to support LPA, LHA, etc.) + + ci correction completer for DCOR + ca add completer + cy 32 bit add carry completer + cY 64 bit add carry completer + cv signed overflow trap completer + ct trap on condition completer for ADDI, SUB + cT trap on condition completer for UADDCM + cb 32 bit borrow completer for SUB + cB 64 bit borrow completer for SUB + + ch left/right half completer + cH signed/unsigned saturation completer + cS signed/unsigned completer at 21 + cz zero/sign extension completer. + c* permutation completer + +Condition operands all have '?' as the prefix: + + ?f Floating point compare conditions (encoded as 5 bits at 31) + + ?a add conditions + ?A 64 bit add conditions + ?@ add branch conditions followed by nullify + ?d non-negated add branch conditions + ?D negated add branch conditions + ?w wide mode non-negated add branch conditions + ?W wide mode negated add branch conditions + + ?s compare/subtract conditions + ?S 64 bit compare/subtract conditions + ?t non-negated compare and branch conditions + ?n 32 bit compare and branch conditions followed by nullify + ?N 64 bit compare and branch conditions followed by nullify + ?Q 64 bit compare and branch conditions for CMPIB instruction + + ?l logical conditions + ?L 64 bit logical conditions + + ?b branch on bit conditions + ?B 64 bit branch on bit conditions + + ?x shift/extract/deposit conditions + ?X 64 bit shift/extract/deposit conditions + ?y shift/extract/deposit conditions followed by nullify for conditional + branches + + ?u unit conditions + ?U 64 bit unit conditions + +Floating point registers all have 'f' as a prefix: + + ft target register at 31 + fT target register with L/R halves at 31 + fa operand 1 register at 10 + fA operand 1 register with L/R halves at 10 + fX Same as fA, except prints a space before register during disasm + fb operand 2 register at 15 + fB operand 2 register with L/R halves at 15 + fC operand 3 register with L/R halves at 16:18,21:23 + fe Like fT, but encoding is different. + fE Same as fe, except prints a space before register during disasm. + fx target register at 15 (only for PA 2.0 long format FLDD/FSTD). + +Float registers for fmpyadd and fmpysub: + + fi mult operand 1 register at 10 + fj mult operand 2 register at 15 + fk mult target register at 20 + fl add/sub operand register at 25 + fm add/sub target register at 31 + +*/ + + +#if 0 +/* List of characters not to put a space after. Note that + "," is included, as the "spopN" operations use literal + commas in their completer sections. */ +static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}"; +#endif + +/* The order of the opcodes in this table is significant: + + * The assembler requires that all instances of the same mnemonic must be + consecutive. If they aren't, the assembler will bomb at runtime. + + * The disassembler should not care about the order of the opcodes. */ + +static const struct pa_opcode pa_opcodes[] = +{ + +/* Pseudo-instructions. */ + +{ "ldi", 0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */ +{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */ + +{ "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT}, +{ "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT}, +{ "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ +{ "cmpb", 0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT}, +{ "cmpb", 0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT}, +{ "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ +{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT}, +{ "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0}, +{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT}, +{ "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ +{ "nop", 0x08000240, 0xffffffff, "", pa10, 0}, /* or 0,0,0 */ +{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10, 0}, /* or r,0,t */ +{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */ + +/* Loads and Stores for integer registers. */ + +{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ceJ(b),x", pa10, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ceK(b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT}, +{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,J(b)", pa10, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,K(b)", pa20, FLAG_STRICT}, +{ "stw", 0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, +{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "sth", 0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, +{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stb", 0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT}, +{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldwa", 0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(b),t", pa10, FLAG_STRICT}, +{ "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(b)", pa10, FLAG_STRICT}, +{ "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldda", 0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, +{ "ldda", 0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(b),t", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, +{ "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(b),t", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(b)", pa10, 0}, +{ "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0}, +{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT}, +{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(b)", pa20, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0}, +{ "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(b)", pa10, 0}, + +/* Immediate instructions. */ +{ "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0}, +{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10, 0}, +{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10, 0}, +{ "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10, 0}, +{ "addil", 0x28000000, 0xfc000000, "k,b", pa10, 0}, + +/* Branching instructions. */ +{ "b", 0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT}, +{ "b", 0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT}, +{ "b", 0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT}, +{ "b", 0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT}, +{ "b", 0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* b,l foo,r0 */ +{ "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10, 0}, +{ "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10, 0}, +{ "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10, 0}, +{ "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0}, +{ "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10, 0}, +{ "bve", 0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT}, +{ "bve", 0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT}, +{ "bve", 0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT}, +{ "bve", 0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "be", 0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT}, +{ "be", 0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT}, +{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0}, +{ "be", 0xe0000000, 0xfc000000, "nz(b)", pa10, 0}, +{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0}, +{ "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0}, +{ "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0}, +{ "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0}, +{ "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0}, +{ "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0}, +{ "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0}, +{ "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0}, +{ "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0}, +{ "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0}, +{ "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, +{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, +{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, +{ "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, +{ "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, +{ "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, +{ "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT}, +{ "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT}, + +/* Computation Instructions. */ + +{ "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT}, +{ "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT}, +{ "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT}, +{ "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT}, +{ "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT}, +{ "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT}, +{ "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT}, +{ "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10, 0}, +{ "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10, 0}, +{ "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT}, +{ "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT}, +{ "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT}, +{ "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT}, +{ "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT}, +{ "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT}, +{ "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT}, +{ "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10, 0}, +{ "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10, 0}, +{ "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT}, +{ "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT}, +{ "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, 0}, +{ "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT}, +{ "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT}, +{ "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0}, + +/* Subword Operation Instructions. */ + +{ "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, +{ "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT}, +{ "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT}, +{ "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, +{ "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT}, +{ "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, +{ "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, +{ "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, +{ "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, +{ "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT}, + + +/* Extract and Deposit Instructions. */ + +{ "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT}, +{ "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT}, +{ "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT}, +{ "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT}, +{ "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0}, +{ "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0}, +{ "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT}, +{ "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT}, +{ "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT}, +{ "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT}, +{ "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0}, +{ "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0}, +{ "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0}, +{ "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0}, +{ "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT}, +{ "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT}, +{ "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT}, +{ "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT}, +{ "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT}, +{ "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT}, +{ "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT}, +{ "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT}, +{ "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0}, +{ "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0}, +{ "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0}, +{ "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0}, +{ "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0}, +{ "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0}, +{ "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0}, +{ "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0}, + +/* System Control Instructions. */ + +{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10, 0}, +{ "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT}, +{ "rfi", 0x00000c00, 0xffffffff, "", pa10, 0}, +{ "rfir", 0x00000ca0, 0xffffffff, "", pa11, 0}, +{ "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, +{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10, 0}, +{ "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, +{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0}, +{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10, 0}, +{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0}, +{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0}, +{ "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT}, +{ "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT}, +{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10, 0}, +{ "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT}, +{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0}, +{ "sync", 0x00000400, 0xffffffff, "", pa10, 0}, +{ "syncdma", 0x00100400, 0xffffffff, "", pa10, 0}, +{ "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT}, +{ "probe", 0x04001180, 0xfc003fa0, "cw(b),x,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc003fa0, "cw(b),R,t", pa10, FLAG_STRICT}, +{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0}, +{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc003fc0, "cZx(b),t", pa10, 0}, +{ "lha", 0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, +{ "lha", 0x04001300, 0xfc003fc0, "cZx(b),t", pa10, 0}, +{ "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10, 0}, +{ "lci", 0x04001300, 0xfc003fe0, "x(b),t", pa10, 0}, +{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT}, +{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(b)", pa20, FLAG_STRICT}, +{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10, 0}, +{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0}, +{ "iitlba", 0x04000040, 0xfc001fff, "x,(b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10, 0}, +{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0}, +{ "iitlbp", 0x04000000, 0xfc001fff, "x,(b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "fic", 0x04000280, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "fice", 0x040002c0, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, +{ "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, +{ "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, + +/* These may be specific to certain versions of the PA. Joel claimed + they were 72000 (7200?) specific. However, I'm almost certain the + mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ +{ "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0}, +{ "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0}, +{ "tocen", 0x14403600, 0xffffffff, "", pa10, 0}, +{ "tocdis", 0x14401620, 0xffffffff, "", pa10, 0}, +{ "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0}, +{ "grshdw", 0x14400620, 0xffffffff, "", pa10, 0}, + +/* gfw and gfr are not in the HP PA 1.1 manual, but they are in either + the Timex FPU or the Mustang ERS (not sure which) manual. */ +{ "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0}, +{ "gfw", 0x04001680, 0xfc003fdf, "cZx(b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(b)", pa11, 0}, + +/* Floating Point Coprocessor Instructions. */ + +{ "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24000000, 0xfc001380, "cxccx(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001380, "cmcc5(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000000, "cJd(b),fe", pa20, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq#(b),fx", pa20, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000000, "cJfe,y(b)", pa20w, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000000, "cJfe,d(b)", pa20, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqfx,#(b)", pa20, FLAG_STRICT}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc001f80, "cXx(b),fT", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cXx(b),ft", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10, 0}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0}, +{ "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0}, +{ "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, +{ "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, +{ "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, +{ "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, +{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, +{ "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, +{ "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT}, +{ "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT}, +{ "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0}, +{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0}, +{ "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0}, +{ "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, +{ "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, +{ "ftest", 0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT}, +{ "ftest", 0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT}, +{ "ftest", 0x30002420, 0xffffffff, "", pa10, 0}, +{ "fid", 0x30000000, 0xffffffff, "", pa11, 0}, + +/* Performance Monitor Instructions. */ + +{ "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT}, +{ "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT}, + +/* Assist Instructions. */ + +{ "spop0", 0x10000000, 0xfc000600, "v,ON", pa10, 0}, +{ "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10, 0}, +{ "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0}, +{ "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0}, +{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucXx(b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucM5(b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucM5(b),t", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, 0}, +{ "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucM5(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucXx(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucM5(b),t", pa20, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(b)", pa10, FLAG_STRICT}, + +/* More pseudo instructions which must follow the main table. */ +{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, +{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, + +}; + +#define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) + +/* SKV 12/18/92. Added some denotations for various operands. */ + +#define PA_IMM11_AT_31 'i' +#define PA_IMM14_AT_31 'j' +#define PA_IMM21_AT_31 'k' +#define PA_DISP12 'w' +#define PA_DISP17 'W' + +#define N_HPPA_OPERAND_FORMATS 5 diff --git a/include/opcode/i370.h b/include/opcode/i370.h new file mode 100644 index 000000000000..e317f23642e6 --- /dev/null +++ b/include/opcode/i370.h @@ -0,0 +1,265 @@ +/* i370.h -- Header file for S/390 opcode table + Copyright 1994, 1995, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. + PowerPC version written by Ian Lance Taylor, Cygnus Support + Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef I370_H +#define I370_H + +/* The opcode table is an array of struct i370_opcode. */ +typedef union +{ + unsigned int i[2]; + unsigned short s[4]; + unsigned char b[8]; +} i370_insn_t; + +struct i370_opcode +{ + /* The opcode name. */ + const char *name; + + /* the length of the instruction */ + char len; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + i370_insn_t opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + i370_insn_t mask; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The defined values + are listed below. */ + unsigned long flags; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct i370_opcode i370_opcodes[]; +extern const int i370_num_opcodes; + +/* Values defined for the flags field of a struct i370_opcode. */ + +/* Opcode is defined for the original 360 architecture. */ +#define I370_OPCODE_360 (0x01) + +/* Opcode is defined for the 370 architecture. */ +#define I370_OPCODE_370 (0x02) + +/* Opcode is defined for the 370-XA architecture. */ +#define I370_OPCODE_370_XA (0x04) + +/* Opcode is defined for the ESA/370 architecture. */ +#define I370_OPCODE_ESA370 (0x08) + +/* Opcode is defined for the ESA/390 architecture. */ +#define I370_OPCODE_ESA390 (0x10) + +/* Opcode is defined for the ESA/390 w/ BFP facility. */ +#define I370_OPCODE_ESA390_BF (0x20) + +/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ +#define I370_OPCODE_ESA390_BS (0x40) + +/* Opcode is defined for the ESA/390 w/ checksum facility. */ +#define I370_OPCODE_ESA390_CK (0x80) + +/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ +#define I370_OPCODE_ESA390_CM (0x100) + +/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ +#define I370_OPCODE_ESA390_FX (0x200) + +/* Opcode is defined for the ESA/390 w/ HFP facility. */ +#define I370_OPCODE_ESA390_HX (0x400) + +/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ +#define I370_OPCODE_ESA390_IR (0x800) + +/* Opcode is defined for the ESA/390 w/ move-inverse facility. */ +#define I370_OPCODE_ESA390_MI (0x1000) + +/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ +#define I370_OPCODE_ESA390_PC (0x2000) + +/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ +#define I370_OPCODE_ESA390_PL (0x4000) + +/* Opcode is defined for the ESA/390 w/ square-root facility. */ +#define I370_OPCODE_ESA390_QR (0x8000) + +/* Opcode is defined for the ESA/390 w/ resume-program facility. */ +#define I370_OPCODE_ESA390_RP (0x10000) + +/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ +#define I370_OPCODE_ESA390_SA (0x20000) + +/* Opcode is defined for the ESA/390 w/ subspace group facility. */ +#define I370_OPCODE_ESA390_SG (0x40000) + +/* Opcode is defined for the ESA/390 w/ string facility. */ +#define I370_OPCODE_ESA390_SR (0x80000) + +/* Opcode is defined for the ESA/390 w/ trap facility. */ +#define I370_OPCODE_ESA390_TR (0x100000) + +#define I370_OPCODE_ESA390_SUPERSET (0x1fffff) + + +/* The operands table is an array of struct i370_operand. */ + +struct i370_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + i370_insn_t (*insert) + (i370_insn_t instruction, long op, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & I370_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + long (*extract) (i370_insn_t instruction, int *invalid); + + /* One bit syntax flags. */ + unsigned long flags; + + /* name -- handy for debugging, otherwise pointless */ + char * name; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the i370_opcodes table. */ + +extern const struct i370_operand i370_operands[]; + +/* Values defined for the flags field of a struct i370_operand. */ + +/* This operand should be wrapped in parentheses rather than + separated from the previous by a comma. This is used for S, RS and + SS form instructions which want their operands to look like + reg,displacement(basereg) */ +#define I370_OPERAND_SBASE (0x01) + +/* This operand is a base register. It may or may not appear next + to an index register, i.e. either of the two forms + reg,displacement(basereg) + reg,displacement(index,basereg) */ +#define I370_OPERAND_BASE (0x02) + +/* This pair of operands should be wrapped in parentheses rather than + separated from the last by a comma. This is used for the RX form + instructions which want their operands to look like + reg,displacement(index,basereg) */ +#define I370_OPERAND_INDEX (0x04) + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define I370_OPERAND_GPR (0x08) + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define I370_OPERAND_FPR (0x10) + +/* This operand is a displacement. */ +#define I370_OPERAND_RELATIVE (0x20) + +/* This operand is a length, such as that in SS form instructions. */ +#define I370_OPERAND_LENGTH (0x40) + +/* This operand is optional, and is zero if omitted. This is used for + the optional B2 field in the shift-left, shift-right instructions. The + assembler must count the number of operands remaining on the line, + and the number of operands remaining for the opcode, and decide + whether this operand is present or not. The disassembler should + print this operand out only if it is not zero. */ +#define I370_OPERAND_OPTIONAL (0x80) + + +/* Define some misc macros. We keep them with the operands table + for simplicity. The macro table is an array of struct i370_macro. */ + +struct i370_macro +{ + /* The macro name. */ + const char *name; + + /* The number of operands the macro takes. */ + unsigned int operands; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The values are the + same as those for the struct i370_opcode flags field. */ + unsigned long flags; + + /* A format string to turn the macro into a normal instruction. + Each %N in the string is replaced with operand number N (zero + based). */ + const char *format; +}; + +extern const struct i370_macro i370_macros[]; +extern const int i370_num_macros; + + +#endif /* I370_H */ diff --git a/include/opcode/i860.h b/include/opcode/i860.h new file mode 100644 index 000000000000..b46a5e5a4eb7 --- /dev/null +++ b/include/opcode/i860.h @@ -0,0 +1,507 @@ +/* Table of opcodes for the i860. + Copyright 1989, 1991, 2000, 2003 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. + +GAS/GDB is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GAS/GDB is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS or GDB; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* Structure of an opcode table entry. */ +struct i860_opcode +{ + /* The opcode name. */ + const char *name; + + /* Bits that must be set. */ + unsigned long match; + + /* Bits that must not be set. */ + unsigned long lose; + + const char *args; + + /* Nonzero if this is a possible expand-instruction. */ + char expand; +}; + + +enum expand_type +{ + E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY +}; + + +/* All i860 opcodes are 32 bits, except for the pseudo-instructions + and the operations utilizing a 32-bit address expression, an + unsigned 32-bit constant, or a signed 32-bit constant. + These opcodes are expanded into a two-instruction sequence for + any situation where the immediate operand does not fit in 32 bits. + In the case of the add and subtract operations the expansion is + to a three-instruction sequence (ex: orh, or, adds). In cases + where the address is to be relocated, the instruction is + expanded to handle the worse case, this could be optimized at + the final link if the actual address were known. + + The pseudoinstructions are: mov, fmov, pmov, nop, and fnop. + These instructions are implemented as a one or two instruction + sequence of other operations. + + The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing one character + for each operand of the instruction. + +Kinds of operands: + # Number used by optimizer. It is ignored. + 1 src1 integer register. + 2 src2 integer register. + d dest register. + c ctrlreg control register. + i 16 bit immediate. + I 16 bit immediate, aligned 2^0. (ld.b) + J 16 bit immediate, aligned 2^1. (ld.s) + K 16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l) + L 16 bit immediate, aligned 2^3. ({p}fld.d, fst.d) + M 16 bit immediate, aligned 2^4. ({p}fld.q, fst.q) + 5 5 bit immediate. + l lbroff 26 bit PC relative immediate. + r sbroff 16 bit PC relative immediate. + s split 16 bit immediate. + S split 16 bit immediate, aligned 2^0. (st.b) + T split 16 bit immediate, aligned 2^1. (st.s) + U split 16 bit immediate, aligned 2^2. (st.l) + e src1 floating point register. + f src2 floating point register. + g dest floating point register. */ + + +/* The order of the opcodes in this table is significant. The assembler + requires that all instances of the same mnemonic must be consecutive. + If they aren't, the assembler will not function properly. + + The order of opcodes does not affect the disassembler. */ + +static const struct i860_opcode i860_opcodes[] = +{ +/* REG-Format Instructions. */ +{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */ +{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */ +{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */ +{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */ +{ "ld.s", 0x14000000, 0xe8000001, "J(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */ +{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */ +{ "ld.l", 0x14000001, 0xe8000000, "K(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */ + +{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */ +{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */ +{ "st.s", 0x1c000000, 0xe0000001, "1,T(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */ +{ "st.l", 0x1c000001, 0xe0000000, "1,U(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */ + +{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */ + +{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */ +{ "fld.l", 0x24000002, 0xd8000001, "K(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */ +{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */ +{ "fld.l", 0x24000003, 0xd8000000, "K(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */ +{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */ +{ "fld.d", 0x24000000, 0xd8000007, "L(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */ +{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */ +{ "fld.d", 0x24000001, 0xd8000006, "L(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */ +{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */ +{ "fld.q", 0x24000004, 0xd8000003, "M(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */ +{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */ +{ "fld.q", 0x24000005, 0xd8000002, "M(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */ + +{ "pfld.l", 0x60000002, 0x9c000001, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */ +{ "pfld.l", 0x64000002, 0x98000001, "K(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */ +{ "pfld.l", 0x60000003, 0x9c000000, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */ +{ "pfld.l", 0x64000003, 0x98000000, "K(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */ +{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */ +{ "pfld.d", 0x64000000, 0x98000007, "L(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */ +{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */ +{ "pfld.d", 0x64000001, 0x98000006, "L(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */ +{ "pfld.q", 0x60000004, 0x9c000003, "1(2),g", XP_ONLY }, /* pfld.q isrc1(isrc2),fdest */ +{ "pfld.q", 0x64000004, 0x98000003, "L(2),g", XP_ONLY }, /* pfld.q #const(isrc2),fdest */ +{ "pfld.q", 0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY }, /* pfld.q isrc1(isrc2)++,fdest */ +{ "pfld.q", 0x64000005, 0x98000002, "L(2)++,g", XP_ONLY }, /* pfld.q #const(isrc2)++,fdest */ + +{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */ +{ "fst.l", 0x2c000002, 0xd0000001, "g,K(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */ +{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */ +{ "fst.l", 0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */ +{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ +{ "fst.d", 0x2c000000, 0xd0000007, "g,L(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ +{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ +{ "fst.d", 0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ +{ "fst.q", 0x28000004, 0xd4000003, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ +{ "fst.q", 0x2c000004, 0xd0000003, "g,M(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ +{ "fst.q", 0x28000005, 0xd4000002, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ +{ "fst.q", 0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ + +{ "pst.d", 0x3c000000, 0xc0000007, "g,L(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */ +{ "pst.d", 0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */ + +{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */ +{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */ +{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */ +{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */ +{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */ +{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */ +{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */ +{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */ + +{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */ +{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */ +{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */ +{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */ +{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */ +{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */ +{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */ + +{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */ +{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */ +{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */ +{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */ + +{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */ + +{ "flush", 0x34000004, 0xc81f0003, "L(2)", E_ADDR }, /* flush #const(isrc2) */ +{ "flush", 0x34000005, 0xc81f0002, "L(2)++", E_ADDR }, /* flush #const(isrc2)++ */ + +{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */ +{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */ +{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */ +{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */ +{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */ +{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */ +{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */ +{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */ +{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */ +{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */ +{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */ +{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */ + +{ "bte", 0x58000000, 0xa4000000, "1,2,r", 0 }, /* bte isrc1s,isrc2,sbroff */ +{ "bte", 0x5c000000, 0xa0000000, "5,2,r", 0 }, /* bte #const5,isrc2,sbroff */ +{ "btne", 0x50000000, 0xac000000, "1,2,r", 0 }, /* btne isrc1s,isrc2,sbroff */ +{ "btne", 0x54000000, 0xa8000000, "5,2,r", 0 }, /* btne #const5,isrc2,sbroff */ +{ "bla", 0xb4000000, 0x48000000, "1,2,r", E_DELAY }, /* bla isrc1s,isrc2,sbroff */ +{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */ + +/* Core Escape Instruction Format */ +{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */ +{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */ +{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */ +{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */ +{ "ldio.l", 0x4c000408, 0xb00003f7, "2,d", XP_ONLY }, /* ldio.l isrc2,idest */ +{ "ldio.s", 0x4c000208, 0xb00005f7, "2,d", XP_ONLY }, /* ldio.s isrc2,idest */ +{ "ldio.b", 0x4c000008, 0xb00007f7, "2,d", XP_ONLY }, /* ldio.b isrc2,idest */ +{ "stio.l", 0x4c000409, 0xb00003f6, "1,2", XP_ONLY }, /* stio.l isrc1ni,isrc2 */ +{ "stio.s", 0x4c000209, 0xb00005f6, "1,2", XP_ONLY }, /* stio.s isrc1ni,isrc2 */ +{ "stio.b", 0x4c000009, 0xb00007f6, "1,2", XP_ONLY }, /* stio.b isrc1ni,isrc2 */ +{ "ldint.l", 0x4c00040a, 0xb00003f5, "2,d", XP_ONLY }, /* ldint.l isrc2,idest */ +{ "ldint.s", 0x4c00020a, 0xb00005f5, "2,d", XP_ONLY }, /* ldint.s isrc2,idest */ +{ "ldint.b", 0x4c00000a, 0xb00007f5, "2,d", XP_ONLY }, /* ldint.b isrc2,idest */ +{ "scyc.b", 0x4c00000b, 0xb00007f4, "2", XP_ONLY }, /* scyc.b isrc2 */ + +/* CTRL-Format Instructions */ +{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */ +{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */ +{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */ +{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */ +{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */ +{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */ + +/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest. */ +{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 }, +{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 }, +{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 }, +{ "r2pt.ss", 0x48000401, 0xb40001fe, "e,f,g", 0 }, +{ "r2pt.sd", 0x48000481, 0xb400017e, "e,f,g", 0 }, +{ "r2pt.dd", 0x48000581, 0xb400007e, "e,f,g", 0 }, +{ "r2ap1.ss", 0x48000402, 0xb40001fd, "e,f,g", 0 }, +{ "r2ap1.sd", 0x48000482, 0xb400017d, "e,f,g", 0 }, +{ "r2ap1.dd", 0x48000582, 0xb400007d, "e,f,g", 0 }, +{ "r2apt.ss", 0x48000403, 0xb40001fc, "e,f,g", 0 }, +{ "r2apt.sd", 0x48000483, 0xb400017c, "e,f,g", 0 }, +{ "r2apt.dd", 0x48000583, 0xb400007c, "e,f,g", 0 }, +{ "i2p1.ss", 0x48000404, 0xb40001fb, "e,f,g", 0 }, +{ "i2p1.sd", 0x48000484, 0xb400017b, "e,f,g", 0 }, +{ "i2p1.dd", 0x48000584, 0xb400007b, "e,f,g", 0 }, +{ "i2pt.ss", 0x48000405, 0xb40001fa, "e,f,g", 0 }, +{ "i2pt.sd", 0x48000485, 0xb400017a, "e,f,g", 0 }, +{ "i2pt.dd", 0x48000585, 0xb400007a, "e,f,g", 0 }, +{ "i2ap1.ss", 0x48000406, 0xb40001f9, "e,f,g", 0 }, +{ "i2ap1.sd", 0x48000486, 0xb4000179, "e,f,g", 0 }, +{ "i2ap1.dd", 0x48000586, 0xb4000079, "e,f,g", 0 }, +{ "i2apt.ss", 0x48000407, 0xb40001f8, "e,f,g", 0 }, +{ "i2apt.sd", 0x48000487, 0xb4000178, "e,f,g", 0 }, +{ "i2apt.dd", 0x48000587, 0xb4000078, "e,f,g", 0 }, +{ "rat1p2.ss", 0x48000408, 0xb40001f7, "e,f,g", 0 }, +{ "rat1p2.sd", 0x48000488, 0xb4000177, "e,f,g", 0 }, +{ "rat1p2.dd", 0x48000588, 0xb4000077, "e,f,g", 0 }, +{ "m12apm.ss", 0x48000409, 0xb40001f6, "e,f,g", 0 }, +{ "m12apm.sd", 0x48000489, 0xb4000176, "e,f,g", 0 }, +{ "m12apm.dd", 0x48000589, 0xb4000076, "e,f,g", 0 }, +{ "ra1p2.ss", 0x4800040a, 0xb40001f5, "e,f,g", 0 }, +{ "ra1p2.sd", 0x4800048a, 0xb4000175, "e,f,g", 0 }, +{ "ra1p2.dd", 0x4800058a, 0xb4000075, "e,f,g", 0 }, +{ "m12ttpa.ss", 0x4800040b, 0xb40001f4, "e,f,g", 0 }, +{ "m12ttpa.sd", 0x4800048b, 0xb4000174, "e,f,g", 0 }, +{ "m12ttpa.dd", 0x4800058b, 0xb4000074, "e,f,g", 0 }, +{ "iat1p2.ss", 0x4800040c, 0xb40001f3, "e,f,g", 0 }, +{ "iat1p2.sd", 0x4800048c, 0xb4000173, "e,f,g", 0 }, +{ "iat1p2.dd", 0x4800058c, 0xb4000073, "e,f,g", 0 }, +{ "m12tpm.ss", 0x4800040d, 0xb40001f2, "e,f,g", 0 }, +{ "m12tpm.sd", 0x4800048d, 0xb4000172, "e,f,g", 0 }, +{ "m12tpm.dd", 0x4800058d, 0xb4000072, "e,f,g", 0 }, +{ "ia1p2.ss", 0x4800040e, 0xb40001f1, "e,f,g", 0 }, +{ "ia1p2.sd", 0x4800048e, 0xb4000171, "e,f,g", 0 }, +{ "ia1p2.dd", 0x4800058e, 0xb4000071, "e,f,g", 0 }, +{ "m12tpa.ss", 0x4800040f, 0xb40001f0, "e,f,g", 0 }, +{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 }, +{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest. */ +{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 }, +{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 }, +{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 }, +{ "r2st.ss", 0x48000411, 0xb40001ee, "e,f,g", 0 }, +{ "r2st.sd", 0x48000491, 0xb400016e, "e,f,g", 0 }, +{ "r2st.dd", 0x48000591, 0xb400006e, "e,f,g", 0 }, +{ "r2as1.ss", 0x48000412, 0xb40001ed, "e,f,g", 0 }, +{ "r2as1.sd", 0x48000492, 0xb400016d, "e,f,g", 0 }, +{ "r2as1.dd", 0x48000592, 0xb400006d, "e,f,g", 0 }, +{ "r2ast.ss", 0x48000413, 0xb40001ec, "e,f,g", 0 }, +{ "r2ast.sd", 0x48000493, 0xb400016c, "e,f,g", 0 }, +{ "r2ast.dd", 0x48000593, 0xb400006c, "e,f,g", 0 }, +{ "i2s1.ss", 0x48000414, 0xb40001eb, "e,f,g", 0 }, +{ "i2s1.sd", 0x48000494, 0xb400016b, "e,f,g", 0 }, +{ "i2s1.dd", 0x48000594, 0xb400006b, "e,f,g", 0 }, +{ "i2st.ss", 0x48000415, 0xb40001ea, "e,f,g", 0 }, +{ "i2st.sd", 0x48000495, 0xb400016a, "e,f,g", 0 }, +{ "i2st.dd", 0x48000595, 0xb400006a, "e,f,g", 0 }, +{ "i2as1.ss", 0x48000416, 0xb40001e9, "e,f,g", 0 }, +{ "i2as1.sd", 0x48000496, 0xb4000169, "e,f,g", 0 }, +{ "i2as1.dd", 0x48000596, 0xb4000069, "e,f,g", 0 }, +{ "i2ast.ss", 0x48000417, 0xb40001e8, "e,f,g", 0 }, +{ "i2ast.sd", 0x48000497, 0xb4000168, "e,f,g", 0 }, +{ "i2ast.dd", 0x48000597, 0xb4000068, "e,f,g", 0 }, +{ "rat1s2.ss", 0x48000418, 0xb40001e7, "e,f,g", 0 }, +{ "rat1s2.sd", 0x48000498, 0xb4000167, "e,f,g", 0 }, +{ "rat1s2.dd", 0x48000598, 0xb4000067, "e,f,g", 0 }, +{ "m12asm.ss", 0x48000419, 0xb40001e6, "e,f,g", 0 }, +{ "m12asm.sd", 0x48000499, 0xb4000166, "e,f,g", 0 }, +{ "m12asm.dd", 0x48000599, 0xb4000066, "e,f,g", 0 }, +{ "ra1s2.ss", 0x4800041a, 0xb40001e5, "e,f,g", 0 }, +{ "ra1s2.sd", 0x4800049a, 0xb4000165, "e,f,g", 0 }, +{ "ra1s2.dd", 0x4800059a, 0xb4000065, "e,f,g", 0 }, +{ "m12ttsa.ss", 0x4800041b, 0xb40001e4, "e,f,g", 0 }, +{ "m12ttsa.sd", 0x4800049b, 0xb4000164, "e,f,g", 0 }, +{ "m12ttsa.dd", 0x4800059b, 0xb4000064, "e,f,g", 0 }, +{ "iat1s2.ss", 0x4800041c, 0xb40001e3, "e,f,g", 0 }, +{ "iat1s2.sd", 0x4800049c, 0xb4000163, "e,f,g", 0 }, +{ "iat1s2.dd", 0x4800059c, 0xb4000063, "e,f,g", 0 }, +{ "m12tsm.ss", 0x4800041d, 0xb40001e2, "e,f,g", 0 }, +{ "m12tsm.sd", 0x4800049d, 0xb4000162, "e,f,g", 0 }, +{ "m12tsm.dd", 0x4800059d, 0xb4000062, "e,f,g", 0 }, +{ "ia1s2.ss", 0x4800041e, 0xb40001e1, "e,f,g", 0 }, +{ "ia1s2.sd", 0x4800049e, 0xb4000161, "e,f,g", 0 }, +{ "ia1s2.dd", 0x4800059e, 0xb4000061, "e,f,g", 0 }, +{ "m12tsa.ss", 0x4800041f, 0xb40001e0, "e,f,g", 0 }, +{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 }, +{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest. */ +{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 }, +{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 }, +{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 }, +{ "mr2pt.ss", 0x48000001, 0xb40005fe, "e,f,g", 0 }, +{ "mr2pt.sd", 0x48000081, 0xb400057e, "e,f,g", 0 }, +{ "mr2pt.dd", 0x48000181, 0xb400047e, "e,f,g", 0 }, +{ "mr2mp1.ss", 0x48000002, 0xb40005fd, "e,f,g", 0 }, +{ "mr2mp1.sd", 0x48000082, 0xb400057d, "e,f,g", 0 }, +{ "mr2mp1.dd", 0x48000182, 0xb400047d, "e,f,g", 0 }, +{ "mr2mpt.ss", 0x48000003, 0xb40005fc, "e,f,g", 0 }, +{ "mr2mpt.sd", 0x48000083, 0xb400057c, "e,f,g", 0 }, +{ "mr2mpt.dd", 0x48000183, 0xb400047c, "e,f,g", 0 }, +{ "mi2p1.ss", 0x48000004, 0xb40005fb, "e,f,g", 0 }, +{ "mi2p1.sd", 0x48000084, 0xb400057b, "e,f,g", 0 }, +{ "mi2p1.dd", 0x48000184, 0xb400047b, "e,f,g", 0 }, +{ "mi2pt.ss", 0x48000005, 0xb40005fa, "e,f,g", 0 }, +{ "mi2pt.sd", 0x48000085, 0xb400057a, "e,f,g", 0 }, +{ "mi2pt.dd", 0x48000185, 0xb400047a, "e,f,g", 0 }, +{ "mi2mp1.ss", 0x48000006, 0xb40005f9, "e,f,g", 0 }, +{ "mi2mp1.sd", 0x48000086, 0xb4000579, "e,f,g", 0 }, +{ "mi2mp1.dd", 0x48000186, 0xb4000479, "e,f,g", 0 }, +{ "mi2mpt.ss", 0x48000007, 0xb40005f8, "e,f,g", 0 }, +{ "mi2mpt.sd", 0x48000087, 0xb4000578, "e,f,g", 0 }, +{ "mi2mpt.dd", 0x48000187, 0xb4000478, "e,f,g", 0 }, +{ "mrmt1p2.ss", 0x48000008, 0xb40005f7, "e,f,g", 0 }, +{ "mrmt1p2.sd", 0x48000088, 0xb4000577, "e,f,g", 0 }, +{ "mrmt1p2.dd", 0x48000188, 0xb4000477, "e,f,g", 0 }, +{ "mm12mpm.ss", 0x48000009, 0xb40005f6, "e,f,g", 0 }, +{ "mm12mpm.sd", 0x48000089, 0xb4000576, "e,f,g", 0 }, +{ "mm12mpm.dd", 0x48000189, 0xb4000476, "e,f,g", 0 }, +{ "mrm1p2.ss", 0x4800000a, 0xb40005f5, "e,f,g", 0 }, +{ "mrm1p2.sd", 0x4800008a, 0xb4000575, "e,f,g", 0 }, +{ "mrm1p2.dd", 0x4800018a, 0xb4000475, "e,f,g", 0 }, +{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 }, +{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 }, +{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 }, +{ "mimt1p2.ss", 0x4800000c, 0xb40005f3, "e,f,g", 0 }, +{ "mimt1p2.sd", 0x4800008c, 0xb4000573, "e,f,g", 0 }, +{ "mimt1p2.dd", 0x4800018c, 0xb4000473, "e,f,g", 0 }, +{ "mm12tpm.ss", 0x4800000d, 0xb40005f2, "e,f,g", 0 }, +{ "mm12tpm.sd", 0x4800008d, 0xb4000572, "e,f,g", 0 }, +{ "mm12tpm.dd", 0x4800018d, 0xb4000472, "e,f,g", 0 }, +{ "mim1p2.ss", 0x4800000e, 0xb40005f1, "e,f,g", 0 }, +{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 }, +{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest. */ +{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 }, +{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 }, +{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 }, +{ "mr2st.ss", 0x48000011, 0xb40005ee, "e,f,g", 0 }, +{ "mr2st.sd", 0x48000091, 0xb400056e, "e,f,g", 0 }, +{ "mr2st.dd", 0x48000191, 0xb400046e, "e,f,g", 0 }, +{ "mr2ms1.ss", 0x48000012, 0xb40005ed, "e,f,g", 0 }, +{ "mr2ms1.sd", 0x48000092, 0xb400056d, "e,f,g", 0 }, +{ "mr2ms1.dd", 0x48000192, 0xb400046d, "e,f,g", 0 }, +{ "mr2mst.ss", 0x48000013, 0xb40005ec, "e,f,g", 0 }, +{ "mr2mst.sd", 0x48000093, 0xb400056c, "e,f,g", 0 }, +{ "mr2mst.dd", 0x48000193, 0xb400046c, "e,f,g", 0 }, +{ "mi2s1.ss", 0x48000014, 0xb40005eb, "e,f,g", 0 }, +{ "mi2s1.sd", 0x48000094, 0xb400056b, "e,f,g", 0 }, +{ "mi2s1.dd", 0x48000194, 0xb400046b, "e,f,g", 0 }, +{ "mi2st.ss", 0x48000015, 0xb40005ea, "e,f,g", 0 }, +{ "mi2st.sd", 0x48000095, 0xb400056a, "e,f,g", 0 }, +{ "mi2st.dd", 0x48000195, 0xb400046a, "e,f,g", 0 }, +{ "mi2ms1.ss", 0x48000016, 0xb40005e9, "e,f,g", 0 }, +{ "mi2ms1.sd", 0x48000096, 0xb4000569, "e,f,g", 0 }, +{ "mi2ms1.dd", 0x48000196, 0xb4000469, "e,f,g", 0 }, +{ "mi2mst.ss", 0x48000017, 0xb40005e8, "e,f,g", 0 }, +{ "mi2mst.sd", 0x48000097, 0xb4000568, "e,f,g", 0 }, +{ "mi2mst.dd", 0x48000197, 0xb4000468, "e,f,g", 0 }, +{ "mrmt1s2.ss", 0x48000018, 0xb40005e7, "e,f,g", 0 }, +{ "mrmt1s2.sd", 0x48000098, 0xb4000567, "e,f,g", 0 }, +{ "mrmt1s2.dd", 0x48000198, 0xb4000467, "e,f,g", 0 }, +{ "mm12msm.ss", 0x48000019, 0xb40005e6, "e,f,g", 0 }, +{ "mm12msm.sd", 0x48000099, 0xb4000566, "e,f,g", 0 }, +{ "mm12msm.dd", 0x48000199, 0xb4000466, "e,f,g", 0 }, +{ "mrm1s2.ss", 0x4800001a, 0xb40005e5, "e,f,g", 0 }, +{ "mrm1s2.sd", 0x4800009a, 0xb4000565, "e,f,g", 0 }, +{ "mrm1s2.dd", 0x4800019a, 0xb4000465, "e,f,g", 0 }, +{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 }, +{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 }, +{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 }, +{ "mimt1s2.ss", 0x4800001c, 0xb40005e3, "e,f,g", 0 }, +{ "mimt1s2.sd", 0x4800009c, 0xb4000563, "e,f,g", 0 }, +{ "mimt1s2.dd", 0x4800019c, 0xb4000463, "e,f,g", 0 }, +{ "mm12tsm.ss", 0x4800001d, 0xb40005e2, "e,f,g", 0 }, +{ "mm12tsm.sd", 0x4800009d, 0xb4000562, "e,f,g", 0 }, +{ "mm12tsm.dd", 0x4800019d, 0xb4000462, "e,f,g", 0 }, +{ "mim1s2.ss", 0x4800001e, 0xb40005e1, "e,f,g", 0 }, +{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 }, +{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 }, + +{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.ss", 0x48000420, 0xb40001df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.sd", 0x480004a0, 0xb400015f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.dd", 0x480005a0, 0xb400005f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul3.dd", 0x480005a4, 0xb400005b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */ +{ "fmlow.dd", 0x480001a1, 0xb400045e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */ +{ "frcp.ss", 0x48000022, 0xb40005dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frcp.sd", 0x480000a2, 0xb400055d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frcp.dd", 0x480001a2, 0xb400045d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frsqr.ss", 0x48000023, 0xb40005dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "frsqr.sd", 0x480000a3, 0xb400055c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "frsqr.dd", 0x480001a3, 0xb400045c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "fadd.ss", 0x48000030, 0xb40005cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "fadd.sd", 0x480000b0, 0xb400054f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "fadd.dd", 0x480001b0, 0xb400044f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.ss", 0x48000430, 0xb40001cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.sd", 0x480004b0, 0xb400014f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.dd", 0x480005b0, 0xb400004f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "fsub.ss", 0x48000031, 0xb40005ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "fsub.sd", 0x480000b1, 0xb400054e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "fsub.dd", 0x480001b1, 0xb400044e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.ss", 0x48000431, 0xb40001ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.sd", 0x480004b1, 0xb400014e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.dd", 0x480005b1, 0xb400004e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "fix.sd", 0x480000b2, 0xb400054d, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "fix.dd", 0x480001b2, 0xb400044d, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "pfix.sd", 0x480004b2, 0xb400014d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "pfix.dd", 0x480005b2, 0xb400004d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "famov.ss", 0x48000033, 0xb40005cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.dd", 0x480001b3, 0xb400044c, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "pfamov.ss", 0x48000433, 0xb40001cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +/* Opcode pfgt has R bit cleared; pfle has R bit set. */ +{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +/* Opcode pfgt has R bit cleared; pfle has R bit set. */ +{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ +{ "pfeq.dd", 0x48000535, 0xb40000ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ +{ "ftrunc.sd", 0x480000ba, 0xb4000545, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "ftrunc.dd", 0x480001ba, 0xb4000445, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "pftrunc.sd", 0x480004ba, 0xb4000145, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "pftrunc.dd", 0x480005ba, 0xb4000045, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "fxfr", 0x48000040, 0xb40005bf, "e,d", 0 }, /* fxfr fsrc1,idest */ +{ "fiadd.ss", 0x48000049, 0xb40005b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ +{ "fiadd.dd", 0x480001c9, 0xb4000436, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ +{ "pfiadd.ss", 0x48000449, 0xb40001b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ +{ "pfiadd.dd", 0x480005c9, 0xb4000036, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ +{ "fisub.ss", 0x4800004d, 0xb40005b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ +{ "fisub.dd", 0x480001cd, 0xb4000432, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ +{ "pfisub.ss", 0x4800044d, 0xb40001b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ +{ "pfisub.dd", 0x480005cd, 0xb4000032, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ +{ "fzchkl", 0x480001d7, 0xb4000428, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */ +{ "pfzchkl", 0x480005d7, 0xb4000028, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */ +{ "fzchks", 0x480001df, 0xb4000420, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */ +{ "pfzchks", 0x480005df, 0xb4000020, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */ +{ "faddp", 0x480001d0, 0xb400042f, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */ +{ "pfaddp", 0x480005d0, 0xb400002f, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */ +{ "faddz", 0x480001d1, 0xb400042e, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */ +{ "pfaddz", 0x480005d1, 0xb400002e, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */ +{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */ +{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */ + +/* Floating point pseudo-instructions. */ +{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */ +{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */ +{ "fmov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.sd fsrc1,fdest */ +{ "fmov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.ds fsrc1,fdest */ +{ "pfmov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.ds fsrc1,fdest */ +{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */ +{ 0, 0, 0, 0, 0 }, + +}; + +#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0])) + + diff --git a/include/opcode/i960.h b/include/opcode/i960.h new file mode 100644 index 000000000000..33b56e635619 --- /dev/null +++ b/include/opcode/i960.h @@ -0,0 +1,525 @@ +/* Basic 80960 instruction formats. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + The 'COJ' instructions are actually COBR instructions with the 'b' in + the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if necessary: + if the displacement will not fit in 13 bits, the assembler will replace them + with the corresponding compare and branch instructions. + + All of the 'MEMn' instructions are the same format; the 'n' in the name + indicates the default index scale factor (the size of the datum operated on). + + The FBRA formats are not actually an instruction format. They are the + "convenience directives" for branching on floating-point comparisons, + each of which generates 2 instructions (a 'bno' and one other branch). + + The CALLJ format is not actually an instruction format. It indicates that + the instruction generated (a CTRL-format 'call') should have its relocation + specially flagged for link-time replacement with a 'bal' or 'calls' if + appropriate. */ + +#define CTRL 0 +#define COBR 1 +#define COJ 2 +#define REG 3 +#define MEM1 4 +#define MEM2 5 +#define MEM4 6 +#define MEM8 7 +#define MEM12 8 +#define MEM16 9 +#define FBRA 10 +#define CALLJ 11 + +/* Masks for the mode bits in REG format instructions */ +#define M1 0x0800 +#define M2 0x1000 +#define M3 0x2000 + +/* Generate the 12-bit opcode for a REG format instruction by placing the + * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits + * 7-10. + */ + +#define REG_OPC(opc) ((opc & 0xff0) << 20) | ((opc & 0xf) << 7) + +/* Generate a template for a REG format instruction: place the opcode bits + * in the appropriate fields and OR in mode bits for the operands that will not + * be used. I.e., + * set m1=1, if src1 will not be used + * set m2=1, if src2 will not be used + * set m3=1, if dst will not be used + * + * Setting the "unused" mode bits to 1 speeds up instruction execution(!). + * The information is also useful to us because some 1-operand REG instructions + * use the src1 field, others the dst field; and some 2-operand REG instructions + * use src1/src2, others src1/dst. The set mode bits enable us to distinguish. + */ +#define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */ +#define R_1(opc) ( REG_OPC(opc) | M2 | M3 ) /* 1 operand: src1 */ +#define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */ +#define R_2(opc) ( REG_OPC(opc) | M3 ) /* 2 ops: src1/src2 */ +#define R_2D(opc) ( REG_OPC(opc) | M2 ) /* 2 ops: src1/dst */ +#define R_3(opc) ( REG_OPC(opc) ) /* 3 operands */ + +/* DESCRIPTOR BYTES FOR REGISTER OPERANDS + * + * Interpret names as follows: + * R: global or local register only + * RS: global, local, or (if target allows) special-function register only + * RL: global or local register, or integer literal + * RSL: global, local, or (if target allows) special-function register; + * or integer literal + * F: global, local, or floating-point register + * FL: global, local, or floating-point register; or literal (including + * floating point) + * + * A number appended to a name indicates that registers must be aligned, + * as follows: + * 2: register number must be multiple of 2 + * 4: register number must be multiple of 4 + */ + +#define SFR 0x10 /* Mask for the "sfr-OK" bit */ +#define LIT 0x08 /* Mask for the "literal-OK" bit */ +#define FP 0x04 /* Mask for "floating-point-OK" bit */ + +/* This macro ors the bits together. Note that 'align' is a mask + * for the low 0, 1, or 2 bits of the register number, as appropriate. + */ +#define OP(align,lit,fp,sfr) ( align | lit | fp | sfr ) + +#define R OP( 0, 0, 0, 0 ) +#define RS OP( 0, 0, 0, SFR ) +#define RL OP( 0, LIT, 0, 0 ) +#define RSL OP( 0, LIT, 0, SFR ) +#define F OP( 0, 0, FP, 0 ) +#define FL OP( 0, LIT, FP, 0 ) +#define R2 OP( 1, 0, 0, 0 ) +#define RL2 OP( 1, LIT, 0, 0 ) +#define F2 OP( 1, 0, FP, 0 ) +#define FL2 OP( 1, LIT, FP, 0 ) +#define R4 OP( 3, 0, 0, 0 ) +#define RL4 OP( 3, LIT, 0, 0 ) +#define F4 OP( 3, 0, FP, 0 ) +#define FL4 OP( 3, LIT, FP, 0 ) + +#define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */ + +/* Macros to extract info from the register operand descriptor byte 'od'. + */ +#define SFR_OK(od) (od & SFR) /* TRUE if sfr operand allowed */ +#define LIT_OK(od) (od & LIT) /* TRUE if literal operand allowed */ +#define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */ +#define REG_ALIGN(od,n) ((od & 0x3 & n) == 0) + /* TRUE if reg #n is properly aligned */ +#define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/ + +/* Description of a single i80960 instruction */ +struct i960_opcode { + long opcode; /* 32 bits, constant fields filled in, rest zeroed */ + char *name; /* Assembler mnemonic */ + short iclass; /* Class: see #defines below */ + char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */ + char num_ops; /* Number of operands */ + char operand[3];/* Operand descriptors; same order as assembler instr */ +}; + +/* Classes of 960 intructions: + * - each instruction falls into one class. + * - each target architecture supports one or more classes. + * + * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!: see targ_has_iclass(). + */ +#define I_BASE 0x01 /* 80960 base instruction set */ +#define I_CX 0x02 /* 80960Cx instruction */ +#define I_DEC 0x04 /* Decimal instruction */ +#define I_FP 0x08 /* Floating point instruction */ +#define I_KX 0x10 /* 80960Kx instruction */ +#define I_MIL 0x20 /* Military instruction */ +#define I_CASIM 0x40 /* CA simulator instruction */ +#define I_CX2 0x80 /* Cx/Jx/Hx instructions */ +#define I_JX 0x100 /* Jx/Hx instruction */ +#define I_HX 0x200 /* Hx instructions */ + +/****************************************************************************** + * + * TABLE OF i960 INSTRUCTION DESCRIPTIONS + * + ******************************************************************************/ + +const struct i960_opcode i960_opcodes[] = { + + /* if a CTRL instruction has an operand, it's always a displacement */ + + /* callj default=='call' */ + { 0x09000000, "callj", I_BASE, CALLJ, 1, { 0, 0, 0 } }, + { 0x08000000, "b", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x09000000, "call", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x0a000000, "ret", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x0b000000, "bal", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x10000000, "bno", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bf same as bno */ + { 0x10000000, "bf", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bru same as bno */ + { 0x10000000, "bru", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x11000000, "bg", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brg same as bg */ + { 0x11000000, "brg", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x12000000, "be", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bre same as be */ + { 0x12000000, "bre", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x13000000, "bge", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brge same as bge */ + { 0x13000000, "brge", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x14000000, "bl", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brl same as bl */ + { 0x14000000, "brl", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x15000000, "bne", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brlg same as bne */ + { 0x15000000, "brlg", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x16000000, "ble", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* brle same as ble */ + { 0x16000000, "brle", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x17000000, "bo", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bt same as bo */ + { 0x17000000, "bt", I_BASE, CTRL, 1, { 0, 0, 0 } }, + /* bro same as bo */ + { 0x17000000, "bro", I_BASE, CTRL, 1, { 0, 0, 0 } }, + { 0x18000000, "faultno", I_BASE, CTRL, 0, { 0, 0, 0 } }, + /* faultf same as faultno */ + { 0x18000000, "faultf", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x19000000, "faultg", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1a000000, "faulte", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1b000000, "faultge", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1c000000, "faultl", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1d000000, "faultne", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1e000000, "faultle", I_BASE, CTRL, 0, { 0, 0, 0 } }, + { 0x1f000000, "faulto", I_BASE, CTRL, 0, { 0, 0, 0 } }, + /* faultt syn for faulto */ + { 0x1f000000, "faultt", I_BASE, CTRL, 0, { 0, 0, 0 } }, + + { 0x01000000, "syscall", I_CASIM,CTRL, 0, { 0, 0, 0 } }, + + /* If a COBR (or COJ) has 3 operands, the last one is always a + * displacement and does not appear explicitly in the table. + */ + + { 0x20000000, "testno", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x21000000, "testg", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x22000000, "teste", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x23000000, "testge", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x24000000, "testl", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x25000000, "testne", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x26000000, "testle", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x27000000, "testo", I_BASE, COBR, 1, { R, 0, 0 } }, + { 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x38000000, "cmpibno", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x39000000, "cmpibg", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3a000000, "cmpibe", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3b000000, "cmpibge", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3c000000, "cmpibl", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3d000000, "cmpibne", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3e000000, "cmpible", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x3f000000, "cmpibo", I_BASE, COBR, 3, { RL, RS, 0 } }, + { 0x31000000, "cmpojg", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x32000000, "cmpoje", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x33000000, "cmpojge", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x34000000, "cmpojl", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x35000000, "cmpojne", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x36000000, "cmpojle", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x38000000, "cmpijno", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x39000000, "cmpijg", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3a000000, "cmpije", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3b000000, "cmpijge", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3c000000, "cmpijl", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3d000000, "cmpijne", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3e000000, "cmpijle", I_BASE, COJ, 3, { RL, RS, 0 } }, + { 0x3f000000, "cmpijo", I_BASE, COJ, 3, { RL, RS, 0 } }, + + { 0x80000000, "ldob", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0x82000000, "stob", I_BASE, MEM1, 2, { R, M, 0 } }, + { 0x84000000, "bx", I_BASE, MEM1, 1, { M, 0, 0 } }, + { 0x85000000, "balx", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0x86000000, "callx", I_BASE, MEM1, 1, { M, 0, 0 } }, + { 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } }, + { 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } }, + { 0x8c000000, "lda", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0x90000000, "ld", I_BASE, MEM4, 2, { M, R, 0 } }, + { 0x92000000, "st", I_BASE, MEM4, 2, { R, M, 0 } }, + { 0x98000000, "ldl", I_BASE, MEM8, 2, { M, R2, 0 } }, + { 0x9a000000, "stl", I_BASE, MEM8, 2, { R2, M, 0 } }, + { 0xa0000000, "ldt", I_BASE, MEM12, 2, { M, R4, 0 } }, + { 0xa2000000, "stt", I_BASE, MEM12, 2, { R4, M, 0 } }, + { 0xb0000000, "ldq", I_BASE, MEM16, 2, { M, R4, 0 } }, + { 0xb2000000, "stq", I_BASE, MEM16, 2, { R4, M, 0 } }, + { 0xc0000000, "ldib", I_BASE, MEM1, 2, { M, R, 0 } }, + { 0xc2000000, "stib", I_BASE, MEM1, 2, { R, M, 0 } }, + { 0xc8000000, "ldis", I_BASE, MEM2, 2, { M, R, 0 } }, + { 0xca000000, "stis", I_BASE, MEM2, 2, { R, M, 0 } }, + + { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x582), "andnot", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x583), "setbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x584), "notand", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x586), "xor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x587), "or", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x588), "nor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x589), "xnor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x58a), "not", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_3(0x58b), "ornot", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58c), "clrbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58d), "notor", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58e), "nand", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x58f), "alterbit", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x590), "addo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x591), "addi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x592), "subo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x593), "subi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x598), "shro", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59a), "shrdi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59b), "shri", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59c), "shlo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59d), "rotate", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x59e), "shli", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2(0x5a0), "cmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5a1), "cmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5a2), "concmpo", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5a3), "concmpi", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_3(0x5a4), "cmpinco", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5a5), "cmpinci", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5a6), "cmpdeco", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5a7), "cmpdeci", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2(0x5ac), "scanbyte", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x5ae), "chkbit", I_BASE, REG, 2, { RSL,RSL, 0 } }, + { R_3(0x5b0), "addc", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x5b2), "subc", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x5cc), "mov", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_2D(0x5dc), "movl", I_BASE, REG, 2, { RL2,R2, 0 } }, + { R_2D(0x5ec), "movt", I_BASE, REG, 2, { RL4,R4, 0 } }, + { R_2D(0x5fc), "movq", I_BASE, REG, 2, { RL4,R4, 0 } }, + { R_3(0x610), "atmod", I_BASE, REG, 3, { RS, RSL,R } }, + { R_3(0x612), "atadd", I_BASE, REG, 3, { RS, RSL,RS } }, + { R_2D(0x640), "spanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_2D(0x641), "scanbit", I_BASE, REG, 2, { RSL,RS, 0 } }, + { R_3(0x645), "modac", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x650), "modify", I_BASE, REG, 3, { RSL,RSL,R } }, + { R_3(0x651), "extract", I_BASE, REG, 3, { RSL,RSL,R } }, + { R_3(0x654), "modtc", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x655), "modpc", I_BASE, REG, 3, { RSL,RSL,R } }, + { R_1(0x660), "calls", I_BASE, REG, 1, { RSL, 0, 0 } }, + { R_0(0x66b), "mark", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_0(0x66c), "fmark", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_0(0x66d), "flushreg", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_0(0x66f), "syncf", I_BASE, REG, 0, { 0, 0, 0 } }, + { R_3(0x670), "emul", I_BASE, REG, 3, { RSL,RSL,R2 } }, + { R_3(0x671), "ediv", I_BASE, REG, 3, { RSL,RL2,RS } }, + { R_2D(0x672), "cvtadr", I_CASIM,REG, 2, { RL, R2, 0 } }, + { R_3(0x701), "mulo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x708), "remo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x70b), "divo", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x741), "muli", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x748), "remi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x749), "modi", I_BASE, REG, 3, { RSL,RSL,RS } }, + { R_3(0x74b), "divi", I_BASE, REG, 3, { RSL,RSL,RS } }, + + /* Floating-point instructions */ + + { R_2D(0x674), "cvtir", I_FP, REG, 2, { RL, F, 0 } }, + { R_2D(0x675), "cvtilr", I_FP, REG, 2, { RL, F, 0 } }, + { R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } }, + { R_3(0x677), "scaler", I_FP, REG, 3, { RL, FL, F } }, + { R_3(0x680), "atanr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x681), "logepr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x682), "logr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x683), "remr", I_FP, REG, 3, { FL, FL, F } }, + { R_2(0x684), "cmpor", I_FP, REG, 2, { FL, FL, 0 } }, + { R_2(0x685), "cmpr", I_FP, REG, 2, { FL, FL, 0 } }, + { R_2D(0x688), "sqrtr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x689), "expr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68a), "logbnr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68b), "roundr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68c), "sinr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68d), "cosr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x68e), "tanr", I_FP, REG, 2, { FL, F, 0 } }, + { R_1(0x68f), "classr", I_FP, REG, 1, { FL, 0, 0 } }, + { R_3(0x690), "atanrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x691), "logeprl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x692), "logrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x693), "remrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_2(0x694), "cmporl", I_FP, REG, 2, { FL2,FL2, 0 } }, + { R_2(0x695), "cmprl", I_FP, REG, 2, { FL2,FL2, 0 } }, + { R_2D(0x698), "sqrtrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x699), "exprl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69a), "logbnrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69b), "roundrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69c), "sinrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69d), "cosrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x69e), "tanrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_1(0x69f), "classrl", I_FP, REG, 1, { FL2, 0, 0 } }, + { R_2D(0x6c0), "cvtri", I_FP, REG, 2, { FL, R, 0 } }, + { R_2D(0x6c1), "cvtril", I_FP, REG, 2, { FL, R2, 0 } }, + { R_2D(0x6c2), "cvtzri", I_FP, REG, 2, { FL, R, 0 } }, + { R_2D(0x6c3), "cvtzril", I_FP, REG, 2, { FL, R2, 0 } }, + { R_2D(0x6c9), "movr", I_FP, REG, 2, { FL, F, 0 } }, + { R_2D(0x6d9), "movrl", I_FP, REG, 2, { FL2,F2, 0 } }, + { R_2D(0x6e1), "movre", I_FP, REG, 2, { FL4,F4, 0 } }, + { R_3(0x6e2), "cpysre", I_FP, REG, 3, { FL4,FL4,F4 } }, + { R_3(0x6e3), "cpyrsre", I_FP, REG, 3, { FL4,FL4,F4 } }, + { R_3(0x78b), "divr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x78c), "mulr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x78d), "subr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x78f), "addr", I_FP, REG, 3, { FL, FL, F } }, + { R_3(0x79b), "divrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x79c), "mulrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x79d), "subrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + { R_3(0x79f), "addrl", I_FP, REG, 3, { FL2,FL2,F2 } }, + + /* These are the floating point branch instructions. Each actually + * generates 2 branch instructions: the first a CTRL instruction with + * the indicated opcode, and the second a 'bno'. + */ + + { 0x12000000, "brue", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x11000000, "brug", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x13000000, "bruge", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x14000000, "brul", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x16000000, "brule", I_FP, FBRA, 1, { 0, 0, 0 } }, + { 0x15000000, "brulg", I_FP, FBRA, 1, { 0, 0, 0 } }, + + + /* Decimal instructions */ + + { R_3(0x642), "daddc", I_DEC, REG, 3, { RSL,RSL,RS } }, + { R_3(0x643), "dsubc", I_DEC, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x644), "dmovt", I_DEC, REG, 2, { RSL,RS, 0 } }, + + + /* KX extensions */ + + { R_2(0x600), "synmov", I_KX, REG, 2, { R, R, 0 } }, + { R_2(0x601), "synmovl", I_KX, REG, 2, { R, R, 0 } }, + { R_2(0x602), "synmovq", I_KX, REG, 2, { R, R, 0 } }, + { R_2D(0x615), "synld", I_KX, REG, 2, { R, R, 0 } }, + + + /* MC extensions */ + + { R_3(0x603), "cmpstr", I_MIL, REG, 3, { R, R, RL } }, + { R_3(0x604), "movqstr", I_MIL, REG, 3, { R, R, RL } }, + { R_3(0x605), "movstr", I_MIL, REG, 3, { R, R, RL } }, + { R_2D(0x613), "inspacc", I_MIL, REG, 2, { R, R, 0 } }, + { R_2D(0x614), "ldphy", I_MIL, REG, 2, { R, R, 0 } }, + { R_3(0x617), "fill", I_MIL, REG, 3, { R, RL, RL } }, + { R_2D(0x646), "condrec", I_MIL, REG, 2, { R, R, 0 } }, + { R_2D(0x656), "receive", I_MIL, REG, 2, { R, R, 0 } }, + { R_3(0x662), "send", I_MIL, REG, 3, { R, RL, R } }, + { R_1(0x663), "sendserv", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x664), "resumprcs", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x665), "schedprcs", I_MIL, REG, 1, { R, 0, 0 } }, + { R_0(0x666), "saveprcs", I_MIL, REG, 0, { 0, 0, 0 } }, + { R_1(0x668), "condwait", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x669), "wait", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1(0x66a), "signal", I_MIL, REG, 1, { R, 0, 0 } }, + { R_1D(0x673), "ldtime", I_MIL, REG, 1, { R2, 0, 0 } }, + + + /* CX extensions */ + + { R_3(0x5d8), "eshro", I_CX2, REG, 3, { RSL,RSL,RS } }, + { R_3(0x630), "sdma", I_CX, REG, 3, { RSL,RSL,RL } }, + { R_3(0x631), "udma", I_CX, REG, 0, { 0, 0, 0 } }, + { R_3(0x659), "sysctl", I_CX2, REG, 3, { RSL,RSL,RL } }, + + + /* Jx extensions. */ + { R_3(0x780), "addono", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x790), "addog", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a0), "addoe", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b0), "addoge", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c0), "addol", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d0), "addone", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e0), "addole", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f0), "addoo", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x781), "addino", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x791), "addig", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a1), "addie", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b1), "addige", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c1), "addil", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d1), "addine", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e1), "addile", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f1), "addio", I_JX, REG, 3, { RSL,RSL,RS } }, + + { R_2D(0x5ad), "bswap", I_JX, REG, 2, { RSL, RS, 0 } }, + + { R_2(0x594), "cmpob", I_JX, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x595), "cmpib", I_JX, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x596), "cmpos", I_JX, REG, 2, { RSL,RSL, 0 } }, + { R_2(0x597), "cmpis", I_JX, REG, 2, { RSL,RSL, 0 } }, + + { R_3(0x784), "selno", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x794), "selg", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a4), "sele", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b4), "selge", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c4), "sell", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d4), "selne", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e4), "selle", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f4), "selo", I_JX, REG, 3, { RSL,RSL,RS } }, + + { R_3(0x782), "subono", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x792), "subog", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a2), "suboe", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b2), "suboge", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c2), "subol", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d2), "subone", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e2), "subole", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f2), "suboo", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x783), "subino", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x793), "subig", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7a3), "subie", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7b3), "subige", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7c3), "subil", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7d3), "subine", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7e3), "subile", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_3(0x7f3), "subio", I_JX, REG, 3, { RSL,RSL,RS } }, + + { R_3(0x65c), "dcctl", I_JX, REG, 3, { RSL,RSL,RL } }, + { R_3(0x65b), "icctl", I_JX, REG, 3, { RSL,RSL,RS } }, + { R_2D(0x658), "intctl", I_JX, REG, 2, { RSL, RS, 0 } }, + { R_0(0x5b4), "intdis", I_JX, REG, 0, { 0, 0, 0 } }, + { R_0(0x5b5), "inten", I_JX, REG, 0, { 0, 0, 0 } }, + { R_0(0x65d), "halt", I_JX, REG, 1, { RSL, 0, 0 } }, + + /* Hx extensions. */ + { 0xac000000, "dcinva", I_HX, MEM1, 1, { M, 0, 0 } }, + + /* END OF TABLE */ + + { 0, NULL, 0, 0, 0, { 0, 0, 0 } } +}; + + /* end of i960-opcode.h */ diff --git a/include/opcode/m68hc11.h b/include/opcode/m68hc11.h new file mode 100644 index 000000000000..648c23b56156 --- /dev/null +++ b/include/opcode/m68hc11.h @@ -0,0 +1,427 @@ +/* m68hc11.h -- Header file for Motorola 68HC11 & 68HC12 opcode table + Copyright 1999, 2000, 2002, 2003 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _OPCODE_M68HC11_H +#define _OPCODE_M68HC11_H + +/* Flags for the definition of the 68HC11 & 68HC12 CCR. */ +#define M6811_S_BIT 0x80 /* Stop disable */ +#define M6811_X_BIT 0x40 /* X-interrupt mask */ +#define M6811_H_BIT 0x20 /* Half carry flag */ +#define M6811_I_BIT 0x10 /* I-interrupt mask */ +#define M6811_N_BIT 0x08 /* Negative */ +#define M6811_Z_BIT 0x04 /* Zero */ +#define M6811_V_BIT 0x02 /* Overflow */ +#define M6811_C_BIT 0x01 /* Carry */ + +/* 68HC11 register address offsets (range 0..0x3F or 0..64). + The absolute address of the I/O register depends on the setting + of the M6811_INIT register. At init time, the I/O registers are + mapped at 0x1000. Address of registers is then: + + 0x1000 + M6811_xxx +*/ +#define M6811_PORTA 0x00 /* Port A register */ +#define M6811__RES1 0x01 /* Unused/Reserved */ +#define M6811_PIOC 0x02 /* Parallel I/O Control register */ +#define M6811_PORTC 0x03 /* Port C register */ +#define M6811_PORTB 0x04 /* Port B register */ +#define M6811_PORTCL 0x05 /* Alternate latched port C */ +#define M6811__RES6 0x06 /* Unused/Reserved */ +#define M6811_DDRC 0x07 /* Data direction register for port C */ +#define M6811_PORTD 0x08 /* Port D register */ +#define M6811_DDRD 0x09 /* Data direction register for port D */ +#define M6811_PORTE 0x0A /* Port E input register */ +#define M6811_CFORC 0x0B /* Compare Force Register */ +#define M6811_OC1M 0x0C /* OC1 Action Mask register */ +#define M6811_OC1D 0x0D /* OC1 Action Data register */ +#define M6811_TCTN 0x0E /* Timer Counter Register */ +#define M6811_TCTN_H 0x0E /* " " " High part */ +#define M6811_TCTN_L 0x0F /* " " " Low part */ +#define M6811_TIC1 0x10 /* Input capture 1 register */ +#define M6811_TIC1_H 0x10 /* " " " High part */ +#define M6811_TIC1_L 0x11 /* " " " Low part */ +#define M6811_TIC2 0x12 /* Input capture 2 register */ +#define M6811_TIC2_H 0x12 /* " " " High part */ +#define M6811_TIC2_L 0x13 /* " " " Low part */ +#define M6811_TIC3 0x14 /* Input capture 3 register */ +#define M6811_TIC3_H 0x14 /* " " " High part */ +#define M6811_TIC3_L 0x15 /* " " " Low part */ +#define M6811_TOC1 0x16 /* Output Compare 1 register */ +#define M6811_TOC1_H 0x16 /* " " " High part */ +#define M6811_TOC1_L 0x17 /* " " " Low part */ +#define M6811_TOC2 0x18 /* Output Compare 2 register */ +#define M6811_TOC2_H 0x18 /* " " " High part */ +#define M6811_TOC2_L 0x19 /* " " " Low part */ +#define M6811_TOC3 0x1A /* Output Compare 3 register */ +#define M6811_TOC3_H 0x1A /* " " " High part */ +#define M6811_TOC3_L 0x1B /* " " " Low part */ +#define M6811_TOC4 0x1C /* Output Compare 4 register */ +#define M6811_TOC4_H 0x1C /* " " " High part */ +#define M6811_TOC4_L 0x1D /* " " " Low part */ +#define M6811_TOC5 0x1E /* Output Compare 5 register */ +#define M6811_TOC5_H 0x1E /* " " " High part */ +#define M6811_TOC5_L 0x1F /* " " " Low part */ +#define M6811_TCTL1 0x20 /* Timer Control register 1 */ +#define M6811_TCTL2 0x21 /* Timer Control register 2 */ +#define M6811_TMSK1 0x22 /* Timer Interrupt Mask Register 1 */ +#define M6811_TFLG1 0x23 /* Timer Interrupt Flag Register 1 */ +#define M6811_TMSK2 0x24 /* Timer Interrupt Mask Register 2 */ +#define M6811_TFLG2 0x25 /* Timer Interrupt Flag Register 2 */ +#define M6811_PACTL 0x26 /* Pulse Accumulator Control Register */ +#define M6811_PACNT 0x27 /* Pulse Accumulator Count Register */ +#define M6811_SPCR 0x28 /* SPI Control register */ +#define M6811_SPSR 0x29 /* SPI Status register */ +#define M6811_SPDR 0x2A /* SPI Data register */ +#define M6811_BAUD 0x2B /* SCI Baud register */ +#define M6811_SCCR1 0x2C /* SCI Control register 1 */ +#define M6811_SCCR2 0x2D /* SCI Control register 2 */ +#define M6811_SCSR 0x2E /* SCI Status register */ +#define M6811_SCDR 0x2F /* SCI Data (Read => RDR, Write => TDR) */ +#define M6811_ADCTL 0x30 /* A/D Control register */ +#define M6811_ADR1 0x31 /* A/D, Analog Result register 1 */ +#define M6811_ADR2 0x32 /* A/D, Analog Result register 2 */ +#define M6811_ADR3 0x33 /* A/D, Analog Result register 3 */ +#define M6811_ADR4 0x34 /* A/D, Analog Result register 4 */ +#define M6811__RES35 0x35 +#define M6811__RES36 0x36 +#define M6811__RES37 0x37 +#define M6811__RES38 0x38 +#define M6811_OPTION 0x39 /* System Configuration Options */ +#define M6811_COPRST 0x3A /* Arm/Reset COP Timer Circuitry */ +#define M6811_PPROG 0x3B /* EEPROM Programming Control Register */ +#define M6811_HPRIO 0x3C /* Highest priority I-Bit int and misc */ +#define M6811_INIT 0x3D /* Ram and I/O mapping register */ +#define M6811_TEST1 0x3E /* Factory test control register */ +#define M6811_CONFIG 0x3F /* COP, ROM and EEPROM enables */ + + +/* Flags of the CONFIG register (in EEPROM). */ +#define M6811_NOSEC 0x08 /* Security mode disable */ +#define M6811_NOCOP 0x04 /* COP system disable */ +#define M6811_ROMON 0x02 /* Enable on-chip rom */ +#define M6811_EEON 0x01 /* Enable on-chip eeprom */ + +/* Flags of the PPROG register. */ +#define M6811_BYTE 0x10 /* Byte mode */ +#define M6811_ROW 0x08 /* Row mode */ +#define M6811_ERASE 0x04 /* Erase mode select (1 = erase, 0 = read) */ +#define M6811_EELAT 0x02 /* EEPROM Latch Control */ +#define M6811_EEPGM 0x01 /* EEPROM Programming Voltage Enable */ + +/* Flags of the PIOC register. */ +#define M6811_STAF 0x80 /* Strobe A Interrupt Status Flag */ +#define M6811_STAI 0x40 /* Strobe A Interrupt Enable Mask */ +#define M6811_CWOM 0x20 /* Port C Wire OR mode */ +#define M6811_HNDS 0x10 /* Handshake mode */ +#define M6811_OIN 0x08 /* Output or Input handshaking */ +#define M6811_PLS 0x04 /* Pulse/Interlocked Handshake Operation */ +#define M6811_EGA 0x02 /* Active Edge for Strobe A */ +#define M6811_INVB 0x01 /* Invert Strobe B */ + +/* Flags of the SCCR1 register. */ +#define M6811_R8 0x80 /* Receive Data bit 8 */ +#define M6811_T8 0x40 /* Transmit data bit 8 */ +#define M6811__SCCR1_5 0x20 /* Unused */ +#define M6811_M 0x10 /* SCI Character length */ +#define M6811_WAKE 0x08 /* Wake up method select (0=idle, 1=addr mark) */ + +/* Flags of the SCCR2 register. */ +#define M6811_TIE 0x80 /* Transmit Interrupt enable */ +#define M6811_TCIE 0x40 /* Transmit Complete Interrupt Enable */ +#define M6811_RIE 0x20 /* Receive Interrupt Enable */ +#define M6811_ILIE 0x10 /* Idle Line Interrupt Enable */ +#define M6811_TE 0x08 /* Transmit Enable */ +#define M6811_RE 0x04 /* Receive Enable */ +#define M6811_RWU 0x02 /* Receiver Wake Up */ +#define M6811_SBK 0x01 /* Send Break */ + +/* Flags of the SCSR register. */ +#define M6811_TDRE 0x80 /* Transmit Data Register Empty */ +#define M6811_TC 0x40 /* Transmit Complete */ +#define M6811_RDRF 0x20 /* Receive Data Register Full */ +#define M6811_IDLE 0x10 /* Idle Line Detect */ +#define M6811_OR 0x08 /* Overrun Error */ +#define M6811_NF 0x04 /* Noise Flag */ +#define M6811_FE 0x02 /* Framing Error */ +#define M6811__SCSR_0 0x01 /* Unused */ + +/* Flags of the BAUD register. */ +#define M6811_TCLR 0x80 /* Clear Baud Rate (TEST mode) */ +#define M6811__BAUD_6 0x40 /* Not used */ +#define M6811_SCP1 0x20 /* SCI Baud rate prescaler select */ +#define M6811_SCP0 0x10 +#define M6811_RCKB 0x08 /* Baud Rate Clock Check (TEST mode) */ +#define M6811_SCR2 0x04 /* SCI Baud rate select */ +#define M6811_SCR1 0x02 +#define M6811_SCR0 0x01 + +#define M6811_BAUD_DIV_1 (0) +#define M6811_BAUD_DIV_3 (M6811_SCP0) +#define M6811_BAUD_DIV_4 (M6811_SCP1) +#define M6811_BAUD_DIV_13 (M6811_SCP1|M6811_SCP0) + +/* Flags of the SPCR register. */ +#define M6811_SPIE 0x80 /* Serial Peripheral Interrupt Enable */ +#define M6811_SPE 0x40 /* Serial Peripheral System Enable */ +#define M6811_DWOM 0x20 /* Port D Wire-OR mode option */ +#define M6811_MSTR 0x10 /* Master Mode Select */ +#define M6811_CPOL 0x08 /* Clock Polarity */ +#define M6811_CPHA 0x04 /* Clock Phase */ +#define M6811_SPR1 0x02 /* SPI Clock Rate Select */ +#define M6811_SPR0 0x01 + +/* Flags of the SPSR register. */ +#define M6811_SPIF 0x80 /* SPI Transfer Complete flag */ +#define M6811_WCOL 0x40 /* Write Collision */ +#define M6811_MODF 0x10 /* Mode Fault */ + +/* Flags of the ADCTL register. */ +#define M6811_CCF 0x80 /* Conversions Complete Flag */ +#define M6811_SCAN 0x20 /* Continuous Scan Control */ +#define M6811_MULT 0x10 /* Multiple Channel/Single Channel Control */ +#define M6811_CD 0x08 /* Channel Select D */ +#define M6811_CC 0x04 /* C */ +#define M6811_CB 0x02 /* B */ +#define M6811_CA 0x01 /* A */ + +/* Flags of the CFORC register. */ +#define M6811_FOC1 0x80 /* Force Output Compare 1 */ +#define M6811_FOC2 0x40 /* 2 */ +#define M6811_FOC3 0x20 /* 3 */ +#define M6811_FOC4 0x10 /* 4 */ +#define M6811_FOC5 0x08 /* 5 */ + +/* Flags of the OC1M register. */ +#define M6811_OC1M7 0x80 /* Output Compare 7 */ +#define M6811_OC1M6 0x40 /* 6 */ +#define M6811_OC1M5 0x20 /* 5 */ +#define M6811_OC1M4 0x10 /* 4 */ +#define M6811_OC1M3 0x08 /* 3 */ + +/* Flags of the OC1D register. */ +#define M6811_OC1D7 0x80 +#define M6811_OC1D6 0x40 +#define M6811_OC1D5 0x20 +#define M6811_OC1D4 0x10 +#define M6811_OC1D3 0x08 + +/* Flags of the TCTL1 register. */ +#define M6811_OM2 0x80 /* Output Mode 2 */ +#define M6811_OL2 0x40 /* Output Level 2 */ +#define M6811_OM3 0x20 +#define M6811_OL3 0x10 +#define M6811_OM4 0x08 +#define M6811_OL4 0x04 +#define M6811_OM5 0x02 +#define M6811_OL5 0x01 + +/* Flags of the TCTL2 register. */ +#define M6811_EDG1B 0x20 /* Input Edge Capture Control 1 */ +#define M6811_EDG1A 0x10 +#define M6811_EDG2B 0x08 /* Input 2 */ +#define M6811_EDG2A 0x04 +#define M6811_EDG3B 0x02 /* Input 3 */ +#define M6811_EDG3A 0x01 + +/* Flags of the TMSK1 register. */ +#define M6811_OC1I 0x80 /* Output Compare 1 Interrupt */ +#define M6811_OC2I 0x40 /* 2 */ +#define M6811_OC3I 0x20 /* 3 */ +#define M6811_OC4I 0x10 /* 4 */ +#define M6811_OC5I 0x08 /* 5 */ +#define M6811_IC1I 0x04 /* Input Capture 1 Interrupt */ +#define M6811_IC2I 0x02 /* 2 */ +#define M6811_IC3I 0x01 /* 3 */ + +/* Flags of the TFLG1 register. */ +#define M6811_OC1F 0x80 /* Output Compare 1 Flag */ +#define M6811_OC2F 0x40 /* 2 */ +#define M6811_OC3F 0x20 /* 3 */ +#define M6811_OC4F 0x10 /* 4 */ +#define M6811_OC5F 0x08 /* 5 */ +#define M6811_IC1F 0x04 /* Input Capture 1 Flag */ +#define M6811_IC2F 0x02 /* 2 */ +#define M6811_IC3F 0x01 /* 3 */ + +/* Flags of Timer Interrupt Mask Register 2 (TMSK2). */ +#define M6811_TOI 0x80 /* Timer Overflow Interrupt Enable */ +#define M6811_RTII 0x40 /* RTI Interrupt Enable */ +#define M6811_PAOVI 0x20 /* Pulse Accumulator Overflow Interrupt En. */ +#define M6811_PAII 0x10 /* Pulse Accumulator Interrupt Enable */ +#define M6811_PR1 0x02 /* Timer prescaler */ +#define M6811_PR0 0x01 /* Timer prescaler */ +#define M6811_TPR_1 0x00 /* " " prescale div 1 */ +#define M6811_TPR_4 0x01 /* " " prescale div 4 */ +#define M6811_TPR_8 0x02 /* " " prescale div 8 */ +#define M6811_TPR_16 0x03 /* " " prescale div 16 */ + +/* Flags of Timer Interrupt Flag Register 2 (M6811_TFLG2). */ +#define M6811_TOF 0x80 /* Timer overflow bit */ +#define M6811_RTIF 0x40 /* Read time interrupt flag */ +#define M6811_PAOVF 0x20 /* Pulse accumulator overflow Interrupt flag */ +#define M6811_PAIF 0x10 /* Pulse accumulator Input Edge " " " */ + +/* Flags of Pulse Accumulator Control Register (PACTL). */ +#define M6811_DDRA7 0x80 /* Data direction for port A bit 7 */ +#define M6811_PAEN 0x40 /* Pulse accumulator system enable */ +#define M6811_PAMOD 0x20 /* Pulse accumulator mode */ +#define M6811_PEDGE 0x10 /* Pulse accumulator edge control */ +#define M6811_RTR1 0x02 /* RTI Interrupt rates select */ +#define M6811_RTR0 0x01 /* " " " " */ + +/* Flags of the Options register. */ +#define M6811_ADPU 0x80 /* A/D Powerup */ +#define M6811_CSEL 0x40 /* A/D/EE Charge pump clock source select */ +#define M6811_IRQE 0x20 /* IRQ Edge/Level sensitive */ +#define M6811_DLY 0x10 /* Stop exit turn on delay */ +#define M6811_CME 0x08 /* Clock Monitor enable */ +#define M6811_CR1 0x02 /* COP timer rate select */ +#define M6811_CR0 0x01 /* COP timer rate select */ + +/* Flags of the HPRIO register. */ +#define M6811_RBOOT 0x80 /* Read Bootstrap ROM */ +#define M6811_SMOD 0x40 /* Special Mode */ +#define M6811_MDA 0x20 /* Mode Select A */ +#define M6811_IRV 0x10 /* Internal Read Visibility */ +#define M6811_PSEL3 0x08 /* Priority Select */ +#define M6811_PSEL2 0x04 +#define M6811_PSEL1 0x02 +#define M6811_PSEL0 0x01 + +/* Some insns used by gas to turn relative branches into absolute ones. */ +#define M6811_BRA 0x20 +#define M6811_JMP 0x7e +#define M6811_BSR 0x8d +#define M6811_JSR 0xbd +#define M6812_JMP 0x06 +#define M6812_BSR 0x07 +#define M6812_JSR 0x16 + +/* Instruction code pages. Code page 1 is the default. */ +/*#define M6811_OPCODE_PAGE1 0x00*/ +#define M6811_OPCODE_PAGE2 0x18 +#define M6811_OPCODE_PAGE3 0x1A +#define M6811_OPCODE_PAGE4 0xCD + + +/* 68HC11 operands formats as stored in the m6811_opcode table. These + flags do not correspond to anything in the 68HC11 or 68HC12. + They are only used by GAS to recognize operands. */ +#define M6811_OP_NONE 0 /* No operand */ +#define M6811_OP_DIRECT 0x0001 /* Page 0 addressing: *<val-8bits> */ +#define M6811_OP_IMM8 0x0002 /* 8 bits immediat: #<val-8bits> */ +#define M6811_OP_IMM16 0x0004 /* 16 bits immediat: #<val-16bits> */ +#define M6811_OP_IND16 0x0008 /* Indirect abs: <val-16> */ +#define M6812_OP_IND16_P2 0x0010 /* Second parameter indirect abs. */ +#define M6812_OP_REG 0x0020 /* Register operand 1 */ +#define M6812_OP_REG_2 0x0040 /* Register operand 2 */ + +#define M6811_OP_IX 0x0080 /* Indirect IX: <val-8>,x */ +#define M6811_OP_IY 0x0100 /* Indirect IY: <val-8>,y */ +#define M6812_OP_IDX 0x0200 /* Indirect: N,r N,[+-]r[+-] N:5-bits */ +#define M6812_OP_IDX_1 0x0400 /* N,r N:9-bits */ +#define M6812_OP_IDX_2 0x0800 /* N,r N:16-bits */ +#define M6812_OP_D_IDX 0x1000 /* Indirect indexed: [D,r] */ +#define M6812_OP_D_IDX_2 0x2000 /* [N,r] N:16-bits */ +#define M6812_OP_PAGE 0x4000 /* Page number */ +#define M6811_OP_MASK 0x07FFF +#define M6811_OP_BRANCH 0x00008000 /* Branch, jsr, call */ +#define M6811_OP_BITMASK 0x00010000 /* Bitmask: #<val-8> */ +#define M6811_OP_JUMP_REL 0x00020000 /* Pc-Relative: <val-8> */ +#define M6812_OP_JUMP_REL16 0x00040000 /* Pc-relative: <val-16> */ +#define M6811_OP_PAGE1 0x0000 +#define M6811_OP_PAGE2 0x00080000 /* Need a page2 opcode before */ +#define M6811_OP_PAGE3 0x00100000 /* Need a page3 opcode before */ +#define M6811_OP_PAGE4 0x00200000 /* Need a page4 opcode before */ +#define M6811_MAX_OPERANDS 3 /* Max operands: brset <dst> <mask> <b> */ + +#define M6812_ACC_OFFSET 0x00400000 /* A,r B,r D,r */ +#define M6812_ACC_IND 0x00800000 /* [D,r] */ +#define M6812_PRE_INC 0x01000000 /* n,+r n = -8..8 */ +#define M6812_PRE_DEC 0x02000000 /* n,-r */ +#define M6812_POST_INC 0x04000000 /* n,r+ */ +#define M6812_POST_DEC 0x08000000 /* n,r- */ +#define M6812_INDEXED_IND 0x10000000 /* [n,r] n = 16-bits */ +#define M6812_INDEXED 0x20000000 /* n,r n = 5, 9 or 16-bits */ +#define M6812_OP_IDX_P2 0x40000000 + +/* Markers to identify some instructions. */ +#define M6812_OP_EXG_MARKER 0x01000000 /* exg r1,r2 */ +#define M6812_OP_TFR_MARKER 0x02000000 /* tfr r1,r2 */ +#define M6812_OP_SEX_MARKER 0x04000000 /* sex r1,r2 */ + +#define M6812_OP_EQ_MARKER 0x80000000 /* dbeq/ibeq/tbeq */ +#define M6812_OP_DBCC_MARKER 0x04000000 /* dbeq/dbne */ +#define M6812_OP_IBCC_MARKER 0x02000000 /* ibeq/ibne */ +#define M6812_OP_TBCC_MARKER 0x01000000 + +#define M6812_OP_TRAP_ID 0x80000000 /* trap #N */ + +#define M6811_OP_HIGH_ADDR 0x01000000 /* Used internally by gas. */ +#define M6811_OP_LOW_ADDR 0x02000000 + +#define M68HC12_BANK_VIRT 0x010000 +#define M68HC12_BANK_MASK 0x00003fff +#define M68HC12_BANK_BASE 0x00008000 +#define M68HC12_BANK_SHIFT 14 +#define M68HC12_BANK_PAGE_MASK 0x0ff + + +/* CPU identification. */ +#define cpu6811 0x01 +#define cpu6812 0x02 +#define cpu6812s 0x04 + +/* The opcode table is an array of struct m68hc11_opcode. */ +struct m68hc11_opcode { + const char* name; /* Op-code name */ + long format; + unsigned char size; + unsigned char opcode; + unsigned char cycles_low; + unsigned char cycles_high; + unsigned char set_flags_mask; + unsigned char clr_flags_mask; + unsigned char chg_flags_mask; + unsigned char arch; +}; + +/* Alias definition for 68HC12. */ +struct m68hc12_opcode_alias +{ + const char* name; + const char* translation; + unsigned char size; + unsigned char code1; + unsigned char code2; +}; + +/* The opcode table. The table contains all the opcodes (all pages). + You can't rely on the order. */ +extern const struct m68hc11_opcode m68hc11_opcodes[]; +extern const int m68hc11_num_opcodes; + +/* Alias table for 68HC12. It translates some 68HC11 insn which are not + implemented in 68HC12 but have equivalent translations. */ +extern const struct m68hc12_opcode_alias m68hc12_alias[]; +extern const int m68hc12_num_alias; + +#endif /* _OPCODE_M68HC11_H */ diff --git a/include/opcode/m68k.h b/include/opcode/m68k.h new file mode 100644 index 000000000000..3f189841d8f8 --- /dev/null +++ b/include/opcode/m68k.h @@ -0,0 +1,358 @@ +/* Opcode table header for m680[01234]0/m6888[12]/m68851. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, + 2003 Free Software Foundation, Inc. + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 1, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* These are used as bit flags for the arch field in the m68k_opcode + structure. */ +#define _m68k_undef 0 +#define m68000 0x001 +#define m68008 m68000 /* Synonym for -m68000. otherwise unused. */ +#define m68010 0x002 +#define m68020 0x004 +#define m68030 0x008 +#define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences; + gas will deal with the few differences. */ +#define m68040 0x010 +/* There is no 68050. */ +#define m68060 0x020 +#define m68881 0x040 +#define m68882 m68881 /* Synonym for -m68881. otherwise unused. */ +#define m68851 0x080 +#define cpu32 0x100 /* e.g., 68332 */ +#define mcf5200 0x200 +#define mcf5206e 0x400 +#define mcf5307 0x800 +#define mcf5407 0x1000 +#define mcfv4e 0x2000 +#define mcf528x 0x4000 + + /* Handy aliases. */ +#define m68040up (m68040 | m68060) +#define m68030up (m68030 | m68040up) +#define m68020up (m68020 | m68030up) +#define m68010up (m68010 | cpu32 | m68020up) +#define m68000up (m68000 | m68010up) +#define mcf (mcf5200 | mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e) +#define mcf5206eup (mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e) +#define mcf5307up (mcf5307 | mcf5407 | mcfv4e) +#define mcfv4up (mcf5407 | mcfv4e) +#define mcfv4eup (mcfv4e) + +#define cfloat (mcfv4e) +#define mfloat (m68881 | m68882 | m68040 | m68060) +#define mmmu (m68851 | m68030 | m68040 | m68060) + +/* The structure used to hold information for an opcode. */ + +struct m68k_opcode +{ + /* The opcode name. */ + const char *name; + /* The opcode itself. */ + unsigned long opcode; + /* The mask used by the disassembler. */ + unsigned long match; + /* The arguments. */ + const char *args; + /* The architectures which support this opcode. */ + unsigned int arch; +}; + +/* The structure used to hold information for an opcode alias. */ + +struct m68k_opcode_alias +{ + /* The alias name. */ + const char *alias; + /* The instruction for which this is an alias. */ + const char *primary; +}; + +/* We store four bytes of opcode for all opcodes because that is the + most any of them need. The actual length of an instruction is + always at least 2 bytes, and is as much longer as necessary to hold + the operands it has. + + The match field is a mask saying which bits must match particular + opcode in order for an instruction to be an instance of that + opcode. + + The args field is a string containing two characters for each + operand of the instruction. The first specifies the kind of + operand; the second, the place it is stored. */ + +/* Kinds of operands: + Characters used: AaBbCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWwXxYyZz0123|*~%;@!&$?/<>#^+- + + D data register only. Stored as 3 bits. + A address register only. Stored as 3 bits. + a address register indirect only. Stored as 3 bits. + R either kind of register. Stored as 4 bits. + r either kind of register indirect only. Stored as 4 bits. + At the moment, used only for cas2 instruction. + F floating point coprocessor register only. Stored as 3 bits. + O an offset (or width): immediate data 0-31 or data register. + Stored as 6 bits in special format for BF... insns. + + autoincrement only. Stored as 3 bits (number of the address register). + - autodecrement only. Stored as 3 bits (number of the address register). + Q quick immediate data. Stored as 3 bits. + This matches an immediate operand only when value is in range 1 .. 8. + M moveq immediate data. Stored as 8 bits. + This matches an immediate operand only when value is in range -128..127 + T trap vector immediate data. Stored as 4 bits. + + k K-factor for fmove.p instruction. Stored as a 7-bit constant or + a three bit register offset, depending on the field type. + + # immediate data. Stored in special places (b, w or l) + which say how many bits to store. + ^ immediate data for floating point instructions. Special places + are offset by 2 bytes from '#'... + B pc-relative address, converted to an offset + that is treated as immediate data. + d displacement and register. Stores the register as 3 bits + and stores the displacement in the entire second word. + + C the CCR. No need to store it; this is just for filtering validity. + S the SR. No need to store, just as with CCR. + U the USP. No need to store, just as with CCR. + E the ACC. No need to store, just as with CCR. + G the MACSR. No need to store, just as with CCR. + H the MASK. No need to store, just as with CCR. + + I Coprocessor ID. Not printed if 1. The Coprocessor ID is always + extracted from the 'd' field of word one, which means that an extended + coprocessor opcode can be skipped using the 'i' place, if needed. + + s System Control register for the floating point coprocessor. + + J Misc register for movec instruction, stored in 'j' format. + Possible values: + 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10] + 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10] + 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf] + 0x003 TC MMU Translation Control [60, 40] + 0x004 ITT0 Instruction Transparent + Translation reg 0 [60, 40] + 0x005 ITT1 Instruction Transparent + Translation reg 1 [60, 40] + 0x006 DTT0 Data Transparent + Translation reg 0 [60, 40] + 0x007 DTT1 Data Transparent + Translation reg 1 [60, 40] + 0x008 BUSCR Bus Control Register [60] + 0x800 USP User Stack Pointer [60, 40, 30, 20, 10] + 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf] + 0x802 CAAR Cache Address Register [ 30, 20] + 0x803 MSP Master Stack Pointer [ 40, 30, 20] + 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20] + 0x805 MMUSR MMU Status reg [ 40] + 0x806 URP User Root Pointer [60, 40] + 0x807 SRP Supervisor Root Pointer [60, 40] + 0x808 PCR Processor Configuration reg [60] + 0xC00 ROMBAR ROM Base Address Register [520X] + 0xC04 RAMBAR0 RAM Base Address Register 0 [520X] + 0xC05 RAMBAR1 RAM Base Address Register 0 [520X] + 0xC0F MBAR0 RAM Base Address Register 0 [520X] + 0xC04 FLASHBAR FLASH Base Address Register [mcf528x] + 0xC05 RAMBAR Static RAM Base Address Register [mcf528x] + + L Register list of the type d0-d7/a0-a7 etc. + (New! Improved! Can also hold fp0-fp7, as well!) + The assembler tries to see if the registers match the insn by + looking at where the insn wants them stored. + + l Register list like L, but with all the bits reversed. + Used for going the other way. . . + + c cache identifier which may be "nc" for no cache, "ic" + for instruction cache, "dc" for data cache, or "bc" + for both caches. Used in cinv and cpush. Always + stored in position "d". + + u Any register, with ``upper'' or ``lower'' specification. Used + in the mac instructions with size word. + + The remainder are all stored as 6 bits using an address mode and a + register number; they differ in which addressing modes they match. + + * all (modes 0-6,7.0-4) + ~ alterable memory (modes 2-6,7.0,7.1) + (not 0,1,7.2-4) + % alterable (modes 0-6,7.0,7.1) + (not 7.2-4) + ; data (modes 0,2-6,7.0-4) + (not 1) + @ data, but not immediate (modes 0,2-6,7.0-3) + (not 1,7.4) + ! control (modes 2,5,6,7.0-3) + (not 0,1,3,4,7.4) + & alterable control (modes 2,5,6,7.0,7.1) + (not 0,1,7.2-4) + $ alterable data (modes 0,2-6,7.0,7.1) + (not 1,7.2-4) + ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) + (not 1,3,4,7.2-4) + / control, or data register (modes 0,2,5,6,7.0-3) + (not 1,3,4,7.4) + > *save operands (modes 2,4,5,6,7.0,7.1) + (not 0,1,3,7.2-4) + < *restore operands (modes 2,3,5,6,7.0-3) + (not 0,1,4,7.4) + + coldfire move operands: + m (modes 0-4) + n (modes 5,7.2) + o (modes 6,7.0,7.1,7.3,7.4) + p (modes 0-5) + + coldfire bset/bclr/btst/mulsl/mulul operands: + q (modes 0,2-5) + v (modes 0,2-5,7.0,7.1) + b (modes 0,2-5,7.2) + w (modes 2-5,7.2) + y (modes 2,5) + z (modes 2,5,7.2) + x mov3q immediate operand. */ + +/* For the 68851: */ +/* I didn't use much imagination in choosing the + following codes, so many of them aren't very + mnemonic. -rab + + 0 32 bit pmmu register + Possible values: + 000 TC Translation Control Register (68030, 68851) + + 1 16 bit pmmu register + 111 AC Access Control (68851) + + 2 8 bit pmmu register + 100 CAL Current Access Level (68851) + 101 VAL Validate Access Level (68851) + 110 SCC Stack Change Control (68851) + + 3 68030-only pmmu registers (32 bit) + 010 TT0 Transparent Translation reg 0 + (aka Access Control reg 0 -- AC0 -- on 68ec030) + 011 TT1 Transparent Translation reg 1 + (aka Access Control reg 1 -- AC1 -- on 68ec030) + + W wide pmmu registers + Possible values: + 001 DRP Dma Root Pointer (68851) + 010 SRP Supervisor Root Pointer (68030, 68851) + 011 CRP Cpu Root Pointer (68030, 68851) + + f function code register (68030, 68851) + 0 SFC + 1 DFC + + V VAL register only (68851) + + X BADx, BACx (16 bit) + 100 BAD Breakpoint Acknowledge Data (68851) + 101 BAC Breakpoint Acknowledge Control (68851) + + Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030) + Z PCSR (68851) + + | memory (modes 2-6, 7.*) + + t address test level (68030 only) + Stored as 3 bits, range 0-7. + Also used for breakpoint instruction now. + +*/ + +/* Places to put an operand, for non-general operands: + Characters used: BbCcDdghijkLlMmNnostWw123456789 + + s source, low bits of first word. + d dest, shifted 9 in first word + 1 second word, shifted 12 + 2 second word, shifted 6 + 3 second word, shifted 0 + 4 third word, shifted 12 + 5 third word, shifted 6 + 6 third word, shifted 0 + 7 second word, shifted 7 + 8 second word, shifted 10 + 9 second word, shifted 5 + D store in both place 1 and place 3; for divul and divsl. + B first word, low byte, for branch displacements + W second word (entire), for branch displacements + L second and third words (entire), for branch displacements + (also overloaded for move16) + b second word, low byte + w second word (entire) [variable word/long branch offset for dbra] + W second word (entire) (must be signed 16 bit value) + l second and third word (entire) + g variable branch offset for bra and similar instructions. + The place to store depends on the magnitude of offset. + t store in both place 7 and place 8; for floating point operations + c branch offset for cpBcc operations. + The place to store is word two if bit six of word one is zero, + and words two and three if bit six of word one is one. + i Increment by two, to skip over coprocessor extended operands. Only + works with the 'I' format. + k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number. + Also used for dynamic fmovem instruction. + C floating point coprocessor constant - 7 bits. Also used for static + K-factors... + j Movec register #, stored in 12 low bits of second word. + m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word + and remaining 3 bits of register shifted 9 bits in first word. + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split + with MSB shifted 6 bits in first word and remaining 3 bits of + register shifted 9 bits in first word. No upper/lower + indication is done.) Use with `R' or `u' format. + o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + M For M[S]ACw; 4 bits in low bits of first word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + N For M[S]ACw; 4 bits in low bits of second word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + h shift indicator (scale factor), 1 bit shifted 10 in second word + + Places to put operand, for general operands: + d destination, shifted 6 bits in first word + b source, at low bit of first word, and immediate uses one byte + w source, at low bit of first word, and immediate uses two bytes + l source, at low bit of first word, and immediate uses four bytes + s source, at low bit of first word. + Used sometimes in contexts where immediate is not allowed anyway. + f single precision float, low bit of 1st word, immediate uses 4 bytes + F double precision float, low bit of 1st word, immediate uses 8 bytes + x extended precision float, low bit of 1st word, immediate uses 12 bytes + p packed float, low bit of 1st word, immediate uses 12 bytes +*/ + +extern const struct m68k_opcode m68k_opcodes[]; +extern const struct m68k_opcode_alias m68k_opcode_aliases[]; + +extern const int m68k_numopcodes, m68k_numaliases; + +/* end of m68k-opcode.h */ diff --git a/include/opcode/m88k.h b/include/opcode/m88k.h new file mode 100644 index 000000000000..6a163bbe934d --- /dev/null +++ b/include/opcode/m88k.h @@ -0,0 +1,453 @@ +/* Table of opcodes for the Motorola M88k family. + Copyright 1989, 1990, 1991, 1993, 2001 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* + * Disassembler Instruction Table + * + * The first field of the table is the opcode field. If an opcode + * is specified which has any non-opcode bits on, a system error + * will occur when the system attempts the install it into the + * instruction table. The second parameter is a pointer to the + * instruction mnemonic. Each operand is specified by offset, width, + * and type. The offset is the bit number of the least significant + * bit of the operand with bit 0 being the least significant bit of + * the instruction. The width is the number of bits used to specify + * the operand. The type specifies the output format to be used for + * the operand. The valid formats are: register, register indirect, + * hex constant, and bit field specification. The last field is a + * pointer to the next instruction in the linked list. These pointers + * are initialized by init_disasm(). + * + * Revision History + * + * Revision 1.0 11/08/85 Creation date + * 1.1 02/05/86 Updated instruction mnemonic table MD + * 1.2 06/16/86 Updated SIM_FLAGS for floating point + * 1.3 09/20/86 Updated for new encoding + * 05/11/89 R. Trawick adapted from Motorola disassembler + */ + +#include <stdio.h> + +/* Define the number of bits in the primary opcode field of the instruction, + the destination field, the source 1 and source 2 fields. */ + +/* Size of opcode field. */ +#define OP 8 + +/* Size of destination. */ +#define DEST 6 + +/* Size of source1. */ +#define SOURCE1 6 + +/* Size of source2. */ +#define SOURCE2 6 + +/* Number of registers. */ +#define REGs 32 + +/* Type definitions. */ + +typedef unsigned int UINT; +#define WORD long +#define FLAG unsigned +#define STATE short + +/* The next four equates define the priorities that the various classes + * of instructions have regarding writing results back into registers and + * signalling exceptions. */ + +/* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */ +#undef PMEM + +/* Integer priority. */ +#define PINT 0 + +/* Floating point priority. */ +#define PFLT 1 + +/* Memory priority. */ +#define PMEM 2 + +/* Not applicable, instruction doesn't write to regs. */ +#define NA 3 + +/* Highest of these priorities. */ +#define HIPRI 3 + +/* The instruction registers are an artificial mechanism to speed up + * simulator execution. In the real processor, an instruction register + * is 32 bits wide. In the simulator, the 32 bit instruction is kept in + * a structure field called rawop, and the instruction is partially decoded, + * and split into various fields and flags which make up the other fields + * of the structure. + * The partial decode is done when the instructions are initially loaded + * into simulator memory. The simulator code memory is not an array of + * 32 bit words, but is an array of instruction register structures. + * Yes this wastes memory, but it executes much quicker. + */ + +struct IR_FIELDS +{ + unsigned op:OP, + dest: DEST, + src1: SOURCE1, + src2: SOURCE2; + int ltncy, + extime, + /* Writeback priority. */ + wb_pri; + /* Immediate size. */ + unsigned imm_flags:2, + /* Register source 1 used. */ + rs1_used:1, + /* Register source 2 used. */ + rs2_used:1, + /* Register source/dest. used. */ + rsd_used:1, + /* Complement. */ + c_flag:1, + /* Upper half word. */ + u_flag:1, + /* Execute next. */ + n_flag:1, + /* Uses writeback slot. */ + wb_flag:1, + /* Dest size. */ + dest_64:1, + /* Source 1 size. */ + s1_64:1, + /* Source 2 size. */ + s2_64:1, + scale_flag:1, + /* Scaled register. */ + brk_flg:1; +}; + +struct mem_segs +{ + /* Pointer (returned by calloc) to segment. */ + struct mem_wrd *seg; + + /* Base load address from file headers. */ + unsigned long baseaddr; + + /* Ending address of segment. */ + unsigned long endaddr; + + /* Segment control flags (none defined). */ + int flags; +}; + +#define MAXSEGS (10) /* max number of segment allowed */ +#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */ + +#if 0 +#define BRK_RD (0x01) /* break on memory read */ +#define BRK_WR (0x02) /* break on memory write */ +#define BRK_EXEC (0x04) /* break on execution */ +#define BRK_CNT (0x08) /* break on terminal count */ +#endif + +struct mem_wrd +{ + /* Simulator instruction break down. */ + struct IR_FIELDS opcode; + union { + /* Memory element break down. */ + unsigned long l; + unsigned short s[2]; + unsigned char c[4]; + } mem; +}; + +/* Size of each 32 bit memory model. */ +#define MEMWRDSIZE (sizeof (struct mem_wrd)) + +extern struct mem_segs memory[]; +extern struct PROCESSOR m78000; + +struct PROCESSOR +{ + unsigned WORD + /* Execute instruction pointer. */ + ip, + /* Vector base register. */ + vbr, + /* Processor status register. */ + psr; + + /* Source 1. */ + WORD S1bus, + /* Source 2. */ + S2bus, + /* Destination. */ + Dbus, + /* Data address bus. */ + DAbus, + ALU, + /* Data registers. */ + Regs[REGs], + /* Max clocks before reg is available. */ + time_left[REGs], + /* Writeback priority of reg. */ + wb_pri[REGs], + /* Integer unit control regs. */ + SFU0_regs[REGs], + /* Floating point control regs. */ + SFU1_regs[REGs], + Scoreboard[REGs], + Vbr; + unsigned WORD scoreboard, + Psw, + Tpsw; + /* Waiting for a jump instruction. */ + FLAG jump_pending:1; +}; + +/* Size of immediate field. */ + +#define i26bit 1 +#define i16bit 2 +#define i10bit 3 + +/* Definitions for fields in psr. */ + +#define mode 31 +#define rbo 30 +#define ser 29 +#define carry 28 +#define sf7m 11 +#define sf6m 10 +#define sf5m 9 +#define sf4m 8 +#define sf3m 7 +#define sf2m 6 +#define sf1m 5 +#define mam 4 +#define inm 3 +#define exm 2 +#define trm 1 +#define ovfm 0 + +/* The 1 clock operations. */ + +#define ADDU 1 +#define ADDC 2 +#define ADDUC 3 +#define ADD 4 + +#define SUBU ADD+1 +#define SUBB ADD+2 +#define SUBUB ADD+3 +#define SUB ADD+4 + +#define AND_ ADD+5 +#define OR ADD+6 +#define XOR ADD+7 +#define CMP ADD+8 + +/* Loads. */ + +#define LDAB CMP+1 +#define LDAH CMP+2 +#define LDA CMP+3 +#define LDAD CMP+4 + +#define LDB LDAD+1 +#define LDH LDAD+2 +#define LD LDAD+3 +#define LDD LDAD+4 +#define LDBU LDAD+5 +#define LDHU LDAD+6 + +/* Stores. */ + +#define STB LDHU+1 +#define STH LDHU+2 +#define ST LDHU+3 +#define STD LDHU+4 + +/* Exchange. */ + +#define XMEMBU LDHU+5 +#define XMEM LDHU+6 + +/* Branches. */ + +#define JSR STD+1 +#define BSR STD+2 +#define BR STD+3 +#define JMP STD+4 +#define BB1 STD+5 +#define BB0 STD+6 +#define RTN STD+7 +#define BCND STD+8 + +/* Traps. */ + +#define TB1 BCND+1 +#define TB0 BCND+2 +#define TCND BCND+3 +#define RTE BCND+4 +#define TBND BCND+5 + +/* Misc. */ + +#define MUL TBND + 1 +#define DIV MUL +2 +#define DIVU MUL +3 +#define MASK MUL +4 +#define FF0 MUL +5 +#define FF1 MUL +6 +#define CLR MUL +7 +#define SET MUL +8 +#define EXT MUL +9 +#define EXTU MUL +10 +#define MAK MUL +11 +#define ROT MUL +12 + +/* Control register manipulations. */ + +#define LDCR ROT +1 +#define STCR ROT +2 +#define XCR ROT +3 + +#define FLDCR ROT +4 +#define FSTCR ROT +5 +#define FXCR ROT +6 + +#define NOP XCR +1 + +/* Floating point instructions. */ + +#define FADD NOP +1 +#define FSUB NOP +2 +#define FMUL NOP +3 +#define FDIV NOP +4 +#define FSQRT NOP +5 +#define FCMP NOP +6 +#define FIP NOP +7 +#define FLT NOP +8 +#define INT NOP +9 +#define NINT NOP +10 +#define TRNC NOP +11 +#define FLDC NOP +12 +#define FSTC NOP +13 +#define FXC NOP +14 + +#define UEXT(src,off,wid) \ + ((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1)) + +#define SEXT(src,off,wid) \ + (((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) ) + +#define MAKE(src,off,wid) \ + ((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off)) + +#define opword(n) (unsigned long) (memaddr->mem.l) + +/* Constants and masks. */ + +#define SFU0 0x80000000 +#define SFU1 0x84000000 +#define SFU7 0x9c000000 +#define RRI10 0xf0000000 +#define RRR 0xf4000000 +#define SFUMASK 0xfc00ffe0 +#define RRRMASK 0xfc00ffe0 +#define RRI10MASK 0xfc00fc00 +#define DEFMASK 0xfc000000 +#define CTRL 0x0000f000 +#define CTRLMASK 0xfc00f800 + +/* Operands types. */ + +enum operand_type +{ + HEX = 1, + REG = 2, + CONT = 3, + IND = 3, + BF = 4, + /* Scaled register. */ + REGSC = 5, + /* Control register. */ + CRREG = 6, + /* Floating point control register. */ + FCRREG = 7, + PCREL = 8, + CONDMASK = 9, + /* Extended register. */ + XREG = 10, + /* Decimal. */ + DEC = 11 +}; + +/* Hashing specification. */ + +#define HASHVAL 79 + +/* Structure templates. */ + +typedef struct +{ + unsigned int offset; + unsigned int width; + enum operand_type type; +} OPSPEC; + +struct SIM_FLAGS +{ + int ltncy, /* latency (max number of clocks needed to execute). */ + extime, /* execution time (min number of clocks needed to execute). */ + wb_pri; /* writeback slot priority. */ + unsigned op:OP, /* simulator version of opcode. */ + imm_flags:2, /* 10,16 or 26 bit immediate flags. */ + rs1_used:1, /* register source 1 used. */ + rs2_used:1, /* register source 2 used. */ + rsd_used:1, /* register source/dest used. */ + c_flag:1, /* complement. */ + u_flag:1, /* upper half word. */ + n_flag:1, /* execute next. */ + wb_flag:1, /* uses writeback slot. */ + dest_64:1, /* double precision dest. */ + s1_64:1, /* double precision source 1. */ + s2_64:1, /* double precision source 2. */ + scale_flag:1; /* register is scaled. */ +}; + +typedef struct INSTRUCTAB { + unsigned int opcode; + char *mnemonic; + OPSPEC op1,op2,op3; + struct SIM_FLAGS flgs; +} INSTAB; + + +#define NO_OPERAND {0,0,0} + +extern const INSTAB instructions[]; + +/* + * Local Variables: + * fill-column: 131 + * End: + */ diff --git a/include/opcode/mmix.h b/include/opcode/mmix.h new file mode 100644 index 000000000000..d2aef32bdfed --- /dev/null +++ b/include/opcode/mmix.h @@ -0,0 +1,186 @@ +/* mmix.h -- Header file for MMIX opcode table + Copyright (C) 2001, 2003 Free Software Foundation, Inc. + Written by Hans-Peter Nilsson (hp@bitrange.com) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version 2, +or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We could have just a char*[] table indexed by the register number, but + that would not allow for synonyms. The table is terminated with an + entry with a NULL name. */ +struct mmix_spec_reg +{ + const char *name; + unsigned int number; +}; + +/* General indication of the type of instruction. */ +enum mmix_insn_type + { + mmix_type_pseudo, + mmix_type_normal, + mmix_type_branch, + mmix_type_condbranch, + mmix_type_memaccess_octa, + mmix_type_memaccess_tetra, + mmix_type_memaccess_wyde, + mmix_type_memaccess_byte, + mmix_type_memaccess_block, + mmix_type_jsr + }; + +/* Type of operands an instruction takes. Use when parsing assembly code + and disassembling. */ +enum mmix_operands_type + { + mmix_operands_none = 0, + + /* All operands are registers: "$X,$Y,$Z". */ + mmix_operands_regs, + + /* "$X,YZ", like SETH. */ + mmix_operands_reg_yz, + + /* The regular "$X,$Y,$Z|Z". + The Z is optional; if only "$X,$Y" is given, then "$X,$Y,0" is + assumed. */ + mmix_operands_regs_z_opt, + + /* The regular "$X,$Y,$Z|Z". */ + mmix_operands_regs_z, + + /* "Address"; only JMP. Zero operands allowed unless GNU syntax. */ + mmix_operands_jmp, + + /* "$X|X,$Y,$Z|Z": PUSHGO; like "3", but X can be expressed as an + integer. */ + mmix_operands_pushgo, + + /* Two registers or a register and a byte, like FLOT, possibly with + rounding: "$X,$Z|Z" or "$X,ROUND_MODE,$Z|Z". */ + mmix_operands_roundregs_z, + + /* "X,YZ", POP. Unless GNU syntax, zero or one operand is allowed. */ + mmix_operands_pop, + + /* Two registers, possibly with rounding: "$X,$Z" or + "$X,ROUND_MODE,$Z". */ + mmix_operands_roundregs, + + /* "XYZ", like SYNC. */ + mmix_operands_sync, + + /* "X,$Y,$Z|Z", like SYNCD. */ + mmix_operands_x_regs_z, + + /* "$X,Y,$Z|Z", like NEG and NEGU. The Y field is optional, default 0. */ + mmix_operands_neg, + + /* "$X,Address, like GETA or branches. */ + mmix_operands_regaddr, + + /* "$X|X,Address, like PUSHJ. */ + mmix_operands_pushj, + + /* "$X,spec_reg"; GET. */ + mmix_operands_get, + + /* "spec_reg,$Z|Z"; PUT. */ + mmix_operands_put, + + /* Two registers, "$X,$Y". */ + mmix_operands_set, + + /* "$X,0"; SAVE. */ + mmix_operands_save, + + /* "0,$Z"; UNSAVE. */ + mmix_operands_unsave, + + /* "X,Y,Z"; like SWYM or TRAP. Zero (or 1 if GNU syntax) to three + operands, interpreted as 0; XYZ; X, YZ and X, Y, Z. */ + mmix_operands_xyz_opt, + + /* Just "Z", like RESUME. Unless GNU syntax, the operand can be omitted + and will then be assumed zero. */ + mmix_operands_resume, + + /* These are specials to handle that pseudo-directives are specified + like ordinary insns when being mmixal-compatible. They signify the + specific pseudo-directive rather than the operands type. */ + + /* LOC. */ + mmix_operands_loc, + + /* PREFIX. */ + mmix_operands_prefix, + + /* BYTE. */ + mmix_operands_byte, + + /* WYDE. */ + mmix_operands_wyde, + + /* TETRA. */ + mmix_operands_tetra, + + /* OCTA. */ + mmix_operands_octa, + + /* LOCAL. */ + mmix_operands_local, + + /* BSPEC. */ + mmix_operands_bspec, + + /* ESPEC. */ + mmix_operands_espec, + }; + +struct mmix_opcode + { + const char *name; + unsigned long match; + unsigned long lose; + enum mmix_operands_type operands; + + /* This is used by the disassembly function. */ + enum mmix_insn_type type; + }; + +/* Declare the actual tables. */ +extern const struct mmix_opcode mmix_opcodes[]; + +/* This one is terminated with an entry with a NULL name. */ +extern const struct mmix_spec_reg mmix_spec_regs[]; + +/* Some insn values we use when padding and synthesizing address loads. */ +#define IMM_OFFSET_BIT 1 +#define COND_INV_BIT 0x8 +#define PRED_INV_BIT 0x10 + +#define PUSHGO_INSN_BYTE 0xbe +#define GO_INSN_BYTE 0x9e +#define SETL_INSN_BYTE 0xe3 +#define INCML_INSN_BYTE 0xe6 +#define INCMH_INSN_BYTE 0xe5 +#define INCH_INSN_BYTE 0xe4 +#define SWYM_INSN_BYTE 0xfd +#define JMP_INSN_BYTE 0xf0 + +/* We can have 256 - 32 (local registers) - 1 ($255 is not allocatable) + global registers. */ +#define MAX_GREGS 223 diff --git a/include/opcode/mn10200.h b/include/opcode/mn10200.h new file mode 100644 index 000000000000..42fa94b0c6ef --- /dev/null +++ b/include/opcode/mn10200.h @@ -0,0 +1,110 @@ +/* mn10200.h -- Header file for Matsushita 10200 opcode table + Copyright 1996, 1997 Free Software Foundation, Inc. + Written by Jeff Law, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef MN10200_H +#define MN10200_H + +/* The opcode table is an array of struct mn10200_opcode. */ + +struct mn10200_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* The format of this opcode. */ + unsigned char format; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct mn10200_opcode mn10200_opcodes[]; +extern const int mn10200_num_opcodes; + + +/* The operands table is an array of struct mn10200_operand. */ + +struct mn10200_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the mn10200_opcodes table. */ + +extern const struct mn10200_operand mn10200_operands[]; + +/* Values defined for the flags field of a struct mn10200_operand. */ +#define MN10200_OPERAND_DREG 0x1 + +#define MN10200_OPERAND_AREG 0x2 + +#define MN10200_OPERAND_PSW 0x4 + +#define MN10200_OPERAND_MDR 0x8 + +#define MN10200_OPERAND_SIGNED 0x10 + +#define MN10200_OPERAND_PROMOTE 0x20 + +#define MN10200_OPERAND_PAREN 0x40 + +#define MN10200_OPERAND_REPEATED 0x80 + +#define MN10200_OPERAND_EXTENDED 0x100 + +#define MN10200_OPERAND_NOCHECK 0x200 + +#define MN10200_OPERAND_PCREL 0x400 + +#define MN10200_OPERAND_MEMADDR 0x800 + +#define MN10200_OPERAND_RELAX 0x1000 + +#define FMT_1 1 +#define FMT_2 2 +#define FMT_3 3 +#define FMT_4 4 +#define FMT_5 5 +#define FMT_6 6 +#define FMT_7 7 +#endif /* MN10200_H */ diff --git a/include/opcode/mn10300.h b/include/opcode/mn10300.h new file mode 100644 index 000000000000..bd7faa110aa3 --- /dev/null +++ b/include/opcode/mn10300.h @@ -0,0 +1,169 @@ +/* mn10300.h -- Header file for Matsushita 10300 opcode table + Copyright 1996, 1997, 1998, 1999 Free Software Foundation, Inc. + Written by Jeff Law, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef MN10300_H +#define MN10300_H + +/* The opcode table is an array of struct mn10300_opcode. */ + +#define MN10300_MAX_OPERANDS 8 +struct mn10300_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* A bitmask. For each operand, nonzero if it must not have the same + register specification as all other operands with a nonzero bit in + this flag. ie 0x81 would indicate that operands 7 and 0 must not + match. Note that we count operands from left to right as they appear + in the operands specification below. */ + unsigned int no_match_operands; + + /* The format of this opcode. */ + unsigned char format; + + /* Bitmask indicating what cpu variants this opcode is available on. + We assume mn10300 base opcodes are available everywhere, so we only + have to note opcodes which are available on other variants. */ + unsigned int machine; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[MN10300_MAX_OPERANDS]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct mn10300_opcode mn10300_opcodes[]; +extern const int mn10300_num_opcodes; + + +/* The operands table is an array of struct mn10300_operand. */ + +struct mn10300_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the mn10300_opcodes table. */ + +extern const struct mn10300_operand mn10300_operands[]; + +/* Values defined for the flags field of a struct mn10300_operand. */ +#define MN10300_OPERAND_DREG 0x1 + +#define MN10300_OPERAND_AREG 0x2 + +#define MN10300_OPERAND_SP 0x4 + +#define MN10300_OPERAND_PSW 0x8 + +#define MN10300_OPERAND_MDR 0x10 + +#define MN10300_OPERAND_SIGNED 0x20 + +#define MN10300_OPERAND_PROMOTE 0x40 + +#define MN10300_OPERAND_PAREN 0x80 + +#define MN10300_OPERAND_REPEATED 0x100 + +#define MN10300_OPERAND_EXTENDED 0x200 + +#define MN10300_OPERAND_SPLIT 0x400 + +#define MN10300_OPERAND_REG_LIST 0x800 + +#define MN10300_OPERAND_PCREL 0x1000 + +#define MN10300_OPERAND_MEMADDR 0x2000 + +#define MN10300_OPERAND_RELAX 0x4000 + +#define MN10300_OPERAND_USP 0x8000 + +#define MN10300_OPERAND_SSP 0x10000 + +#define MN10300_OPERAND_MSP 0x20000 + +#define MN10300_OPERAND_PC 0x40000 + +#define MN10300_OPERAND_EPSW 0x80000 + +#define MN10300_OPERAND_RREG 0x100000 + +#define MN10300_OPERAND_XRREG 0x200000 + +#define MN10300_OPERAND_PLUS 0x400000 + +#define MN10300_OPERAND_24BIT 0x800000 + +#define MN10300_OPERAND_FSREG 0x1000000 + +#define MN10300_OPERAND_FDREG 0x2000000 + +#define MN10300_OPERAND_FPCR 0x4000000 + +/* Opcode Formats. */ +#define FMT_S0 1 +#define FMT_S1 2 +#define FMT_S2 3 +#define FMT_S4 4 +#define FMT_S6 5 +#define FMT_D0 6 +#define FMT_D1 7 +#define FMT_D2 8 +#define FMT_D4 9 +#define FMT_D5 10 +#define FMT_D6 11 +#define FMT_D7 12 +#define FMT_D8 13 +#define FMT_D9 14 +#define FMT_D10 15 +#define FMT_D3 16 + +/* Variants of the mn10300 which have additional opcodes. */ +#define MN103 300 +#define AM30 300 + +#define AM33 330 +#define AM33_2 332 + +#endif /* MN10300_H */ diff --git a/include/opcode/msp430.h b/include/opcode/msp430.h new file mode 100644 index 000000000000..19702254eefc --- /dev/null +++ b/include/opcode/msp430.h @@ -0,0 +1,111 @@ +/* Opcode table for the TI MSP430 microcontrollers + + Copyright 2002 Free Software Foundation, Inc. + Contributed by Dmitry Diky <diwil@mail.ru> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef __MSP430_H_ +#define __MSP430_H_ + +struct msp430_operand_s +{ + int ol; /* Operand length words. */ + int am; /* Addr mode. */ + int reg; /* Register. */ + int mode; /* Pperand mode. */ +#define OP_REG 0 +#define OP_EXP 1 +#ifndef DASM_SECTION + expressionS exp; +#endif +}; + +#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */ + +struct msp430_opcode_s +{ + char *name; + int fmt; + int insn_opnumb; + int bin_opcode; + int bin_mask; +}; + +#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask } + +static struct msp430_opcode_s msp430_opcodes[] = +{ + MSP_INSN (and, 1, 2, 0xf000, 0xf000), + MSP_INSN (inv, 0, 1, 0xe330, 0xfff0), + MSP_INSN (xor, 1, 2, 0xe000, 0xf000), + MSP_INSN (setz, 0, 0, 0xd322, 0xffff), + MSP_INSN (setc, 0, 0, 0xd312, 0xffff), + MSP_INSN (eint, 0, 0, 0xd232, 0xffff), + MSP_INSN (setn, 0, 0, 0xd222, 0xffff), + MSP_INSN (bis, 1, 2, 0xd000, 0xf000), + MSP_INSN (clrz, 0, 0, 0xc322, 0xffff), + MSP_INSN (clrc, 0, 0, 0xc312, 0xffff), + MSP_INSN (dint, 0, 0, 0xc232, 0xffff), + MSP_INSN (clrn, 0, 0, 0xc222, 0xffff), + MSP_INSN (bic, 1, 2, 0xc000, 0xf000), + MSP_INSN (bit, 1, 2, 0xb000, 0xf000), + MSP_INSN (dadc, 0, 1, 0xa300, 0xff30), + MSP_INSN (dadd, 1, 2, 0xa000, 0xf000), + MSP_INSN (tst, 0, 1, 0x9300, 0xff30), + MSP_INSN (cmp, 1, 2, 0x9000, 0xf000), + MSP_INSN (decd, 0, 1, 0x8320, 0xff30), + MSP_INSN (dec, 0, 1, 0x8310, 0xff30), + MSP_INSN (sub, 1, 2, 0x8000, 0xf000), + MSP_INSN (sbc, 0, 1, 0x7300, 0xff30), + MSP_INSN (subc, 1, 2, 0x7000, 0xf000), + MSP_INSN (adc, 0, 1, 0x6300, 0xff30), + MSP_INSN (rlc, 0, 2, 0x6000, 0xf000), + MSP_INSN (addc, 1, 2, 0x6000, 0xf000), + MSP_INSN (incd, 0, 1, 0x5320, 0xff30), + MSP_INSN (inc, 0, 1, 0x5310, 0xff30), + MSP_INSN (rla, 0, 2, 0x5000, 0xf000), + MSP_INSN (add, 1, 2, 0x5000, 0xf000), + MSP_INSN (nop, 0, 0, 0x4303, 0xffff), + MSP_INSN (clr, 0, 1, 0x4300, 0xff30), + MSP_INSN (ret, 0, 0, 0x4130, 0xff30), + MSP_INSN (pop, 0, 1, 0x4130, 0xff30), + MSP_INSN (br, 0, 3, 0x4000, 0xf000), + MSP_INSN (mov, 1, 2, 0x4000, 0xf000), + MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00), + MSP_INSN (jl, 3, 1, 0x3800, 0xfc00), + MSP_INSN (jge, 3, 1, 0x3400, 0xfc00), + MSP_INSN (jn, 3, 1, 0x3000, 0xfc00), + MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00), + MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00), + MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00), + MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00), + MSP_INSN (jz, 3, 1, 0x2400, 0xfc00), + MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00), + MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00), + MSP_INSN (jne, 3, 1, 0x2000, 0xfc00), + MSP_INSN (reti, 2, 0, 0x1300, 0xffc0), + MSP_INSN (call, 2, 1, 0x1280, 0xffc0), + MSP_INSN (push, 2, 1, 0x1200, 0xff80), + MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0), + MSP_INSN (rra, 2, 1, 0x1100, 0xff80), + MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0), + MSP_INSN (rrc, 2, 1, 0x1000, 0xff80), + + /* End of instruction set. */ + { NULL, 0, 0, 0, 0 } +}; + +#endif diff --git a/include/opcode/ns32k.h b/include/opcode/ns32k.h new file mode 100644 index 000000000000..68a0dbaa4bd0 --- /dev/null +++ b/include/opcode/ns32k.h @@ -0,0 +1,487 @@ +/* ns32k-opcode.h -- Opcode table for National Semi 32k processor + Copyright 1987, 1991, 1994, 2002 Free Software Foundation, Inc. + +This file is part of GAS, the GNU Assembler. + +GAS is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GAS is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GAS; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#ifdef SEQUENT_COMPATABILITY +#define DEF_MODEC 20 +#define DEF_MODEL 21 +#endif + +#ifndef DEF_MODEC +#define DEF_MODEC 20 +#endif + +#ifndef DEF_MODEL +#define DEF_MODEL 20 +#endif +/* + After deciding the instruction entry (via hash.c) the instruction parser + will try to match the operands after the instruction to the required set + given in the entry operandfield. Every operand will result in a change in + the opcode or the addition of data to the opcode. + The operands in the source instruction are checked for inconsistent + semantics. + + F : 32 bit float general form + L : 64 bit float " + B : byte " + W : word " + D : double-word " + A : double-word gen-address-form ie no regs, no immediate + I : integer writeable gen int except immediate (A + reg) + Z : floating writeable gen float except immediate (Z + freg) + d : displacement + b : displacement - pc relative addressing acb + p : displacement - pc relative addressing br bcond bsr cxp + q : quick + i : immediate (8 bits) + This is not a standard ns32k operandtype, it is used to build + instructions like svc arg1,arg2 + Svc is the instruction SuperVisorCall and is sometimes used to + call OS-routines from usermode. Some args might be handy! + r : register number (3 bits) + O : setcfg instruction optionslist + C : cinv instruction optionslist + S : stringinstruction optionslist + U : registerlist save,enter + u : registerlist restore,exit + M : mmu register + P : cpu register + g : 3:rd operand of inss or exts instruction + G : 4:th operand of inss or exts instruction + Those operands are encoded in the same byte. + This byte is placed last in the instruction. + f : operand of sfsr + H : sequent-hack for bsr (Warning) + +column 1 instructions + 2 number of bits in opcode. + 3 number of bits in opcode explicitly + determined by the instruction type. + 4 opcodeseed, the number we build our opcode + from. + 5 operandtypes, used by operandparser. + 6 size in bytes of immediate +*/ +struct ns32k_opcode { + const char *name; + unsigned char opcode_id_size; /* not used by the assembler */ + unsigned char opcode_size; + unsigned long opcode_seed; + const char *operands; + unsigned char im_size; /* not used by dissassembler */ + const char *default_args; /* default to those args when none given */ + char default_modec; /* default to this addr-mode when ambigous + ie when the argument of a general addr-mode + is a plain constant */ + char default_model; /* is a plain label */ +}; + +#ifdef comment +/* This section was from the gdb version of this file. */ + +#ifndef ns32k_opcodeT +#define ns32k_opcodeT int +#endif /* no ns32k_opcodeT */ + +struct not_wot /* ns32k opcode table: wot to do with this */ + /* particular opcode */ +{ + int obits; /* number of opcode bits */ + int ibits; /* number of instruction bits */ + ns32k_opcodeT code; /* op-code (may be > 8 bits!) */ + const char *args; /* how to compile said opcode */ +}; + +struct not /* ns32k opcode text */ +{ + const char *name; /* opcode name: lowercase string [key] */ + struct not_wot detail; /* rest of opcode table [datum] */ +}; + +/* Instructions look like this: + + basic instruction--1, 2, or 3 bytes + index byte for operand A, if operand A is indexed--1 byte + index byte for operand B, if operand B is indexed--1 byte + addressing extension for operand A + addressing extension for operand B + implied operands + + Operand A is the operand listed first in the following opcode table. + Operand B is the operand listed second in the following opcode table. + All instructions have at most 2 general operands, so this is enough. + The implied operands are associated with operands other than A and B. + + Each operand has a digit and a letter. + + The digit gives the position in the assembly language. The letter, + one of the following, tells us what kind of operand it is. */ + +/* F : 32 bit float + * L : 64 bit float + * B : byte + * W : word + * D : double-word + * I : integer not immediate + * Z : floating not immediate + * d : displacement + * q : quick + * i : immediate (8 bits) + * r : register number (3 bits) + * p : displacement - pc relative addressing +*/ + + +#endif /* comment */ + +static const struct ns32k_opcode ns32k_opcodes[]= +{ + { "absf", 14,24, 0x35be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "absl", 14,24, 0x34be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "absb", 14,24, 0x304e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "absw", 14,24, 0x314e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "absd", 14,24, 0x334e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "acbb", 7,16, 0x4c, "2I1q3p", 1, "", DEF_MODEC,DEF_MODEL }, + { "acbw", 7,16, 0x4d, "2I1q3p", 2, "", DEF_MODEC,DEF_MODEL }, + { "acbd", 7,16, 0x4f, "2I1q3p", 4, "", DEF_MODEC,DEF_MODEL }, + { "addf", 14,24, 0x01be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "addl", 14,24, 0x00be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "addb", 6,16, 0x00, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "addw", 6,16, 0x01, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "addd", 6,16, 0x03, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "addcb", 6,16, 0x10, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "addcw", 6,16, 0x11, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "addcd", 6,16, 0x13, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "addpb", 14,24, 0x3c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "addpw", 14,24, 0x3d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "addpd", 14,24, 0x3f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "addqb", 7,16, 0x0c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, + { "addqw", 7,16, 0x0d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, + { "addqd", 7,16, 0x0f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, + { "addr", 6,16, 0x27, "1A2I", 4, "", 21,21 }, + { "adjspb", 11,16, 0x057c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "adjspw", 11,16, 0x057d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "adjspd", 11,16, 0x057f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, + { "andb", 6,16, 0x28, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "andw", 6,16, 0x29, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "andd", 6,16, 0x2b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "ashb", 14,24, 0x044e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ashw", 14,24, 0x054e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ashd", 14,24, 0x074e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "beq", 8,8, 0x0a, "1p", 0, "", 21,21 }, + { "bne", 8,8, 0x1a, "1p", 0, "", 21,21 }, + { "bcs", 8,8, 0x2a, "1p", 0, "", 21,21 }, + { "bcc", 8,8, 0x3a, "1p", 0, "", 21,21 }, + { "bhi", 8,8, 0x4a, "1p", 0, "", 21,21 }, + { "bls", 8,8, 0x5a, "1p", 0, "", 21,21 }, + { "bgt", 8,8, 0x6a, "1p", 0, "", 21,21 }, + { "ble", 8,8, 0x7a, "1p", 0, "", 21,21 }, + { "bfs", 8,8, 0x8a, "1p", 0, "", 21,21 }, + { "bfc", 8,8, 0x9a, "1p", 0, "", 21,21 }, + { "blo", 8,8, 0xaa, "1p", 0, "", 21,21 }, + { "bhs", 8,8, 0xba, "1p", 0, "", 21,21 }, + { "blt", 8,8, 0xca, "1p", 0, "", 21,21 }, + { "bge", 8,8, 0xda, "1p", 0, "", 21,21 }, + { "but", 8,8, 0xea, "1p", 0, "", 21,21 }, + { "buf", 8,8, 0xfa, "1p", 0, "", 21,21 }, + { "bicb", 6,16, 0x08, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "bicw", 6,16, 0x09, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "bicd", 6,16, 0x0b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "bicpsrb", 11,16, 0x17c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "bicpsrw", 11,16, 0x17d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "bispsrb", 11,16, 0x37c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "bispsrw", 11,16, 0x37d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "bpt", 8,8, 0xf2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "br", 8,8, 0xea, "1p", 0, "", 21,21 }, +#ifdef SEQUENT_COMPATABILITY + { "bsr", 8,8, 0x02, "1H", 0, "", 21,21 }, +#else + { "bsr", 8,8, 0x02, "1p", 0, "", 21,21 }, +#endif + { "caseb", 11,16, 0x77c, "1B", 1, "", DEF_MODEC,DEF_MODEL }, + { "casew", 11,16, 0x77d, "1W", 2, "", DEF_MODEC,DEF_MODEL }, + { "cased", 11,16, 0x77f, "1D", 4, "", DEF_MODEC,DEF_MODEL }, + { "cbitb", 14,24, 0x084e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "cbitw", 14,24, 0x094e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "cbitd", 14,24, 0x0b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "cbitib", 14,24, 0x0c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "cbitiw", 14,24, 0x0d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "cbitid", 14,24, 0x0f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "checkb", 11,24, 0x0ee, "2A3B1r", 1, "", DEF_MODEC,DEF_MODEL }, + { "checkw", 11,24, 0x1ee, "2A3W1r", 2, "", DEF_MODEC,DEF_MODEL }, + { "checkd", 11,24, 0x3ee, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, + { "cinv", 14,24, 0x271e, "2D1C", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpf", 14,24, 0x09be, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpl", 14,24, 0x08be, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, + { "cmpb", 6,16, 0x04, "1B2B", 1, "", DEF_MODEC,DEF_MODEL }, + { "cmpw", 6,16, 0x05, "1W2W", 2, "", DEF_MODEC,DEF_MODEL }, + { "cmpd", 6,16, 0x07, "1D2D", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpmb", 14,24, 0x04ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, + { "cmpmw", 14,24, 0x05ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, + { "cmpmd", 14,24, 0x07ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpqb", 7,16, 0x1c, "2B1q", 1, "", DEF_MODEC,DEF_MODEL }, + { "cmpqw", 7,16, 0x1d, "2W1q", 2, "", DEF_MODEC,DEF_MODEL }, + { "cmpqd", 7,16, 0x1f, "2D1q", 4, "", DEF_MODEC,DEF_MODEL }, + { "cmpsb", 16,24, 0x040e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "cmpsw", 16,24, 0x050e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "cmpsd", 16,24, 0x070e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "cmpst", 16,24, 0x840e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "comb", 14,24, 0x344e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "comw", 14,24, 0x354e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "comd", 14,24, 0x374e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "cvtp", 11,24, 0x036e, "2A3D1r", 4, "", DEF_MODEC,DEF_MODEL }, + { "cxp", 8,8, 0x22, "1p", 0, "", 21,21 }, + { "cxpd", 11,16, 0x07f, "1A", 4, "", DEF_MODEC,DEF_MODEL }, + { "deib", 14,24, 0x2cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "deiw", 14,24, 0x2dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "deid", 14,24, 0x2fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "dia", 8,8, 0xc2, "", 1, "", DEF_MODEC,DEF_MODEL }, + { "divf", 14,24, 0x21be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "divl", 14,24, 0x20be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "divb", 14,24, 0x3cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "divw", 14,24, 0x3dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "divd", 14,24, 0x3fce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "enter", 8,8, 0x82, "1U2d", 0, "", DEF_MODEC,DEF_MODEL }, + { "exit", 8,8, 0x92, "1u", 0, "", DEF_MODEC,DEF_MODEL }, + { "extb", 11,24, 0x02e, "2I3B1r4d", 1, "", DEF_MODEC,DEF_MODEL }, + { "extw", 11,24, 0x12e, "2I3W1r4d", 2, "", DEF_MODEC,DEF_MODEL }, + { "extd", 11,24, 0x32e, "2I3D1r4d", 4, "", DEF_MODEC,DEF_MODEL }, + { "extsb", 14,24, 0x0cce, "1I2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, + { "extsw", 14,24, 0x0dce, "1I2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, + { "extsd", 14,24, 0x0fce, "1I2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, + { "ffsb", 14,24, 0x046e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ffsw", 14,24, 0x056e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "ffsd", 14,24, 0x076e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "flag", 8,8, 0xd2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "floorfb", 14,24, 0x3c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "floorfw", 14,24, 0x3d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "floorfd", 14,24, 0x3f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "floorlb", 14,24, 0x383e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "floorlw", 14,24, 0x393e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "floorld", 14,24, 0x3b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "ibitb", 14,24, 0x384e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "ibitw", 14,24, 0x394e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "ibitd", 14,24, 0x3b4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "indexb", 11,24, 0x42e, "2B3B1r", 1, "", DEF_MODEC,DEF_MODEL }, + { "indexw", 11,24, 0x52e, "2W3W1r", 2, "", DEF_MODEC,DEF_MODEL }, + { "indexd", 11,24, 0x72e, "2D3D1r", 4, "", DEF_MODEC,DEF_MODEL }, + { "insb", 11,24, 0x0ae, "2B3I1r4d", 1, "", DEF_MODEC,DEF_MODEL }, + { "insw", 11,24, 0x1ae, "2W3I1r4d", 2, "", DEF_MODEC,DEF_MODEL }, + { "insd", 11,24, 0x3ae, "2D3I1r4d", 4, "", DEF_MODEC,DEF_MODEL }, + { "inssb", 14,24, 0x08ce, "1B2I4G3g", 1, "", DEF_MODEC,DEF_MODEL }, + { "inssw", 14,24, 0x09ce, "1W2I4G3g", 2, "", DEF_MODEC,DEF_MODEL }, + { "inssd", 14,24, 0x0bce, "1D2I4G3g", 4, "", DEF_MODEC,DEF_MODEL }, + { "jsr", 11,16, 0x67f, "1A", 4, "", 21,21 }, + { "jump", 11,16, 0x27f, "1A", 4, "", 21,21 }, + { "lfsr", 19,24, 0x00f3e,"1D", 4, "", DEF_MODEC,DEF_MODEL }, + { "lmr", 15,24, 0x0b1e, "2D1M", 4, "", DEF_MODEC,DEF_MODEL }, + { "lprb", 7,16, 0x6c, "2B1P", 1, "", DEF_MODEC,DEF_MODEL }, + { "lprw", 7,16, 0x6d, "2W1P", 2, "", DEF_MODEC,DEF_MODEL }, + { "lprd", 7,16, 0x6f, "2D1P", 4, "", DEF_MODEC,DEF_MODEL }, + { "lshb", 14,24, 0x144e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "lshw", 14,24, 0x154e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "lshd", 14,24, 0x174e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "meib", 14,24, 0x24ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "meiw", 14,24, 0x25ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "meid", 14,24, 0x27ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "modb", 14,24, 0x38ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "modw", 14,24, 0x39ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "modd", 14,24, 0x3bce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "movf", 14,24, 0x05be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movl", 14,24, 0x04be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "movb", 6,16, 0x14, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movw", 6,16, 0x15, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "movd", 6,16, 0x17, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "movbf", 14,24, 0x043e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, + { "movwf", 14,24, 0x053e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, + { "movdf", 14,24, 0x073e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movbl", 14,24, 0x003e, "1B2Z", 1, "", DEF_MODEC,DEF_MODEL }, + { "movwl", 14,24, 0x013e, "1W2Z", 2, "", DEF_MODEC,DEF_MODEL }, + { "movdl", 14,24, 0x033e, "1D2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movfl", 14,24, 0x1b3e, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "movlf", 14,24, 0x163e, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "movmb", 14,24, 0x00ce, "1A2A3b", 1, "", DEF_MODEC,DEF_MODEL }, + { "movmw", 14,24, 0x01ce, "1A2A3b", 2, "", DEF_MODEC,DEF_MODEL }, + { "movmd", 14,24, 0x03ce, "1A2A3b", 4, "", DEF_MODEC,DEF_MODEL }, + { "movqb", 7,16, 0x5c, "2I1q", 1, "", DEF_MODEC,DEF_MODEL }, + { "movqw", 7,16, 0x5d, "2I1q", 2, "", DEF_MODEC,DEF_MODEL }, + { "movqd", 7,16, 0x5f, "2I1q", 4, "", DEF_MODEC,DEF_MODEL }, + { "movsb", 16,24, 0x000e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movsw", 16,24, 0x010e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movsd", 16,24, 0x030e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movst", 16,24, 0x800e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "movsub", 14,24, 0x0cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "movsuw", 14,24, 0x0dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "movsud", 14,24, 0x0fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "movusb", 14,24, 0x1cae, "1A2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "movusw", 14,24, 0x1dae, "1A2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "movusd", 14,24, 0x1fae, "1A2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "movxbd", 14,24, 0x1cce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movxwd", 14,24, 0x1dce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "movxbw", 14,24, 0x10ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movzbd", 14,24, 0x18ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "movzwd", 14,24, 0x19ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "movzbw", 14,24, 0x14ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "mulf", 14,24, 0x31be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "mull", 14,24, 0x30be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "mulb", 14,24, 0x20ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "mulw", 14,24, 0x21ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "muld", 14,24, 0x23ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "negf", 14,24, 0x15be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "negl", 14,24, 0x14be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "negb", 14,24, 0x204e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "negw", 14,24, 0x214e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "negd", 14,24, 0x234e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "nop", 8,8, 0xa2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "notb", 14,24, 0x244e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "notw", 14,24, 0x254e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "notd", 14,24, 0x274e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "orb", 6,16, 0x18, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "orw", 6,16, 0x19, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "ord", 6,16, 0x1b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "quob", 14,24, 0x30ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "quow", 14,24, 0x31ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "quod", 14,24, 0x33ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "rdval", 19,24, 0x0031e,"1A", 4, "", DEF_MODEC,DEF_MODEL }, + { "remb", 14,24, 0x34ce, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "remw", 14,24, 0x35ce, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "remd", 14,24, 0x37ce, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "restore", 8,8, 0x72, "1u", 0, "", DEF_MODEC,DEF_MODEL }, + { "ret", 8,8, 0x12, "1d", 0, "", DEF_MODEC,DEF_MODEL }, + { "reti", 8,8, 0x52, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "rett", 8,8, 0x42, "1d", 0, "", DEF_MODEC,DEF_MODEL }, + { "rotb", 14,24, 0x004e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "rotw", 14,24, 0x014e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "rotd", 14,24, 0x034e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "roundfb", 14,24, 0x243e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "roundfw", 14,24, 0x253e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "roundfd", 14,24, 0x273e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "roundlb", 14,24, 0x203e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "roundlw", 14,24, 0x213e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "roundld", 14,24, 0x233e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "rxp", 8,8, 0x32, "1d", 0, "", DEF_MODEC,DEF_MODEL }, + { "seqb", 11,16, 0x3c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "seqw", 11,16, 0x3d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "seqd", 11,16, 0x3f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sneb", 11,16, 0xbc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "snew", 11,16, 0xbd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sned", 11,16, 0xbf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "scsb", 11,16, 0x13c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "scsw", 11,16, 0x13d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "scsd", 11,16, 0x13f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sccb", 11,16, 0x1bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sccw", 11,16, 0x1bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sccd", 11,16, 0x1bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "shib", 11,16, 0x23c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "shiw", 11,16, 0x23d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "shid", 11,16, 0x23f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "slsb", 11,16, 0x2bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "slsw", 11,16, 0x2bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "slsd", 11,16, 0x2bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgtb", 11,16, 0x33c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgtw", 11,16, 0x33d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgtd", 11,16, 0x33f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sleb", 11,16, 0x3bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "slew", 11,16, 0x3bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sled", 11,16, 0x3bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsb", 11,16, 0x43c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsw", 11,16, 0x43d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsd", 11,16, 0x43f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfcb", 11,16, 0x4bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfcw", 11,16, 0x4bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfcd", 11,16, 0x4bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "slob", 11,16, 0x53c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "slow", 11,16, 0x53d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "slod", 11,16, 0x53f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "shsb", 11,16, 0x5bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "shsw", 11,16, 0x5bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "shsd", 11,16, 0x5bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sltb", 11,16, 0x63c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sltw", 11,16, 0x63d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sltd", 11,16, 0x63f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgeb", 11,16, 0x6bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sgew", 11,16, 0x6bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sged", 11,16, 0x6bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sutb", 11,16, 0x73c, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sutw", 11,16, 0x73d, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sutd", 11,16, 0x73f, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "sufb", 11,16, 0x7bc, "1B", 0, "", DEF_MODEC,DEF_MODEL }, + { "sufw", 11,16, 0x7bd, "1W", 0, "", DEF_MODEC,DEF_MODEL }, + { "sufd", 11,16, 0x7bf, "1D", 0, "", DEF_MODEC,DEF_MODEL }, + { "save", 8,8, 0x62, "1U", 0, "", DEF_MODEC,DEF_MODEL }, + { "sbitb", 14,24, 0x184e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "sbitw", 14,24, 0x194e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "sbitd", 14,24, 0x1b4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "sbitib", 14,24, 0x1c4e, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "sbitiw", 14,24, 0x1d4e, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "sbitid", 14,24, 0x1f4e, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "setcfg", 15,24, 0x0b0e, "1O", 0, "", DEF_MODEC,DEF_MODEL }, + { "sfsr", 14,24, 0x373e, "1f", 0, "", DEF_MODEC,DEF_MODEL }, + { "skpsb", 16,24, 0x0c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "skpsw", 16,24, 0x0d0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "skpsd", 16,24, 0x0f0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "skpst", 16,24, 0x8c0e, "1S", 0, "[]", DEF_MODEC,DEF_MODEL }, + { "smr", 15,24, 0x0f1e, "2I1M", 4, "", DEF_MODEC,DEF_MODEL }, + { "sprb", 7,16, 0x2c, "2I1P", 1, "", DEF_MODEC,DEF_MODEL }, + { "sprw", 7,16, 0x2d, "2I1P", 2, "", DEF_MODEC,DEF_MODEL }, + { "sprd", 7,16, 0x2f, "2I1P", 4, "", DEF_MODEC,DEF_MODEL }, + { "subf", 14,24, 0x11be, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "subl", 14,24, 0x10be, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "subb", 6,16, 0x20, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "subw", 6,16, 0x21, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "subd", 6,16, 0x23, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "subcb", 6,16, 0x30, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "subcw", 6,16, 0x31, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "subcd", 6,16, 0x33, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "subpb", 14,24, 0x2c4e, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "subpw", 14,24, 0x2d4e, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "subpd", 14,24, 0x2f4e, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, +#ifdef NS32K_SVC_IMMED_OPERANDS + { "svc", 8,8, 0xe2, "2i1i", 1, "", DEF_MODEC,DEF_MODEL }, /* not really, but some unix uses it */ +#else + { "svc", 8,8, 0xe2, "", 0, "", DEF_MODEC,DEF_MODEL }, +#endif + { "tbitb", 6,16, 0x34, "1B2A", 1, "", DEF_MODEC,DEF_MODEL }, + { "tbitw", 6,16, 0x35, "1W2A", 2, "", DEF_MODEC,DEF_MODEL }, + { "tbitd", 6,16, 0x37, "1D2A", 4, "", DEF_MODEC,DEF_MODEL }, + { "truncfb", 14,24, 0x2c3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "truncfw", 14,24, 0x2d3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "truncfd", 14,24, 0x2f3e, "1F2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "trunclb", 14,24, 0x283e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "trunclw", 14,24, 0x293e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "truncld", 14,24, 0x2b3e, "1L2I", 8, "", DEF_MODEC,DEF_MODEL }, + { "wait", 8,8, 0xb2, "", 0, "", DEF_MODEC,DEF_MODEL }, + { "wrval", 19,24, 0x0071e,"1A", 0, "", DEF_MODEC,DEF_MODEL }, + { "xorb", 6,16, 0x38, "1B2I", 1, "", DEF_MODEC,DEF_MODEL }, + { "xorw", 6,16, 0x39, "1W2I", 2, "", DEF_MODEC,DEF_MODEL }, + { "xord", 6,16, 0x3b, "1D2I", 4, "", DEF_MODEC,DEF_MODEL }, + { "dotf", 14,24, 0x0dfe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, + { "dotl", 14,24, 0x0cfe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, + { "logbf", 14,24, 0x15fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "logbl", 14,24, 0x14fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, + { "polyf", 14,24, 0x09fe, "1F2F", 4, "", DEF_MODEC,DEF_MODEL }, + { "polyl", 14,24, 0x08fe, "1L2L", 8, "", DEF_MODEC,DEF_MODEL }, + { "scalbf", 14,24, 0x11fe, "1F2Z", 4, "", DEF_MODEC,DEF_MODEL }, + { "scalbl", 14,24, 0x10fe, "1L2Z", 8, "", DEF_MODEC,DEF_MODEL }, +}; + +#define MAX_ARGS 4 +#define ARG_LEN 50 + diff --git a/include/opcode/or32.h b/include/opcode/or32.h new file mode 100644 index 000000000000..d72b9bda35f0 --- /dev/null +++ b/include/opcode/or32.h @@ -0,0 +1,180 @@ +/* Table of opcodes for the OpenRISC 1000 ISA. + Copyright 2002, 2003 Free Software Foundation, Inc. + Contributed by Damjan Lampret (lampret@opencores.org). + + This file is part of or1k_gen_isa, or1ksim, GDB and GAS. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* We treat all letters the same in encode/decode routines so + we need to assign some characteristics to them like signess etc. */ + +#ifndef OR32_H_ISA +#define OR32_H_ISA + +#define NUM_UNSIGNED (0) +#define NUM_SIGNED (1) + +#define MAX_GPRS 32 +#define PAGE_SIZE 4096 +#undef __HALF_WORD_INSN__ + +#define OPERAND_DELIM (',') + +#define OR32_IF_DELAY (1) +#define OR32_W_FLAG (2) +#define OR32_R_FLAG (4) + +struct or32_letter +{ + char letter; + int sign; + /* int reloc; relocation per letter ?? */ +}; + +/* Main instruction specification array. */ +struct or32_opcode +{ + /* Name of the instruction. */ + char *name; + + /* A string of characters which describe the operands. + Valid characters are: + ,() Itself. Characters appears in the assembly code. + rA Register operand. + rB Register operand. + rD Register operand. + I An immediate operand, range -32768 to 32767. + J An immediate operand, range . (unused) + K An immediate operand, range 0 to 65535. + L An immediate operand, range 0 to 63. + M An immediate operand, range . (unused) + N An immediate operand, range -33554432 to 33554431. + O An immediate operand, range . (unused). */ + char *args; + + /* Opcode and operand encoding. */ + char *encoding; + void (*exec) (void); + unsigned int flags; +}; + +#define OPTYPE_LAST (0x80000000) +#define OPTYPE_OP (0x40000000) +#define OPTYPE_REG (0x20000000) +#define OPTYPE_SIG (0x10000000) +#define OPTYPE_DIS (0x08000000) +#define OPTYPE_DST (0x04000000) +#define OPTYPE_SBIT (0x00001F00) +#define OPTYPE_SHR (0x0000001F) +#define OPTYPE_SBIT_SHR (8) + +/* MM: Data how to decode operands. */ +extern struct insn_op_struct +{ + unsigned long type; + unsigned long data; +} **op_start; + +#ifdef HAS_EXECUTION +extern void l_invalid (void); +extern void l_sfne (void); +extern void l_bf (void); +extern void l_add (void); +extern void l_sw (void); +extern void l_sb (void); +extern void l_sh (void); +extern void l_lwz (void); +extern void l_lbs (void); +extern void l_lbz (void); +extern void l_lhs (void); +extern void l_lhz (void); +extern void l_movhi (void); +extern void l_and (void); +extern void l_or (void); +extern void l_xor (void); +extern void l_sub (void); +extern void l_mul (void); +extern void l_div (void); +extern void l_divu (void); +extern void l_sll (void); +extern void l_sra (void); +extern void l_srl (void); +extern void l_j (void); +extern void l_jal (void); +extern void l_jalr (void); +extern void l_jr (void); +extern void l_rfe (void); +extern void l_nop (void); +extern void l_bnf (void); +extern void l_sfeq (void); +extern void l_sfgts (void); +extern void l_sfges (void); +extern void l_sflts (void); +extern void l_sfles (void); +extern void l_sfgtu (void); +extern void l_sfgeu (void); +extern void l_sfltu (void); +extern void l_sfleu (void); +extern void l_mtspr (void); +extern void l_mfspr (void); +extern void l_sys (void); +extern void l_trap (void); /* CZ 21/06/01. */ +extern void l_macrc (void); +extern void l_mac (void); +extern void l_msb (void); +extern void l_invalid (void); +extern void l_cust1 (void); +extern void l_cust2 (void); +extern void l_cust3 (void); +extern void l_cust4 (void); +#endif +extern void l_none (void); + +extern const struct or32_letter or32_letters[]; + +extern const struct or32_opcode or32_opcodes[]; + +extern const unsigned int or32_num_opcodes; + +/* Calculates instruction length in bytes. Always 4 for OR32. */ +extern int insn_len (int); + +/* Is individual insn's operand signed or unsigned? */ +extern int letter_signed (char); + +/* Number of letters in the individual lettered operand. */ +extern int letter_range (char); + +/* MM: Returns index of given instruction name. */ +extern int insn_index (char *); + +/* MM: Returns instruction name from index. */ +extern const char *insn_name (int); + +/* MM: Constructs new FSM, based on or32_opcodes. */ +extern void build_automata (void); + +/* MM: Destructs FSM. */ +extern void destruct_automata (void); + +/* MM: Decodes instruction using FSM. Call build_automata first. */ +extern int insn_decode (unsigned int); + +/* Disassemble one instruction from insn to disassemble. + Return the size of the instruction. */ +int disassemble_insn (unsigned long); + +#endif diff --git a/include/opcode/pdp11.h b/include/opcode/pdp11.h new file mode 100644 index 000000000000..228c221fc1bc --- /dev/null +++ b/include/opcode/pdp11.h @@ -0,0 +1,85 @@ +/* PDP-11 opcde list. + Copyright 2001, 2002 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +GDB and GAS are free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB and GAS are distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB or GAS; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* + * PDP-11 opcode types. + */ + +#define PDP11_OPCODE_NO_OPS 0 +#define PDP11_OPCODE_REG 1 /* register */ +#define PDP11_OPCODE_OP 2 /* generic operand */ +#define PDP11_OPCODE_REG_OP 3 /* register and generic operand */ +#define PDP11_OPCODE_REG_OP_REV 4 /* register and generic operand, + reversed syntax */ +#define PDP11_OPCODE_AC_FOP 5 /* fpu accumulator and generic float + operand */ +#define PDP11_OPCODE_OP_OP 6 /* two generic operands */ +#define PDP11_OPCODE_DISPL 7 /* pc-relative displacement */ +#define PDP11_OPCODE_REG_DISPL 8 /* redister and pc-relative + displacement */ +#define PDP11_OPCODE_IMM8 9 /* 8-bit immediate */ +#define PDP11_OPCODE_IMM6 10 /* 6-bit immediate */ +#define PDP11_OPCODE_IMM3 11 /* 3-bit immediate */ +#define PDP11_OPCODE_ILLEGAL 12 /* illegal instruction */ +#define PDP11_OPCODE_FOP_AC 13 /* generic float argument, then fpu + accumulator */ +#define PDP11_OPCODE_FOP 14 /* generic float operand */ +#define PDP11_OPCODE_AC_OP 15 /* fpu accumulator and generic int + operand */ +#define PDP11_OPCODE_OP_AC 16 /* generic int argument, then fpu + accumulator */ + +/* + * PDP-11 instruction set extensions. + * + * Please keep the numbers low, as they are used as indices into + * an array. + */ + +#define PDP11_NONE 0 /* not in instruction set */ +#define PDP11_BASIC 1 /* basic instruction set (11/20 etc) */ +#define PDP11_CSM 2 /* commercial instruction set */ +#define PDP11_CIS 3 /* commercial instruction set */ +#define PDP11_EIS 4 /* extended instruction set (11/45 etc) */ +#define PDP11_FIS 5 /* KEV11 floating-point instructions */ +#define PDP11_FPP 6 /* FP-11 floating-point instructions */ +#define PDP11_LEIS 7 /* limited extended instruction set + (11/40 etc) */ +#define PDP11_MFPT 8 /* move from processor type */ +#define PDP11_MPROC 9 /* multiprocessor instructions: tstset, + wrtlck */ +#define PDP11_MXPS 10 /* move from/to processor status */ +#define PDP11_SPL 11 /* set priority level */ +#define PDP11_UCODE 12 /* microcode instructions: ldub, med, xfc */ +#define PDP11_EXT_NUM 13 /* total number of extension types */ + +struct pdp11_opcode +{ + const char *name; + int opcode; + int mask; + int type; + int extension; +}; + +extern const struct pdp11_opcode pdp11_opcodes[]; +extern const struct pdp11_opcode pdp11_aliases[]; +extern const int pdp11_num_opcodes, pdp11_num_aliases; + +/* end of pdp11.h */ diff --git a/include/opcode/pj.h b/include/opcode/pj.h new file mode 100644 index 000000000000..f9e44dbef18a --- /dev/null +++ b/include/opcode/pj.h @@ -0,0 +1,49 @@ +/* Definitions for decoding the picoJava opcode table. + Copyright 1999, 2002, 2003 Free Software Foundation, Inc. + Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* Names used to describe the type of instruction arguments, used by + the assembler and disassembler. Attributes are encoded in various fields. */ + +/* reloc size pcrel uns */ +#define O_N 0 +#define O_16 (1<<4 | 2 | (0<<6) | (0<<3)) +#define O_U16 (1<<4 | 2 | (0<<6) | (1<<3)) +#define O_R16 (2<<4 | 2 | (1<<6) | (0<<3)) +#define O_8 (3<<4 | 1 | (0<<6) | (0<<3)) +#define O_U8 (3<<4 | 1 | (0<<6) | (1<<3)) +#define O_R8 (4<<4 | 1 | (0<<6) | (0<<3)) +#define O_R32 (5<<4 | 4 | (1<<6) | (0<<3)) +#define O_32 (6<<4 | 4 | (0<<6) | (0<<3)) + +#define ASIZE(x) ((x) & 0x7) +#define PCREL(x) (!!((x) & (1<<6))) +#define UNS(x) (!!((x) & (1<<3))) + + +typedef struct pj_opc_info_t +{ + short opcode; + short opcode_next; + char len; + unsigned char arg[2]; + union { + const char *name; + void (*func) (struct pj_opc_info_t *, char *); + } u; +} pj_opc_info_t; diff --git a/include/opcode/pyr.h b/include/opcode/pyr.h new file mode 100644 index 000000000000..d0bed6a47e2e --- /dev/null +++ b/include/opcode/pyr.h @@ -0,0 +1,305 @@ +/* pyramid.opcode.h -- gdb initial attempt. + + Copyright 2001 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* pyramid opcode table: wot to do with this + particular opcode */ + +struct pyr_datum +{ + char nargs; + char * args; /* how to compile said opcode */ + unsigned long mask; /* Bit vector: which operand modes are valid + for this opcode */ + unsigned char code; /* op-code (always 6(?) bits */ +}; + +typedef struct pyr_insn_format +{ + unsigned int mode :4; + unsigned int operator :8; + unsigned int index_scale :2; + unsigned int index_reg :6; + unsigned int operand_1 :6; + unsigned int operand_2:6; +} pyr_insn_format; + + +/* We store four bytes of opcode for all opcodes. + Pyramid is sufficiently RISCy that: + - insns are always an integral number of words; + - the length of any insn can be told from the first word of + the insn. (ie, if there are zero, one, or two words of + immediate operand/offset). + + + The args component is a string containing two characters for each + operand of the instruction. The first specifies the kind of operand; + the second, the place it is stored. */ + +/* Kinds of operands: + mask assembler syntax description + 0x0001: movw Rn,Rn register to register + 0x0002: movw K,Rn quick immediate to register + 0x0004: movw I,Rn long immediate to register + 0x0008: movw (Rn),Rn register indirect to register + movw (Rn)[x],Rn register indirect to register + 0x0010: movw I(Rn),Rn offset register indirect to register + movw I(Rn)[x],Rn offset register indirect, indexed, to register + + 0x0020: movw Rn,(Rn) register to register indirect + 0x0040: movw K,(Rn) quick immediate to register indirect + 0x0080: movw I,(Rn) long immediate to register indirect + 0x0100: movw (Rn),(Rn) register indirect to-register indirect + 0x0100: movw (Rn),(Rn) register indirect to-register indirect + 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect + 0x0200: movw I(Rn),(Rn) register indirect+offset to register indirect + + 0x0400: movw Rn,I(Rn) register to register indirect+offset + 0x0800: movw K,I(Rn) quick immediate to register indirect+offset + 0x1000: movw I,I(Rn) long immediate to register indirect+offset + 0x1000: movw (Rn),I(Rn) register indirect to-register indirect+offset + 0x1000: movw I(Rn),I(Rn) register indirect+offset to register indirect + +offset + 0x0000: (irregular) ??? + + + Each insn has a four-bit field encoding the type(s) of its operands. +*/ + +/* Some common combinations + */ + +/* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/ +#define GEN_TO_REG (31) + +#define UNKNOWN ((unsigned long)-1) +#define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15)) + +#define CONVERT (1|8|0x10|0x20|0x200) + +#define K_TO_REG (2) +#define I_TO_REG (4) +#define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG) +#define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG) + +/* The assembler requires that this array be sorted as follows: + all instances of the same mnemonic must be consecutive. + All instances of the same mnemonic with the same number of operands + must be consecutive. + */ + +struct pyr_opcode /* pyr opcode text */ +{ + char * name; /* opcode name: lowercase string [key] */ + struct pyr_datum datum; /* rest of opcode table [datum] */ +}; + +#define pyr_how args +#define pyr_nargs nargs +#define pyr_mask mask +#define pyr_name name + +struct pyr_opcode pyr_opcodes[] = +{ + {"movb", { 2, "", UNKNOWN, 0x11}, }, + {"movh", { 2, "", UNKNOWN, 0x12} }, + {"movw", { 2, "", ANY, 0x10} }, + {"movl", { 2, "", ANY, 0x13} }, + {"mnegw", { 2, "", (0x1|0x8|0x10), 0x14} }, + {"mnegf", { 2, "", 0x1, 0x15} }, + {"mnegd", { 2, "", 0x1, 0x16} }, + {"mcomw", { 2, "", (0x1|0x8|0x10), 0x17} }, + {"mabsw", { 2, "", (0x1|0x8|0x10), 0x18} }, + {"mabsf", { 2, "", 0x1, 0x19} }, + {"mabsd", { 2, "", 0x1, 0x1a} }, + {"mtstw", { 2, "", (0x1|0x8|0x10), 0x1c} }, + {"mtstf", { 2, "", 0x1, 0x1d} }, + {"mtstd", { 2, "", 0x1, 0x1e} }, + {"mova", { 2, "", 0x8|0x10, 0x1f} }, + {"movzbw", { 2, "", (0x1|0x8|0x10), 0x20} }, + {"movzhw", { 2, "", (0x1|0x8|0x10), 0x21} }, + /* 2 insns out of order here */ + {"movbl", { 2, "", 1, 0x4f} }, + {"filbl", { 2, "", 1, 0x4e} }, + + {"cvtbw", { 2, "", CONVERT, 0x22} }, + {"cvthw", { 2, "", CONVERT, 0x23} }, + {"cvtwb", { 2, "", CONVERT, 0x24} }, + {"cvtwh", { 2, "", CONVERT, 0x25} }, + {"cvtwf", { 2, "", CONVERT, 0x26} }, + {"cvtwd", { 2, "", CONVERT, 0x27} }, + {"cvtfw", { 2, "", CONVERT, 0x28} }, + {"cvtfd", { 2, "", CONVERT, 0x29} }, + {"cvtdw", { 2, "", CONVERT, 0x2a} }, + {"cvtdf", { 2, "", CONVERT, 0x2b} }, + + {"addw", { 2, "", GEN_TO_REG, 0x40} }, + {"addwc", { 2, "", GEN_TO_REG, 0x41} }, + {"subw", { 2, "", GEN_TO_REG, 0x42} }, + {"subwb", { 2, "", GEN_TO_REG, 0x43} }, + {"rsubw", { 2, "", GEN_TO_REG, 0x44} }, + {"mulw", { 2, "", GEN_TO_REG, 0x45} }, + {"emul", { 2, "", GEN_TO_REG, 0x47} }, + {"umulw", { 2, "", GEN_TO_REG, 0x46} }, + {"divw", { 2, "", GEN_TO_REG, 0x48} }, + {"ediv", { 2, "", GEN_TO_REG, 0x4a} }, + {"rdivw", { 2, "", GEN_TO_REG, 0x4b} }, + {"udivw", { 2, "", GEN_TO_REG, 0x49} }, + {"modw", { 2, "", GEN_TO_REG, 0x4c} }, + {"umodw", { 2, "", GEN_TO_REG, 0x4d} }, + + + {"addf", { 2, "", 1, 0x50} }, + {"addd", { 2, "", 1, 0x51} }, + {"subf", { 2, "", 1, 0x52} }, + {"subd", { 2, "", 1, 0x53} }, + {"mulf", { 2, "", 1, 0x56} }, + {"muld", { 2, "", 1, 0x57} }, + {"divf", { 2, "", 1, 0x58} }, + {"divd", { 2, "", 1, 0x59} }, + + + {"cmpb", { 2, "", UNKNOWN, 0x61} }, + {"cmph", { 2, "", UNKNOWN, 0x62} }, + {"cmpw", { 2, "", UNKNOWN, 0x60} }, + {"ucmpb", { 2, "", UNKNOWN, 0x66} }, + /* WHY no "ucmph"??? */ + {"ucmpw", { 2, "", UNKNOWN, 0x65} }, + {"xchw", { 2, "", UNKNOWN, 0x0f} }, + + + {"andw", { 2, "", GEN_TO_REG, 0x30} }, + {"orw", { 2, "", GEN_TO_REG, 0x31} }, + {"xorw", { 2, "", GEN_TO_REG, 0x32} }, + {"bicw", { 2, "", GEN_TO_REG, 0x33} }, + {"lshlw", { 2, "", GEN_TO_REG, 0x38} }, + {"ashlw", { 2, "", GEN_TO_REG, 0x3a} }, + {"ashll", { 2, "", GEN_TO_REG, 0x3c} }, + {"ashrw", { 2, "", GEN_TO_REG, 0x3b} }, + {"ashrl", { 2, "", GEN_TO_REG, 0x3d} }, + {"rotlw", { 2, "", GEN_TO_REG, 0x3e} }, + {"rotrw", { 2, "", GEN_TO_REG, 0x3f} }, + + /* push and pop insns are "going away next release". */ + {"pushw", { 2, "", GEN_TO_REG, 0x0c} }, + {"popw", { 2, "", (0x1|0x8|0x10), 0x0d} }, + {"pusha", { 2, "", (0x8|0x10), 0x0e} }, + + {"bitsw", { 2, "", UNKNOWN, 0x35} }, + {"bitcw", { 2, "", UNKNOWN, 0x36} }, + /* some kind of ibra/dbra insns??*/ + {"icmpw", { 2, "", UNKNOWN, 0x67} }, + {"dcmpw", { 2, "", (1|4|0x20|0x80|0x400|0x1000), 0x69} },/*FIXME*/ + {"acmpw", { 2, "", 1, 0x6b} }, + + /* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op + insn with a 2nd op of tr14. The assembler will have to grok this. */ + {"call", { 2, "", GEN_TO_REG, 0x04} }, + {"call", { 1, "", GEN_TO_REG, 0x04} }, + + {"callk", { 1, "", UNKNOWN, 0x06} },/* system call?*/ + /* Ret is usually written as a 0-op insn, but gets disassembled as a + 1-op insn. The operand is always tr15. */ + {"ret", { 0, "", UNKNOWN, 0x09} }, + {"ret", { 1, "", UNKNOWN, 0x09} }, + {"adsf", { 2, "", (1|2|4), 0x08} }, + {"retd", { 2, "", UNKNOWN, 0x0a} }, + {"btc", { 2, "", UNKNOWN, 0x01} }, + {"bfc", { 2, "", UNKNOWN, 0x02} }, + /* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */ + {"jump", { 1, "", UNKNOWN, 0x00} }, + {"btp", { 2, "", UNKNOWN, 0xf00} }, + /* read control-stack pointer is another 1-or-2 operand insn. */ + {"rcsp", { 2, "", UNKNOWN, 0x01f} }, + {"rcsp", { 1, "", UNKNOWN, 0x01f} } +}; + +/* end: pyramid.opcode.h */ +/* One day I will have to take the time to find out what operands + are valid for these insns, and guess at what they mean. + + I can't imagine what the "I???" insns (iglob, etc) do. + + the arithmetic-sounding insns ending in "p" sound awfully like BCD + arithmetic insns: + dshlp -> Decimal SHift Left Packed + dshrp -> Decimal SHift Right Packed + and cvtlp would be convert long to packed. + I have no idea how the operands are interpreted; but having them be + a long register with (address, length) of an in-memory packed BCD operand + would not be surprising. + They are unlikely to be a packed bcd string: 64 bits of long give + is only 15 digits+sign, which isn't enough for COBOL. + */ +#if 0 + {"wcsp", { 2, "", UNKNOWN, 0x00} }, /*write csp?*/ + /* The OSx Operating System Porting Guide claims SSL does things + with tr12 (a register reserved to it) to do with static block-structure + references. SSL=Set Static Link? It's "Going away next release". */ + {"ssl", { 2, "", UNKNOWN, 0x00} }, + {"ccmps", { 2, "", UNKNOWN, 0x00} }, + {"lcd", { 2, "", UNKNOWN, 0x00} }, + {"uemul", { 2, "", UNKNOWN, 0x00} }, /*unsigned emul*/ + {"srf", { 2, "", UNKNOWN, 0x00} }, /*Gidget time???*/ + {"mnegp", { 2, "", UNKNOWN, 0x00} }, /move-neg phys?*/ + {"ldp", { 2, "", UNKNOWN, 0x00} }, /*load phys?*/ + {"ldti", { 2, "", UNKNOWN, 0x00} }, + {"ldb", { 2, "", UNKNOWN, 0x00} }, + {"stp", { 2, "", UNKNOWN, 0x00} }, + {"stti", { 2, "", UNKNOWN, 0x00} }, + {"stb", { 2, "", UNKNOWN, 0x00} }, + {"stu", { 2, "", UNKNOWN, 0x00} }, + {"addp", { 2, "", UNKNOWN, 0x00} }, + {"subp", { 2, "", UNKNOWN, 0x00} }, + {"mulp", { 2, "", UNKNOWN, 0x00} }, + {"divp", { 2, "", UNKNOWN, 0x00} }, + {"dshlp", { 2, "", UNKNOWN, 0x00} }, /* dec shl packed? */ + {"dshrp", { 2, "", UNKNOWN, 0x00} }, /* dec shr packed? */ + {"movs", { 2, "", UNKNOWN, 0x00} }, /*move (string?)?*/ + {"cmpp", { 2, "", UNKNOWN, 0x00} }, /* cmp phys?*/ + {"cmps", { 2, "", UNKNOWN, 0x00} }, /* cmp (string?)?*/ + {"cvtlp", { 2, "", UNKNOWN, 0x00} }, /* cvt long to p??*/ + {"cvtpl", { 2, "", UNKNOWN, 0x00} }, /* cvt p to l??*/ + {"dintr", { 2, "", UNKNOWN, 0x00} }, /* ?? intr ?*/ + {"rphysw", { 2, "", UNKNOWN, 0x00} }, /* read phys word?*/ + {"wphysw", { 2, "", UNKNOWN, 0x00} }, /* write phys word?*/ + {"cmovs", { 2, "", UNKNOWN, 0x00} }, + {"rsubw", { 2, "", UNKNOWN, 0x00} }, + {"bicpsw", { 2, "", UNKNOWN, 0x00} }, /* clr bit in psw? */ + {"bispsw", { 2, "", UNKNOWN, 0x00} }, /* set bit in psw? */ + {"eio", { 2, "", UNKNOWN, 0x00} }, /* ?? ?io ? */ + {"callp", { 2, "", UNKNOWN, 0x00} }, /* call phys?*/ + {"callr", { 2, "", UNKNOWN, 0x00} }, + {"lpcxt", { 2, "", UNKNOWN, 0x00} }, /*load proc context*/ + {"rei", { 2, "", UNKNOWN, 0x00} }, /*ret from intrpt*/ + {"rport", { 2, "", UNKNOWN, 0x00} }, /*read-port?*/ + {"rtod", { 2, "", UNKNOWN, 0x00} }, /*read-time-of-day?*/ + {"ssi", { 2, "", UNKNOWN, 0x00} }, + {"vtpa", { 2, "", UNKNOWN, 0x00} }, /*virt-to-phys-addr?*/ + {"wicl", { 2, "", UNKNOWN, 0x00} }, /* write icl ? */ + {"wport", { 2, "", UNKNOWN, 0x00} }, /*write-port?*/ + {"wtod", { 2, "", UNKNOWN, 0x00} }, /*write-time-of-day?*/ + {"flic", { 2, "", UNKNOWN, 0x00} }, + {"iglob", { 2, "", UNKNOWN, 0x00} }, /* I global? */ + {"iphys", { 2, "", UNKNOWN, 0x00} }, /* I physical? */ + {"ipid", { 2, "", UNKNOWN, 0x00} }, /* I pid? */ + {"ivect", { 2, "", UNKNOWN, 0x00} }, /* I vector? */ + {"lamst", { 2, "", UNKNOWN, 0x00} }, + {"tio", { 2, "", UNKNOWN, 0x00} }, +#endif diff --git a/include/opcode/tahoe.h b/include/opcode/tahoe.h new file mode 100644 index 000000000000..b5cee249ee44 --- /dev/null +++ b/include/opcode/tahoe.h @@ -0,0 +1,213 @@ +/* + * Ported by the State University of New York at Buffalo by the Distributed + * Computer Systems Lab, Department of Computer Science, 1991. + */ + +#ifndef tahoe_opcodeT +#define tahoe_opcodeT int +#endif /* no tahoe_opcodeT */ + +struct vot_wot /* tahoe opcode table: wot to do with this */ + /* particular opcode */ +{ + char * args; /* how to compile said opcode */ + tahoe_opcodeT code; /* op-code (may be > 8 bits!) */ +}; + +struct vot /* tahoe opcode text */ +{ + char * name; /* opcode name: lowercase string [key] */ + struct vot_wot detail; /* rest of opcode table [datum] */ +}; + +#define vot_how args +#define vot_code code +#define vot_detail detail +#define vot_name name + +static struct vot +votstrs[] = +{ +{ "halt", {"", 0x00 } }, +{ "sinf", {"", 0x05 } }, +{ "ldf", {"rl", 0x06 } }, +{ "ldd", {"rq", 0x07 } }, +{ "addb2", {"rbmb", 0x08 } }, +{ "movb", {"rbwb", 0x09 } }, +{ "addw2", {"rwmw", 0x0a } }, +{ "movw", {"rwww", 0x0b } }, +{ "addl2", {"rlml", 0x0c } }, +{ "movl", {"rlwl", 0x0d } }, +{ "bbs", {"rlvlbw", 0x0e } }, +{ "nop", {"", 0x10 } }, +{ "brb", {"bb", 0x11 } }, +{ "brw", {"bw", 0x13 } }, +{ "cosf", {"", 0x15 } }, +{ "lnf", {"rl", 0x16 } }, +{ "lnd", {"rq", 0x17 } }, +{ "addb3", {"rbrbwb", 0x18 } }, +{ "cmpb", {"rbwb", 0x19 } }, +{ "addw3", {"rwrwww", 0x1a } }, +{ "cmpw", {"rwww", 0x1b } }, +{ "addl3", {"rlrlwl", 0x1c } }, +{ "cmpl", {"rlwl", 0x1d } }, +{ "bbc", {"rlvlbw", 0x1e } }, +{ "rei", {"", 0x20 } }, +{ "bneq", {"bb", 0x21 } }, +{ "bnequ", {"bb", 0x21 } }, +{ "cvtwl", {"rwwl", 0x23 } }, +{ "stf", {"wl", 0x26 } }, +{ "std", {"wq", 0x27 } }, +{ "subb2", {"rbmb", 0x28 } }, +{ "mcomb", {"rbwb", 0x29 } }, +{ "subw2", {"rwmw", 0x2a } }, +{ "mcomw", {"rwww", 0x2b } }, +{ "subl2", {"rlml", 0x2c } }, +{ "mcoml", {"rlwl", 0x2d } }, +{ "emul", {"rlrlrlwq", 0x2e } }, +{ "aoblss", {"rlmlbw", 0x2f } }, +{ "bpt", {"", 0x30 } }, +{ "beql", {"bb", 0x31 } }, +{ "beqlu", {"bb", 0x31 } }, +{ "cvtwb", {"rwwb", 0x33 } }, +{ "logf", {"", 0x35 } }, +{ "cmpf", {"rl", 0x36 } }, +{ "cmpd", {"rq", 0x37 } }, +{ "subb3", {"rbrbwb", 0x38 } }, +{ "bitb", {"rbrb", 0x39 } }, +{ "subw3", {"rwrwww", 0x3a } }, +{ "bitw", {"rwrw", 0x3b } }, +{ "subl3", {"rlrlwl", 0x3c } }, +{ "bitl", {"rlrl", 0x3d } }, +{ "ediv", {"rlrqwlwl", 0x3e } }, +{ "aobleq", {"rlmlbw", 0x3f } }, +{ "ret", {"", 0x40 } }, +{ "bgtr", {"bb", 0x41 } }, +{ "sqrtf", {"", 0x45 } }, +{ "cmpf2", {"rl", 0x46 } }, +{ "cmpd2", {"rqrq", 0x47 } }, +{ "shll", {"rbrlwl", 0x48 } }, +{ "clrb", {"wb", 0x49 } }, +{ "shlq", {"rbrqwq", 0x4a } }, +{ "clrw", {"ww", 0x4b } }, +{ "mull2", {"rlml", 0x4c } }, +{ "clrl", {"wl", 0x4d } }, +{ "shal", {"rbrlwl", 0x4e } }, +{ "bleq", {"bb", 0x51 } }, +{ "expf", {"", 0x55 } }, +{ "tstf", {"", 0x56 } }, +{ "tstd", {"", 0x57 } }, +{ "shrl", {"rbrlwl", 0x58 } }, +{ "tstb", {"rb", 0x59 } }, +{ "shrq", {"rbrqwq", 0x5a } }, +{ "tstw", {"rw", 0x5b } }, +{ "mull3", {"rlrlwl", 0x5c } }, +{ "tstl", {"rl", 0x5d } }, +{ "shar", {"rbrlwl", 0x5e } }, +{ "bbssi", {"rlmlbw", 0x5f } }, +{ "ldpctx", {"", 0x60 } }, +{ "pushd", {"", 0x67 } }, +{ "incb", {"mb", 0x69 } }, +{ "incw", {"mw", 0x6b } }, +{ "divl2", {"rlml", 0x6c } }, +{ "incl", {"ml", 0x6d } }, +{ "cvtlb", {"rlwb", 0x6f } }, +{ "svpctx", {"", 0x70 } }, +{ "jmp", {"ab", 0x71 } }, +{ "cvlf", {"rl", 0x76 } }, +{ "cvld", {"rl", 0x77 } }, +{ "decb", {"mb", 0x79 } }, +{ "decw", {"mw", 0x7b } }, +{ "divl3", {"rlrlwl", 0x7c } }, +{ "decl", {"ml", 0x7d } }, +{ "cvtlw", {"rlww", 0x7f } }, +{ "bgeq", {"bb", 0x81 } }, +{ "movs2", {"abab", 0x82 } }, +{ "cvfl", {"wl", 0x86 } }, +{ "cvdl", {"wl", 0x87 } }, +{ "orb2", {"rbmb", 0x88 } }, +{ "cvtbl", {"rbwl", 0x89 } }, +{ "orw2", {"rwmw", 0x8a } }, +{ "bispsw", {"rw", 0x8b } }, +{ "orl2", {"rlml", 0x8c } }, +{ "adwc", {"rlml", 0x8d } }, +{ "adda", {"rlml", 0x8e } }, +{ "blss", {"bb", 0x91 } }, +{ "cmps2", {"abab", 0x92 } }, +{ "ldfd", {"rl", 0x97 } }, +{ "orb3", {"rbrbwb", 0x98 } }, +{ "cvtbw", {"rbww", 0x99 } }, +{ "orw3", {"rwrwww", 0x9a } }, +{ "bicpsw", {"rw", 0x9b } }, +{ "orl3", {"rlrlwl", 0x9c } }, +{ "sbwc", {"rlml", 0x9d } }, +{ "suba", {"rlml", 0x9e } }, +{ "bgtru", {"bb", 0xa1 } }, +{ "cvdf", {"", 0xa6 } }, +{ "andb2", {"rbmb", 0xa8 } }, +{ "movzbl", {"rbwl", 0xa9 } }, +{ "andw2", {"rwmw", 0xaa } }, +{ "loadr", {"rwal", 0xab } }, +{ "andl2", {"rlml", 0xac } }, +{ "mtpr", {"rlrl", 0xad } }, +{ "ffs", {"rlwl", 0xae } }, +{ "blequ", {"bb", 0xb1 } }, +{ "negf", {"", 0xb6 } }, +{ "negd", {"", 0xb7 } }, +{ "andb3", {"rbrbwb", 0xb8 } }, +{ "movzbw", {"rbww", 0xb9 } }, +{ "andw3", {"rwrwww", 0xba } }, +{ "storer", {"rwal", 0xbb } }, +{ "andl3", {"rlrlwl", 0xbc } }, +{ "mfpr", {"rlwl", 0xbd } }, +{ "ffc", {"rlwl", 0xbe } }, +{ "calls", {"rbab", 0xbf } }, +{ "prober", {"rbabrl", 0xc0 } }, +{ "bvc", {"bb", 0xc1 } }, +{ "movs3", {"ababrw", 0xc2 } }, +{ "movzwl", {"rwwl", 0xc3 } }, +{ "addf", {"rl", 0xc6 } }, +{ "addd", {"rq", 0xc7 } }, +{ "xorb2", {"rbmb", 0xc8 } }, +{ "movob", {"rbwb", 0xc9 } }, +{ "xorw2", {"rwmw", 0xca } }, +{ "movow", {"rwww", 0xcb } }, +{ "xorl2", {"rlml", 0xcc } }, +{ "movpsl", {"wl", 0xcd } }, +{ "kcall", {"rw", 0xcf } }, +{ "probew", {"rbabrl", 0xd0 } }, +{ "bvs", {"bb", 0xd1 } }, +{ "cmps3", {"ababrw", 0xd2 } }, +{ "subf", {"rq", 0xd6 } }, +{ "subd", {"rq", 0xd7 } }, +{ "xorb3", {"rbrbwb", 0xd8 } }, +{ "pushb", {"rb", 0xd9 } }, +{ "xorw3", {"rwrwww", 0xda } }, +{ "pushw", {"rw", 0xdb } }, +{ "xorl3", {"rlrlwl", 0xdc } }, +{ "pushl", {"rl", 0xdd } }, +{ "insque", {"abab", 0xe0 } }, +{ "bcs", {"bb", 0xe1 } }, +{ "bgequ", {"bb", 0xe1 } }, +{ "mulf", {"rq", 0xe6 } }, +{ "muld", {"rq", 0xe7 } }, +{ "mnegb", {"rbwb", 0xe8 } }, +{ "movab", {"abwl", 0xe9 } }, +{ "mnegw", {"rwww", 0xea } }, +{ "movaw", {"awwl", 0xeb } }, +{ "mnegl", {"rlwl", 0xec } }, +{ "moval", {"alwl", 0xed } }, +{ "remque", {"ab", 0xf0 } }, +{ "bcc", {"bb", 0xf1 } }, +{ "blssu", {"bb", 0xf1 } }, +{ "divf", {"rq", 0xf6 } }, +{ "divd", {"rq", 0xf7 } }, +{ "movblk", {"alalrw", 0xf8 } }, +{ "pushab", {"ab", 0xf9 } }, +{ "pushaw", {"aw", 0xfb } }, +{ "casel", {"rlrlrl", 0xfc } }, +{ "pushal", {"al", 0xfd } }, +{ "callf", {"rbab", 0xfe } }, +{ "" , "" } /* empty is end sentinel */ + +}; diff --git a/include/opcode/tic30.h b/include/opcode/tic30.h new file mode 100644 index 000000000000..a70027591188 --- /dev/null +++ b/include/opcode/tic30.h @@ -0,0 +1,691 @@ +/* tic30.h -- Header file for TI TMS320C30 opcode table + Copyright 1998 Free Software Foundation, Inc. + Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a + header file. */ + +#ifndef _TMS320_H_ +#define _TMS320_H_ + +struct _register +{ + char *name; + unsigned char opcode; + unsigned char regtype; +}; + +typedef struct _register reg; + +#define REG_Rn 0x01 +#define REG_ARn 0x02 +#define REG_DP 0x03 +#define REG_OTHER 0x04 + +static const reg tic30_regtab[] = { + { "r0", 0x00, REG_Rn }, + { "r1", 0x01, REG_Rn }, + { "r2", 0x02, REG_Rn }, + { "r3", 0x03, REG_Rn }, + { "r4", 0x04, REG_Rn }, + { "r5", 0x05, REG_Rn }, + { "r6", 0x06, REG_Rn }, + { "r7", 0x07, REG_Rn }, + { "ar0",0x08, REG_ARn }, + { "ar1",0x09, REG_ARn }, + { "ar2",0x0A, REG_ARn }, + { "ar3",0x0B, REG_ARn }, + { "ar4",0x0C, REG_ARn }, + { "ar5",0x0D, REG_ARn }, + { "ar6",0x0E, REG_ARn }, + { "ar7",0x0F, REG_ARn }, + { "dp", 0x10, REG_DP }, + { "ir0",0x11, REG_OTHER }, + { "ir1",0x12, REG_OTHER }, + { "bk", 0x13, REG_OTHER }, + { "sp", 0x14, REG_OTHER }, + { "st", 0x15, REG_OTHER }, + { "ie", 0x16, REG_OTHER }, + { "if", 0x17, REG_OTHER }, + { "iof",0x18, REG_OTHER }, + { "rs", 0x19, REG_OTHER }, + { "re", 0x1A, REG_OTHER }, + { "rc", 0x1B, REG_OTHER }, + { "R0", 0x00, REG_Rn }, + { "R1", 0x01, REG_Rn }, + { "R2", 0x02, REG_Rn }, + { "R3", 0x03, REG_Rn }, + { "R4", 0x04, REG_Rn }, + { "R5", 0x05, REG_Rn }, + { "R6", 0x06, REG_Rn }, + { "R7", 0x07, REG_Rn }, + { "AR0",0x08, REG_ARn }, + { "AR1",0x09, REG_ARn }, + { "AR2",0x0A, REG_ARn }, + { "AR3",0x0B, REG_ARn }, + { "AR4",0x0C, REG_ARn }, + { "AR5",0x0D, REG_ARn }, + { "AR6",0x0E, REG_ARn }, + { "AR7",0x0F, REG_ARn }, + { "DP", 0x10, REG_DP }, + { "IR0",0x11, REG_OTHER }, + { "IR1",0x12, REG_OTHER }, + { "BK", 0x13, REG_OTHER }, + { "SP", 0x14, REG_OTHER }, + { "ST", 0x15, REG_OTHER }, + { "IE", 0x16, REG_OTHER }, + { "IF", 0x17, REG_OTHER }, + { "IOF",0x18, REG_OTHER }, + { "RS", 0x19, REG_OTHER }, + { "RE", 0x1A, REG_OTHER }, + { "RC", 0x1B, REG_OTHER }, + { "", 0, 0 } +}; + +static const reg *const tic30_regtab_end + = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]); + +/* Indirect Addressing Modes Modification Fields */ +/* Indirect Addressing with Displacement */ +#define PreDisp_Add 0x00 +#define PreDisp_Sub 0x01 +#define PreDisp_Add_Mod 0x02 +#define PreDisp_Sub_Mod 0x03 +#define PostDisp_Add_Mod 0x04 +#define PostDisp_Sub_Mod 0x05 +#define PostDisp_Add_Circ 0x06 +#define PostDisp_Sub_Circ 0x07 +/* Indirect Addressing with Index Register IR0 */ +#define PreIR0_Add 0x08 +#define PreIR0_Sub 0x09 +#define PreIR0_Add_Mod 0x0A +#define PreIR0_Sub_Mod 0x0B +#define PostIR0_Add_Mod 0x0C +#define PostIR0_Sub_Mod 0x0D +#define PostIR0_Add_Circ 0x0E +#define PostIR0_Sub_Circ 0x0F +/* Indirect Addressing with Index Register IR1 */ +#define PreIR1_Add 0x10 +#define PreIR1_Sub 0x11 +#define PreIR1_Add_Mod 0x12 +#define PreIR1_Sub_Mod 0x13 +#define PostIR1_Add_Mod 0x14 +#define PostIR1_Sub_Mod 0x15 +#define PostIR1_Add_Circ 0x16 +#define PostIR1_Sub_Circ 0x17 +/* Indirect Addressing (Special Cases) */ +#define IndirectOnly 0x18 +#define PostIR0_Add_BitRev 0x19 + +typedef struct { + char *syntax; + unsigned char modfield; + unsigned char displacement; +} ind_addr_type; + +#define IMPLIED_DISP 0x01 +#define DISP_REQUIRED 0x02 +#define NO_DISP 0x03 + +static const ind_addr_type tic30_indaddr_tab[] = { + { "*+ar", PreDisp_Add, IMPLIED_DISP }, + { "*-ar", PreDisp_Sub, IMPLIED_DISP }, + { "*++ar", PreDisp_Add_Mod, IMPLIED_DISP }, + { "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP }, + { "*ar++", PostDisp_Add_Mod, IMPLIED_DISP }, + { "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP }, + { "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP }, + { "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP }, + { "*+ar()", PreDisp_Add, DISP_REQUIRED }, + { "*-ar()", PreDisp_Sub, DISP_REQUIRED }, + { "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED }, + { "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED }, + { "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED }, + { "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED }, + { "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED }, + { "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED }, + { "*+ar(ir0)", PreIR0_Add, NO_DISP }, + { "*-ar(ir0)", PreIR0_Sub, NO_DISP }, + { "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP }, + { "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP }, + { "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP }, + { "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP }, + { "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP }, + { "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP }, + { "*+ar(ir1)", PreIR1_Add, NO_DISP }, + { "*-ar(ir1)", PreIR1_Sub, NO_DISP }, + { "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP }, + { "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP }, + { "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP }, + { "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP }, + { "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP }, + { "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP }, + { "*ar", IndirectOnly, NO_DISP }, + { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP }, + { "", 0,0 } +}; + +static const ind_addr_type *const tic30_indaddrtab_end + = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]); + +/* Possible operand types */ +/* Register types */ +#define Rn 0x0001 +#define ARn 0x0002 +#define DPReg 0x0004 +#define OtherReg 0x0008 +/* Addressing mode types */ +#define Direct 0x0010 +#define Indirect 0x0020 +#define Imm16 0x0040 +#define Disp 0x0080 +#define Imm24 0x0100 +#define Abs24 0x0200 +/* 3 operand addressing mode types */ +#define op3T1 0x0400 +#define op3T2 0x0800 +/* Interrupt vector */ +#define IVector 0x1000 +/* Not required */ +#define NotReq 0x2000 + +#define GAddr1 Rn | Direct | Indirect | Imm16 +#define GAddr2 GAddr1 | AllReg +#define TAddr1 op3T1 | Rn | Indirect +#define TAddr2 op3T2 | Rn | Indirect +#define Reg Rn | ARn +#define AllReg Reg | DPReg | OtherReg + +typedef struct _template +{ + char *name; + unsigned int operands; /* how many operands */ + unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */ + /* the bits in opcode_modifier are used to generate the final opcode from + the base_opcode. These bits also are used to detect alternate forms of + the same instruction */ + unsigned int opcode_modifier; + + /* opcode_modifier bits: */ +#define AddressMode 0x00600000 +#define PCRel 0x02000000 +#define StackOp 0x001F0000 +#define Rotate StackOp + + /* operand_types[i] describes the type of operand i. This is made + by OR'ing together all of the possible type masks. (e.g. + 'operand_types[i] = Reg|Imm' specifies that operand i can be + either a register or an immediate operand */ + unsigned int operand_types[3]; + /* This defines the number type of an immediate argument to an instruction. */ + int imm_arg_type; +#define Imm_None 0 +#define Imm_Float 1 +#define Imm_SInt 2 +#define Imm_UInt 3 +} +template; + +static const template tic30_optab[] = { + { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, + { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, + { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None }, + { "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, + { "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, + { "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float }, + { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }, + { "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None }, + { "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None }, + { "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None }, + { "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None }, + { "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt }, + { "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ + { "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None }, + { "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/ + { "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None }, + { "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None }, + { "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None }, + { "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None }, + { "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, + { "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, + { "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, + { "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None }, + { "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None }, + { "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, + { "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, + { "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, + { "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, + { "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None }, + { "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, + { "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, + { "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, + { "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, + { "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, + { "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, + { "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, + { "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None }, + { "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None }, + { "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None }, + { "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None }, + { "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, + { "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, + { "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None }, + { "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None }, + { "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None }, + { "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None }, + { "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None }, + { "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, + { "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, + { "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, + { "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None }, + { "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None }, + { "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, + { "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, + { "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, + { "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, + { "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None }, + { "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, + { "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, + { "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, + { "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, + { "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, + { "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, + { "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None }, + { "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None }, + { "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None }, + { "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, + { "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, + { "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None }, + { "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None }, + { "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None }, + { "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None }, + { "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None }, + { "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, + { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt }, + { "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt }, + { "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None }, + { "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, + { "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, + { "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, + { "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, + { "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, + { "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, + { "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, + { "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None }, + { "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, + { "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, + { "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, + { "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None }, + { "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None }, + { "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, + { "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, + { "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, + { "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, + { "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None }, + { "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, + { "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, + { "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, + { "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, + { "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None }, + { "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None }, + { "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None }, + { "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None }, + { "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None }, + { "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, + { "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, + { "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, + { "" ,0,0x00000000,0, { 0, 0, 0 }, 0 } +}; + +static const template *const tic30_optab_end = + tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]); + +typedef struct { + char *name; + unsigned int operands_1; + unsigned int operands_2; + unsigned int base_opcode; + unsigned int operand_types[2][3]; + /* Which operand fits into which part of the final opcode word. */ + int oporder; +} partemplate; + +/* oporder defines - not very descriptive. */ +#define OO_4op1 0 +#define OO_4op2 1 +#define OO_4op3 2 +#define OO_5op1 3 +#define OO_5op2 4 +#define OO_PField 5 + +static const partemplate tic30_paroptab[] = { + { "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, + OO_4op2 }, + { "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, + OO_4op2 }, + { "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn }, + { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, + { "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, + OO_4op1 }, + { "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, + OO_4op3 }, + { "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, + OO_4op3 }, + { "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, + OO_5op2 }, + { "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, + OO_5op1 }, + { "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 } +}; + +static const partemplate *const tic30_paroptab_end = + tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]); + +#endif diff --git a/include/opcode/tic4x.h b/include/opcode/tic4x.h new file mode 100644 index 000000000000..0e6af6460a77 --- /dev/null +++ b/include/opcode/tic4x.h @@ -0,0 +1,1079 @@ +/* Table of opcodes for the Texas Instruments TMS320C[34]X family. + + Copyright (C) 2002, 2003 Free Software Foundation. + + Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +*/ + +#define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33) +#define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44) + +/* Define some bitfield extraction/insertion macros. */ +#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l)))) +#define EXTRU(inst, m, l) EXTR ((unsigned long)(inst), (m), (l)) +#define EXTRS(inst, m, l) EXTR ((long)(inst), (m), (l)) +#define INSERTU(inst, val, m, l) (inst |= ((val) << (l))) +#define INSERTS(inst, val, m, l) INSERTU (inst, ((val) & ((1 << ((m) - (l) + 1)) - 1)), m, l) + +/* Define register numbers. */ +typedef enum + { + REG_R0, REG_R1, REG_R2, REG_R3, + REG_R4, REG_R5, REG_R6, REG_R7, + REG_AR0, REG_AR1, REG_AR2, REG_AR3, + REG_AR4, REG_AR5, REG_AR6, REG_AR7, + REG_DP, REG_IR0, REG_IR1, REG_BK, + REG_SP, REG_ST, REG_DIE, REG_IIE, + REG_IIF, REG_RS, REG_RE, REG_RC, + REG_R8, REG_R9, REG_R10, REG_R11, + REG_IVTP, REG_TVTP + } +c4x_reg_t; + +/* Note that the actual register numbers for IVTP is 0 and TVTP is 1. */ + +#define REG_IE REG_DIE /* C3x only */ +#define REG_IF REG_IIE /* C3x only */ +#define REG_IOF REG_IIF /* C3x only */ + +#define TIC3X_REG_MAX REG_RC +#define TIC4X_REG_MAX REG_TVTP + +/* Register table size including C4x expansion regs. */ +#define REG_TABLE_SIZE (TIC4X_REG_MAX + 1) + +struct tic4x_register +{ + char * name; + unsigned long regno; +}; + +typedef struct tic4x_register tic4x_register_t; + +/* We could store register synonyms here. */ +static const tic4x_register_t tic3x_registers[] = +{ + {"f0", REG_R0}, + {"r0", REG_R0}, + {"f1", REG_R1}, + {"r1", REG_R1}, + {"f2", REG_R2}, + {"r2", REG_R2}, + {"f3", REG_R3}, + {"r3", REG_R3}, + {"f4", REG_R4}, + {"r4", REG_R4}, + {"f5", REG_R5}, + {"r5", REG_R5}, + {"f6", REG_R6}, + {"r6", REG_R6}, + {"f7", REG_R7}, + {"r7", REG_R7}, + {"ar0", REG_AR0}, + {"ar1", REG_AR1}, + {"ar2", REG_AR2}, + {"ar3", REG_AR3}, + {"ar4", REG_AR4}, + {"ar5", REG_AR5}, + {"ar6", REG_AR6}, + {"ar7", REG_AR7}, + {"dp", REG_DP}, + {"ir0", REG_IR0}, + {"ir1", REG_IR1}, + {"bk", REG_BK}, + {"sp", REG_SP}, + {"st", REG_ST}, + {"ie", REG_IE}, + {"if", REG_IF}, + {"iof", REG_IOF}, + {"rs", REG_RS}, + {"re", REG_RE}, + {"rc", REG_RC}, + {"", 0} +}; + +const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1); + +/* Define C4x registers in addition to C3x registers. */ +static const tic4x_register_t tic4x_registers[] = +{ + {"die", REG_DIE}, /* Clobbers C3x REG_IE */ + {"iie", REG_IIE}, /* Clobbers C3x REG_IF */ + {"iif", REG_IIF}, /* Clobbers C3x REG_IOF */ + {"f8", REG_R8}, + {"r8", REG_R8}, + {"f9", REG_R9}, + {"r9", REG_R9}, + {"f10", REG_R10}, + {"r10", REG_R10}, + {"f11", REG_R11}, + {"r11", REG_R11}, + {"ivtp", REG_IVTP}, + {"tvtp", REG_TVTP}, + {"", 0} +}; + +const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1); + +struct tic4x_cond +{ + char * name; + unsigned long cond; +}; + +typedef struct tic4x_cond tic4x_cond_t; + +/* Define conditional branch/load suffixes. Put desired form for + disassembler last. */ +static const tic4x_cond_t tic4x_conds[] = +{ + { "u", 0x00 }, + { "c", 0x01 }, { "lo", 0x01 }, + { "ls", 0x02 }, + { "hi", 0x03 }, + { "nc", 0x04 }, { "hs", 0x04 }, + { "z", 0x05 }, { "eq", 0x05 }, + { "nz", 0x06 }, { "ne", 0x06 }, + { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 }, + { "le", 0x08 }, + { "p", 0x09 }, { "gt", 0x09 }, + { "nn", 0x0a }, { "ge", 0x0a }, + { "nv", 0x0c }, + { "v", 0x0d }, + { "nuf", 0x0e }, + { "uf", 0x0f }, + { "nlv", 0x10 }, + { "lv", 0x11 }, + { "nluf", 0x12 }, + { "luf", 0x13 }, + { "zuf", 0x14 }, + /* Dummy entry, not included in num_conds. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", 0x0} +}; + +const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1); + +struct tic4x_indirect +{ + char * name; + unsigned long modn; +}; + +typedef struct tic4x_indirect tic4x_indirect_t; + +/* Define indirect addressing modes where: + d displacement (signed) + y ir0 + z ir1 */ + +static const tic4x_indirect_t tic4x_indirects[] = +{ + { "*+a(d)", 0x00 }, + { "*-a(d)", 0x01 }, + { "*++a(d)", 0x02 }, + { "*--a(d)", 0x03 }, + { "*a++(d)", 0x04 }, + { "*a--(d)", 0x05 }, + { "*a++(d)%", 0x06 }, + { "*a--(d)%", 0x07 }, + { "*+a(y)", 0x08 }, + { "*-a(y)", 0x09 }, + { "*++a(y)", 0x0a }, + { "*--a(y)", 0x0b }, + { "*a++(y)", 0x0c }, + { "*a--(y)", 0x0d }, + { "*a++(y)%", 0x0e }, + { "*a--(y)%", 0x0f }, + { "*+a(z)", 0x10 }, + { "*-a(z)", 0x11 }, + { "*++a(z)", 0x12 }, + { "*--a(z)", 0x13 }, + { "*a++(z)", 0x14 }, + { "*a--(z)", 0x15 }, + { "*a++(z)%", 0x16 }, + { "*a--(z)%", 0x17 }, + { "*a", 0x18 }, + { "*a++(y)b", 0x19 }, + /* Dummy entry, not included in num_indirects. This + lets code examine entry i+1 without checking + if we've run off the end of the table. */ + { "", 0x0} +}; + +#define TIC3X_MODN_MAX 0x19 + +const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1); + +/* Instruction template. */ +struct tic4x_inst +{ + char * name; + unsigned long opcode; + unsigned long opmask; + char * args; + unsigned long oplevel; +}; + +typedef struct tic4x_inst tic4x_inst_t; + +/* Opcode infix + B condition 16--20 U,C,Z,LO,HI, etc. + C condition 23--27 U,C,Z,LO,HI, etc. + + Arguments + , required arg follows + ; optional arg follows + + Argument types bits [classes] - example + ----------------------------------------------------------- + * indirect (all) 0--15 [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0) + # direct (for LDP) 0--15 [Z] - @start, start + @ direct 0--15 [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start + A address register 22--24 [D] - AR0, AR7 + B unsigned integer 0--23 [I,I2] - @start, start (absolute on C3x, relative on C4x) + C indirect (disp - C4x) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(5) + E register (all) 0--7 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP + e register (0-11) 0--7 [S,SC,S2] - R0, R7, R11 + F short float immediate 0--15 [AF,B,BA,BB] - 3.5, 0e-3.5e-1 + G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP + g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11 + H register (0-7) 18--16 [LS,M,P,Q] - R0, R7 + I indirect (no disp) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0) + i indirect (enhanced) 0--7 [LL,LS,M,P,Q,QC] - *+AR0(1), R5 + J indirect (no disp) 8--15 [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0) + j indirect (enhanced) 8--15 [M] - *+AR0(1), R5 + K register 19--21 [LL,M,Q,QC] - R0, R7 + L register 22--24 [LL,LS,P,Q,QC] - R0, R7 + M register (R2,R3) 22--22 [M] R2, R3 + N register (R0,R1) 23--23 [M] R0, R1 + O indirect(disp - C4x) 8--15 [S,SC,S2,T,TC,T2] - *+AR0(5) + P displacement (PC Rel) 0--15 [D,J,JS] - @start, start + Q register (all) 0--15 [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP + q register (0-11) 0--15 [AF,B,BB] - R0, R7, R11 + R register (all) 16--20 [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP + r register (0-11) 16--20 [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11 + S short int immediate 0--15 [A,AB,AY,BI] - -5, 5 + T integer (C4x) 16--20 [Z] - -5, 12 + U unsigned integer 0--15 [AU,A3] - 0, 65535 + V vector (C4x: 0--8) 0--4 [Z] - 25, 7 + W short int (C4x) 0--7 [T,TC,T2,T2C] - -3, 5 + X expansion reg (C4x) 0--4 [Z] - IVTP, TVTP + Y address reg (C4x) 16--20 [Z] - AR0, DP, SP, IR0 + Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP +*/ + +#define TIC4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */ +#define TIC4X_NAME_MAX 16 /* Max number of chars in parallel name. */ + +/* Define the instruction level */ +#define OP_C3X 0x1 /* C30 support - supported by all */ +#define OP_C4X 0x2 /* C40 support - C40, C44 */ +#define OP_ENH 0x4 /* Class LL,LS,M,P,Q,QC enhancements. Argument type + I and J is enhanced in these classes - C31>=6.0, + C32>=2.0, C33 */ +#define OP_LPWR 0x8 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0, + LC31, C31>=5.0, C32 */ +#define OP_IDLE2 0x10 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0, + C32, C33, C40>=5.0, C44 */ + +/* The following class definition is a classification scheme for + putting instructions with similar type of arguments together. It + simplifies the op-code definitions significantly, as we then only + need to use the class macroes for 95% of the DSP's opcodes. +*/ + +/* A: General 2-operand integer operations + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register (R) + Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI, + SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn, + MBn, MHn, MPYSHI, MPYUHI +*/ +#define A_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ + { name, opcode|0x00600000, 0xffe00000, "S,R", level } + +/* AB: General 2-operand integer operation with condition + Syntax: <i>c src, dst + c = Condition + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register (R) + Instr: 1/0 - LDIc +*/ +#define AB_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \ + { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \ + { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \ + { name, opcode|0x40600000, 0xf0600000, "S,R", level } + +/* AU: General 2-operand unsigned integer operation + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) + dst = Register (R) + Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn +*/ +#define AU_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ + { name, opcode|0x00600000, 0xffe00000, "U,R", level } + +/* AF: General 2-operand float to integer operation + Syntax: <i> src, dst + src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) + dst = Register (R) + Instr: 1/0 - FIX +*/ +#define AF_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \ + { name, opcode|0x00600000, 0xffe00000, "F,R", level } + +/* A2: Limited 1-operand (integer) operation + Syntax: <i> src + src = Register (Q), Indirect (*), None + Instr: 1/0 - NOP +*/ +#define A2_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*", level }, \ + { name, opcode|0x00000000, 0xffe00000, "" , level } + +/* A3: General 1-operand unsigned integer operation + Syntax: <i> src + src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U) + Instr: 1/0 - RPTS +*/ +#define A3_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffff0000, "Q", level }, \ + { name, opcode|0x00200000, 0xffff0000, "@", level }, \ + { name, opcode|0x00400000, 0xffff0000, "*", level }, \ + { name, opcode|0x00600000, 0xffff0000, "U", level } + +/* A6: Limited 2-operand integer operation + Syntax: <i> src, dst + src = Direct (@), Indirect (*) + dst = Register (R) + Instr: 1/1 - LDII, C4x: SIGI +*/ +#define A6_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,R", level } + +/* A7: Limited 2-operand integer store operation + Syntax: <i> src, dst + src = Register (R) + dst = Direct (@), Indirect (*) + Instr: 2/0 - STI, STII +*/ +#define A7_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \ + { name, opcode|0x00400000, 0xffe00000, "R,*", level } + +/* AY: General 2-operand signed address load operation + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Address register - ARx, IRx, DP, BK, SP (Y) + Instr: 0/1 - C4x: LDA + Note: Q and Y should *never* be the same register +*/ +#define AY_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \ + { name, opcode|0x00600000, 0xffe00000, "S,Y", level } + +/* B: General 2-operand float operation + Syntax: <i> src, dst + src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (r) + Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND, + SUBF, SUBRF, C4x: RSQRF, TOIEEE +*/ +#define B_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ + { name, opcode|0x00600000, 0xffe00000, "F,r", level } + +/* BA: General 2-operand integer to float operation + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (r) + Instr: 0/1 - C4x: CRCPF +*/ +#define BA_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ + { name, opcode|0x00600000, 0xffe00000, "F,r", level } + +/* BB: General 2-operand conditional float operation + Syntax: <i>c src, dst + c = Condition + src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F) + dst = Register 0-11 (r) + Instr: 1/0 - LDFc +*/ +#define BB_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \ + { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \ + { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \ + { name, opcode|0x40600000, 0xf0600000, "F,r", level } + +/* BI: General 2-operand integer to float operation (yet different to BA) + Syntax: <i> src, dst + src = Register (Q), Direct (@), Indirect (*), Signed immediate (S) + dst = Register 0-11 (r) + Instr: 1/0 - FLOAT +*/ +#define BI_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \ + { name, opcode|0x00600000, 0xffe00000, "S,r", level } + +/* B6: Limited 2-operand float operation + Syntax: <i> src, dst + src = Direct (@), Indirect (*) + dst = Register 0-11 (r) + Instr: 1/1 - LDFI, C4x: FRIEEE +*/ +#define B6_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \ + { name, opcode|0x00400000, 0xffe00000, "*,r", level } + +/* B7: Limited 2-operand float store operation + Syntax: <i> src, dst + src = Register 0-11 (r) + dst = Direct (@), Indirect (*) + Instr: 2/0 - STF, STFI +*/ +#define B7_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \ + { name, opcode|0x00400000, 0xffe00000, "r,*", level } + +/* D: Decrement and brach operations + Syntax: <i>c ARn, dst + c = condition + ARn = AR register 0-7 (A) + dst = Register (Q), PC-relative (P) + Instr: 2/0 - DBc, DBcD + Alias: <name1> <name2> +*/ +#define D_CLASS_INSN(name1, name2, opcode, level) \ + { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \ + { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \ + { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \ + { name2, opcode|0x02000000, 0xfe200000, "A,P", level } + +/* I: General branch operations + Syntax: <i> dst + dst = Address (B) + Instr: 3/1 - BR, BRD, CALL, C4x: LAJ +*/ + +/* I2: General branch operations (C4x addition) + Syntax: <i> dst + dst = Address (B), C4x: Register (Q) + Instr: 2/0 - RPTB, RPTBD +*/ + +/* J: General conditional branch operations + Syntax: <i>c dst + c = Condition + dst = Register (Q), PC-relative (P) + Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc + Alias: <name1> <name2> +*/ +#define J_CLASS_INSN(name1, name2, opcode, level) \ + { name1, opcode|0x00000000, 0xffe00000, "Q", level }, \ + { name1, opcode|0x02000000, 0xffe00000, "P", level }, \ + { name2, opcode|0x00000000, 0xffe00000, "Q", level }, \ + { name2, opcode|0x02000000, 0xffe00000, "P", level } + +/* JS: General conditional branch operations + Syntax: <i>c dst + c = Condition + dst = Register (Q), PC-relative (P) + Instr: 1/1 - CALLc, C4X: LAJc +*/ + +/* LL: Load-load parallell operation + Syntax: <i> src2, dst2 || <i> src1, dst1 + src1 = Indirect 0,1,IR0,IR1 (J) + dst1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1, ENH: Register (i) + dst2 = Register 0-7 (L) + Instr: 2/0 - LDF||LDF, LDI||LDI + Alias: i||i, i1||i2, i2||i1 +*/ +#define LL_CLASS_INSN(name, opcode, level) \ + { name "_" name , opcode, 0xfe000000, "i;L|J,K", level }, \ + { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \ + { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level } + +/* LS: Store-store parallell operation + Syntax: <i> src2, dst2 || <i> src1, dst1 + src1 = Register 0-7 (H) + dst1 = Indirect 0,1,IR0,IR1 (J) + src2 = Register 0-7 (L) + dst2 = Indirect 0,1,IR0,IR1, ENH: register (i) + Instr: 2/0 - STF||STF, STI||STI + Alias: i||i, i1||i2, i2||i1. +*/ +#define LS_CLASS_INSN(name, opcode, level) \ + { name "_" name , opcode, 0xfe000000, "L;i|H,J", level }, \ + { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \ + { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level } + +/* M: General multiply and add/sub operations + Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual + <ia> src3,src1,dst1 || <ib> src2,src4,dst2 [01] - Manual + <ia> src1,src3,dst1 || <ib> src2,src4,dst2 [01] + <ia> src1,src2,dst1 || <ib> src4,src3,dst2 [02] - Manual + <ia> src3,src1,dst1 || <ib> src4,src2,dst2 [03] - Manual + <ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03] + src1 = Register 0-7 (K) + src2 = Register 0-7 (H) + src3 = Indirect 0,1,IR0,IR1, ENH: register (j) + src4 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-1 (N) + dst2 = Register 2-3 (M) + Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3 + Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3 +*/ +#define M_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \ + { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \ + { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \ + { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \ + { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \ + { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \ + { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ + { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ + { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \ + { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \ + { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \ + { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \ + { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \ + { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \ + { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level } + +/* P: General 2-operand operation with parallell store + Syntax: <ia> src2, dst1 || <ib> src3, dst2 + src2 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 9/2 - ABSF||STF, ABSI||STI, FIX||STI, FLOAT||STF, LDF||STF, + LDI||STI, NEGF||STF, NEGI||STI, NOT||STI, C4x: FRIEEE||STF, + TOIEEE||STF + Alias: a||b, b||a +*/ +#define P_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \ + { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level } + +/* Q: General 3-operand operation with parallell store + Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2 + src1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI + Alias: a||b, b||a, a3||b, b||a3 +*/ +#define Q_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \ + { nameb "_" namea , opcode, 0xfe000000, "H,J|K,i;L", level }, \ + { namea "3_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \ + { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,i;L", level } + +/* QC: General commutative 3-operand operation with parallell store + Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2 + <ia> src1, src2, dst1 || <ib> src3, dst2 - Manual + src1 = Register 0-7 (K) + src2 = Indirect 0,1,IR0,IR1, ENH: register (i) + dst1 = Register 0-7 (L) + src3 = Register 0-7 (H) + dst2 = Indirect 0,1,IR0,IR1 (J) + Instr: 7/0 - ADDF3||STF, ADDI3||STI, AND3||STI, MPYF3||STF, MPYI3||STI, + OR3||STI, XOR3||STI + Alias: a||b, b||a, a3||b, b||a3 +*/ +#define QC_CLASS_INSN(namea, nameb, opcode, level) \ + { namea "_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \ + { namea "_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \ + { nameb "_" namea , opcode, 0xfe000000, "H,J|i;K;L", level }, \ + { nameb "_" namea , opcode, 0xfe000000, "H,J|K;i;L", level }, \ + { namea "3_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \ + { namea "3_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \ + { nameb "_" namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \ + { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K;i;L", level } + +/* R: General register integer operation + Syntax: <i> dst + dst = Register (R) + Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC +*/ +#define R_CLASS_INSN(name, opcode, level) \ + { name, opcode, 0xffe0ffff, "R", level } + +/* RF: General register float operation + Syntax: <i> dst + dst = Register 0-11 (r) + Instr: 2/0 - POPF, PUSHF +*/ +#define RF_CLASS_INSN(name, opcode, level) \ + { name, opcode, 0xffe0ffff, "r", level } + +/* S: General 3-operand float operation + Syntax: <i> src2, src1, dst + src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register 0-11 (r) + Instr: 1/0 - SUBF3 + Alias: i, i3 +*/ +#define S_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X } + +/* SC: General commutative 3-operand float operation + Syntax: <i> src2, src1, dst - Manual + <i> src1, src2, dst + src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register 0-11 (r) + Instr: 2/0 - ADDF3, MPYF3 + Alias: i, i3 +*/ +#define SC_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name, opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name, opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "e,g;r", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "e,J,r", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,g;r", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,r", level }, \ + { name "3", opcode|0x30200000, 0xffe00000, "g,C,r", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,g;r", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,r", OP_C4X } + +/* S2: General 3-operand float operation with 2 args + Syntax: <i> src2, src1 + src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C) + src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + Instr: 1/0 - CMPF3 + Alias: i, i3 +*/ +#define S2_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "e,g", level }, \ + { name, opcode|0x20200000, 0xffe00000, "e,J", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,g", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name, opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "e,g", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "e,J", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,g", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,g", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } + +/* T: General 3-operand integer operand + Syntax: <i> src2, src1, dst + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register (R) + Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3 + Alias: i, i3 +*/ +#define T_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X } + +/* TC: General commutative 3-operand integer operation + Syntax: <i> src2, src1, dst + <i> src1, src2, dst + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + dst = Register (R) + Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI + Alias: i, i3 +*/ +#define TC_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name, opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G;R", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J,R", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G;R", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J,R", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G;R", OP_C4X }, \ + { name "3", opcode|0x30000000, 0xffe00000, "G,W,R", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G;R", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "G,C,R", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O,R", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "O,W,R", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O,R", OP_C4X } + +/* T2: General 3-operand integer operation with 2 args + Syntax: <i> src2, src1 + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O) + Instr: 1/0 - CMPI3 + Alias: i, i3 +*/ +#define T2_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } + +/* T2C: General commutative 3-operand integer operation with 2 args + Syntax: <i> src2, src1 - Manual + <i> src1, src2 + src2 = Register (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C), Immediate (W) + src1 = Register (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (0) + Instr: 1/0 - TSTB3 + Alias: i, i3 +*/ +#define T2C_CLASS_INSN(name, opcode, level) \ + { name, opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name, opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name, opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name, opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name, opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name, opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name, opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name, opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \ + { name, opcode|0x30600000, 0xffe00000, "C,O", OP_C4X }, \ + { name "3", opcode|0x20000000, 0xffe00000, "E,G", level }, \ + { name "3", opcode|0x20200000, 0xffe00000, "E,J", level }, \ + { name "3", opcode|0x20400000, 0xffe00000, "I,G", level }, \ + { name "3", opcode|0x20600000, 0xffe00000, "I,J", level }, \ + { name "3", opcode|0x30000000, 0xffe00000, "W,G", OP_C4X }, \ + { name "3", opcode|0x30000000, 0xffe00000, "G,W", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "C,G", OP_C4X }, \ + { name "3", opcode|0x30200000, 0xffe00000, "G,C", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "W,O", OP_C4X }, \ + { name "3", opcode|0x30400000, 0xffe00000, "O,W", OP_C4X }, \ + { name "3", opcode|0x30600000, 0xffe00000, "C,O", OP_C4X } + +/* Z: Misc operations with or without arguments + Syntax: <i> <arg1>,... + Instr: 16 - RETIc, RETSc, SIGI(c3X), SWI, IDLE, IDLE2, RETIcD, + TRAPc, LATc, LDEP, LDEHI, LDEPE, LDPK, STIK, LDP, IACK +*/ + + +/* Define tic4x opcodes for assembler and disassembler. */ +static const tic4x_inst_t tic4x_insts[] = +{ + /* Put synonyms after the desired forms in table so that they get + overwritten in the lookup table. The disassembler will thus + print the `proper' mnemonics. Note that the disassembler + only decodes the 11 MSBs, so instructions like ldp @0x500 will + be printed as ldiu 5, dp. Note that with parallel instructions, + the second part is executed before the first part, unless + the sti1||sti2 form is used. We also allow sti2||sti1 + which is equivalent to the default sti||sti form. + */ + B_CLASS_INSN( "absf", 0x00000000, OP_C3X ), + P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ), + A_CLASS_INSN( "absi", 0x00800000, OP_C3X ), + P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ), + A_CLASS_INSN( "addc", 0x01000000, OP_C3X ), + TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ), + B_CLASS_INSN( "addf", 0x01800000, OP_C3X ), + SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ), + QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ), + A_CLASS_INSN( "addi", 0x02000000, OP_C3X ), + TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ), + QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ), + AU_CLASS_INSN( "and", 0x02800000, OP_C3X ), + TC_CLASS_INSN( "and", 0x01800000, OP_C3X ), + QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ), + AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ), + T_CLASS_INSN( "andn", 0x02000000, OP_C3X ), + A_CLASS_INSN( "ash", 0x03800000, OP_C3X ), + T_CLASS_INSN( "ash", 0x02800000, OP_C3X ), + Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ), + J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ), + J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ), + J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ), + J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ), + { "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ + { "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ + { "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */ + { "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */ + { "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */ + B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ), + S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ), + A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ), + T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ), + D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ), + D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ), + AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ), + P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ), + BI_CLASS_INSN( "float", 0x05800000, OP_C3X ), + P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ), + B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ), + P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ), + { "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */ + { "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */ + { "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ + { "idlez", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ + { "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE2 }, /* Z_CLASS */ + { "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */ + { "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */ + { "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */ + { "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ), + A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ), + A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ), + A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ), + AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ), + AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ), + AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ), + AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ), + AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ), + B_CLASS_INSN( "lde", 0x06800000, OP_C3X ), + { "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */ + B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ), + LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ), + P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ), + BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ), + B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ), + { "ldhi", 0x1fe00000, 0xffe00000, "U,R" , OP_C4X }, /* Z_CLASS */ + { "ldhi", 0x1fe00000, 0xffe00000, "#,R" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ), + LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ), + P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ), + AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ), + A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ), + { "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */ + B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ), + { "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */ + { "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ), + A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ), + AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ), + AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ), + { "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */ + A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ), + T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ), + Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ), + A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ), + A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ), + A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ), + A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ), + A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ), + A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ), + A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ), + A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ), + { "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */ + A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ), + A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ), + A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ), + A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ), + A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ), + A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ), + A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ), + A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ), + B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ), + SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ), + M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ), + QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ), + M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ), + A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ), + TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ), + M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ), + QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ), + M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ), + A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ), + TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ), + A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ), + TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ), + A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ), + B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ), + P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ), + A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ), + P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ), + A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ), + B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ), + AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ), + P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ), + AU_CLASS_INSN( "or", 0x10000000, OP_C3X ), + TC_CLASS_INSN( "or", 0x05800000, OP_C3X ), + QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ), + R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ), + RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ), + R_CLASS_INSN( "push", 0x0f200000, OP_C3X ), + RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ), + BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ), + { "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ + { "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */ + { "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */ + { "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */ + { "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ + { "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */ + B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ), + R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ), + R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ), + R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ), + R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ), + { "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */ + { "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */ + { "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */ + { "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */ + A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ), + B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ), + { "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */ + A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ), + B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ), + LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ), + B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ), + A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ), + { "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */ + { "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */ + LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ), + A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ), + { "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */ + { "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */ + A_CLASS_INSN( "subb", 0x16800000, OP_C3X ), + T_CLASS_INSN( "subb", 0x06000000, OP_C3X ), + A_CLASS_INSN( "subc", 0x17000000, OP_C3X ), + B_CLASS_INSN( "subf", 0x17800000, OP_C3X ), + S_CLASS_INSN( "subf", 0x06800000, OP_C3X ), + Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ), + A_CLASS_INSN( "subi", 0x18000000, OP_C3X ), + T_CLASS_INSN( "subi", 0x07000000, OP_C3X ), + Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ), + A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ), + B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ), + A_CLASS_INSN( "subri", 0x19800000, OP_C3X ), + { "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */ + B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ), + P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ), + { "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */ + { "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */ + AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ), + T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ), + AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ), + TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ), + QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ), + + /* Dummy entry, not included in tic4x_num_insts. This + lets code examine entry i + 1 without checking + if we've run off the end of the table. */ + { "", 0x0, 0x00, "", 0 } +}; + +const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1); diff --git a/include/opcode/tic54x.h b/include/opcode/tic54x.h new file mode 100644 index 000000000000..ae657225d610 --- /dev/null +++ b/include/opcode/tic54x.h @@ -0,0 +1,163 @@ +/* tic54x.h -- Header file for TI TMS320C54X opcode table + Copyright 1999, 2000 Free Software Foundation, Inc. + Written by Timothy Wall (twall@cygnus.com) + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#ifndef _opcode_tic54x_h_ +#define _opcode_tic54x_h_ + +typedef struct _symbol +{ + const char *name; + unsigned short value; +} symbol; + +enum optype { + OPT = 0x8000, + OP_None = 0x0, + + OP_Xmem, /* AR3 or AR4, indirect */ + OP_Ymem, /* AR3 or AR4, indirect */ + OP_pmad, /* PROG mem, direct */ + OP_dmad, /* DATA mem, direct */ + OP_Smem, + OP_Lmem, /* 32-bit single-addressed (direct/indirect) */ + OP_MMR, + OP_PA, + OP_Sind, + OP_xpmad, + OP_xpmad_ms7, + OP_MMRX, + OP_MMRY, + + OP_SRC1, /* src accumulator in bit 8 */ + OP_SRC, /* src accumulator in bit 9 */ + OP_RND, /* rounded result dst accumulator, opposite of bit 8 */ + OP_DST, /* dst accumulator in bit 8 */ + OP_ARX, /* arX in bits 0-3 */ + OP_SHIFT, /* -16 to 15 (SHIFT), bits 0-4 */ + OP_SHFT, /* 0 to 15 (SHIFT1 in summary), bits 0-3 */ + OP_B, /* ACC B only */ + OP_A, /* ACC A only */ + + OP_lk, /* 16-bit immediate, '#' optional */ + OP_TS, + OP_k8, /* -128 <= k <= 128 */ + OP_16, /* literal "16" */ + OP_BITC, /* 0 to 16 */ + OP_CC, /* condition code */ + OP_CC2, /* 4-bit condition code */ + OP_CC3, /* 2-bit condition code */ + OP_123, /* 1, 2, or 3 */ + OP_031, /* 0-31, numeric */ + OP_k5, /* 0 to 31 */ + OP_k8u, /* 0 to 255 */ + OP_ASM, /* "ASM" */ + OP_T, /* "T" */ + OP_DP, /* "DP" */ + OP_ARP, /* "ARP" */ + OP_k3, /* 0-7 */ + OP_lku, /* 0 to 65535 */ + OP_N, /* 0/1 or ST0/ST1 */ + OP_SBIT, /* status bit or 0-15 */ + OP_12, /* one or two */ + OP_k9, /* 9 bits of data page (DP) address */ + OP_TRN, /* "TRN" */ + +}; + +typedef struct _template +{ + /* The opcode mnemonic */ + const char *name; + unsigned int words; /* insn size in words */ + int minops, maxops; /* min/max operand count */ + /* The significant bits in the opcode. Other bits are zero. + Instructions with more than 16 bits of opcode store the rest in the upper + 16 bits. + */ + unsigned short opcode; +#define INDIRECT(OP) ((OP)&0x80) +#define MOD(OP) (((OP)>>3)&0xF) +#define ARF(OP) ((OP)&0x7) +#define IS_LKADDR(OP) (INDIRECT(OP) && MOD(OP)>=12) +#define SRC(OP) ((OP)&0x200) +#define DST(OP) ((OP)&0x100) +#define SRC1(OP) ((OP)&0x100) +#define SHIFT(OP) (((OP)&0x10)?(((OP)&0x1F)-32):((OP)&0x1F)) +#define SHFT(OP) ((OP)&0xF) +#define ARX(OP) ((OP)&0x7) +#define XMEM(OP) (((OP)&0x00F0)>>4) +#define YMEM(OP) ((OP)&0x000F) +#define XMOD(C) (((C)&0xC)>>2) +#define XARX(C) (((C)&0x3)+2) +#define CC3(OP) (((OP)>>8)&0x3) +#define SBIT(OP) ((OP)&0xF) +#define MMR(OP) ((OP)&0x7F) +#define MMRX(OP) ((((OP)>>4)&0xF)+16) +#define MMRY(OP) (((OP)&0xF)+16) + +#define OPTYPE(X) ((X)&~OPT) + + /* Ones in this mask indicate which bits must match the opcode field. + Zeroes indicate don't care bits (operands and/or opcode options) */ + unsigned short mask; + + /* An array of operand codes (at most 4 operands) */ +#define MAX_OPERANDS 4 + enum optype operand_types[MAX_OPERANDS]; + + /* Special purpose flags (e.g. branch type, parallel, delay, etc) + */ + unsigned short flags; +#define B_NEXT 0 /* normal execution, next insn is next address */ +#define B_BRANCH 1 /* next insn is in opcode */ +#define B_RET 2 /* next insn is on stack */ +#define B_BACC 3 /* next insn is in acc */ +#define B_REPEAT 4 /* next insn repeats */ +#define FL_BMASK 0x07 + +#define FL_DELAY 0x10 /* instruction uses delay slots */ +#define FL_EXT 0x20 /* instruction takes two words */ +#define FL_FAR 0x40 /* far mode addressing */ +#define FL_LP 0x80 /* LP-only instruction */ +#define FL_NR 0x100 /* no repeat allowed */ +#define FL_SMR 0x200 /* Smem read (for flagging write-only *+ARx */ + +#define FL_PAR 0x400 /* Parallel instruction. */ + + unsigned short opcode2, mask2; /* some insns have an extended opcode */ + + const char* parname; + enum optype paroperand_types[MAX_OPERANDS]; + +} template; + +extern const template tic54x_unknown_opcode; +extern const template tic54x_optab[]; +extern const template tic54x_paroptab[]; +extern const symbol mmregs[], regs[]; +extern const symbol condition_codes[], cc2_codes[], status_bits[]; +extern const symbol cc3_codes[]; +extern const char *misc_symbols[]; +struct disassemble_info; +extern const template* tic54x_get_insn (struct disassemble_info *, + bfd_vma, unsigned short, int *); + +#endif /* _opcode_tic54x_h_ */ diff --git a/include/opcode/tic80.h b/include/opcode/tic80.h new file mode 100644 index 000000000000..c6a79df286f6 --- /dev/null +++ b/include/opcode/tic80.h @@ -0,0 +1,282 @@ +/* tic80.h -- Header file for TI TMS320C80 (MV) opcode table + Copyright 1996, 1997, 2003 Free Software Foundation, Inc. + Written by Fred Fish (fnf@cygnus.com), Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef TIC80_H +#define TIC80_H + +/* The opcode table is an array of struct tic80_opcode. */ + +struct tic80_opcode +{ + /* The opcode name. */ + + const char *name; + + /* The opcode itself. Those bits which will be filled in with operands + are zeroes. */ + + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a mask + containing ones indicating those bits which must match the opcode + field, and zeroes indicating those bits which need not match (and are + presumably filled in by operands). */ + + unsigned long mask; + + /* Special purpose flags for this opcode. */ + + unsigned char flags; + + /* An array of operand codes. Each code is an index into the operand + table. They appear in the order which the operands must appear in + assembly code, and are terminated by a zero. FIXME: Adjust size to + match actual requirements when TIc80 support is complete */ + + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise in + the order in which the disassembler should consider instructions. + FIXME: This isn't currently true. */ + +extern const struct tic80_opcode tic80_opcodes[]; +extern const int tic80_num_opcodes; + + +/* The operands table is an array of struct tic80_operand. */ + +struct tic80_operand +{ + /* The number of bits in the operand. */ + + int bits; + + /* How far the operand is left shifted in the instruction. */ + + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + + unsigned long (*insert) + (unsigned long instruction, long op, const char **errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & TIC80_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + + long (*extract) (unsigned long instruction, int *invalid); + + /* One bit syntax flags. */ + + unsigned long flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the tic80_opcodes table. */ + +extern const struct tic80_operand tic80_operands[]; + + +/* Values defined for the flags field of a struct tic80_operand. + + Note that flags for all predefined symbols, such as the general purpose + registers (ex: r10), control registers (ex: FPST), condition codes (ex: + eq0.b), bit numbers (ex: gt.b), etc are large enough that they can be + or'd into an int where the lower bits contain the actual numeric value + that correponds to this predefined symbol. This way a single int can + contain both the value of the symbol and it's type. + */ + +/* This operand must be an even register number. Floating point numbers + for example are stored in even/odd register pairs. */ + +#define TIC80_OPERAND_EVEN (1 << 0) + +/* This operand must be an odd register number and must be one greater than + the register number of the previous operand. I.E. the second register in + an even/odd register pair. */ + +#define TIC80_OPERAND_ODD (1 << 1) + +/* This operand takes signed values. */ + +#define TIC80_OPERAND_SIGNED (1 << 2) + +/* This operand may be either a predefined constant name or a numeric value. + An example would be a condition code like "eq0.b" which has the numeric + value 0x2. */ + +#define TIC80_OPERAND_NUM (1 << 3) + +/* This operand should be wrapped in parentheses rather than separated + from the previous one by a comma. This is used for various + instructions, like the load and store instructions, which want + their operands to look like "displacement(reg)" */ + +#define TIC80_OPERAND_PARENS (1 << 4) + +/* This operand is a PC relative branch offset. The disassembler prints + these symbolically if possible. Note that the offsets are taken as word + offsets. */ + +#define TIC80_OPERAND_PCREL (1 << 5) + +/* This flag is a hint to the disassembler for using hex as the prefered + printing format, even for small positive or negative immediate values. + Normally values in the range -999 to 999 are printed as signed decimal + values and other values are printed in hex. */ + +#define TIC80_OPERAND_BITFIELD (1 << 6) + +/* This operand may have a ":m" modifier specified by bit 17 in a short + immediate form instruction. */ + +#define TIC80_OPERAND_M_SI (1 << 7) + +/* This operand may have a ":m" modifier specified by bit 15 in a long + immediate or register form instruction. */ + +#define TIC80_OPERAND_M_LI (1 << 8) + +/* This operand may have a ":s" modifier specified in bit 11 in a long + immediate or register form instruction. */ + +#define TIC80_OPERAND_SCALED (1 << 9) + +/* This operand is a floating point value */ + +#define TIC80_OPERAND_FLOAT (1 << 10) + +/* This operand is an byte offset from a base relocation. The lower + two bits of the final relocated address are ignored when the value is + written to the program counter. */ + +#define TIC80_OPERAND_BASEREL (1 << 11) + +/* This operand is an "endmask" field for a shift instruction. + It is treated special in that it can have values of 0-32, + where 0 and 32 result in the same instruction. The assembler + must be able to accept both endmask values. This disassembler + has no way of knowing from the instruction which value was + given at assembly time, so it just uses '0'. */ + +#define TIC80_OPERAND_ENDMASK (1 << 12) + +/* This operand is one of the 32 general purpose registers. + The disassembler prints these with a leading 'r'. */ + +#define TIC80_OPERAND_GPR (1 << 27) + +/* This operand is a floating point accumulator register. + The disassembler prints these with a leading 'a'. */ + +#define TIC80_OPERAND_FPA ( 1 << 28) + +/* This operand is a control register number, either numeric or + symbolic (like "EIF", "EPC", etc). + The disassembler prints these symbolically. */ + +#define TIC80_OPERAND_CR (1 << 29) + +/* This operand is a condition code, either numeric or + symbolic (like "eq0.b", "ne0.w", etc). + The disassembler prints these symbolically. */ + +#define TIC80_OPERAND_CC (1 << 30) + +/* This operand is a bit number, either numeric or + symbolic (like "eq.b", "or.f", etc). + The disassembler prints these symbolically. + Note that they appear in the instruction in 1's complement relative + to the values given in the manual. */ + +#define TIC80_OPERAND_BITNUM (1 << 31) + +/* This mask is used to strip operand bits from an int that contains + both operand bits and a numeric value in the lsbs. */ + +#define TIC80_OPERAND_MASK (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR | TIC80_OPERAND_CC | TIC80_OPERAND_BITNUM) + + +/* Flag bits for the struct tic80_opcode flags field. */ + +#define TIC80_VECTOR 01 /* Is a vector instruction */ +#define TIC80_NO_R0_DEST 02 /* Register r0 cannot be a destination register */ + + +/* The opcodes library contains a table that allows translation from predefined + symbol names to numeric values, and vice versa. */ + +/* Structure to hold information about predefined symbols. */ + +struct predefined_symbol +{ + char *name; /* name to recognize */ + int value; +}; + +#define PDS_NAME(pdsp) ((pdsp) -> name) +#define PDS_VALUE(pdsp) ((pdsp) -> value) + +/* Translation array. */ +extern const struct predefined_symbol tic80_predefined_symbols[]; +/* How many members in the array. */ +extern const int tic80_num_predefined_symbols; + +/* Translate value to symbolic name. */ +const char *tic80_value_to_symbol (int val, int class); + +/* Translate symbolic name to value. */ +int tic80_symbol_to_value (char *name, int class); + +const struct predefined_symbol *tic80_next_predefined_symbol + (const struct predefined_symbol *); + +#endif /* TIC80_H */ diff --git a/include/opcode/v850.h b/include/opcode/v850.h new file mode 100644 index 000000000000..75689bff67a3 --- /dev/null +++ b/include/opcode/v850.h @@ -0,0 +1,166 @@ +/* v850.h -- Header file for NEC V850 opcode table + Copyright 1996, 1997, 2001, 2003 Free Software Foundation, Inc. + Written by J.T. Conklin, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef V850_H +#define V850_H + +/* The opcode table is an array of struct v850_opcode. */ + +struct v850_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; + + /* Which (if any) operand is a memory operand. */ + unsigned int memop; + + /* Target processor(s). A bit field of processors which support + this instruction. Note a bit field is used as some instructions + are available on multiple, different processor types, whereas + other instructions are only available on one specific type. */ + unsigned int processors; +}; + +/* Values for the processors field in the v850_opcode structure. */ +#define PROCESSOR_V850 (1 << 0) /* Just the V850. */ +#define PROCESSOR_ALL -1 /* Any processor. */ +#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */ +#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */ +#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */ +#define PROCESSOR_V850E1 (1 << 3) /* Just the V850E1. */ + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct v850_opcode v850_opcodes[]; +extern const int v850_num_opcodes; + + +/* The operands table is an array of struct v850_operand. */ + +struct v850_operand +{ + /* The number of bits in the operand. */ + /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */ + int bits; + + /* (bits >= 0): How far the operand is left shifted in the instruction. */ + /* (bits == -1): Bit mask of the bits in the operand. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned long (* insert) + (unsigned long instruction, long op, const char ** errmsg); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1); + if (o->flags & V850_OPERAND_SIGNED) + op = (op << (32 - o->bits)) >> (32 - o->bits); + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + unsigned long (* extract) (unsigned long instruction, int * invalid); + + /* One bit syntax flags. */ + int flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the v850_opcodes table. */ + +extern const struct v850_operand v850_operands[]; + +/* Values defined for the flags field of a struct v850_operand. */ + +/* This operand names a general purpose register */ +#define V850_OPERAND_REG 0x01 + +/* This operand names a system register */ +#define V850_OPERAND_SRG 0x02 + +/* This operand names a condition code used in the setf instruction */ +#define V850_OPERAND_CC 0x04 + +/* This operand takes signed values */ +#define V850_OPERAND_SIGNED 0x08 + +/* This operand is the ep register. */ +#define V850_OPERAND_EP 0x10 + +/* This operand is a PC displacement */ +#define V850_OPERAND_DISP 0x20 + +/* This is a relaxable operand. Only used for D9->D22 branch relaxing + right now. We may need others in the future (or maybe handle them like + promoted operands on the mn10300?) */ +#define V850_OPERAND_RELAX 0x40 + +/* The register specified must not be r0 */ +#define V850_NOT_R0 0x80 + +/* push/pop type instruction, V850E specific. */ +#define V850E_PUSH_POP 0x100 + +/* 16 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE16 0x200 + +/* 32 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE32 0x400 + +#endif /* V850_H */ diff --git a/include/opcode/vax.h b/include/opcode/vax.h new file mode 100644 index 000000000000..6fda6b2552aa --- /dev/null +++ b/include/opcode/vax.h @@ -0,0 +1,382 @@ +/* Vax opcde list. + Copyright 1989, 1991, 1992, 1995 Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +GDB and GAS are free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB and GAS are distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB or GAS; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef vax_opcodeT +#define vax_opcodeT int +#endif /* no vax_opcodeT */ + +struct vot_wot /* vax opcode table: wot to do with this */ + /* particular opcode */ +{ + const char *args; /* how to compile said opcode */ + vax_opcodeT code; /* op-code (may be > 8 bits!) */ +}; + +struct vot /* vax opcode text */ +{ + const char *name; /* opcode name: lowercase string [key] */ + struct vot_wot detail; /* rest of opcode table [datum] */ +}; + +#define vot_how args +#define vot_code code +#define vot_detail detail +#define vot_name name + +static const struct vot +votstrs[] = +{ +{ "halt", {"", 0x00 } }, +{ "nop", {"", 0x01 } }, +{ "rei", {"", 0x02 } }, +{ "bpt", {"", 0x03 } }, +{ "ret", {"", 0x04 } }, +{ "rsb", {"", 0x05 } }, +{ "ldpctx", {"", 0x06 } }, +{ "svpctx", {"", 0x07 } }, +{ "cvtps", {"rwabrwab", 0x08 } }, +{ "cvtsp", {"rwabrwab", 0x09 } }, +{ "index", {"rlrlrlrlrlwl", 0x0a } }, +{ "crc", {"abrlrwab", 0x0b } }, +{ "prober", {"rbrwab", 0x0c } }, +{ "probew", {"rbrwab", 0x0d } }, +{ "insque", {"abab", 0x0e } }, +{ "remque", {"abwl", 0x0f } }, +{ "bsbb", {"bb", 0x10 } }, +{ "brb", {"bb", 0x11 } }, +{ "bneq", {"bb", 0x12 } }, +{ "bnequ", {"bb", 0x12 } }, +{ "beql", {"bb", 0x13 } }, +{ "beqlu", {"bb", 0x13 } }, +{ "bgtr", {"bb", 0x14 } }, +{ "bleq", {"bb", 0x15 } }, +{ "jsb", {"ab", 0x16 } }, +{ "jmp", {"ab", 0x17 } }, +{ "bgeq", {"bb", 0x18 } }, +{ "blss", {"bb", 0x19 } }, +{ "bgtru", {"bb", 0x1a } }, +{ "blequ", {"bb", 0x1b } }, +{ "bvc", {"bb", 0x1c } }, +{ "bvs", {"bb", 0x1d } }, +{ "bcc", {"bb", 0x1e } }, +{ "bgequ", {"bb", 0x1e } }, +{ "blssu", {"bb", 0x1f } }, +{ "bcs", {"bb", 0x1f } }, +{ "addp4", {"rwabrwab", 0x20 } }, +{ "addp6", {"rwabrwabrwab", 0x21 } }, +{ "subp4", {"rwabrwab", 0x22 } }, +{ "subp6", {"rwabrwabrwab", 0x23 } }, +{ "cvtpt", {"rwababrwab", 0x24 } }, +{ "mulp", {"rwabrwabrwab", 0x25 } }, +{ "cvttp", {"rwababrwab", 0x26 } }, +{ "divp", {"rwabrwabrwab", 0x27 } }, +{ "movc3", {"rwabab", 0x28 } }, +{ "cmpc3", {"rwabab", 0x29 } }, +{ "scanc", {"rwababrb", 0x2a } }, +{ "spanc", {"rwababrb", 0x2b } }, +{ "movc5", {"rwabrbrwab", 0x2c } }, +{ "cmpc5", {"rwabrbrwab", 0x2d } }, +{ "movtc", {"rwabrbabrwab", 0x2e } }, +{ "movtuc", {"rwabrbabrwab", 0x2f } }, +{ "bsbw", {"bw", 0x30 } }, +{ "brw", {"bw", 0x31 } }, +{ "cvtwl", {"rwwl", 0x32 } }, +{ "cvtwb", {"rwwb", 0x33 } }, +{ "movp", {"rwabab", 0x34 } }, +{ "cmpp3", {"rwabab", 0x35 } }, +{ "cvtpl", {"rwabwl", 0x36 } }, +{ "cmpp4", {"rwabrwab", 0x37 } }, +{ "editpc", {"rwababab", 0x38 } }, +{ "matchc", {"rwabrwab", 0x39 } }, +{ "locc", {"rbrwab", 0x3a } }, +{ "skpc", {"rbrwab", 0x3b } }, +{ "movzwl", {"rwwl", 0x3c } }, +{ "acbw", {"rwrwmwbw", 0x3d } }, +{ "movaw", {"awwl", 0x3e } }, +{ "pushaw", {"aw", 0x3f } }, +{ "addf2", {"rfmf", 0x40 } }, +{ "addf3", {"rfrfwf", 0x41 } }, +{ "subf2", {"rfmf", 0x42 } }, +{ "subf3", {"rfrfwf", 0x43 } }, +{ "mulf2", {"rfmf", 0x44 } }, +{ "mulf3", {"rfrfwf", 0x45 } }, +{ "divf2", {"rfmf", 0x46 } }, +{ "divf3", {"rfrfwf", 0x47 } }, +{ "cvtfb", {"rfwb", 0x48 } }, +{ "cvtfw", {"rfww", 0x49 } }, +{ "cvtfl", {"rfwl", 0x4a } }, +{ "cvtrfl", {"rfwl", 0x4b } }, +{ "cvtbf", {"rbwf", 0x4c } }, +{ "cvtwf", {"rwwf", 0x4d } }, +{ "cvtlf", {"rlwf", 0x4e } }, +{ "acbf", {"rfrfmfbw", 0x4f } }, +{ "movf", {"rfwf", 0x50 } }, +{ "cmpf", {"rfrf", 0x51 } }, +{ "mnegf", {"rfwf", 0x52 } }, +{ "tstf", {"rf", 0x53 } }, +{ "emodf", {"rfrbrfwlwf", 0x54 } }, +{ "polyf", {"rfrwab", 0x55 } }, +{ "cvtfd", {"rfwd", 0x56 } }, + /* opcode 57 is not defined yet */ +{ "adawi", {"rwmw", 0x58 } }, + /* opcode 59 is not defined yet */ + /* opcode 5a is not defined yet */ + /* opcode 5b is not defined yet */ +{ "insqhi", {"abaq", 0x5c } }, +{ "insqti", {"abaq", 0x5d } }, +{ "remqhi", {"aqwl", 0x5e } }, +{ "remqti", {"aqwl", 0x5f } }, +{ "addd2", {"rdmd", 0x60 } }, +{ "addd3", {"rdrdwd", 0x61 } }, +{ "subd2", {"rdmd", 0x62 } }, +{ "subd3", {"rdrdwd", 0x63 } }, +{ "muld2", {"rdmd", 0x64 } }, +{ "muld3", {"rdrdwd", 0x65 } }, +{ "divd2", {"rdmd", 0x66 } }, +{ "divd3", {"rdrdwd", 0x67 } }, +{ "cvtdb", {"rdwb", 0x68 } }, +{ "cvtdw", {"rdww", 0x69 } }, +{ "cvtdl", {"rdwl", 0x6a } }, +{ "cvtrdl", {"rdwl", 0x6b } }, +{ "cvtbd", {"rbwd", 0x6c } }, +{ "cvtwd", {"rwwd", 0x6d } }, +{ "cvtld", {"rlwd", 0x6e } }, +{ "acbd", {"rdrdmdbw", 0x6f } }, +{ "movd", {"rdwd", 0x70 } }, +{ "cmpd", {"rdrd", 0x71 } }, +{ "mnegd", {"rdwd", 0x72 } }, +{ "tstd", {"rd", 0x73 } }, +{ "emodd", {"rdrbrdwlwd", 0x74 } }, +{ "polyd", {"rdrwab", 0x75 } }, +{ "cvtdf", {"rdwf", 0x76 } }, + /* opcode 77 is not defined yet */ +{ "ashl", {"rbrlwl", 0x78 } }, +{ "ashq", {"rbrqwq", 0x79 } }, +{ "emul", {"rlrlrlwq", 0x7a } }, +{ "ediv", {"rlrqwlwl", 0x7b } }, +{ "clrd", {"wd", 0x7c } }, +{ "clrg", {"wg", 0x7c } }, +{ "clrq", {"wd", 0x7c } }, +{ "movq", {"rqwq", 0x7d } }, +{ "movaq", {"aqwl", 0x7e } }, +{ "movad", {"adwl", 0x7e } }, +{ "pushaq", {"aq", 0x7f } }, +{ "pushad", {"ad", 0x7f } }, +{ "addb2", {"rbmb", 0x80 } }, +{ "addb3", {"rbrbwb", 0x81 } }, +{ "subb2", {"rbmb", 0x82 } }, +{ "subb3", {"rbrbwb", 0x83 } }, +{ "mulb2", {"rbmb", 0x84 } }, +{ "mulb3", {"rbrbwb", 0x85 } }, +{ "divb2", {"rbmb", 0x86 } }, +{ "divb3", {"rbrbwb", 0x87 } }, +{ "bisb2", {"rbmb", 0x88 } }, +{ "bisb3", {"rbrbwb", 0x89 } }, +{ "bicb2", {"rbmb", 0x8a } }, +{ "bicb3", {"rbrbwb", 0x8b } }, +{ "xorb2", {"rbmb", 0x8c } }, +{ "xorb3", {"rbrbwb", 0x8d } }, +{ "mnegb", {"rbwb", 0x8e } }, +{ "caseb", {"rbrbrb", 0x8f } }, +{ "movb", {"rbwb", 0x90 } }, +{ "cmpb", {"rbrb", 0x91 } }, +{ "mcomb", {"rbwb", 0x92 } }, +{ "bitb", {"rbrb", 0x93 } }, +{ "clrb", {"wb", 0x94 } }, +{ "tstb", {"rb", 0x95 } }, +{ "incb", {"mb", 0x96 } }, +{ "decb", {"mb", 0x97 } }, +{ "cvtbl", {"rbwl", 0x98 } }, +{ "cvtbw", {"rbww", 0x99 } }, +{ "movzbl", {"rbwl", 0x9a } }, +{ "movzbw", {"rbww", 0x9b } }, +{ "rotl", {"rbrlwl", 0x9c } }, +{ "acbb", {"rbrbmbbw", 0x9d } }, +{ "movab", {"abwl", 0x9e } }, +{ "pushab", {"ab", 0x9f } }, +{ "addw2", {"rwmw", 0xa0 } }, +{ "addw3", {"rwrwww", 0xa1 } }, +{ "subw2", {"rwmw", 0xa2 } }, +{ "subw3", {"rwrwww", 0xa3 } }, +{ "mulw2", {"rwmw", 0xa4 } }, +{ "mulw3", {"rwrwww", 0xa5 } }, +{ "divw2", {"rwmw", 0xa6 } }, +{ "divw3", {"rwrwww", 0xa7 } }, +{ "bisw2", {"rwmw", 0xa8 } }, +{ "bisw3", {"rwrwww", 0xa9 } }, +{ "bicw2", {"rwmw", 0xaa } }, +{ "bicw3", {"rwrwww", 0xab } }, +{ "xorw2", {"rwmw", 0xac } }, +{ "xorw3", {"rwrwww", 0xad } }, +{ "mnegw", {"rwww", 0xae } }, +{ "casew", {"rwrwrw", 0xaf } }, +{ "movw", {"rwww", 0xb0 } }, +{ "cmpw", {"rwrw", 0xb1 } }, +{ "mcomw", {"rwww", 0xb2 } }, +{ "bitw", {"rwrw", 0xb3 } }, +{ "clrw", {"ww", 0xb4 } }, +{ "tstw", {"rw", 0xb5 } }, +{ "incw", {"mw", 0xb6 } }, +{ "decw", {"mw", 0xb7 } }, +{ "bispsw", {"rw", 0xb8 } }, +{ "bicpsw", {"rw", 0xb9 } }, +{ "popr", {"rw", 0xba } }, +{ "pushr", {"rw", 0xbb } }, +{ "chmk", {"rw", 0xbc } }, +{ "chme", {"rw", 0xbd } }, +{ "chms", {"rw", 0xbe } }, +{ "chmu", {"rw", 0xbf } }, +{ "addl2", {"rlml", 0xc0 } }, +{ "addl3", {"rlrlwl", 0xc1 } }, +{ "subl2", {"rlml", 0xc2 } }, +{ "subl3", {"rlrlwl", 0xc3 } }, +{ "mull2", {"rlml", 0xc4 } }, +{ "mull3", {"rlrlwl", 0xc5 } }, +{ "divl2", {"rlml", 0xc6 } }, +{ "divl3", {"rlrlwl", 0xc7 } }, +{ "bisl2", {"rlml", 0xc8 } }, +{ "bisl3", {"rlrlwl", 0xc9 } }, +{ "bicl2", {"rlml", 0xca } }, +{ "bicl3", {"rlrlwl", 0xcb } }, +{ "xorl2", {"rlml", 0xcc } }, +{ "xorl3", {"rlrlwl", 0xcd } }, +{ "mnegl", {"rlwl", 0xce } }, +{ "casel", {"rlrlrl", 0xcf } }, +{ "movl", {"rlwl", 0xd0 } }, +{ "cmpl", {"rlrl", 0xd1 } }, +{ "mcoml", {"rlwl", 0xd2 } }, +{ "bitl", {"rlrl", 0xd3 } }, +{ "clrf", {"wf", 0xd4 } }, +{ "clrl", {"wl", 0xd4 } }, +{ "tstl", {"rl", 0xd5 } }, +{ "incl", {"ml", 0xd6 } }, +{ "decl", {"ml", 0xd7 } }, +{ "adwc", {"rlml", 0xd8 } }, +{ "sbwc", {"rlml", 0xd9 } }, +{ "mtpr", {"rlrl", 0xda } }, +{ "mfpr", {"rlwl", 0xdb } }, +{ "movpsl", {"wl", 0xdc } }, +{ "pushl", {"rl", 0xdd } }, +{ "moval", {"alwl", 0xde } }, +{ "movaf", {"afwl", 0xde } }, +{ "pushal", {"al", 0xdf } }, +{ "pushaf", {"af", 0xdf } }, +{ "bbs", {"rlvbbb", 0xe0 } }, +{ "bbc", {"rlvbbb", 0xe1 } }, +{ "bbss", {"rlvbbb", 0xe2 } }, +{ "bbcs", {"rlvbbb", 0xe3 } }, +{ "bbsc", {"rlvbbb", 0xe4 } }, +{ "bbcc", {"rlvbbb", 0xe5 } }, +{ "bbssi", {"rlvbbb", 0xe6 } }, +{ "bbcci", {"rlvbbb", 0xe7 } }, +{ "blbs", {"rlbb", 0xe8 } }, +{ "blbc", {"rlbb", 0xe9 } }, +{ "ffs", {"rlrbvbwl", 0xea } }, +{ "ffc", {"rlrbvbwl", 0xeb } }, +{ "cmpv", {"rlrbvbrl", 0xec } }, +{ "cmpzv", {"rlrbvbrl", 0xed } }, +{ "extv", {"rlrbvbwl", 0xee } }, +{ "extzv", {"rlrbvbwl", 0xef } }, +{ "insv", {"rlrlrbvb", 0xf0 } }, +{ "acbl", {"rlrlmlbw", 0xf1 } }, +{ "aoblss", {"rlmlbb", 0xf2 } }, +{ "aobleq", {"rlmlbb", 0xf3 } }, +{ "sobgeq", {"mlbb", 0xf4 } }, +{ "sobgtr", {"mlbb", 0xf5 } }, +{ "cvtlb", {"rlwb", 0xf6 } }, +{ "cvtlw", {"rlww", 0xf7 } }, +{ "ashp", {"rbrwabrbrwab", 0xf8 } }, +{ "cvtlp", {"rlrwab", 0xf9 } }, +{ "callg", {"abab", 0xfa } }, +{ "calls", {"rlab", 0xfb } }, +{ "xfc", {"", 0xfc } }, + /* undefined opcodes here */ +{ "cvtdh", {"rdwh", 0x32fd } }, +{ "cvtgf", {"rgwh", 0x33fd } }, +{ "addg2", {"rgmg", 0x40fd } }, +{ "addg3", {"rgrgwg", 0x41fd } }, +{ "subg2", {"rgmg", 0x42fd } }, +{ "subg3", {"rgrgwg", 0x43fd } }, +{ "mulg2", {"rgmg", 0x44fd } }, +{ "mulg3", {"rgrgwg", 0x45fd } }, +{ "divg2", {"rgmg", 0x46fd } }, +{ "divg3", {"rgrgwg", 0x47fd } }, +{ "cvtgb", {"rgwb", 0x48fd } }, +{ "cvtgw", {"rgww", 0x49fd } }, +{ "cvtgl", {"rgwl", 0x4afd } }, +{ "cvtrgl", {"rgwl", 0x4bfd } }, +{ "cvtbg", {"rbwg", 0x4cfd } }, +{ "cvtwg", {"rwwg", 0x4dfd } }, +{ "cvtlg", {"rlwg", 0x4efd } }, +{ "acbg", {"rgrgmgbw", 0x4ffd } }, +{ "movg", {"rgwg", 0x50fd } }, +{ "cmpg", {"rgrg", 0x51fd } }, +{ "mnegg", {"rgwg", 0x52fd } }, +{ "tstg", {"rg", 0x53fd } }, +{ "emodg", {"rgrwrgwlwg", 0x54fd } }, +{ "polyg", {"rgrwab", 0x55fd } }, +{ "cvtgh", {"rgwh", 0x56fd } }, + /* undefined opcodes here */ +{ "addh2", {"rhmh", 0x60fd } }, +{ "addh3", {"rhrhwh", 0x61fd } }, +{ "subh2", {"rhmh", 0x62fd } }, +{ "subh3", {"rhrhwh", 0x63fd } }, +{ "mulh2", {"rhmh", 0x64fd } }, +{ "mulh3", {"rhrhwh", 0x65fd } }, +{ "divh2", {"rhmh", 0x66fd } }, +{ "divh3", {"rhrhwh", 0x67fd } }, +{ "cvthb", {"rhwb", 0x68fd } }, +{ "cvthw", {"rhww", 0x69fd } }, +{ "cvthl", {"rhwl", 0x6afd } }, +{ "cvtrhl", {"rhwl", 0x6bfd } }, +{ "cvtbh", {"rbwh", 0x6cfd } }, +{ "cvtwh", {"rwwh", 0x6dfd } }, +{ "cvtlh", {"rlwh", 0x6efd } }, +{ "acbh", {"rhrhmhbw", 0x6ffd } }, +{ "movh", {"rhwh", 0x70fd } }, +{ "cmph", {"rhrh", 0x71fd } }, +{ "mnegh", {"rhwh", 0x72fd } }, +{ "tsth", {"rh", 0x73fd } }, +{ "emodh", {"rhrwrhwlwh", 0x74fd } }, +{ "polyh", {"rhrwab", 0x75fd } }, +{ "cvthg", {"rhwg", 0x76fd } }, + /* undefined opcodes here */ +{ "clrh", {"wh", 0x7cfd } }, +{ "clro", {"wo", 0x7cfd } }, +{ "movo", {"rowo", 0x7dfd } }, +{ "movah", {"ahwl", 0x7efd } }, +{ "movao", {"aowl", 0x7efd } }, +{ "pushah", {"ah", 0x7ffd } }, +{ "pushao", {"ao", 0x7ffd } }, + /* undefined opcodes here */ +{ "cvtfh", {"rfwh", 0x98fd } }, +{ "cvtfg", {"rfwg", 0x99fd } }, + /* undefined opcodes here */ +{ "cvthf", {"rhwf", 0xf6fd } }, +{ "cvthd", {"rhwd", 0xf7fd } }, + /* undefined opcodes here */ +{ "bugl", {"rl", 0xfdff } }, +{ "bugw", {"rw", 0xfeff } }, + /* undefined opcodes here */ + +{ "", {"", 0} } /* empty is end sentinel */ + +}; /* votstrs */ + +/* end: vax.opcode.h */ diff --git a/include/os9k.h b/include/os9k.h new file mode 100644 index 000000000000..596f56d5a6ab --- /dev/null +++ b/include/os9k.h @@ -0,0 +1,181 @@ +/* os9k.h - OS-9000 i386 module header definitions + Copyright 2000 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#if !defined(_MODULE_H) +#define _MODULE_H + +#define _MPF386 + +/* Size of common header less parity field. */ +#define N_M_PARITY (sizeof(mh_com)-sizeof(unisgned short)) +#define OLD_M_PARITY 46 +#define M_PARITY N_M_PARITY + +#ifdef _MPF68K +#define MODSYNC 0x4afc /* Module header sync code for 680x0 processors. */ +#endif + +#ifdef _MPF386 +#define MODSYNC 0x4afc /* Module header sync code for 80386 processors. */ +#endif + +#define MODREV 1 /* Module format revision 1. */ +#define CRCCON 0x800063 /* CRC polynomial constant. */ + +/* Module access permission values. */ +#define MP_OWNER_READ 0x0001 +#define MP_OWNER_WRITE 0x0002 +#define MP_OWNER_EXEC 0x0004 +#define MP_GROUP_READ 0x0010 +#define MP_GROUP_WRITE 0x0020 +#define MP_GROUP_EXEC 0x0040 +#define MP_WORLD_READ 0x0100 +#define MP_WORLD_WRITE 0x0200 +#define MP_WORLD_EXEC 0x0400 +#define MP_WORLD_ACCESS 0x0777 +#define MP_OWNER_MASK 0x000f +#define MP_GROUP_MASK 0x00f0 +#define MP_WORLD_MASK 0x0f00 +#define MP_SYSTM_MASK 0xf000 + +/* Module Type/Language values. */ +#define MT_ANY 0 +#define MT_PROGRAM 0x0001 +#define MT_SUBROUT 0x0002 +#define MT_MULTI 0x0003 +#define MT_DATA 0x0004 +#define MT_TRAPLIB 0x000b +#define MT_SYSTEM 0x000c +#define MT_FILEMAN 0x000d +#define MT_DEVDRVR 0x000e +#define MT_DEVDESC 0x000f +#define MT_MASK 0xff00 + +#define ML_ANY 0 +#define ML_OBJECT 1 +#define ML_ICODE 2 +#define ML_PCODE 3 +#define ML_CCODE 4 +#define ML_CBLCODE 5 +#define ML_FRTNCODE 6 +#define ML_MASK 0x00ff + +#define mktypelang(type, lang) (((type) << 8) | (lang)) + +/* Module Attribute values. */ +#define MA_REENT 0x80 +#define MA_GHOST 0x40 +#define MA_SUPER 0x20 +#define MA_MASK 0xff00 +#define MR_MASK 0x00ff + +#define mkattrevs(attr, revs) (((attr) << 8) | (revs)) + +#define m_user m_owner.grp_usr.usr +#define m_group m_owner.grp_usr.grp +#define m_group_user m_owner.group_user + +/* Macro definitions for accessing module header fields. */ +#define MODNAME(mod) ((u_char*)((u_char*)mod + ((Mh_com)mod)->m_name)) +#if 0 +/* Appears not to be used, and the u_int32 typedef is gone (because it + conflicted with a Mach header. */ +#define MODSIZE(mod) ((u_int32)((Mh_com)mod)->m_size) +#endif /* 0 */ +#define MHCOM_BYTES_SIZE 80 +#define N_BADMAG(a) (((a).a_info) != MODSYNC) + +typedef struct mh_com +{ + /* Sync bytes ($4afc). */ + unsigned char m_sync[2]; + unsigned char m_sysrev[2]; /* System revision check value. */ + unsigned char m_size[4]; /* Module size. */ + unsigned char m_owner[4]; /* Group/user id. */ + unsigned char m_name[4]; /* Offset to module name. */ + unsigned char m_access[2]; /* Access permissions. */ + unsigned char m_tylan[2]; /* Type/lang. */ + unsigned char m_attrev[2]; /* Rev/attr. */ + unsigned char m_edit[2]; /* Edition. */ + unsigned char m_needs[4]; /* Module hardware requirements flags. (reserved). */ + unsigned char m_usage[4]; /* Comment string offset. */ + unsigned char m_symbol[4]; /* Symbol table offset. */ + unsigned char m_exec[4]; /* Offset to execution entry point. */ + unsigned char m_excpt[4]; /* Offset to exception entry point. */ + unsigned char m_data[4]; /* Data storage requirement. */ + unsigned char m_stack[4]; /* Stack size. */ + unsigned char m_idata[4]; /* Offset to initialized data. */ + unsigned char m_idref[4]; /* Offset to data reference lists. */ + unsigned char m_init[4]; /* Initialization routine offset. */ + unsigned char m_term[4]; /* Termination routine offset. */ + unsigned char m_ident[2]; /* Ident code for ident program. */ + char m_spare[8]; /* Reserved bytes. */ + unsigned char m_parity[2]; /* Header parity. */ +} mh_com,*Mh_com; + +/* Executable memory module. */ +typedef mh_com *Mh_exec,mh_exec; + +/* Data memory module. */ +typedef mh_com *Mh_data,mh_data; + +/* File manager memory module. */ +typedef mh_com *Mh_fman,mh_fman; + +/* Device driver module. */ +typedef mh_com *Mh_drvr,mh_drvr; + +/* Trap handler module. */ +typedef mh_com mh_trap, *Mh_trap; + +/* Device descriptor module. */ +typedef mh_com *Mh_dev,mh_dev; + +/* Configuration module. */ +typedef mh_com *Mh_config, mh_config; + +#if 0 + +#if !defined(_MODDIR_H) +/* Go get _os_fmod (and others). */ +#include <moddir.h> +#endif + +error_code _os_crc (void *, u_int32, int *); +error_code _os_datmod (char *, u_int32, u_int16 *, u_int16 *, u_int32, void **, mh_data **); +error_code _os_get_moddir (void *, u_int32 *); +error_code _os_initdata (mh_com *, void *); +error_code _os_link (char **, mh_com **, void **, u_int16 *, u_int16 *); +error_code _os_linkm (mh_com *, void **, u_int16 *, u_int16 *); +error_code _os_load (char *, mh_com **, void **, u_int32, u_int16 *, u_int16 *, u_int32); +error_code _os_mkmodule (char *, u_int32, u_int16 *, u_int16 *, u_int32, void **, mh_com **, u_int32); +error_code _os_modaddr (void *, mh_com **); +error_code _os_setcrc (mh_com *); +error_code _os_slink (u_int32, char *, void **, void **, mh_com **); +error_code _os_slinkm (u_int32, mh_com *, void **, void **); +error_code _os_unlink (mh_com *); +error_code _os_unload (char *, u_int32); +error_code _os_tlink (u_int32, char *, void **, mh_trap **, void *, u_int32); +error_code _os_tlinkm (u_int32, mh_com *, void **, void *, u_int32); +error_code _os_iodel (mh_com *); +error_code _os_vmodul (mh_com *, mh_com *, u_int32); +#endif /* 0 */ + +#endif diff --git a/include/regs/ChangeLog b/include/regs/ChangeLog deleted file mode 100644 index e69de29bb2d1..000000000000 --- a/include/regs/ChangeLog +++ /dev/null diff --git a/include/wait.h b/include/wait.h deleted file mode 100644 index fa3c9ccb1d7e..000000000000 --- a/include/wait.h +++ /dev/null @@ -1,63 +0,0 @@ -/* Define how to access the int that the wait system call stores. - This has been compatible in all Unix systems since time immemorial, - but various well-meaning people have defined various different - words for the same old bits in the same old int (sometimes claimed - to be a struct). We just know it's an int and we use these macros - to access the bits. */ - -/* The following macros are defined equivalently to their definitions - in POSIX.1. We fail to define WNOHANG and WUNTRACED, which POSIX.1 - <sys/wait.h> defines, since our code does not use waitpid(). We - also fail to declare wait() and waitpid(). */ - -#ifndef WIFEXITED -#define WIFEXITED(w) (((w)&0377) == 0) -#endif - -#ifndef WIFSIGNALED -#define WIFSIGNALED(w) (((w)&0377) != 0177 && ((w)&~0377) == 0) -#endif - -#ifndef WIFSTOPPED -#ifdef IBM6000 - -/* Unfortunately, the above comment (about being compatible in all Unix - systems) is not quite correct for AIX, sigh. And AIX 3.2 can generate - status words like 0x57c (sigtrap received after load), and gdb would - choke on it. */ - -#define WIFSTOPPED(w) ((w)&0x40) - -#else -#define WIFSTOPPED(w) (((w)&0377) == 0177) -#endif -#endif - -#ifndef WEXITSTATUS -#define WEXITSTATUS(w) (((w) >> 8) & 0377) /* same as WRETCODE */ -#endif - -#ifndef WTERMSIG -#define WTERMSIG(w) ((w) & 0177) -#endif - -#ifndef WSTOPSIG -#define WSTOPSIG WEXITSTATUS -#endif - -/* These are not defined in POSIX, but are used by our programs. */ - -#define WAITTYPE int - -#ifndef WCOREDUMP -#define WCOREDUMP(w) (((w)&0200) != 0) -#endif - -#ifndef WSETEXIT -#define WSETEXIT(w,status) ((w) = (0 | ((status) << 8))) -#endif - -#ifndef WSETSTOP -#define WSETSTOP(w,sig) ((w) = (0177 | ((sig) << 8))) -#endif - diff --git a/include/xtensa-config.h b/include/xtensa-config.h new file mode 100644 index 000000000000..4191c3685758 --- /dev/null +++ b/include/xtensa-config.h @@ -0,0 +1,139 @@ +/* Xtensa configuration settings. + Copyright (C) 2001,2002,2003 Free Software Foundation, Inc. + Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef XTENSA_CONFIG_H +#define XTENSA_CONFIG_H + +/* The macros defined here match those with the same names in the Xtensa + compile-time HAL (Hardware Abstraction Layer). Please refer to the + Xtensa System Software Reference Manual for documentation of these + macros. */ + +#undef XCHAL_HAVE_BE +#define XCHAL_HAVE_BE 1 + +#undef XCHAL_HAVE_DENSITY +#define XCHAL_HAVE_DENSITY 1 + +#undef XCHAL_HAVE_CONST16 +#define XCHAL_HAVE_CONST16 0 + +#undef XCHAL_HAVE_ABS +#define XCHAL_HAVE_ABS 1 + +#undef XCHAL_HAVE_ADDX +#define XCHAL_HAVE_ADDX 1 + +#undef XCHAL_HAVE_L32R +#define XCHAL_HAVE_L32R 1 + +#undef XCHAL_HAVE_MAC16 +#define XCHAL_HAVE_MAC16 0 + +#undef XCHAL_HAVE_MUL16 +#define XCHAL_HAVE_MUL16 0 + +#undef XCHAL_HAVE_MUL32 +#define XCHAL_HAVE_MUL32 0 + +#undef XCHAL_HAVE_DIV32 +#define XCHAL_HAVE_DIV32 0 + +#undef XCHAL_HAVE_NSA +#define XCHAL_HAVE_NSA 1 + +#undef XCHAL_HAVE_MINMAX +#define XCHAL_HAVE_MINMAX 0 + +#undef XCHAL_HAVE_SEXT +#define XCHAL_HAVE_SEXT 0 + +#undef XCHAL_HAVE_LOOPS +#define XCHAL_HAVE_LOOPS 1 + +#undef XCHAL_HAVE_BOOLEANS +#define XCHAL_HAVE_BOOLEANS 0 + +#undef XCHAL_HAVE_FP +#define XCHAL_HAVE_FP 0 + +#undef XCHAL_HAVE_FP_DIV +#define XCHAL_HAVE_FP_DIV 0 + +#undef XCHAL_HAVE_FP_RECIP +#define XCHAL_HAVE_FP_RECIP 0 + +#undef XCHAL_HAVE_FP_SQRT +#define XCHAL_HAVE_FP_SQRT 0 + +#undef XCHAL_HAVE_FP_RSQRT +#define XCHAL_HAVE_FP_RSQRT 0 + +#undef XCHAL_HAVE_WINDOWED +#define XCHAL_HAVE_WINDOWED 1 + + +#undef XCHAL_ICACHE_SIZE +#define XCHAL_ICACHE_SIZE 8192 + +#undef XCHAL_DCACHE_SIZE +#define XCHAL_DCACHE_SIZE 8192 + +#undef XCHAL_ICACHE_LINESIZE +#define XCHAL_ICACHE_LINESIZE 16 + +#undef XCHAL_DCACHE_LINESIZE +#define XCHAL_DCACHE_LINESIZE 16 + +#undef XCHAL_ICACHE_LINEWIDTH +#define XCHAL_ICACHE_LINEWIDTH 4 + +#undef XCHAL_DCACHE_LINEWIDTH +#define XCHAL_DCACHE_LINEWIDTH 4 + +#undef XCHAL_DCACHE_IS_WRITEBACK +#define XCHAL_DCACHE_IS_WRITEBACK 0 + + +#undef XCHAL_HAVE_MMU +#define XCHAL_HAVE_MMU 1 + +#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 + + +#undef XCHAL_HAVE_DEBUG +#define XCHAL_HAVE_DEBUG 1 + +#undef XCHAL_NUM_IBREAK +#define XCHAL_NUM_IBREAK 2 + +#undef XCHAL_NUM_DBREAK +#define XCHAL_NUM_DBREAK 2 + +#undef XCHAL_DEBUGLEVEL +#define XCHAL_DEBUGLEVEL 4 + + +#undef XCHAL_EXTRA_SA_SIZE +#define XCHAL_EXTRA_SA_SIZE 0 + +#undef XCHAL_EXTRA_SA_ALIGN +#define XCHAL_EXTRA_SA_ALIGN 1 + +#endif /* !XTENSA_CONFIG_H */ diff --git a/include/xtensa-isa-internal.h b/include/xtensa-isa-internal.h new file mode 100644 index 000000000000..7f221eae48ed --- /dev/null +++ b/include/xtensa-isa-internal.h @@ -0,0 +1,114 @@ +/* Internal definitions for configurable Xtensa ISA support. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* Use the statically-linked version for the GNU tools. */ +#define STATIC_LIBISA 1 + +#define ISA_INTERFACE_VERSION 3 + +struct config_struct +{ + char *param_name; + char *param_value; +}; + +/* Encode/decode function types for immediate operands. */ +typedef uint32 (*xtensa_immed_decode_fn) (uint32); +typedef xtensa_encode_result (*xtensa_immed_encode_fn) (uint32 *); + +/* Field accessor function types. */ +typedef uint32 (*xtensa_get_field_fn) (const xtensa_insnbuf); +typedef void (*xtensa_set_field_fn) (xtensa_insnbuf, uint32); + +/* PC-relative relocation function types. */ +typedef uint32 (*xtensa_do_reloc_fn) (uint32, uint32); +typedef uint32 (*xtensa_undo_reloc_fn) (uint32, uint32); + +/* Instruction decode function type. */ +typedef int (*xtensa_insn_decode_fn) (const xtensa_insnbuf); + +/* Instruction encoding template function type (each of these functions + returns a constant template; they exist only to make it easier for the + TIE compiler to generate endian-independent DLLs). */ +typedef xtensa_insnbuf (*xtensa_encoding_template_fn) (void); + + +typedef struct xtensa_operand_internal_struct +{ + char *operand_kind; /* e.g., "a", "f", "i", "l".... */ + char inout; /* '<', '>', or '='. */ + char isPCRelative; /* Is this a PC-relative offset? */ + xtensa_get_field_fn get_field; /* Get encoded value of the field. */ + xtensa_set_field_fn set_field; /* Set field with an encoded value. */ + xtensa_immed_encode_fn encode; /* Encode the operand value. */ + xtensa_immed_decode_fn decode; /* Decode the value from the field. */ + xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative relocation. */ + xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */ +} xtensa_operand_internal; + + +typedef struct xtensa_iclass_internal_struct +{ + int num_operands; /* Size of "operands" array. */ + xtensa_operand_internal **operands; /* Array of operand structures. */ +} xtensa_iclass_internal; + + +typedef struct xtensa_opcode_internal_struct +{ + const char *name; /* Opcode mnemonic. */ + int length; /* Length in bytes of the insn. */ + xtensa_encoding_template_fn template; /* Fn returning encoding template. */ + xtensa_iclass_internal *iclass; /* Iclass for this opcode. */ +} xtensa_opcode_internal; + + +typedef struct opname_lookup_entry_struct +{ + const char *key; /* Opcode mnemonic. */ + xtensa_opcode opcode; /* Internal opcode number. */ +} opname_lookup_entry; + + +typedef struct xtensa_isa_internal_struct +{ + int is_big_endian; /* Endianness. */ + int insn_size; /* Maximum length in bytes. */ + int insnbuf_size; /* Number of insnbuf_words. */ + int num_opcodes; /* Total number for all modules. */ + xtensa_opcode_internal **opcode_table;/* Indexed by internal opcode #. */ + int num_modules; /* Number of modules (DLLs) loaded. */ + int *module_opcode_base; /* Starting opcode # for each module. */ + xtensa_insn_decode_fn *module_decode_fn; /* Decode fn for each module. */ + opname_lookup_entry *opname_lookup_table; /* Lookup table for each module. */ + struct config_struct *config; /* Table of configuration parameters. */ + int has_density; /* Is density option available? */ +} xtensa_isa_internal; + + +typedef struct xtensa_isa_module_struct +{ + int (*get_num_opcodes_fn) (void); + xtensa_opcode_internal **(*get_opcodes_fn) (void); + int (*decode_insn_fn) (const xtensa_insnbuf); + struct config_struct *(*get_config_table_fn) (void); +} xtensa_isa_module; + +extern xtensa_isa_module xtensa_isa_modules[]; + diff --git a/include/xtensa-isa.h b/include/xtensa-isa.h new file mode 100644 index 000000000000..54f750c9a1af --- /dev/null +++ b/include/xtensa-isa.h @@ -0,0 +1,230 @@ +/* Interface definition for configurable Xtensa ISA support. + Copyright 2003 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef XTENSA_LIBISA_H +#define XTENSA_LIBISA_H + +/* Use the statically-linked version for the GNU tools. */ +#define STATIC_LIBISA 1 + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef uint32 +#define uint32 unsigned int +#endif + +/* This file defines the interface to the Xtensa ISA library. This library + contains most of the ISA-specific information for a particular Xtensa + processor. For example, the set of valid instructions, their opcode + encodings and operand fields are all included here. To support Xtensa's + configurability and user-defined instruction extensions (i.e., TIE), the + library is initialized by loading one or more dynamic libraries; only a + small set of interface code is present in the statically-linked portion + of the library. + + This interface basically defines four abstract data types. + + . an instruction buffer - for holding the raw instruction bits + . ISA info - information about the ISA as a whole + . opcode info - information about individual instructions + . operand info - information about specific instruction operands + + It would be nice to implement these as classes in C++, but the library is + implemented in C to match the expectations of the GNU tools. + Instead, the interface defines a set of functions to access each data + type. With the exception of the instruction buffer, the internal + representations of the data structures are hidden. All accesses must be + made through the functions defined here. */ + +typedef void* xtensa_isa; +typedef void* xtensa_operand; + + +/* Opcodes are represented here using sequential integers beginning with 0. + The specific value used for a particular opcode is only fixed for a + particular instantiation of an xtensa_isa structure, so these values + should only be used internally. */ +typedef int xtensa_opcode; + +/* Define a unique value for undefined opcodes ("static const int" doesn't + seem to work for this because EGCS 1.0.3 on i686-Linux without -O won't + allow it to be used as an initializer). */ +#define XTENSA_UNDEFINED -1 + + +typedef int libisa_module_specifier; + +extern xtensa_isa xtensa_isa_init (void); + + +/* Instruction buffers. */ + +typedef uint32 xtensa_insnbuf_word; +typedef xtensa_insnbuf_word *xtensa_insnbuf; + +/* Get the size in words of the xtensa_insnbuf array. */ +extern int xtensa_insnbuf_size (xtensa_isa); + +/* Allocate (with malloc) an xtensa_insnbuf of the right size. */ +extern xtensa_insnbuf xtensa_insnbuf_alloc (xtensa_isa); + +/* Release (with free) an xtensa_insnbuf of the right size. */ +extern void xtensa_insnbuf_free (xtensa_insnbuf); + +/* Inward and outward conversion from memory images (byte streams) to our + internal instruction representation. */ +extern void xtensa_insnbuf_to_chars (xtensa_isa, const xtensa_insnbuf, + char *); + +extern void xtensa_insnbuf_from_chars (xtensa_isa, xtensa_insnbuf, + const char *); + + +/* ISA information. */ + +/* Load the ISA information from a shared library. If successful, this returns + a value which identifies the ISA for use in subsequent calls to the ISA + library; otherwise, it returns NULL. Multiple ISAs can be loaded to support + heterogeneous multiprocessor systems. */ +extern xtensa_isa xtensa_load_isa (libisa_module_specifier); + +/* Extend an existing set of ISA information by loading an additional shared + library of ISA information. This is primarily intended for loading TIE + extensions. If successful, the return value is non-zero. */ +extern int xtensa_extend_isa (xtensa_isa, libisa_module_specifier); + +/* The default ISA. This variable is set automatically to the ISA most + recently loaded and is provided as a convenience. An exception is the GNU + opcodes library, where there is a fixed interface that does not allow + passing the ISA as a parameter and the ISA must be taken from this global + variable. (Note: Since this variable is just a convenience, it is not + exported when libisa is built as a DLL, due to the hassle of dealing with + declspecs.) */ +extern xtensa_isa xtensa_default_isa; + + +/* Deallocate an xtensa_isa structure. */ +extern void xtensa_isa_free (xtensa_isa); + +/* Get the maximum instruction size in bytes. */ +extern int xtensa_insn_maxlength (xtensa_isa); + +/* Get the total number of opcodes for this processor. */ +extern int xtensa_num_opcodes (xtensa_isa); + +/* Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if + the name is not a valid opcode mnemonic. */ +extern xtensa_opcode xtensa_opcode_lookup (xtensa_isa, const char *); + +/* Decode a binary instruction buffer. Returns the opcode or + XTENSA_UNDEFINED if the instruction is illegal. */ +extern xtensa_opcode xtensa_decode_insn (xtensa_isa, const xtensa_insnbuf); + + +/* Opcode information. */ + +/* Set the opcode field(s) in a binary instruction buffer. The operand + fields are set to zero. */ +extern void xtensa_encode_insn (xtensa_isa, xtensa_opcode, xtensa_insnbuf); + +/* Get the mnemonic name for an opcode. */ +extern const char * xtensa_opcode_name (xtensa_isa, xtensa_opcode); + +/* Find the length (in bytes) of an instruction. */ +extern int xtensa_insn_length (xtensa_isa, xtensa_opcode); + +/* Find the length of an instruction by looking only at the first byte. */ +extern int xtensa_insn_length_from_first_byte (xtensa_isa, char); + +/* Find the number of operands for an instruction. */ +extern int xtensa_num_operands (xtensa_isa, xtensa_opcode); + +/* Get the information about operand number "opnd" of a particular opcode. */ +extern xtensa_operand xtensa_get_operand (xtensa_isa, xtensa_opcode, int); + +/* Operand information. */ + +/* Find the kind of operand. There are three possibilities: + 1) PC-relative immediates (e.g., "l", "L"). These can be identified with + the xtensa_operand_isPCRelative function. + 2) non-PC-relative immediates ("i"). + 3) register-file short names (e.g., "a", "b", "m" and others defined + via TIE). */ +extern char * xtensa_operand_kind (xtensa_operand); + +/* Check if an operand is an input ('<'), output ('>'), or inout ('=') + operand. Note: The output operand of a conditional assignment + (e.g., movnez) appears here as an inout ('=') even if it is declared + in the TIE code as an output ('>'); this allows the compiler to + properly handle register allocation for conditional assignments. */ +extern char xtensa_operand_inout (xtensa_operand); + +/* Get and set the raw (encoded) value of the field for the specified + operand. The "set" function does not check if the value fits in the + field; that is done by the "encode" function below. */ +extern uint32 xtensa_operand_get_field (xtensa_operand, const xtensa_insnbuf); + +extern void xtensa_operand_set_field (xtensa_operand, xtensa_insnbuf, uint32); + + +/* Encode and decode operands. The raw bits in the operand field + may be encoded in a variety of different ways. These functions hide the + details of that encoding. The encode function has a special return type + (xtensa_encode_result) to indicate success or the reason for failure; the + encoded value is returned through the argument pointer. The decode function + has no possibility of failure and returns the decoded value. */ + +typedef enum +{ + xtensa_encode_result_ok, + xtensa_encode_result_align, + xtensa_encode_result_not_in_table, + xtensa_encode_result_too_low, + xtensa_encode_result_too_high, + xtensa_encode_result_not_ok, + xtensa_encode_result_max = xtensa_encode_result_not_ok +} xtensa_encode_result; + +extern xtensa_encode_result xtensa_operand_encode (xtensa_operand, uint32 *); + +extern uint32 xtensa_operand_decode (xtensa_operand, uint32); + + +/* For PC-relative offset operands, the interpretation of the offset may vary + between opcodes, e.g., is it relative to the current PC or that of the next + instruction? The following functions are defined to perform PC-relative + relocations and to undo them (as in the disassembler). The first function + takes the desired address and the PC of the current instruction and returns + the unencoded value to be stored in the offset field. The second function + takes the unencoded offset value and the current PC and returns the address. + Note that these functions do not replace the encode/decode functions; the + operands must be encoded/decoded separately. */ + +extern int xtensa_operand_isPCRelative (xtensa_operand); + +extern uint32 xtensa_operand_do_reloc (xtensa_operand, uint32, uint32); + +extern uint32 xtensa_operand_undo_reloc (xtensa_operand, uint32, uint32); + +#ifdef __cplusplus +} +#endif +#endif /* XTENSA_LIBISA_H */ |