diff options
Diffstat (limited to 'lib/Headers/avxintrin.h')
| -rw-r--r-- | lib/Headers/avxintrin.h | 3096 |
1 files changed, 2531 insertions, 565 deletions
diff --git a/lib/Headers/avxintrin.h b/lib/Headers/avxintrin.h index 32e8546817b3..be03ba346031 100644 --- a/lib/Headers/avxintrin.h +++ b/lib/Headers/avxintrin.h @@ -57,7 +57,7 @@ typedef long long __m256i __attribute__((__vector_size__(32))); /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VADDPD / ADDPD instruction. +/// This intrinsic corresponds to the <c> VADDPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing one of the source operands. @@ -75,7 +75,7 @@ _mm256_add_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VADDPS / ADDPS instruction. +/// This intrinsic corresponds to the <c> VADDPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing one of the source operands. @@ -93,7 +93,7 @@ _mm256_add_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VSUBPD / SUBPD instruction. +/// This intrinsic corresponds to the <c> VSUBPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing the minuend. @@ -111,7 +111,7 @@ _mm256_sub_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VSUBPS / SUBPS instruction. +/// This intrinsic corresponds to the <c> VSUBPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing the minuend. @@ -130,7 +130,7 @@ _mm256_sub_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VADDSUBPD / ADDSUBPD instruction. +/// This intrinsic corresponds to the <c> VADDSUBPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing the left source operand. @@ -149,7 +149,7 @@ _mm256_addsub_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VADDSUBPS / ADDSUBPS instruction. +/// This intrinsic corresponds to the <c> VADDSUBPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing the left source operand. @@ -167,7 +167,7 @@ _mm256_addsub_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VDIVPD / DIVPD instruction. +/// This intrinsic corresponds to the <c> VDIVPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing the dividend. @@ -185,7 +185,7 @@ _mm256_div_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VDIVPS / DIVPS instruction. +/// This intrinsic corresponds to the <c> VDIVPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing the dividend. @@ -204,7 +204,7 @@ _mm256_div_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMAXPD / MAXPD instruction. +/// This intrinsic corresponds to the <c> VMAXPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing one of the operands. @@ -223,7 +223,7 @@ _mm256_max_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMAXPS / MAXPS instruction. +/// This intrinsic corresponds to the <c> VMAXPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing one of the operands. @@ -242,7 +242,7 @@ _mm256_max_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMINPD / MINPD instruction. +/// This intrinsic corresponds to the <c> VMINPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing one of the operands. @@ -261,7 +261,7 @@ _mm256_min_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMINPS / MINPS instruction. +/// This intrinsic corresponds to the <c> VMINPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing one of the operands. @@ -279,7 +279,7 @@ _mm256_min_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMULPD / MULPD instruction. +/// This intrinsic corresponds to the <c> VMULPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing one of the operands. @@ -297,7 +297,7 @@ _mm256_mul_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VMULPS / MULPS instruction. +/// This intrinsic corresponds to the <c> VMULPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing one of the operands. @@ -316,7 +316,7 @@ _mm256_mul_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VSQRTPD / SQRTPD instruction. +/// This intrinsic corresponds to the <c> VSQRTPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double]. @@ -333,7 +333,7 @@ _mm256_sqrt_pd(__m256d __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VSQRTPS / SQRTPS instruction. +/// This intrinsic corresponds to the <c> VSQRTPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float]. @@ -350,7 +350,7 @@ _mm256_sqrt_ps(__m256 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VRSQRTPS / RSQRTPS instruction. +/// This intrinsic corresponds to the <c> VRSQRTPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float]. @@ -367,7 +367,7 @@ _mm256_rsqrt_ps(__m256 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VRCPPS / RCPPS instruction. +/// This intrinsic corresponds to the <c> VRCPPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float]. @@ -389,24 +389,24 @@ _mm256_rcp_ps(__m256 __a) /// __m256d _mm256_round_pd(__m256d V, const int M); /// \endcode /// -/// This intrinsic corresponds to the \c VROUNDPD / ROUNDPD instruction. +/// This intrinsic corresponds to the <c> VROUNDPD </c> instruction. /// /// \param V /// A 256-bit vector of [4 x double]. /// \param M -/// An integer value that specifies the rounding operation. -/// Bits [7:4] are reserved. -/// Bit [3] is a precision exception value: -/// 0: A normal PE exception is used. -/// 1: The PE field is not updated. -/// Bit [2] is the rounding control source: -/// 0: Use bits [1:0] of M. -/// 1: Use the current MXCSR setting. -/// Bits [1:0] contain the rounding control definition: -/// 00: Nearest. -/// 01: Downward (toward negative infinity). -/// 10: Upward (toward positive infinity). -/// 11: Truncated. +/// An integer value that specifies the rounding operation. \n +/// Bits [7:4] are reserved. \n +/// Bit [3] is a precision exception value: \n +/// 0: A normal PE exception is used. \n +/// 1: The PE field is not updated. \n +/// Bit [2] is the rounding control source: \n +/// 0: Use bits [1:0] of \a M. \n +/// 1: Use the current MXCSR setting. \n +/// Bits [1:0] contain the rounding control definition: \n +/// 00: Nearest. \n +/// 01: Downward (toward negative infinity). \n +/// 10: Upward (toward positive infinity). \n +/// 11: Truncated. /// \returns A 256-bit vector of [4 x double] containing the rounded values. #define _mm256_round_pd(V, M) __extension__ ({ \ (__m256d)__builtin_ia32_roundpd256((__v4df)(__m256d)(V), (M)); }) @@ -421,24 +421,24 @@ _mm256_rcp_ps(__m256 __a) /// __m256 _mm256_round_ps(__m256 V, const int M); /// \endcode /// -/// This intrinsic corresponds to the \c VROUNDPS / ROUNDPS instruction. +/// This intrinsic corresponds to the <c> VROUNDPS </c> instruction. /// /// \param V /// A 256-bit vector of [8 x float]. /// \param M -/// An integer value that specifies the rounding operation. -/// Bits [7:4] are reserved. -/// Bit [3] is a precision exception value: -/// 0: A normal PE exception is used. -/// 1: The PE field is not updated. -/// Bit [2] is the rounding control source: -/// 0: Use bits [1:0] of M. -/// 1: Use the current MXCSR setting. -/// Bits [1:0] contain the rounding control definition: -/// 00: Nearest. -/// 01: Downward (toward negative infinity). -/// 10: Upward (toward positive infinity). -/// 11: Truncated. +/// An integer value that specifies the rounding operation. \n +/// Bits [7:4] are reserved. \n +/// Bit [3] is a precision exception value: \n +/// 0: A normal PE exception is used. \n +/// 1: The PE field is not updated. \n +/// Bit [2] is the rounding control source: \n +/// 0: Use bits [1:0] of \a M. \n +/// 1: Use the current MXCSR setting. \n +/// Bits [1:0] contain the rounding control definition: \n +/// 00: Nearest. \n +/// 01: Downward (toward negative infinity). \n +/// 10: Upward (toward positive infinity). \n +/// 11: Truncated. /// \returns A 256-bit vector of [8 x float] containing the rounded values. #define _mm256_round_ps(V, M) __extension__ ({ \ (__m256)__builtin_ia32_roundps256((__v8sf)(__m256)(V), (M)); }) @@ -453,7 +453,7 @@ _mm256_rcp_ps(__m256 __a) /// __m256d _mm256_ceil_pd(__m256d V); /// \endcode /// -/// This intrinsic corresponds to the \c VROUNDPD / ROUNDPD instruction. +/// This intrinsic corresponds to the <c> VROUNDPD </c> instruction. /// /// \param V /// A 256-bit vector of [4 x double]. @@ -470,7 +470,7 @@ _mm256_rcp_ps(__m256 __a) /// __m256d _mm256_floor_pd(__m256d V); /// \endcode /// -/// This intrinsic corresponds to the \c VROUNDPD / ROUNDPD instruction. +/// This intrinsic corresponds to the <c> VROUNDPD </c> instruction. /// /// \param V /// A 256-bit vector of [4 x double]. @@ -488,7 +488,7 @@ _mm256_rcp_ps(__m256 __a) /// __m256 _mm256_ceil_ps(__m256 V); /// \endcode /// -/// This intrinsic corresponds to the \c VROUNDPS / ROUNDPS instruction. +/// This intrinsic corresponds to the <c> VROUNDPS </c> instruction. /// /// \param V /// A 256-bit vector of [8 x float]. @@ -505,7 +505,7 @@ _mm256_rcp_ps(__m256 __a) /// __m256 _mm256_floor_ps(__m256 V); /// \endcode /// -/// This intrinsic corresponds to the \c VROUNDPS / ROUNDPS instruction. +/// This intrinsic corresponds to the <c> VROUNDPS </c> instruction. /// /// \param V /// A 256-bit vector of [8 x float]. @@ -517,7 +517,7 @@ _mm256_rcp_ps(__m256 __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VANDPD / ANDPD instruction. +/// This intrinsic corresponds to the <c> VANDPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing one of the source operands. @@ -535,7 +535,7 @@ _mm256_and_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VANDPS / ANDPS instruction. +/// This intrinsic corresponds to the <c> VANDPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing one of the source operands. @@ -554,7 +554,7 @@ _mm256_and_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VANDNPD / ANDNPD instruction. +/// This intrinsic corresponds to the <c> VANDNPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing the left source operand. The @@ -575,7 +575,7 @@ _mm256_andnot_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VANDNPS / ANDNPS instruction. +/// This intrinsic corresponds to the <c> VANDNPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing the left source operand. The @@ -595,7 +595,7 @@ _mm256_andnot_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VORPD / ORPD instruction. +/// This intrinsic corresponds to the <c> VORPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing one of the source operands. @@ -613,7 +613,7 @@ _mm256_or_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VORPS / ORPS instruction. +/// This intrinsic corresponds to the <c> VORPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing one of the source operands. @@ -631,7 +631,7 @@ _mm256_or_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VXORPD / XORPD instruction. +/// This intrinsic corresponds to the <c> VXORPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing one of the source operands. @@ -649,7 +649,7 @@ _mm256_xor_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VXORPS / XORPS instruction. +/// This intrinsic corresponds to the <c> VXORPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing one of the source operands. @@ -669,7 +669,7 @@ _mm256_xor_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VHADDPD / HADDPD instruction. +/// This intrinsic corresponds to the <c> VHADDPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing one of the source operands. @@ -692,7 +692,7 @@ _mm256_hadd_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VHADDPS / HADDPS instruction. +/// This intrinsic corresponds to the <c> VHADDPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing one of the source operands. @@ -715,7 +715,7 @@ _mm256_hadd_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VHSUBPD / HSUBPD instruction. +/// This intrinsic corresponds to the <c> VHSUBPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double] containing one of the source operands. @@ -738,7 +738,7 @@ _mm256_hsub_pd(__m256d __a, __m256d __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VHSUBPS / HSUBPS instruction. +/// This intrinsic corresponds to the <c> VHSUBPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float] containing one of the source operands. @@ -762,23 +762,23 @@ _mm256_hsub_ps(__m256 __a, __m256 __b) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VPERMILPD / PERMILPD instruction. +/// This intrinsic corresponds to the <c> VPERMILPD </c> instruction. /// /// \param __a /// A 128-bit vector of [2 x double]. /// \param __c /// A 128-bit integer vector operand specifying how the values are to be -/// copied. -/// Bit [1]: -/// 0: Bits [63:0] of the source are copied to bits [63:0] of the -/// returned vector. -/// 1: Bits [127:64] of the source are copied to bits [63:0] of the -/// returned vector. -/// Bit [65]: -/// 0: Bits [63:0] of the source are copied to bits [127:64] of the -/// returned vector. -/// 1: Bits [127:64] of the source are copied to bits [127:64] of the -/// returned vector. +/// copied. \n +/// Bit [1]: \n +/// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned +/// vector. \n +/// 1: Bits [127:64] of the source are copied to bits [63:0] of the +/// returned vector. \n +/// Bit [65]: \n +/// 0: Bits [63:0] of the source are copied to bits [127:64] of the +/// returned vector. \n +/// 1: Bits [127:64] of the source are copied to bits [127:64] of the +/// returned vector. /// \returns A 128-bit vector of [2 x double] containing the copied values. static __inline __m128d __DEFAULT_FN_ATTRS _mm_permutevar_pd(__m128d __a, __m128i __c) @@ -786,37 +786,37 @@ _mm_permutevar_pd(__m128d __a, __m128i __c) return (__m128d)__builtin_ia32_vpermilvarpd((__v2df)__a, (__v2di)__c); } -/// \brief Copies the values in a 256-bit vector of [4 x double] as -/// specified by the 256-bit integer vector operand. +/// \brief Copies the values in a 256-bit vector of [4 x double] as specified +/// by the 256-bit integer vector operand. /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VPERMILPD / PERMILPD instruction. +/// This intrinsic corresponds to the <c> VPERMILPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double]. /// \param __c /// A 256-bit integer vector operand specifying how the values are to be -/// copied. -/// Bit [1]: -/// 0: Bits [63:0] of the source are copied to bits [63:0] of the -/// returned vector. -/// 1: Bits [127:64] of the source are copied to bits [63:0] of the -/// returned vector. -/// Bit [65]: -/// 0: Bits [63:0] of the source are copied to bits [127:64] of the -/// returned vector. -/// 1: Bits [127:64] of the source are copied to bits [127:64] of the -/// returned vector. -/// Bit [129]: -/// 0: Bits [191:128] of the source are copied to bits [191:128] of the -/// returned vector. -/// 1: Bits [255:192] of the source are copied to bits [191:128] of the -/// returned vector. -/// Bit [193]: -/// 0: Bits [191:128] of the source are copied to bits [255:192] of the -/// returned vector. -/// 1: Bits [255:192] of the source are copied to bits [255:192] of the +/// copied. \n +/// Bit [1]: \n +/// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned +/// vector. \n +/// 1: Bits [127:64] of the source are copied to bits [63:0] of the +/// returned vector. \n +/// Bit [65]: \n +/// 0: Bits [63:0] of the source are copied to bits [127:64] of the +/// returned vector. \n +/// 1: Bits [127:64] of the source are copied to bits [127:64] of the +/// returned vector. \n +/// Bit [129]: \n +/// 0: Bits [191:128] of the source are copied to bits [191:128] of the +/// returned vector. \n +/// 1: Bits [255:192] of the source are copied to bits [191:128] of the +/// returned vector. \n +/// Bit [193]: \n +/// 0: Bits [191:128] of the source are copied to bits [255:192] of the +/// returned vector. \n +/// 1: Bits [255:192] of the source are copied to bits [255:192] of the /// returned vector. /// \returns A 256-bit vector of [4 x double] containing the copied values. static __inline __m256d __DEFAULT_FN_ATTRS @@ -827,52 +827,51 @@ _mm256_permutevar_pd(__m256d __a, __m256i __c) /// \brief Copies the values stored in a 128-bit vector of [4 x float] as /// specified by the 128-bit integer vector operand. -/// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VPERMILPS / PERMILPS instruction. +/// This intrinsic corresponds to the <c> VPERMILPS </c> instruction. /// /// \param __a /// A 128-bit vector of [4 x float]. /// \param __c /// A 128-bit integer vector operand specifying how the values are to be -/// copied. -/// Bits [1:0]: -/// 00: Bits [31:0] of the source are copied to bits [31:0] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [31:0] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [31:0] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [31:0] of the -/// returned vector. -/// Bits [33:32]: -/// 00: Bits [31:0] of the source are copied to bits [63:32] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [63:32] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [63:32] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [63:32] of the -/// returned vector. -/// Bits [65:64]: -/// 00: Bits [31:0] of the source are copied to bits [95:64] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [95:64] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [95:64] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [95:64] of the -/// returned vector. -/// Bits [97:96]: -/// 00: Bits [31:0] of the source are copied to bits [127:96] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [127:96] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [127:96] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [127:96] of the -/// returned vector. +/// copied. \n +/// Bits [1:0]: \n +/// 00: Bits [31:0] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// Bits [33:32]: \n +/// 00: Bits [31:0] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// Bits [65:64]: \n +/// 00: Bits [31:0] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// Bits [97:96]: \n +/// 00: Bits [31:0] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [127:96] of the +/// returned vector. /// \returns A 128-bit vector of [4 x float] containing the copied values. static __inline __m128 __DEFAULT_FN_ATTRS _mm_permutevar_ps(__m128 __a, __m128i __c) @@ -885,85 +884,85 @@ _mm_permutevar_ps(__m128 __a, __m128i __c) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VPERMILPS / PERMILPS instruction. +/// This intrinsic corresponds to the <c> VPERMILPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float]. /// \param __c /// A 256-bit integer vector operand specifying how the values are to be -/// copied. -/// Bits [1:0]: -/// 00: Bits [31:0] of the source are copied to bits [31:0] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [31:0] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [31:0] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [31:0] of the -/// returned vector. -/// Bits [33:32]: -/// 00: Bits [31:0] of the source are copied to bits [63:32] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [63:32] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [63:32] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [63:32] of the -/// returned vector. -/// Bits [65:64]: -/// 00: Bits [31:0] of the source are copied to bits [95:64] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [95:64] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [95:64] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [95:64] of the -/// returned vector. -/// Bits [97:96]: -/// 00: Bits [31:0] of the source are copied to bits [127:96] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [127:96] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [127:96] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [127:96] of the -/// returned vector. -/// Bits [129:128]: -/// 00: Bits [159:128] of the source are copied to bits [159:128] of the -/// returned vector. -/// 01: Bits [191:160] of the source are copied to bits [159:128] of the -/// returned vector. -/// 10: Bits [223:192] of the source are copied to bits [159:128] of the -/// returned vector. -/// 11: Bits [255:224] of the source are copied to bits [159:128] of the -/// returned vector. -/// Bits [161:160]: -/// 00: Bits [159:128] of the source are copied to bits [191:160] of the -/// returned vector. -/// 01: Bits [191:160] of the source are copied to bits [191:160] of the -/// returned vector. -/// 10: Bits [223:192] of the source are copied to bits [191:160] of the -/// returned vector. -/// 11: Bits [255:224] of the source are copied to bits [191:160] of the -/// returned vector. -/// Bits [193:192]: -/// 00: Bits [159:128] of the source are copied to bits [223:192] of the -/// returned vector. -/// 01: Bits [191:160] of the source are copied to bits [223:192] of the -/// returned vector. -/// 10: Bits [223:192] of the source are copied to bits [223:192] of the -/// returned vector. -/// 11: Bits [255:224] of the source are copied to bits [223:192] of the -/// returned vector. -/// Bits [225:224]: -/// 00: Bits [159:128] of the source are copied to bits [255:224] of the -/// returned vector. -/// 01: Bits [191:160] of the source are copied to bits [255:224] of the -/// returned vector. -/// 10: Bits [223:192] of the source are copied to bits [255:224] of the -/// returned vector. -/// 11: Bits [255:224] of the source are copied to bits [255:224] of the -/// returned vector. +/// copied. \n +/// Bits [1:0]: \n +/// 00: Bits [31:0] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// Bits [33:32]: \n +/// 00: Bits [31:0] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// Bits [65:64]: \n +/// 00: Bits [31:0] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// Bits [97:96]: \n +/// 00: Bits [31:0] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// Bits [129:128]: \n +/// 00: Bits [159:128] of the source are copied to bits [159:128] of the +/// returned vector. \n +/// 01: Bits [191:160] of the source are copied to bits [159:128] of the +/// returned vector. \n +/// 10: Bits [223:192] of the source are copied to bits [159:128] of the +/// returned vector. \n +/// 11: Bits [255:224] of the source are copied to bits [159:128] of the +/// returned vector. \n +/// Bits [161:160]: \n +/// 00: Bits [159:128] of the source are copied to bits [191:160] of the +/// returned vector. \n +/// 01: Bits [191:160] of the source are copied to bits [191:160] of the +/// returned vector. \n +/// 10: Bits [223:192] of the source are copied to bits [191:160] of the +/// returned vector. \n +/// 11: Bits [255:224] of the source are copied to bits [191:160] of the +/// returned vector. \n +/// Bits [193:192]: \n +/// 00: Bits [159:128] of the source are copied to bits [223:192] of the +/// returned vector. \n +/// 01: Bits [191:160] of the source are copied to bits [223:192] of the +/// returned vector. \n +/// 10: Bits [223:192] of the source are copied to bits [223:192] of the +/// returned vector. \n +/// 11: Bits [255:224] of the source are copied to bits [223:192] of the +/// returned vector. \n +/// Bits [225:224]: \n +/// 00: Bits [159:128] of the source are copied to bits [255:224] of the +/// returned vector. \n +/// 01: Bits [191:160] of the source are copied to bits [255:224] of the +/// returned vector. \n +/// 10: Bits [223:192] of the source are copied to bits [255:224] of the +/// returned vector. \n +/// 11: Bits [255:224] of the source are copied to bits [255:224] of the +/// returned vector. /// \returns A 256-bit vector of [8 x float] containing the copied values. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_permutevar_ps(__m256 __a, __m256i __c) @@ -971,8 +970,8 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) return (__m256)__builtin_ia32_vpermilvarps256((__v8sf)__a, (__v8si)__c); } -/// \brief Copies the values in a 128-bit vector of [2 x double] as -/// specified by the immediate integer operand. +/// \brief Copies the values in a 128-bit vector of [2 x double] as specified +/// by the immediate integer operand. /// /// \headerfile <x86intrin.h> /// @@ -980,30 +979,31 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// __m128d _mm_permute_pd(__m128d A, const int C); /// \endcode /// -/// This intrinsic corresponds to the \c VPERMILPD / PERMILPD instruction. +/// This intrinsic corresponds to the <c> VPERMILPD </c> instruction. /// /// \param A /// A 128-bit vector of [2 x double]. /// \param C -/// An immediate integer operand specifying how the values are to be copied. -/// Bit [0]: -/// 0: Bits [63:0] of the source are copied to bits [63:0] of the -/// returned vector. -/// 1: Bits [127:64] of the source are copied to bits [63:0] of the -/// returned vector. -/// Bit [1]: -/// 0: Bits [63:0] of the source are copied to bits [127:64] of the -/// returned vector. -/// 1: Bits [127:64] of the source are copied to bits [127:64] of the -/// returned vector. +/// An immediate integer operand specifying how the values are to be +/// copied. \n +/// Bit [0]: \n +/// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned +/// vector. \n +/// 1: Bits [127:64] of the source are copied to bits [63:0] of the +/// returned vector. \n +/// Bit [1]: \n +/// 0: Bits [63:0] of the source are copied to bits [127:64] of the +/// returned vector. \n +/// 1: Bits [127:64] of the source are copied to bits [127:64] of the +/// returned vector. /// \returns A 128-bit vector of [2 x double] containing the copied values. #define _mm_permute_pd(A, C) __extension__ ({ \ (__m128d)__builtin_shufflevector((__v2df)(__m128d)(A), \ (__v2df)_mm_undefined_pd(), \ ((C) >> 0) & 0x1, ((C) >> 1) & 0x1); }) -/// \brief Copies the values in a 256-bit vector of [4 x double] as -/// specified by the immediate integer operand. +/// \brief Copies the values in a 256-bit vector of [4 x double] as specified by +/// the immediate integer operand. /// /// \headerfile <x86intrin.h> /// @@ -1011,32 +1011,33 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// __m256d _mm256_permute_pd(__m256d A, const int C); /// \endcode /// -/// This intrinsic corresponds to the \c VPERMILPD / PERMILPD instruction. +/// This intrinsic corresponds to the <c> VPERMILPD </c> instruction. /// /// \param A /// A 256-bit vector of [4 x double]. /// \param C -/// An immediate integer operand specifying how the values are to be copied. -/// Bit [0]: -/// 0: Bits [63:0] of the source are copied to bits [63:0] of the -/// returned vector. -/// 1: Bits [127:64] of the source are copied to bits [63:0] of the -/// returned vector. -/// Bit [1]: -/// 0: Bits [63:0] of the source are copied to bits [127:64] of the -/// returned vector. -/// 1: Bits [127:64] of the source are copied to bits [127:64] of the -/// returned vector. -/// Bit [2]: -/// 0: Bits [191:128] of the source are copied to bits [191:128] of the -/// returned vector. -/// 1: Bits [255:192] of the source are copied to bits [191:128] of the -/// returned vector. -/// Bit [3]: -/// 0: Bits [191:128] of the source are copied to bits [255:192] of the -/// returned vector. -/// 1: Bits [255:192] of the source are copied to bits [255:192] of the -/// returned vector. +/// An immediate integer operand specifying how the values are to be +/// copied. \n +/// Bit [0]: \n +/// 0: Bits [63:0] of the source are copied to bits [63:0] of the returned +/// vector. \n +/// 1: Bits [127:64] of the source are copied to bits [63:0] of the +/// returned vector. \n +/// Bit [1]: \n +/// 0: Bits [63:0] of the source are copied to bits [127:64] of the +/// returned vector. \n +/// 1: Bits [127:64] of the source are copied to bits [127:64] of the +/// returned vector. \n +/// Bit [2]: \n +/// 0: Bits [191:128] of the source are copied to bits [191:128] of the +/// returned vector. \n +/// 1: Bits [255:192] of the source are copied to bits [191:128] of the +/// returned vector. \n +/// Bit [3]: \n +/// 0: Bits [191:128] of the source are copied to bits [255:192] of the +/// returned vector. \n +/// 1: Bits [255:192] of the source are copied to bits [255:192] of the +/// returned vector. /// \returns A 256-bit vector of [4 x double] containing the copied values. #define _mm256_permute_pd(A, C) __extension__ ({ \ (__m256d)__builtin_shufflevector((__v4df)(__m256d)(A), \ @@ -1046,8 +1047,8 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) 2 + (((C) >> 2) & 0x1), \ 2 + (((C) >> 3) & 0x1)); }) -/// \brief Copies the values in a 128-bit vector of [4 x float] as -/// specified by the immediate integer operand. +/// \brief Copies the values in a 128-bit vector of [4 x float] as specified by +/// the immediate integer operand. /// /// \headerfile <x86intrin.h> /// @@ -1055,48 +1056,49 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// __m128 _mm_permute_ps(__m128 A, const int C); /// \endcode /// -/// This intrinsic corresponds to the \c VPERMILPS / PERMILPS instruction. +/// This intrinsic corresponds to the <c> VPERMILPS </c> instruction. /// /// \param A /// A 128-bit vector of [4 x float]. /// \param C -/// An immediate integer operand specifying how the values are to be copied. -/// Bits [1:0]: -/// 00: Bits [31:0] of the source are copied to bits [31:0] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [31:0] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [31:0] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [31:0] of the -/// returned vector. -/// Bits [3:2]: -/// 00: Bits [31:0] of the source are copied to bits [63:32] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [63:32] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [63:32] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [63:32] of the -/// returned vector. -/// Bits [5:4]: -/// 00: Bits [31:0] of the source are copied to bits [95:64] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [95:64] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [95:64] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [95:64] of the -/// returned vector. -/// Bits [7:6]: -/// 00: Bits [31:0] of the source are copied to bits [127:96] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [127:96] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [127:96] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [127:96] of the -/// returned vector. +/// An immediate integer operand specifying how the values are to be +/// copied. \n +/// Bits [1:0]: \n +/// 00: Bits [31:0] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// Bits [3:2]: \n +/// 00: Bits [31:0] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// Bits [5:4]: \n +/// 00: Bits [31:0] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// Bits [7:6]: \n +/// 00: Bits [31:0] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [127:96] of the +/// returned vector. /// \returns A 128-bit vector of [4 x float] containing the copied values. #define _mm_permute_ps(A, C) __extension__ ({ \ (__m128)__builtin_shufflevector((__v4sf)(__m128)(A), \ @@ -1104,8 +1106,8 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) ((C) >> 0) & 0x3, ((C) >> 2) & 0x3, \ ((C) >> 4) & 0x3, ((C) >> 6) & 0x3); }) -/// \brief Copies the values in a 256-bit vector of [8 x float] as -/// specified by the immediate integer operand. +/// \brief Copies the values in a 256-bit vector of [8 x float] as specified by +/// the immediate integer operand. /// /// \headerfile <x86intrin.h> /// @@ -1113,84 +1115,85 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// __m256 _mm256_permute_ps(__m256 A, const int C); /// \endcode /// -/// This intrinsic corresponds to the \c VPERMILPS / PERMILPS instruction. +/// This intrinsic corresponds to the <c> VPERMILPS </c> instruction. /// /// \param A /// A 256-bit vector of [8 x float]. /// \param C -/// An immediate integer operand specifying how the values are to be copied. -/// Bits [1:0]: -/// 00: Bits [31:0] of the source are copied to bits [31:0] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [31:0] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [31:0] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [31:0] of the -/// returned vector. -/// Bits [3:2]: -/// 00: Bits [31:0] of the source are copied to bits [63:32] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [63:32] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [63:32] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [63:32] of the -/// returned vector. -/// Bits [5:4]: -/// 00: Bits [31:0] of the source are copied to bits [95:64] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [95:64] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [95:64] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [95:64] of the -/// returned vector. -/// Bits [7:6]: -/// 00: Bits [31:0] of the source are copied to bits [127:96] of the -/// returned vector. -/// 01: Bits [63:32] of the source are copied to bits [127:96] of the -/// returned vector. -/// 10: Bits [95:64] of the source are copied to bits [127:96] of the -/// returned vector. -/// 11: Bits [127:96] of the source are copied to bits [127:96] of the -/// returned vector. -/// Bits [1:0]: -/// 00: Bits [159:128] of the source are copied to bits [159:128] of the -/// returned vector. -/// 01: Bits [191:160] of the source are copied to bits [159:128] of the -/// returned vector. -/// 10: Bits [223:192] of the source are copied to bits [159:128] of the -/// returned vector. -/// 11: Bits [255:224] of the source are copied to bits [159:128] of the -/// returned vector. -/// Bits [3:2]: -/// 00: Bits [159:128] of the source are copied to bits [191:160] of the -/// returned vector. -/// 01: Bits [191:160] of the source are copied to bits [191:160] of the -/// returned vector. -/// 10: Bits [223:192] of the source are copied to bits [191:160] of the -/// returned vector. -/// 11: Bits [255:224] of the source are copied to bits [191:160] of the -/// returned vector. -/// Bits [5:4]: -/// 00: Bits [159:128] of the source are copied to bits [223:192] of the -/// returned vector. -/// 01: Bits [191:160] of the source are copied to bits [223:192] of the -/// returned vector. -/// 10: Bits [223:192] of the source are copied to bits [223:192] of the -/// returned vector. -/// 11: Bits [255:224] of the source are copied to bits [223:192] of the -/// returned vector. -/// Bits [7:6]: -/// 00: Bits [159:128] of the source are copied to bits [255:224] of the -/// returned vector. -/// 01: Bits [191:160] of the source are copied to bits [255:224] of the -/// returned vector. -/// 10: Bits [223:192] of the source are copied to bits [255:224] of the -/// returned vector. -/// 11: Bits [255:224] of the source are copied to bits [255:224] of the -/// returned vector. +/// An immediate integer operand specifying how the values are to be \n +/// copied. \n +/// Bits [1:0]: \n +/// 00: Bits [31:0] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [31:0] of the +/// returned vector. \n +/// Bits [3:2]: \n +/// 00: Bits [31:0] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [63:32] of the +/// returned vector. \n +/// Bits [5:4]: \n +/// 00: Bits [31:0] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [95:64] of the +/// returned vector. \n +/// Bits [7:6]: \n +/// 00: Bits [31:qq0] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 01: Bits [63:32] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 10: Bits [95:64] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// 11: Bits [127:96] of the source are copied to bits [127:96] of the +/// returned vector. \n +/// Bits [1:0]: \n +/// 00: Bits [159:128] of the source are copied to bits [159:128] of the +/// returned vector. \n +/// 01: Bits [191:160] of the source are copied to bits [159:128] of the +/// returned vector. \n +/// 10: Bits [223:192] of the source are copied to bits [159:128] of the +/// returned vector. \n +/// 11: Bits [255:224] of the source are copied to bits [159:128] of the +/// returned vector. \n +/// Bits [3:2]: \n +/// 00: Bits [159:128] of the source are copied to bits [191:160] of the +/// returned vector. \n +/// 01: Bits [191:160] of the source are copied to bits [191:160] of the +/// returned vector. \n +/// 10: Bits [223:192] of the source are copied to bits [191:160] of the +/// returned vector. \n +/// 11: Bits [255:224] of the source are copied to bits [191:160] of the +/// returned vector. \n +/// Bits [5:4]: \n +/// 00: Bits [159:128] of the source are copied to bits [223:192] of the +/// returned vector. \n +/// 01: Bits [191:160] of the source are copied to bits [223:192] of the +/// returned vector. \n +/// 10: Bits [223:192] of the source are copied to bits [223:192] of the +/// returned vector. \n +/// 11: Bits [255:224] of the source are copied to bits [223:192] of the +/// returned vector. \n +/// Bits [7:6]: \n +/// 00: Bits [159:128] of the source are copied to bits [255:224] of the +/// returned vector. \n +/// 01: Bits [191:160] of the source are copied to bits [255:224] of the +/// returned vector. \n +/// 10: Bits [223:192] of the source are copied to bits [255:224] of the +/// returned vector. \n +/// 11: Bits [255:224] of the source are copied to bits [255:224] of the +/// returned vector. /// \returns A 256-bit vector of [8 x float] containing the copied values. #define _mm256_permute_ps(A, C) __extension__ ({ \ (__m256)__builtin_shufflevector((__v8sf)(__m256)(A), \ @@ -1213,7 +1216,7 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// __m256d _mm256_permute2f128_pd(__m256d V1, __m256d V2, const int M); /// \endcode /// -/// This intrinsic corresponds to the \c VPERM2F128 / PERM2F128 instruction. +/// This intrinsic corresponds to the <c> VPERM2F128 </c> instruction. /// /// \param V1 /// A 256-bit vector of [4 x double]. @@ -1221,25 +1224,25 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// A 256-bit vector of [4 x double. /// \param M /// An immediate integer operand specifying how the values are to be -/// permuted. -/// Bits [1:0]: -/// 00: Bits [127:0] of operand V1 are copied to bits [127:0] of the -/// destination. -/// 01: Bits [255:128] of operand V1 are copied to bits [127:0] of the -/// destination. -/// 10: Bits [127:0] of operand V2 are copied to bits [127:0] of the -/// destination. -/// 11: Bits [255:128] of operand V2 are copied to bits [127:0] of the -/// destination. -/// Bits [5:4]: -/// 00: Bits [127:0] of operand V1 are copied to bits [255:128] of the -/// destination. -/// 01: Bits [255:128] of operand V1 are copied to bits [255:128] of the -/// destination. -/// 10: Bits [127:0] of operand V2 are copied to bits [255:128] of the -/// destination. -/// 11: Bits [255:128] of operand V2 are copied to bits [255:128] of the -/// destination. +/// permuted. \n +/// Bits [1:0]: \n +/// 00: Bits [127:0] of operand \a V1 are copied to bits [127:0] of the +/// destination. \n +/// 01: Bits [255:128] of operand \a V1 are copied to bits [127:0] of the +/// destination. \n +/// 10: Bits [127:0] of operand \a V2 are copied to bits [127:0] of the +/// destination. \n +/// 11: Bits [255:128] of operand \a V2 are copied to bits [127:0] of the +/// destination. \n +/// Bits [5:4]: \n +/// 00: Bits [127:0] of operand \a V1 are copied to bits [255:128] of the +/// destination. \n +/// 01: Bits [255:128] of operand \a V1 are copied to bits [255:128] of the +/// destination. \n +/// 10: Bits [127:0] of operand \a V2 are copied to bits [255:128] of the +/// destination. \n +/// 11: Bits [255:128] of operand \a V2 are copied to bits [255:128] of the +/// destination. /// \returns A 256-bit vector of [4 x double] containing the copied values. #define _mm256_permute2f128_pd(V1, V2, M) __extension__ ({ \ (__m256d)__builtin_ia32_vperm2f128_pd256((__v4df)(__m256d)(V1), \ @@ -1254,7 +1257,7 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// __m256 _mm256_permute2f128_ps(__m256 V1, __m256 V2, const int M); /// \endcode /// -/// This intrinsic corresponds to the \c VPERM2F128 / PERM2F128 instruction. +/// This intrinsic corresponds to the <c> VPERM2F128 </c> instruction. /// /// \param V1 /// A 256-bit vector of [8 x float]. @@ -1262,24 +1265,24 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// A 256-bit vector of [8 x float]. /// \param M /// An immediate integer operand specifying how the values are to be -/// permuted. -/// Bits [1:0]: -/// 00: Bits [127:0] of operand V1 are copied to bits [127:0] of the -/// destination. -/// 01: Bits [255:128] of operand V1 are copied to bits [127:0] of the -/// destination. -/// 10: Bits [127:0] of operand V2 are copied to bits [127:0] of the -/// destination. -/// 11: Bits [255:128] of operand V2 are copied to bits [127:0] of the -/// destination. -/// Bits [5:4]: -/// 00: Bits [127:0] of operand V1 are copied to bits [255:128] of the -/// destination. -/// 01: Bits [255:128] of operand V1 are copied to bits [255:128] of the -/// destination. -/// 10: Bits [127:0] of operand V2 are copied to bits [255:128] of the -/// destination. -/// 11: Bits [255:128] of operand V2 are copied to bits [255:128] of the +/// permuted. \n +/// Bits [1:0]: \n +/// 00: Bits [127:0] of operand \a V1 are copied to bits [127:0] of the +/// destination. \n +/// 01: Bits [255:128] of operand \a V1 are copied to bits [127:0] of the +/// destination. \n +/// 10: Bits [127:0] of operand \a V2 are copied to bits [127:0] of the +/// destination. \n +/// 11: Bits [255:128] of operand \a V2 are copied to bits [127:0] of the +/// destination. \n +/// Bits [5:4]: \n +/// 00: Bits [127:0] of operand \a V1 are copied to bits [255:128] of the +/// destination. \n +/// 01: Bits [255:128] of operand \a V1 are copied to bits [255:128] of the +/// destination. \n +/// 10: Bits [127:0] of operand \a V2 are copied to bits [255:128] of the +/// destination. \n +/// 11: Bits [255:128] of operand \a V2 are copied to bits [255:128] of the /// destination. /// \returns A 256-bit vector of [8 x float] containing the copied values. #define _mm256_permute2f128_ps(V1, V2, M) __extension__ ({ \ @@ -1295,7 +1298,7 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// __m256i _mm256_permute2f128_si256(__m256i V1, __m256i V2, const int M); /// \endcode /// -/// This intrinsic corresponds to the \c VPERM2F128 / PERM2F128 instruction. +/// This intrinsic corresponds to the <c> VPERM2F128 </c> instruction. /// /// \param V1 /// A 256-bit integer vector. @@ -1303,23 +1306,23 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// A 256-bit integer vector. /// \param M /// An immediate integer operand specifying how the values are to be copied. -/// Bits [1:0]: -/// 00: Bits [127:0] of operand V1 are copied to bits [127:0] of the -/// destination. -/// 01: Bits [255:128] of operand V1 are copied to bits [127:0] of the -/// destination. -/// 10: Bits [127:0] of operand V2 are copied to bits [127:0] of the -/// destination. -/// 11: Bits [255:128] of operand V2 are copied to bits [127:0] of the -/// destination. -/// Bits [5:4]: -/// 00: Bits [127:0] of operand V1 are copied to bits [255:128] of the -/// destination. -/// 01: Bits [255:128] of operand V1 are copied to bits [255:128] of the -/// destination. -/// 10: Bits [127:0] of operand V2 are copied to bits [255:128] of the -/// destination. -/// 11: Bits [255:128] of operand V2 are copied to bits [255:128] of the +/// Bits [1:0]: \n +/// 00: Bits [127:0] of operand \a V1 are copied to bits [127:0] of the +/// destination. \n +/// 01: Bits [255:128] of operand \a V1 are copied to bits [127:0] of the +/// destination. \n +/// 10: Bits [127:0] of operand \a V2 are copied to bits [127:0] of the +/// destination. \n +/// 11: Bits [255:128] of operand \a V2 are copied to bits [127:0] of the +/// destination. \n +/// Bits [5:4]: \n +/// 00: Bits [127:0] of operand \a V1 are copied to bits [255:128] of the +/// destination. \n +/// 01: Bits [255:128] of operand \a V1 are copied to bits [255:128] of the +/// destination. \n +/// 10: Bits [127:0] of operand \a V2 are copied to bits [255:128] of the +/// destination. \n +/// 11: Bits [255:128] of operand \a V2 are copied to bits [255:128] of the /// destination. /// \returns A 256-bit integer vector containing the copied values. #define _mm256_permute2f128_si256(V1, V2, M) __extension__ ({ \ @@ -1337,7 +1340,7 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// __m256d _mm256_blend_pd(__m256d V1, __m256d V2, const int M); /// \endcode /// -/// This intrinsic corresponds to the \c VBLENDPD / BLENDPD instruction. +/// This intrinsic corresponds to the <c> VBLENDPD </c> instruction. /// /// \param V1 /// A 256-bit vector of [4 x double]. @@ -1347,9 +1350,9 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// An immediate integer operand, with mask bits [3:0] specifying how the /// values are to be copied. The position of the mask bit corresponds to the /// index of a copied value. When a mask bit is 0, the corresponding 64-bit -/// element in operand V1 is copied to the same position in the destination. -/// When a mask bit is 1, the corresponding 64-bit element in operand V2 is -/// copied to the same position in the destination. +/// element in operand \a V1 is copied to the same position in the +/// destination. When a mask bit is 1, the corresponding 64-bit element in +/// operand \a V2 is copied to the same position in the destination. /// \returns A 256-bit vector of [4 x double] containing the copied values. #define _mm256_blend_pd(V1, V2, M) __extension__ ({ \ (__m256d)__builtin_shufflevector((__v4df)(__m256d)(V1), \ @@ -1369,7 +1372,7 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// __m256 _mm256_blend_ps(__m256 V1, __m256 V2, const int M); /// \endcode /// -/// This intrinsic corresponds to the \c VBLENDPS / BLENDPS instruction. +/// This intrinsic corresponds to the <c> VBLENDPS </c> instruction. /// /// \param V1 /// A 256-bit vector of [8 x float]. @@ -1379,9 +1382,9 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// An immediate integer operand, with mask bits [7:0] specifying how the /// values are to be copied. The position of the mask bit corresponds to the /// index of a copied value. When a mask bit is 0, the corresponding 32-bit -/// element in operand V1 is copied to the same position in the destination. -/// When a mask bit is 1, the corresponding 32-bit element in operand V2 is -/// copied to the same position in the destination. +/// element in operand \a V1 is copied to the same position in the +/// destination. When a mask bit is 1, the corresponding 32-bit element in +/// operand \a V2 is copied to the same position in the destination. /// \returns A 256-bit vector of [8 x float] containing the copied values. #define _mm256_blend_ps(V1, V2, M) __extension__ ({ \ (__m256)__builtin_shufflevector((__v8sf)(__m256)(V1), \ @@ -1401,7 +1404,7 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VBLENDVPD / BLENDVPD instruction. +/// This intrinsic corresponds to the <c> VBLENDVPD </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double]. @@ -1411,9 +1414,9 @@ _mm256_permutevar_ps(__m256 __a, __m256i __c) /// A 256-bit vector operand, with mask bits 255, 191, 127, and 63 specifying /// how the values are to be copied. The position of the mask bit corresponds /// to the most significant bit of a copied value. When a mask bit is 0, the -/// corresponding 64-bit element in operand __a is copied to the same +/// corresponding 64-bit element in operand \a __a is copied to the same /// position in the destination. When a mask bit is 1, the corresponding -/// 64-bit element in operand __b is copied to the same position in the +/// 64-bit element in operand \a __b is copied to the same position in the /// destination. /// \returns A 256-bit vector of [4 x double] containing the copied values. static __inline __m256d __DEFAULT_FN_ATTRS @@ -1429,7 +1432,7 @@ _mm256_blendv_pd(__m256d __a, __m256d __b, __m256d __c) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VBLENDVPS / BLENDVPS instruction. +/// This intrinsic corresponds to the <c> VBLENDVPS </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float]. @@ -1439,9 +1442,9 @@ _mm256_blendv_pd(__m256d __a, __m256d __b, __m256d __c) /// A 256-bit vector operand, with mask bits 255, 223, 191, 159, 127, 95, 63, /// and 31 specifying how the values are to be copied. The position of the /// mask bit corresponds to the most significant bit of a copied value. When -/// a mask bit is 0, the corresponding 32-bit element in operand __a is +/// a mask bit is 0, the corresponding 32-bit element in operand \a __a is /// copied to the same position in the destination. When a mask bit is 1, the -/// corresponding 32-bit element in operand __b is copied to the same +/// corresponding 32-bit element in operand \a __b is copied to the same /// position in the destination. /// \returns A 256-bit vector of [8 x float] containing the copied values. static __inline __m256 __DEFAULT_FN_ATTRS @@ -1455,12 +1458,12 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// \brief Computes two dot products in parallel, using the lower and upper /// halves of two [8 x float] vectors as input to the two computations, and /// returning the two dot products in the lower and upper halves of the -/// [8 x float] result. The immediate integer operand controls which -/// input elements will contribute to the dot product, and where the final -/// results are returned. In general, for each dot product, the four -/// corresponding elements of the input vectors are multiplied; the first -/// two and second two products are summed, then the two sums are added to -/// form the final result. +/// [8 x float] result. The immediate integer operand controls which input +/// elements will contribute to the dot product, and where the final results +/// are returned. In general, for each dot product, the four corresponding +/// elements of the input vectors are multiplied; the first two and second +/// two products are summed, then the two sums are added to form the final +/// result. /// /// \headerfile <x86intrin.h> /// @@ -1468,7 +1471,7 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// __m256 _mm256_dp_ps(__m256 V1, __m256 V2, const int M); /// \endcode /// -/// This intrinsic corresponds to the \c VDPPS / DPPS instruction. +/// This intrinsic corresponds to the <c> VDPPS </c> instruction. /// /// \param V1 /// A vector of [8 x float] values, treated as two [4 x float] vectors. @@ -1510,7 +1513,7 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// __m256 _mm256_shuffle_ps(__m256 a, __m256 b, const int mask); /// \endcode /// -/// This intrinsic corresponds to the \c VSHUFPS / SHUFPS instruction. +/// This intrinsic corresponds to the <c> VSHUFPS </c> instruction. /// /// \param a /// A 256-bit vector of [8 x float]. The four selected elements in this @@ -1522,22 +1525,23 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// destination, according to the bits specified in the immediate operand. /// \param mask /// An immediate value containing an 8-bit value specifying which elements to -/// copy from a and b. Bits [3:0] specify the values copied from operand a. -/// Bits [7:4] specify the values copied from operand b. +/// copy from \a a and \a b \n. +/// Bits [3:0] specify the values copied from operand \a a. \n +/// Bits [7:4] specify the values copied from operand \a b. \n /// The destinations within the 256-bit destination are assigned values as -/// follows, according to the bit value assignments described below: +/// follows, according to the bit value assignments described below: \n /// Bits [1:0] are used to assign values to bits [31:0] and [159:128] in the -/// destination. +/// destination. \n /// Bits [3:2] are used to assign values to bits [63:32] and [191:160] in the -/// destination. +/// destination. \n /// Bits [5:4] are used to assign values to bits [95:64] and [223:192] in the -/// destination. +/// destination. \n /// Bits [7:6] are used to assign values to bits [127:96] and [255:224] in -/// the destination. -/// Bit value assignments: -/// 00: Bits [31:0] and [159:128] are copied from the selected operand. -/// 01: Bits [63:32] and [191:160] are copied from the selected operand. -/// 10: Bits [95:64] and [223:192] are copied from the selected operand. +/// the destination. \n +/// Bit value assignments: \n +/// 00: Bits [31:0] and [159:128] are copied from the selected operand. \n +/// 01: Bits [63:32] and [191:160] are copied from the selected operand. \n +/// 10: Bits [95:64] and [223:192] are copied from the selected operand. \n /// 11: Bits [127:96] and [255:224] are copied from the selected operand. /// \returns A 256-bit vector of [8 x float] containing the shuffled values. #define _mm256_shuffle_ps(a, b, mask) __extension__ ({ \ @@ -1567,7 +1571,7 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// __m256d _mm256_shuffle_pd(__m256d a, __m256d b, const int mask); /// \endcode /// -/// This intrinsic corresponds to the \c VSHUFPD / SHUFPD instruction. +/// This intrinsic corresponds to the <c> VSHUFPD </c> instruction. /// /// \param a /// A 256-bit vector of [4 x double]. @@ -1575,22 +1579,22 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// A 256-bit vector of [4 x double]. /// \param mask /// An immediate value containing 8-bit values specifying which elements to -/// copy from a and b: -/// Bit [0]=0: Bits [63:0] are copied from a to bits [63:0] of the -/// destination. -/// Bit [0]=1: Bits [127:64] are copied from a to bits [63:0] of the -/// destination. -/// Bit [1]=0: Bits [63:0] are copied from b to bits [127:64] of the -/// destination. -/// Bit [1]=1: Bits [127:64] are copied from b to bits [127:64] of the -/// destination. -/// Bit [2]=0: Bits [191:128] are copied from a to bits [191:128] of the -/// destination. -/// Bit [2]=1: Bits [255:192] are copied from a to bits [191:128] of the -/// destination. -/// Bit [3]=0: Bits [191:128] are copied from b to bits [255:192] of the -/// destination. -/// Bit [3]=1: Bits [255:192] are copied from b to bits [255:192] of the +/// copy from \a a and \a b: \n +/// Bit [0]=0: Bits [63:0] are copied from \a a to bits [63:0] of the +/// destination. \n +/// Bit [0]=1: Bits [127:64] are copied from \a a to bits [63:0] of the +/// destination. \n +/// Bit [1]=0: Bits [63:0] are copied from \a b to bits [127:64] of the +/// destination. \n +/// Bit [1]=1: Bits [127:64] are copied from \a b to bits [127:64] of the +/// destination. \n +/// Bit [2]=0: Bits [191:128] are copied from \a a to bits [191:128] of the +/// destination. \n +/// Bit [2]=1: Bits [255:192] are copied from \a a to bits [191:128] of the +/// destination. \n +/// Bit [3]=0: Bits [191:128] are copied from \a b to bits [255:192] of the +/// destination. \n +/// Bit [3]=1: Bits [255:192] are copied from \a b to bits [255:192] of the /// destination. /// \returns A 256-bit vector of [4 x double] containing the shuffled values. #define _mm256_shuffle_pd(a, b, mask) __extension__ ({ \ @@ -1647,7 +1651,7 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// __m128d _mm_cmp_pd(__m128d a, __m128d b, const int c); /// \endcode /// -/// This intrinsic corresponds to the \c VCMPPD / CMPPD instruction. +/// This intrinsic corresponds to the <c> VCMPPD </c> instruction. /// /// \param a /// A 128-bit vector of [2 x double]. @@ -1655,16 +1659,17 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// A 128-bit vector of [2 x double]. /// \param c /// An immediate integer operand, with bits [4:0] specifying which comparison -/// operation to use: -/// 00h, 08h, 10h, 18h: Equal -/// 01h, 09h, 11h, 19h: Less than -/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal (swapped -/// operands) -/// 03h, 0Bh, 13h, 1Bh: Unordered -/// 04h, 0Ch, 14h, 1Ch: Not equal -/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than (swapped operands) +/// operation to use: \n +/// 00h, 08h, 10h, 18h: Equal \n +/// 01h, 09h, 11h, 19h: Less than \n +/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal +/// (swapped operands) \n +/// 03h, 0Bh, 13h, 1Bh: Unordered \n +/// 04h, 0Ch, 14h, 1Ch: Not equal \n +/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than +/// (swapped operands) \n /// 06h, 0Eh, 16h, 1Eh: Not less than or equal / Not greater than or equal -/// (swapped operands) +/// (swapped operands) \n /// 07h, 0Fh, 17h, 1Fh: Ordered /// \returns A 128-bit vector of [2 x double] containing the comparison results. #define _mm_cmp_pd(a, b, c) __extension__ ({ \ @@ -1683,7 +1688,7 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// __m128 _mm_cmp_ps(__m128 a, __m128 b, const int c); /// \endcode /// -/// This intrinsic corresponds to the \c VCMPPS / CMPPS instruction. +/// This intrinsic corresponds to the <c> VCMPPS </c> instruction. /// /// \param a /// A 128-bit vector of [4 x float]. @@ -1691,16 +1696,17 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// A 128-bit vector of [4 x float]. /// \param c /// An immediate integer operand, with bits [4:0] specifying which comparison -/// operation to use: -/// 00h, 08h, 10h, 18h: Equal -/// 01h, 09h, 11h, 19h: Less than -/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal (swapped -/// operands) -/// 03h, 0Bh, 13h, 1Bh: Unordered -/// 04h, 0Ch, 14h, 1Ch: Not equal -/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than (swapped operands) +/// operation to use: \n +/// 00h, 08h, 10h, 18h: Equal \n +/// 01h, 09h, 11h, 19h: Less than \n +/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal +/// (swapped operands) \n +/// 03h, 0Bh, 13h, 1Bh: Unordered \n +/// 04h, 0Ch, 14h, 1Ch: Not equal \n +/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than +/// (swapped operands) \n /// 06h, 0Eh, 16h, 1Eh: Not less than or equal / Not greater than or equal -/// (swapped operands) +/// (swapped operands) \n /// 07h, 0Fh, 17h, 1Fh: Ordered /// \returns A 128-bit vector of [4 x float] containing the comparison results. #define _mm_cmp_ps(a, b, c) __extension__ ({ \ @@ -1719,7 +1725,7 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// __m256d _mm256_cmp_pd(__m256d a, __m256d b, const int c); /// \endcode /// -/// This intrinsic corresponds to the \c VCMPPD / CMPPD instruction. +/// This intrinsic corresponds to the <c> VCMPPD </c> instruction. /// /// \param a /// A 256-bit vector of [4 x double]. @@ -1727,16 +1733,17 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// A 256-bit vector of [4 x double]. /// \param c /// An immediate integer operand, with bits [4:0] specifying which comparison -/// operation to use: -/// 00h, 08h, 10h, 18h: Equal -/// 01h, 09h, 11h, 19h: Less than -/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal (swapped -/// operands) -/// 03h, 0Bh, 13h, 1Bh: Unordered -/// 04h, 0Ch, 14h, 1Ch: Not equal -/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than (swapped operands) +/// operation to use: \n +/// 00h, 08h, 10h, 18h: Equal \n +/// 01h, 09h, 11h, 19h: Less than \n +/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal +/// (swapped operands) \n +/// 03h, 0Bh, 13h, 1Bh: Unordered \n +/// 04h, 0Ch, 14h, 1Ch: Not equal \n +/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than +/// (swapped operands) \n /// 06h, 0Eh, 16h, 1Eh: Not less than or equal / Not greater than or equal -/// (swapped operands) +/// (swapped operands) \n /// 07h, 0Fh, 17h, 1Fh: Ordered /// \returns A 256-bit vector of [4 x double] containing the comparison results. #define _mm256_cmp_pd(a, b, c) __extension__ ({ \ @@ -1755,7 +1762,7 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// __m256 _mm256_cmp_ps(__m256 a, __m256 b, const int c); /// \endcode /// -/// This intrinsic corresponds to the \c VCMPPS / CMPPS instruction. +/// This intrinsic corresponds to the <c> VCMPPS </c> instruction. /// /// \param a /// A 256-bit vector of [8 x float]. @@ -1763,16 +1770,17 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// A 256-bit vector of [8 x float]. /// \param c /// An immediate integer operand, with bits [4:0] specifying which comparison -/// operation to use: -/// 00h, 08h, 10h, 18h: Equal -/// 01h, 09h, 11h, 19h: Less than -/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal (swapped -/// operands) -/// 03h, 0Bh, 13h, 1Bh: Unordered -/// 04h, 0Ch, 14h, 1Ch: Not equal -/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than (swapped operands) +/// operation to use: \n +/// 00h, 08h, 10h, 18h: Equal \n +/// 01h, 09h, 11h, 19h: Less than \n +/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal +/// (swapped operands) \n +/// 03h, 0Bh, 13h, 1Bh: Unordered \n +/// 04h, 0Ch, 14h, 1Ch: Not equal \n +/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than +/// (swapped operands) \n /// 06h, 0Eh, 16h, 1Eh: Not less than or equal / Not greater than or equal -/// (swapped operands) +/// (swapped operands) \n /// 07h, 0Fh, 17h, 1Fh: Ordered /// \returns A 256-bit vector of [8 x float] containing the comparison results. #define _mm256_cmp_ps(a, b, c) __extension__ ({ \ @@ -1790,7 +1798,7 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// __m128d _mm_cmp_sd(__m128d a, __m128d b, const int c); /// \endcode /// -/// This intrinsic corresponds to the \c VCMPSD / CMPSD instruction. +/// This intrinsic corresponds to the <c> VCMPSD </c> instruction. /// /// \param a /// A 128-bit vector of [2 x double]. @@ -1798,16 +1806,17 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// A 128-bit vector of [2 x double]. /// \param c /// An immediate integer operand, with bits [4:0] specifying which comparison -/// operation to use: -/// 00h, 08h, 10h, 18h: Equal -/// 01h, 09h, 11h, 19h: Less than -/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal (swapped -/// operands) -/// 03h, 0Bh, 13h, 1Bh: Unordered -/// 04h, 0Ch, 14h, 1Ch: Not equal -/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than (swapped operands) +/// operation to use: \n +/// 00h, 08h, 10h, 18h: Equal \n +/// 01h, 09h, 11h, 19h: Less than \n +/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal +/// (swapped operands) \n +/// 03h, 0Bh, 13h, 1Bh: Unordered \n +/// 04h, 0Ch, 14h, 1Ch: Not equal \n +/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than +/// (swapped operands) \n /// 06h, 0Eh, 16h, 1Eh: Not less than or equal / Not greater than or equal -/// (swapped operands) +/// (swapped operands) \n /// 07h, 0Fh, 17h, 1Fh: Ordered /// \returns A 128-bit vector of [2 x double] containing the comparison results. #define _mm_cmp_sd(a, b, c) __extension__ ({ \ @@ -1825,7 +1834,7 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// __m128 _mm_cmp_ss(__m128 a, __m128 b, const int c); /// \endcode /// -/// This intrinsic corresponds to the \c VCMPSS / CMPSS instruction. +/// This intrinsic corresponds to the <c> VCMPSS </c> instruction. /// /// \param a /// A 128-bit vector of [4 x float]. @@ -1833,16 +1842,17 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// A 128-bit vector of [4 x float]. /// \param c /// An immediate integer operand, with bits [4:0] specifying which comparison -/// operation to use: -/// 00h, 08h, 10h, 18h: Equal -/// 01h, 09h, 11h, 19h: Less than -/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal (swapped -/// operands) -/// 03h, 0Bh, 13h, 1Bh: Unordered -/// 04h, 0Ch, 14h, 1Ch: Not equal -/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than (swapped operands) +/// operation to use: \n +/// 00h, 08h, 10h, 18h: Equal \n +/// 01h, 09h, 11h, 19h: Less than \n +/// 02h, 0Ah, 12h, 1Ah: Less than or equal / Greater than or equal +/// (swapped operands) \n +/// 03h, 0Bh, 13h, 1Bh: Unordered \n +/// 04h, 0Ch, 14h, 1Ch: Not equal \n +/// 05h, 0Dh, 15h, 1Dh: Not less than / Not greater than +/// (swapped operands) \n /// 06h, 0Eh, 16h, 1Eh: Not less than or equal / Not greater than or equal -/// (swapped operands) +/// (swapped operands) \n /// 07h, 0Fh, 17h, 1Fh: Ordered /// \returns A 128-bit vector of [4 x float] containing the comparison results. #define _mm_cmp_ss(a, b, c) __extension__ ({ \ @@ -1854,8 +1864,8 @@ _mm256_blendv_ps(__m256 __a, __m256 __b, __m256 __c) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VEXTRACTF128+COMPOSITE / -/// EXTRACTF128+COMPOSITE instruction. +/// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c> +/// instruction. /// /// \param __a /// A 256-bit vector of [8 x i32]. @@ -1876,8 +1886,8 @@ _mm256_extract_epi32(__m256i __a, const int __imm) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VEXTRACTF128+COMPOSITE / -/// EXTRACTF128+COMPOSITE instruction. +/// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c> +/// instruction. /// /// \param __a /// A 256-bit integer vector of [16 x i16]. @@ -1898,8 +1908,8 @@ _mm256_extract_epi16(__m256i __a, const int __imm) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VEXTRACTF128+COMPOSITE / -/// EXTRACTF128+COMPOSITE instruction. +/// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c> +/// instruction. /// /// \param __a /// A 256-bit integer vector of [32 x i8]. @@ -1921,8 +1931,8 @@ _mm256_extract_epi8(__m256i __a, const int __imm) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VEXTRACTF128+COMPOSITE / -/// EXTRACTF128+COMPOSITE instruction. +/// This intrinsic corresponds to the <c> VEXTRACTF128+COMPOSITE </c> +/// instruction. /// /// \param __a /// A 256-bit integer vector of [4 x i64]. @@ -1945,8 +1955,8 @@ _mm256_extract_epi64(__m256i __a, const int __imm) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VINSERTF128+COMPOSITE / -/// INSERTF128+COMPOSITE instruction. +/// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c> +/// instruction. /// /// \param __a /// A vector of [8 x i32] to be used by the insert operation. @@ -1955,8 +1965,8 @@ _mm256_extract_epi64(__m256i __a, const int __imm) /// \param __imm /// An immediate integer specifying the index of the vector element to be /// replaced. -/// \returns A copy of vector __a, after replacing its element indexed by __imm -/// with __b. +/// \returns A copy of vector \a __a, after replacing its element indexed by +/// \a __imm with \a __b. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_insert_epi32(__m256i __a, int __b, int const __imm) { @@ -1972,8 +1982,8 @@ _mm256_insert_epi32(__m256i __a, int __b, int const __imm) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VINSERTF128+COMPOSITE / -/// INSERTF128+COMPOSITE instruction. +/// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c> +/// instruction. /// /// \param __a /// A vector of [16 x i16] to be used by the insert operation. @@ -1982,8 +1992,8 @@ _mm256_insert_epi32(__m256i __a, int __b, int const __imm) /// \param __imm /// An immediate integer specifying the index of the vector element to be /// replaced. -/// \returns A copy of vector __a, after replacing its element indexed by __imm -/// with __b. +/// \returns A copy of vector \a __a, after replacing its element indexed by +/// \a __imm with \a __b. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_insert_epi16(__m256i __a, int __b, int const __imm) { @@ -1998,8 +2008,8 @@ _mm256_insert_epi16(__m256i __a, int __b, int const __imm) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VINSERTF128+COMPOSITE / -/// INSERTF128+COMPOSITE instruction. +/// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c> +/// instruction. /// /// \param __a /// A vector of [32 x i8] to be used by the insert operation. @@ -2008,8 +2018,8 @@ _mm256_insert_epi16(__m256i __a, int __b, int const __imm) /// \param __imm /// An immediate integer specifying the index of the vector element to be /// replaced. -/// \returns A copy of vector __a, after replacing its element indexed by __imm -/// with __b. +/// \returns A copy of vector \a __a, after replacing its element indexed by +/// \a __imm with \a __b. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_insert_epi8(__m256i __a, int __b, int const __imm) { @@ -2025,8 +2035,8 @@ _mm256_insert_epi8(__m256i __a, int __b, int const __imm) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VINSERTF128+COMPOSITE / -/// INSERTF128+COMPOSITE instruction. +/// This intrinsic corresponds to the <c> VINSERTF128+COMPOSITE </c> +/// instruction. /// /// \param __a /// A vector of [4 x i64] to be used by the insert operation. @@ -2035,8 +2045,8 @@ _mm256_insert_epi8(__m256i __a, int __b, int const __imm) /// \param __imm /// An immediate integer specifying the index of the vector element to be /// replaced. -/// \returns A copy of vector __a, after replacing its element indexed by __imm -/// with __b. +/// \returns A copy of vector \a __a, after replacing its element indexed by +/// \a __imm with \a __b. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_insert_epi64(__m256i __a, long long __b, int const __imm) { @@ -2051,7 +2061,7 @@ _mm256_insert_epi64(__m256i __a, long long __b, int const __imm) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTDQ2PD / CVTDQ2PD instruction. +/// This intrinsic corresponds to the <c> VCVTDQ2PD </c> instruction. /// /// \param __a /// A 128-bit integer vector of [4 x i32]. @@ -2066,7 +2076,7 @@ _mm256_cvtepi32_pd(__m128i __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTDQ2PS / CVTDQ2PS instruction. +/// This intrinsic corresponds to the <c> VCVTDQ2PS </c> instruction. /// /// \param __a /// A 256-bit integer vector. @@ -2082,7 +2092,7 @@ _mm256_cvtepi32_ps(__m256i __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTPD2PS / CVTPD2PS instruction. +/// This intrinsic corresponds to the <c> VCVTPD2PS </c> instruction. /// /// \param __a /// A 256-bit vector of [4 x double]. @@ -2097,7 +2107,7 @@ _mm256_cvtpd_ps(__m256d __a) /// /// \headerfile <x86intrin.h> /// -/// This intrinsic corresponds to the \c VCVTPS2DQ / CVTPS2DQ instruction. +/// This intrinsic corresponds to the <c> VCVTPS2DQ </c> instruction. /// /// \param __a /// A 256-bit vector of [8 x float]. @@ -2108,24 +2118,66 @@ _mm256_cvtps_epi32(__m256 __a) return (__m256i)__builtin_ia32_cvtps2dq256((__v8sf) __a); } +/// \brief Converts a 128-bit vector of [4 x float] into a 256-bit vector of [4 +/// x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VCVTPS2PD </c> instruction. +/// +/// \param __a +/// A 128-bit vector of [4 x float]. +/// \returns A 256-bit vector of [4 x double] containing the converted values. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_cvtps_pd(__m128 __a) { return (__m256d)__builtin_convertvector((__v4sf)__a, __v4df); } +/// \brief Converts a 256-bit vector of [4 x double] into a 128-bit vector of [4 +/// x i32], truncating the result by rounding towards zero when it is +/// inexact. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VCVTTPD2DQ </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x double]. +/// \returns A 128-bit integer vector containing the converted values. static __inline __m128i __DEFAULT_FN_ATTRS _mm256_cvttpd_epi32(__m256d __a) { return (__m128i)__builtin_ia32_cvttpd2dq256((__v4df) __a); } +/// \brief Converts a 256-bit vector of [4 x double] into a 128-bit vector of [4 +/// x i32]. When a conversion is inexact, the value returned is rounded +/// according to the rounding control bits in the MXCSR register. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VCVTPD2DQ </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x double]. +/// \returns A 128-bit integer vector containing the converted values. static __inline __m128i __DEFAULT_FN_ATTRS _mm256_cvtpd_epi32(__m256d __a) { return (__m128i)__builtin_ia32_cvtpd2dq256((__v4df) __a); } +/// \brief Converts a vector of [8 x float] into a vector of [8 x i32], +/// truncating the result by rounding towards zero when it is inexact. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VCVTTPS2DQ </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x float]. +/// \returns A 256-bit integer vector containing the converted values. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_cvttps_epi32(__m256 __a) { @@ -2152,18 +2204,73 @@ _mm256_cvtss_f32(__m256 __a) } /* Vector replicate */ +/// \brief Moves and duplicates high-order (odd-indexed) values from a 256-bit +/// vector of [8 x float] to float values in a 256-bit vector of +/// [8 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVSHDUP </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x float]. \n +/// Bits [255:224] of \a __a are written to bits [255:224] and [223:192] of +/// the return value. \n +/// Bits [191:160] of \a __a are written to bits [191:160] and [159:128] of +/// the return value. \n +/// Bits [127:96] of \a __a are written to bits [127:96] and [95:64] of the +/// return value. \n +/// Bits [63:32] of \a __a are written to bits [63:32] and [31:0] of the +/// return value. +/// \returns A 256-bit vector of [8 x float] containing the moved and duplicated +/// values. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_movehdup_ps(__m256 __a) { return __builtin_shufflevector((__v8sf)__a, (__v8sf)__a, 1, 1, 3, 3, 5, 5, 7, 7); } +/// \brief Moves and duplicates low-order (even-indexed) values from a 256-bit +/// vector of [8 x float] to float values in a 256-bit vector of [8 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVSLDUP </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x float]. \n +/// Bits [223:192] of \a __a are written to bits [255:224] and [223:192] of +/// the return value. \n +/// Bits [159:128] of \a __a are written to bits [191:160] and [159:128] of +/// the return value. \n +/// Bits [95:64] of \a __a are written to bits [127:96] and [95:64] of the +/// return value. \n +/// Bits [31:0] of \a __a are written to bits [63:32] and [31:0] of the +/// return value. +/// \returns A 256-bit vector of [8 x float] containing the moved and duplicated +/// values. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_moveldup_ps(__m256 __a) { return __builtin_shufflevector((__v8sf)__a, (__v8sf)__a, 0, 0, 2, 2, 4, 4, 6, 6); } +/// \brief Moves and duplicates double-precision floating point values from a +/// 256-bit vector of [4 x double] to double-precision values in a 256-bit +/// vector of [4 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVDDUP </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x double]. \n +/// Bits [63:0] of \a __a are written to bits [127:64] and [63:0] of the +/// return value. \n +/// Bits [191:128] of \a __a are written to bits [255:192] and [191:128] of +/// the return value. +/// \returns A 256-bit vector of [4 x double] containing the moved and +/// duplicated values. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_movedup_pd(__m256d __a) { @@ -2171,24 +2278,98 @@ _mm256_movedup_pd(__m256d __a) } /* Unpack and Interleave */ +/// \brief Unpacks the odd-indexed vector elements from two 256-bit vectors of +/// [4 x double] and interleaves them into a 256-bit vector of [4 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VUNPCKHPD </c> instruction. +/// +/// \param __a +/// A 256-bit floating-point vector of [4 x double]. \n +/// Bits [127:64] are written to bits [63:0] of the return value. \n +/// Bits [255:192] are written to bits [191:128] of the return value. \n +/// \param __b +/// A 256-bit floating-point vector of [4 x double]. \n +/// Bits [127:64] are written to bits [127:64] of the return value. \n +/// Bits [255:192] are written to bits [255:192] of the return value. \n +/// \returns A 256-bit vector of [4 x double] containing the interleaved values. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_unpackhi_pd(__m256d __a, __m256d __b) { return __builtin_shufflevector((__v4df)__a, (__v4df)__b, 1, 5, 1+2, 5+2); } +/// \brief Unpacks the even-indexed vector elements from two 256-bit vectors of +/// [4 x double] and interleaves them into a 256-bit vector of [4 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VUNPCKLPD </c> instruction. +/// +/// \param __a +/// A 256-bit floating-point vector of [4 x double]. \n +/// Bits [63:0] are written to bits [63:0] of the return value. \n +/// Bits [191:128] are written to bits [191:128] of the return value. +/// \param __b +/// A 256-bit floating-point vector of [4 x double]. \n +/// Bits [63:0] are written to bits [127:64] of the return value. \n +/// Bits [191:128] are written to bits [255:192] of the return value. \n +/// \returns A 256-bit vector of [4 x double] containing the interleaved values. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_unpacklo_pd(__m256d __a, __m256d __b) { return __builtin_shufflevector((__v4df)__a, (__v4df)__b, 0, 4, 0+2, 4+2); } +/// \brief Unpacks the 32-bit vector elements 2, 3, 6 and 7 from each of the +/// two 256-bit vectors of [8 x float] and interleaves them into a 256-bit +/// vector of [8 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VUNPCKHPS </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x float]. \n +/// Bits [95:64] are written to bits [31:0] of the return value. \n +/// Bits [127:96] are written to bits [95:64] of the return value. \n +/// Bits [223:192] are written to bits [159:128] of the return value. \n +/// Bits [255:224] are written to bits [223:192] of the return value. +/// \param __b +/// A 256-bit vector of [8 x float]. \n +/// Bits [95:64] are written to bits [63:32] of the return value. \n +/// Bits [127:96] are written to bits [127:96] of the return value. \n +/// Bits [223:192] are written to bits [191:160] of the return value. \n +/// Bits [255:224] are written to bits [255:224] of the return value. +/// \returns A 256-bit vector of [8 x float] containing the interleaved values. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_unpackhi_ps(__m256 __a, __m256 __b) { return __builtin_shufflevector((__v8sf)__a, (__v8sf)__b, 2, 10, 2+1, 10+1, 6, 14, 6+1, 14+1); } +/// \brief Unpacks the 32-bit vector elements 0, 1, 4 and 5 from each of the +/// two 256-bit vectors of [8 x float] and interleaves them into a 256-bit +/// vector of [8 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VUNPCKLPS </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x float]. \n +/// Bits [31:0] are written to bits [31:0] of the return value. \n +/// Bits [63:32] are written to bits [95:64] of the return value. \n +/// Bits [159:128] are written to bits [159:128] of the return value. \n +/// Bits [191:160] are written to bits [223:192] of the return value. +/// \param __b +/// A 256-bit vector of [8 x float]. \n +/// Bits [31:0] are written to bits [63:32] of the return value. \n +/// Bits [63:32] are written to bits [127:96] of the return value. \n +/// Bits [159:128] are written to bits [191:160] of the return value. \n +/// Bits [191:160] are written to bits [255:224] of the return value. +/// \returns A 256-bit vector of [8 x float] containing the interleaved values. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_unpacklo_ps(__m256 __a, __m256 __b) { @@ -2196,90 +2377,401 @@ _mm256_unpacklo_ps(__m256 __a, __m256 __b) } /* Bit Test */ +/// \brief Given two 128-bit floating-point vectors of [2 x double], perform an +/// element-by-element comparison of the double-precision element in the +/// first source vector and the corresponding element in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of double-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of double-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns the value of the ZF flag. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPD </c> instruction. +/// +/// \param __a +/// A 128-bit vector of [2 x double]. +/// \param __b +/// A 128-bit vector of [2 x double]. +/// \returns the ZF flag in the EFLAGS register. static __inline int __DEFAULT_FN_ATTRS _mm_testz_pd(__m128d __a, __m128d __b) { return __builtin_ia32_vtestzpd((__v2df)__a, (__v2df)__b); } +/// \brief Given two 128-bit floating-point vectors of [2 x double], perform an +/// element-by-element comparison of the double-precision element in the +/// first source vector and the corresponding element in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of double-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of double-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns the value of the CF flag. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPD </c> instruction. +/// +/// \param __a +/// A 128-bit vector of [2 x double]. +/// \param __b +/// A 128-bit vector of [2 x double]. +/// \returns the CF flag in the EFLAGS register. static __inline int __DEFAULT_FN_ATTRS _mm_testc_pd(__m128d __a, __m128d __b) { return __builtin_ia32_vtestcpd((__v2df)__a, (__v2df)__b); } +/// \brief Given two 128-bit floating-point vectors of [2 x double], perform an +/// element-by-element comparison of the double-precision element in the +/// first source vector and the corresponding element in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of double-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of double-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns 1 if both the ZF and CF flags are set to 0, +/// otherwise it returns 0. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPD </c> instruction. +/// +/// \param __a +/// A 128-bit vector of [2 x double]. +/// \param __b +/// A 128-bit vector of [2 x double]. +/// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0. static __inline int __DEFAULT_FN_ATTRS _mm_testnzc_pd(__m128d __a, __m128d __b) { return __builtin_ia32_vtestnzcpd((__v2df)__a, (__v2df)__b); } +/// \brief Given two 128-bit floating-point vectors of [4 x float], perform an +/// element-by-element comparison of the single-precision element in the +/// first source vector and the corresponding element in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of single-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of single-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns the value of the ZF flag. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPS </c> instruction. +/// +/// \param __a +/// A 128-bit vector of [4 x float]. +/// \param __b +/// A 128-bit vector of [4 x float]. +/// \returns the ZF flag. static __inline int __DEFAULT_FN_ATTRS _mm_testz_ps(__m128 __a, __m128 __b) { return __builtin_ia32_vtestzps((__v4sf)__a, (__v4sf)__b); } +/// \brief Given two 128-bit floating-point vectors of [4 x float], perform an +/// element-by-element comparison of the single-precision element in the +/// first source vector and the corresponding element in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of single-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of single-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns the value of the CF flag. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPS </c> instruction. +/// +/// \param __a +/// A 128-bit vector of [4 x float]. +/// \param __b +/// A 128-bit vector of [4 x float]. +/// \returns the CF flag. static __inline int __DEFAULT_FN_ATTRS _mm_testc_ps(__m128 __a, __m128 __b) { return __builtin_ia32_vtestcps((__v4sf)__a, (__v4sf)__b); } +/// \brief Given two 128-bit floating-point vectors of [4 x float], perform an +/// element-by-element comparison of the single-precision element in the +/// first source vector and the corresponding element in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of single-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of single-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns 1 if both the ZF and CF flags are set to 0, +/// otherwise it returns 0. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPS </c> instruction. +/// +/// \param __a +/// A 128-bit vector of [4 x float]. +/// \param __b +/// A 128-bit vector of [4 x float]. +/// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0. static __inline int __DEFAULT_FN_ATTRS _mm_testnzc_ps(__m128 __a, __m128 __b) { return __builtin_ia32_vtestnzcps((__v4sf)__a, (__v4sf)__b); } +/// \brief Given two 256-bit floating-point vectors of [4 x double], perform an +/// element-by-element comparison of the double-precision elements in the +/// first source vector and the corresponding elements in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of double-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of double-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns the value of the ZF flag. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPD </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x double]. +/// \param __b +/// A 256-bit vector of [4 x double]. +/// \returns the ZF flag. static __inline int __DEFAULT_FN_ATTRS _mm256_testz_pd(__m256d __a, __m256d __b) { return __builtin_ia32_vtestzpd256((__v4df)__a, (__v4df)__b); } +/// \brief Given two 256-bit floating-point vectors of [4 x double], perform an +/// element-by-element comparison of the double-precision elements in the +/// first source vector and the corresponding elements in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of double-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of double-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns the value of the CF flag. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPD </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x double]. +/// \param __b +/// A 256-bit vector of [4 x double]. +/// \returns the CF flag. static __inline int __DEFAULT_FN_ATTRS _mm256_testc_pd(__m256d __a, __m256d __b) { return __builtin_ia32_vtestcpd256((__v4df)__a, (__v4df)__b); } +/// \brief Given two 256-bit floating-point vectors of [4 x double], perform an +/// element-by-element comparison of the double-precision elements in the +/// first source vector and the corresponding elements in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of double-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of double-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns 1 if both the ZF and CF flags are set to 0, +/// otherwise it returns 0. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPD </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x double]. +/// \param __b +/// A 256-bit vector of [4 x double]. +/// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0. static __inline int __DEFAULT_FN_ATTRS _mm256_testnzc_pd(__m256d __a, __m256d __b) { return __builtin_ia32_vtestnzcpd256((__v4df)__a, (__v4df)__b); } +/// \brief Given two 256-bit floating-point vectors of [8 x float], perform an +/// element-by-element comparison of the single-precision element in the +/// first source vector and the corresponding element in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of single-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of single-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns the value of the ZF flag. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPS </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x float]. +/// \param __b +/// A 256-bit vector of [8 x float]. +/// \returns the ZF flag. static __inline int __DEFAULT_FN_ATTRS _mm256_testz_ps(__m256 __a, __m256 __b) { return __builtin_ia32_vtestzps256((__v8sf)__a, (__v8sf)__b); } +/// \brief Given two 256-bit floating-point vectors of [8 x float], perform an +/// element-by-element comparison of the single-precision element in the +/// first source vector and the corresponding element in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of single-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of single-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns the value of the CF flag. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPS </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x float]. +/// \param __b +/// A 256-bit vector of [8 x float]. +/// \returns the CF flag. static __inline int __DEFAULT_FN_ATTRS _mm256_testc_ps(__m256 __a, __m256 __b) { return __builtin_ia32_vtestcps256((__v8sf)__a, (__v8sf)__b); } +/// \brief Given two 256-bit floating-point vectors of [8 x float], perform an +/// element-by-element comparison of the single-precision elements in the +/// first source vector and the corresponding elements in the second source +/// vector. The EFLAGS register is updated as follows: \n +/// If there is at least one pair of single-precision elements where the +/// sign-bits of both elements are 1, the ZF flag is set to 0. Otherwise the +/// ZF flag is set to 1. \n +/// If there is at least one pair of single-precision elements where the +/// sign-bit of the first element is 0 and the sign-bit of the second element +/// is 1, the CF flag is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns 1 if both the ZF and CF flags are set to 0, +/// otherwise it returns 0. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VTESTPS </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x float]. +/// \param __b +/// A 256-bit vector of [8 x float]. +/// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0. static __inline int __DEFAULT_FN_ATTRS _mm256_testnzc_ps(__m256 __a, __m256 __b) { return __builtin_ia32_vtestnzcps256((__v8sf)__a, (__v8sf)__b); } +/// \brief Given two 256-bit integer vectors, perform a bit-by-bit comparison +/// of the two source vectors and update the EFLAGS register as follows: \n +/// If there is at least one pair of bits where both bits are 1, the ZF flag +/// is set to 0. Otherwise the ZF flag is set to 1. \n +/// If there is at least one pair of bits where the bit from the first source +/// vector is 0 and the bit from the second source vector is 1, the CF flag +/// is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns the value of the ZF flag. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VPTEST </c> instruction. +/// +/// \param __a +/// A 256-bit integer vector. +/// \param __b +/// A 256-bit integer vector. +/// \returns the ZF flag. static __inline int __DEFAULT_FN_ATTRS _mm256_testz_si256(__m256i __a, __m256i __b) { return __builtin_ia32_ptestz256((__v4di)__a, (__v4di)__b); } +/// \brief Given two 256-bit integer vectors, perform a bit-by-bit comparison +/// of the two source vectors and update the EFLAGS register as follows: \n +/// If there is at least one pair of bits where both bits are 1, the ZF flag +/// is set to 0. Otherwise the ZF flag is set to 1. \n +/// If there is at least one pair of bits where the bit from the first source +/// vector is 0 and the bit from the second source vector is 1, the CF flag +/// is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns the value of the CF flag. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VPTEST </c> instruction. +/// +/// \param __a +/// A 256-bit integer vector. +/// \param __b +/// A 256-bit integer vector. +/// \returns the CF flag. static __inline int __DEFAULT_FN_ATTRS _mm256_testc_si256(__m256i __a, __m256i __b) { return __builtin_ia32_ptestc256((__v4di)__a, (__v4di)__b); } +/// \brief Given two 256-bit integer vectors, perform a bit-by-bit comparison +/// of the two source vectors and update the EFLAGS register as follows: \n +/// If there is at least one pair of bits where both bits are 1, the ZF flag +/// is set to 0. Otherwise the ZF flag is set to 1. \n +/// If there is at least one pair of bits where the bit from the first source +/// vector is 0 and the bit from the second source vector is 1, the CF flag +/// is set to 0. Otherwise the CF flag is set to 1. \n +/// This intrinsic returns 1 if both the ZF and CF flags are set to 0, +/// otherwise it returns 0. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VPTEST </c> instruction. +/// +/// \param __a +/// A 256-bit integer vector. +/// \param __b +/// A 256-bit integer vector. +/// \returns 1 if both the ZF and CF flags are set to 0, otherwise returns 0. static __inline int __DEFAULT_FN_ATTRS _mm256_testnzc_si256(__m256i __a, __m256i __b) { @@ -2287,12 +2779,36 @@ _mm256_testnzc_si256(__m256i __a, __m256i __b) } /* Vector extract sign mask */ +/// \brief Extracts the sign bits of double-precision floating point elements +/// in a 256-bit vector of [4 x double] and writes them to the lower order +/// bits of the return value. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVMSKPD </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x double] containing the double-precision +/// floating point values with sign bits to be extracted. +/// \returns The sign bits from the operand, written to bits [3:0]. static __inline int __DEFAULT_FN_ATTRS _mm256_movemask_pd(__m256d __a) { return __builtin_ia32_movmskpd256((__v4df)__a); } +/// \brief Extracts the sign bits of double-precision floating point elements +/// in a 256-bit vector of [8 x float] and writes them to the lower order +/// bits of the return value. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVMSKPS </c> instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x float] containing the double-precision floating +/// point values with sign bits to be extracted. +/// \returns The sign bits from the operand, written to bits [7:0]. static __inline int __DEFAULT_FN_ATTRS _mm256_movemask_ps(__m256 __a) { @@ -2300,12 +2816,22 @@ _mm256_movemask_ps(__m256 __a) } /* Vector __zero */ +/// \brief Zeroes the contents of all XMM or YMM registers. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VZEROALL </c> instruction. static __inline void __DEFAULT_FN_ATTRS _mm256_zeroall(void) { __builtin_ia32_vzeroall(); } +/// \brief Zeroes the upper 128 bits (bits 255:128) of all YMM registers. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VZEROUPPER </c> instruction. static __inline void __DEFAULT_FN_ATTRS _mm256_zeroupper(void) { @@ -2313,6 +2839,18 @@ _mm256_zeroupper(void) } /* Vector load with broadcast */ +/// \brief Loads a scalar single-precision floating point value from the +/// specified address pointed to by \a __a and broadcasts it to the elements +/// of a [4 x float] vector. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VBROADCASTSS </c> instruction. +/// +/// \param __a +/// The single-precision floating point value to be broadcast. +/// \returns A 128-bit vector of [4 x float] whose 32-bit elements are set +/// equal to the broadcast value. static __inline __m128 __DEFAULT_FN_ATTRS _mm_broadcast_ss(float const *__a) { @@ -2320,6 +2858,18 @@ _mm_broadcast_ss(float const *__a) return (__m128)(__v4sf){ __f, __f, __f, __f }; } +/// \brief Loads a scalar double-precision floating point value from the +/// specified address pointed to by \a __a and broadcasts it to the elements +/// of a [4 x double] vector. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VBROADCASTSD </c> instruction. +/// +/// \param __a +/// The double-precision floating point value to be broadcast. +/// \returns A 256-bit vector of [4 x double] whose 64-bit elements are set +/// equal to the broadcast value. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_broadcast_sd(double const *__a) { @@ -2327,6 +2877,18 @@ _mm256_broadcast_sd(double const *__a) return (__m256d)(__v4df){ __d, __d, __d, __d }; } +/// \brief Loads a scalar single-precision floating point value from the +/// specified address pointed to by \a __a and broadcasts it to the elements +/// of a [8 x float] vector. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VBROADCASTSS </c> instruction. +/// +/// \param __a +/// The single-precision floating point value to be broadcast. +/// \returns A 256-bit vector of [8 x float] whose 32-bit elements are set +/// equal to the broadcast value. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_broadcast_ss(float const *__a) { @@ -2334,12 +2896,36 @@ _mm256_broadcast_ss(float const *__a) return (__m256)(__v8sf){ __f, __f, __f, __f, __f, __f, __f, __f }; } +/// \brief Loads the data from a 128-bit vector of [2 x double] from the +/// specified address pointed to by \a __a and broadcasts it to 128-bit +/// elements in a 256-bit vector of [4 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VBROADCASTF128 </c> instruction. +/// +/// \param __a +/// The 128-bit vector of [2 x double] to be broadcast. +/// \returns A 256-bit vector of [4 x double] whose 128-bit elements are set +/// equal to the broadcast value. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_broadcast_pd(__m128d const *__a) { return (__m256d)__builtin_ia32_vbroadcastf128_pd256((__v2df const *)__a); } +/// \brief Loads the data from a 128-bit vector of [4 x float] from the +/// specified address pointed to by \a __a and broadcasts it to 128-bit +/// elements in a 256-bit vector of [8 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VBROADCASTF128 </c> instruction. +/// +/// \param __a +/// The 128-bit vector of [4 x float] to be broadcast. +/// \returns A 256-bit vector of [8 x float] whose 128-bit elements are set +/// equal to the broadcast value. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_broadcast_ps(__m128 const *__a) { @@ -2347,18 +2933,50 @@ _mm256_broadcast_ps(__m128 const *__a) } /* SIMD load ops */ +/// \brief Loads 4 double-precision floating point values from a 32-byte aligned +/// memory location pointed to by \a __p into a vector of [4 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVAPD </c> instruction. +/// +/// \param __p +/// A 32-byte aligned pointer to a memory location containing +/// double-precision floating point values. +/// \returns A 256-bit vector of [4 x double] containing the moved values. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_load_pd(double const *__p) { return *(__m256d *)__p; } +/// \brief Loads 8 single-precision floating point values from a 32-byte aligned +/// memory location pointed to by \a __p into a vector of [8 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVAPS </c> instruction. +/// +/// \param __p +/// A 32-byte aligned pointer to a memory location containing float values. +/// \returns A 256-bit vector of [8 x float] containing the moved values. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_load_ps(float const *__p) { return *(__m256 *)__p; } +/// \brief Loads 4 double-precision floating point values from an unaligned +/// memory location pointed to by \a __p into a vector of [4 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVUPD </c> instruction. +/// +/// \param __p +/// A pointer to a memory location containing double-precision floating +/// point values. +/// \returns A 256-bit vector of [4 x double] containing the moved values. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_loadu_pd(double const *__p) { @@ -2368,6 +2986,17 @@ _mm256_loadu_pd(double const *__p) return ((struct __loadu_pd*)__p)->__v; } +/// \brief Loads 8 single-precision floating point values from an unaligned +/// memory location pointed to by \a __p into a vector of [8 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVUPS </c> instruction. +/// +/// \param __p +/// A pointer to a memory location containing single-precision floating +/// point values. +/// \returns A 256-bit vector of [8 x float] containing the moved values. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_loadu_ps(float const *__p) { @@ -2377,12 +3006,33 @@ _mm256_loadu_ps(float const *__p) return ((struct __loadu_ps*)__p)->__v; } +/// \brief Loads 256 bits of integer data from a 32-byte aligned memory +/// location pointed to by \a __p into elements of a 256-bit integer vector. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVDQA </c> instruction. +/// +/// \param __p +/// A 32-byte aligned pointer to a 256-bit integer vector containing integer +/// values. +/// \returns A 256-bit integer vector containing the moved values. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_load_si256(__m256i const *__p) { return *__p; } +/// \brief Loads 256 bits of integer data from an unaligned memory location +/// pointed to by \a __p into a 256-bit integer vector. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVDQU </c> instruction. +/// +/// \param __p +/// A pointer to a 256-bit integer vector containing integer values. +/// \returns A 256-bit integer vector containing the moved values. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_loadu_si256(__m256i const *__p) { @@ -2392,6 +3042,18 @@ _mm256_loadu_si256(__m256i const *__p) return ((struct __loadu_si256*)__p)->__v; } +/// \brief Loads 256 bits of integer data from an unaligned memory location +/// pointed to by \a __p into a 256-bit integer vector. This intrinsic may +/// perform better than \c _mm256_loadu_si256 when the data crosses a cache +/// line boundary. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VLDDQU </c> instruction. +/// +/// \param __p +/// A pointer to a 256-bit integer vector containing integer values. +/// \returns A 256-bit integer vector containing the moved values. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_lddqu_si256(__m256i const *__p) { @@ -2399,18 +3061,55 @@ _mm256_lddqu_si256(__m256i const *__p) } /* SIMD store ops */ +/// \brief Stores double-precision floating point values from a 256-bit vector +/// of [4 x double] to a 32-byte aligned memory location pointed to by +/// \a __p. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVAPD </c> instruction. +/// +/// \param __p +/// A 32-byte aligned pointer to a memory location that will receive the +/// double-precision floaing point values. +/// \param __a +/// A 256-bit vector of [4 x double] containing the values to be moved. static __inline void __DEFAULT_FN_ATTRS _mm256_store_pd(double *__p, __m256d __a) { *(__m256d *)__p = __a; } +/// \brief Stores single-precision floating point values from a 256-bit vector +/// of [8 x float] to a 32-byte aligned memory location pointed to by \a __p. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVAPS </c> instruction. +/// +/// \param __p +/// A 32-byte aligned pointer to a memory location that will receive the +/// float values. +/// \param __a +/// A 256-bit vector of [8 x float] containing the values to be moved. static __inline void __DEFAULT_FN_ATTRS _mm256_store_ps(float *__p, __m256 __a) { *(__m256 *)__p = __a; } +/// \brief Stores double-precision floating point values from a 256-bit vector +/// of [4 x double] to an unaligned memory location pointed to by \a __p. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVUPD </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that will receive the double-precision +/// floating point values. +/// \param __a +/// A 256-bit vector of [4 x double] containing the values to be moved. static __inline void __DEFAULT_FN_ATTRS _mm256_storeu_pd(double *__p, __m256d __a) { @@ -2420,6 +3119,17 @@ _mm256_storeu_pd(double *__p, __m256d __a) ((struct __storeu_pd*)__p)->__v = __a; } +/// \brief Stores single-precision floating point values from a 256-bit vector +/// of [8 x float] to an unaligned memory location pointed to by \a __p. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVUPS </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that will receive the float values. +/// \param __a +/// A 256-bit vector of [8 x float] containing the values to be moved. static __inline void __DEFAULT_FN_ATTRS _mm256_storeu_ps(float *__p, __m256 __a) { @@ -2429,12 +3139,35 @@ _mm256_storeu_ps(float *__p, __m256 __a) ((struct __storeu_ps*)__p)->__v = __a; } +/// \brief Stores integer values from a 256-bit integer vector to a 32-byte +/// aligned memory location pointed to by \a __p. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVDQA </c> instruction. +/// +/// \param __p +/// A 32-byte aligned pointer to a memory location that will receive the +/// integer values. +/// \param __a +/// A 256-bit integer vector containing the values to be moved. static __inline void __DEFAULT_FN_ATTRS _mm256_store_si256(__m256i *__p, __m256i __a) { *__p = __a; } +/// \brief Stores integer values from a 256-bit integer vector to an unaligned +/// memory location pointed to by \a __p. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVDQU </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that will receive the integer values. +/// \param __a +/// A 256-bit integer vector containing the values to be moved. static __inline void __DEFAULT_FN_ATTRS _mm256_storeu_si256(__m256i *__p, __m256i __a) { @@ -2445,12 +3178,48 @@ _mm256_storeu_si256(__m256i *__p, __m256i __a) } /* Conditional load ops */ +/// \brief Conditionally loads double-precision floating point elements from a +/// memory location pointed to by \a __p into a 128-bit vector of +/// [2 x double], depending on the mask bits associated with each data +/// element. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that contains the double-precision +/// floating point values. +/// \param __m +/// A 128-bit integer vector containing the mask. The most significant bit of +/// each data element represents the mask bits. If a mask bit is zero, the +/// corresponding value in the memory location is not loaded and the +/// corresponding field in the return value is set to zero. +/// \returns A 128-bit vector of [2 x double] containing the loaded values. static __inline __m128d __DEFAULT_FN_ATTRS _mm_maskload_pd(double const *__p, __m128i __m) { return (__m128d)__builtin_ia32_maskloadpd((const __v2df *)__p, (__v2di)__m); } +/// \brief Conditionally loads double-precision floating point elements from a +/// memory location pointed to by \a __p into a 256-bit vector of +/// [4 x double], depending on the mask bits associated with each data +/// element. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that contains the double-precision +/// floating point values. +/// \param __m +/// A 256-bit integer vector of [4 x quadword] containing the mask. The most +/// significant bit of each quadword element represents the mask bits. If a +/// mask bit is zero, the corresponding value in the memory location is not +/// loaded and the corresponding field in the return value is set to zero. +/// \returns A 256-bit vector of [4 x double] containing the loaded values. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_maskload_pd(double const *__p, __m256i __m) { @@ -2458,12 +3227,48 @@ _mm256_maskload_pd(double const *__p, __m256i __m) (__v4di)__m); } +/// \brief Conditionally loads single-precision floating point elements from a +/// memory location pointed to by \a __p into a 128-bit vector of +/// [4 x float], depending on the mask bits associated with each data +/// element. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that contains the single-precision +/// floating point values. +/// \param __m +/// A 128-bit integer vector containing the mask. The most significant bit of +/// each data element represents the mask bits. If a mask bit is zero, the +/// corresponding value in the memory location is not loaded and the +/// corresponding field in the return value is set to zero. +/// \returns A 128-bit vector of [4 x float] containing the loaded values. static __inline __m128 __DEFAULT_FN_ATTRS _mm_maskload_ps(float const *__p, __m128i __m) { return (__m128)__builtin_ia32_maskloadps((const __v4sf *)__p, (__v4si)__m); } +/// \brief Conditionally loads single-precision floating point elements from a +/// memory location pointed to by \a __p into a 256-bit vector of +/// [8 x float], depending on the mask bits associated with each data +/// element. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that contains the single-precision +/// floating point values. +/// \param __m +/// A 256-bit integer vector of [8 x dword] containing the mask. The most +/// significant bit of each dword element represents the mask bits. If a mask +/// bit is zero, the corresponding value in the memory location is not loaded +/// and the corresponding field in the return value is set to zero. +/// \returns A 256-bit vector of [8 x float] containing the loaded values. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_maskload_ps(float const *__p, __m256i __m) { @@ -2471,24 +3276,96 @@ _mm256_maskload_ps(float const *__p, __m256i __m) } /* Conditional store ops */ +/// \brief Moves single-precision floating point values from a 256-bit vector +/// of [8 x float] to a memory location pointed to by \a __p, according to +/// the specified mask. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that will receive the float values. +/// \param __m +/// A 256-bit integer vector of [8 x dword] containing the mask. The most +/// significant bit of each dword element in the mask vector represents the +/// mask bits. If a mask bit is zero, the corresponding value from vector +/// \a __a is not stored and the corresponding field in the memory location +/// pointed to by \a __p is not changed. +/// \param __a +/// A 256-bit vector of [8 x float] containing the values to be stored. static __inline void __DEFAULT_FN_ATTRS _mm256_maskstore_ps(float *__p, __m256i __m, __m256 __a) { __builtin_ia32_maskstoreps256((__v8sf *)__p, (__v8si)__m, (__v8sf)__a); } +/// \brief Moves double-precision values from a 128-bit vector of [2 x double] +/// to a memory location pointed to by \a __p, according to the specified +/// mask. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that will receive the float values. +/// \param __m +/// A 128-bit integer vector containing the mask. The most significant bit of +/// each field in the mask vector represents the mask bits. If a mask bit is +/// zero, the corresponding value from vector \a __a is not stored and the +/// corresponding field in the memory location pointed to by \a __p is not +/// changed. +/// \param __a +/// A 128-bit vector of [2 x double] containing the values to be stored. static __inline void __DEFAULT_FN_ATTRS _mm_maskstore_pd(double *__p, __m128i __m, __m128d __a) { __builtin_ia32_maskstorepd((__v2df *)__p, (__v2di)__m, (__v2df)__a); } +/// \brief Moves double-precision values from a 256-bit vector of [4 x double] +/// to a memory location pointed to by \a __p, according to the specified +/// mask. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMASKMOVPD </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that will receive the float values. +/// \param __m +/// A 256-bit integer vector of [4 x quadword] containing the mask. The most +/// significant bit of each quadword element in the mask vector represents +/// the mask bits. If a mask bit is zero, the corresponding value from vector +/// __a is not stored and the corresponding field in the memory location +/// pointed to by \a __p is not changed. +/// \param __a +/// A 256-bit vector of [4 x double] containing the values to be stored. static __inline void __DEFAULT_FN_ATTRS _mm256_maskstore_pd(double *__p, __m256i __m, __m256d __a) { __builtin_ia32_maskstorepd256((__v4df *)__p, (__v4di)__m, (__v4df)__a); } +/// \brief Moves single-precision floating point values from a 128-bit vector +/// of [4 x float] to a memory location pointed to by \a __p, according to +/// the specified mask. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMASKMOVPS </c> instruction. +/// +/// \param __p +/// A pointer to a memory location that will receive the float values. +/// \param __m +/// A 128-bit integer vector containing the mask. The most significant bit of +/// each field in the mask vector represents the mask bits. If a mask bit is +/// zero, the corresponding value from vector __a is not stored and the +/// corresponding field in the memory location pointed to by \a __p is not +/// changed. +/// \param __a +/// A 128-bit vector of [4 x float] containing the values to be stored. static __inline void __DEFAULT_FN_ATTRS _mm_maskstore_ps(float *__p, __m128i __m, __m128 __a) { @@ -2496,18 +3373,58 @@ _mm_maskstore_ps(float *__p, __m128i __m, __m128 __a) } /* Cacheability support ops */ +/// \brief Moves integer data from a 256-bit integer vector to a 32-byte +/// aligned memory location. To minimize caching, the data is flagged as +/// non-temporal (unlikely to be used again soon). +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVNTDQ </c> instruction. +/// +/// \param __a +/// A pointer to a 32-byte aligned memory location that will receive the +/// integer values. +/// \param __b +/// A 256-bit integer vector containing the values to be moved. static __inline void __DEFAULT_FN_ATTRS _mm256_stream_si256(__m256i *__a, __m256i __b) { __builtin_nontemporal_store((__v4di)__b, (__v4di*)__a); } +/// \brief Moves double-precision values from a 256-bit vector of [4 x double] +/// to a 32-byte aligned memory location. To minimize caching, the data is +/// flagged as non-temporal (unlikely to be used again soon). +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVNTPD </c> instruction. +/// +/// \param __a +/// A pointer to a 32-byte aligned memory location that will receive the +/// integer values. +/// \param __b +/// A 256-bit vector of [4 x double] containing the values to be moved. static __inline void __DEFAULT_FN_ATTRS _mm256_stream_pd(double *__a, __m256d __b) { __builtin_nontemporal_store((__v4df)__b, (__v4df*)__a); } +/// \brief Moves single-precision floating point values from a 256-bit vector +/// of [8 x float] to a 32-byte aligned memory location. To minimize +/// caching, the data is flagged as non-temporal (unlikely to be used again +/// soon). +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVNTPS </c> instruction. +/// +/// \param __p +/// A pointer to a 32-byte aligned memory location that will receive the +/// single-precision floating point values. +/// \param __a +/// A 256-bit vector of [8 x float] containing the values to be moved. static __inline void __DEFAULT_FN_ATTRS _mm256_stream_ps(float *__p, __m256 __a) { @@ -2515,30 +3432,105 @@ _mm256_stream_ps(float *__p, __m256 __a) } /* Create vectors */ +/// \brief Create a 256-bit vector of [4 x double] with undefined values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \returns A 256-bit vector of [4 x double] containing undefined values. static __inline__ __m256d __DEFAULT_FN_ATTRS _mm256_undefined_pd(void) { return (__m256d)__builtin_ia32_undef256(); } +/// \brief Create a 256-bit vector of [8 x float] with undefined values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \returns A 256-bit vector of [8 x float] containing undefined values. static __inline__ __m256 __DEFAULT_FN_ATTRS _mm256_undefined_ps(void) { return (__m256)__builtin_ia32_undef256(); } +/// \brief Create a 256-bit integer vector with undefined values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \returns A 256-bit integer vector containing undefined values. static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_undefined_si256(void) { return (__m256i)__builtin_ia32_undef256(); } +/// \brief Constructs a 256-bit floating-point vector of [4 x double] +/// initialized with the specified double-precision floating-point values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VUNPCKLPD+VINSERTF128 </c> +/// instruction. +/// +/// \param __a +/// A double-precision floating-point value used to initialize bits [255:192] +/// of the result. +/// \param __b +/// A double-precision floating-point value used to initialize bits [191:128] +/// of the result. +/// \param __c +/// A double-precision floating-point value used to initialize bits [127:64] +/// of the result. +/// \param __d +/// A double-precision floating-point value used to initialize bits [63:0] +/// of the result. +/// \returns An initialized 256-bit floating-point vector of [4 x double]. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_set_pd(double __a, double __b, double __c, double __d) { return (__m256d){ __d, __c, __b, __a }; } +/// \brief Constructs a 256-bit floating-point vector of [8 x float] initialized +/// with the specified single-precision floating-point values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic is a utility function and does not correspond to a specific +/// instruction. +/// +/// \param __a +/// A single-precision floating-point value used to initialize bits [255:224] +/// of the result. +/// \param __b +/// A single-precision floating-point value used to initialize bits [223:192] +/// of the result. +/// \param __c +/// A single-precision floating-point value used to initialize bits [191:160] +/// of the result. +/// \param __d +/// A single-precision floating-point value used to initialize bits [159:128] +/// of the result. +/// \param __e +/// A single-precision floating-point value used to initialize bits [127:96] +/// of the result. +/// \param __f +/// A single-precision floating-point value used to initialize bits [95:64] +/// of the result. +/// \param __g +/// A single-precision floating-point value used to initialize bits [63:32] +/// of the result. +/// \param __h +/// A single-precision floating-point value used to initialize bits [31:0] +/// of the result. +/// \returns An initialized 256-bit floating-point vector of [8 x float]. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_set_ps(float __a, float __b, float __c, float __d, float __e, float __f, float __g, float __h) @@ -2546,6 +3538,31 @@ _mm256_set_ps(float __a, float __b, float __c, float __d, return (__m256){ __h, __g, __f, __e, __d, __c, __b, __a }; } +/// \brief Constructs a 256-bit integer vector initialized with the specified +/// 32-bit integral values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic is a utility function and does not correspond to a specific +/// instruction. +/// +/// \param __i0 +/// A 32-bit integral value used to initialize bits [255:224] of the result. +/// \param __i1 +/// A 32-bit integral value used to initialize bits [223:192] of the result. +/// \param __i2 +/// A 32-bit integral value used to initialize bits [191:160] of the result. +/// \param __i3 +/// A 32-bit integral value used to initialize bits [159:128] of the result. +/// \param __i4 +/// A 32-bit integral value used to initialize bits [127:96] of the result. +/// \param __i5 +/// A 32-bit integral value used to initialize bits [95:64] of the result. +/// \param __i6 +/// A 32-bit integral value used to initialize bits [63:32] of the result. +/// \param __i7 +/// A 32-bit integral value used to initialize bits [31:0] of the result. +/// \returns An initialized 256-bit integer vector. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_set_epi32(int __i0, int __i1, int __i2, int __i3, int __i4, int __i5, int __i6, int __i7) @@ -2553,6 +3570,47 @@ _mm256_set_epi32(int __i0, int __i1, int __i2, int __i3, return (__m256i)(__v8si){ __i7, __i6, __i5, __i4, __i3, __i2, __i1, __i0 }; } +/// \brief Constructs a 256-bit integer vector initialized with the specified +/// 16-bit integral values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic is a utility function and does not correspond to a specific +/// instruction. +/// +/// \param __w15 +/// A 16-bit integral value used to initialize bits [255:240] of the result. +/// \param __w14 +/// A 16-bit integral value used to initialize bits [239:224] of the result. +/// \param __w13 +/// A 16-bit integral value used to initialize bits [223:208] of the result. +/// \param __w12 +/// A 16-bit integral value used to initialize bits [207:192] of the result. +/// \param __w11 +/// A 16-bit integral value used to initialize bits [191:176] of the result. +/// \param __w10 +/// A 16-bit integral value used to initialize bits [175:160] of the result. +/// \param __w09 +/// A 16-bit integral value used to initialize bits [159:144] of the result. +/// \param __w08 +/// A 16-bit integral value used to initialize bits [143:128] of the result. +/// \param __w07 +/// A 16-bit integral value used to initialize bits [127:112] of the result. +/// \param __w06 +/// A 16-bit integral value used to initialize bits [111:96] of the result. +/// \param __w05 +/// A 16-bit integral value used to initialize bits [95:80] of the result. +/// \param __w04 +/// A 16-bit integral value used to initialize bits [79:64] of the result. +/// \param __w03 +/// A 16-bit integral value used to initialize bits [63:48] of the result. +/// \param __w02 +/// A 16-bit integral value used to initialize bits [47:32] of the result. +/// \param __w01 +/// A 16-bit integral value used to initialize bits [31:16] of the result. +/// \param __w00 +/// A 16-bit integral value used to initialize bits [15:0] of the result. +/// \returns An initialized 256-bit integer vector. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_set_epi16(short __w15, short __w14, short __w13, short __w12, short __w11, short __w10, short __w09, short __w08, @@ -2563,6 +3621,79 @@ _mm256_set_epi16(short __w15, short __w14, short __w13, short __w12, __w07, __w08, __w09, __w10, __w11, __w12, __w13, __w14, __w15 }; } +/// \brief Constructs a 256-bit integer vector initialized with the specified +/// 8-bit integral values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic is a utility function and does not correspond to a specific +/// instruction. +/// +/// \param __b31 +/// An 8-bit integral value used to initialize bits [255:248] of the result. +/// \param __b30 +/// An 8-bit integral value used to initialize bits [247:240] of the result. +/// \param __b29 +/// An 8-bit integral value used to initialize bits [239:232] of the result. +/// \param __b28 +/// An 8-bit integral value used to initialize bits [231:224] of the result. +/// \param __b27 +/// An 8-bit integral value used to initialize bits [223:216] of the result. +/// \param __b26 +/// An 8-bit integral value used to initialize bits [215:208] of the result. +/// \param __b25 +/// An 8-bit integral value used to initialize bits [207:200] of the result. +/// \param __b24 +/// An 8-bit integral value used to initialize bits [199:192] of the result. +/// \param __b23 +/// An 8-bit integral value used to initialize bits [191:184] of the result. +/// \param __b22 +/// An 8-bit integral value used to initialize bits [183:176] of the result. +/// \param __b21 +/// An 8-bit integral value used to initialize bits [175:168] of the result. +/// \param __b20 +/// An 8-bit integral value used to initialize bits [167:160] of the result. +/// \param __b19 +/// An 8-bit integral value used to initialize bits [159:152] of the result. +/// \param __b18 +/// An 8-bit integral value used to initialize bits [151:144] of the result. +/// \param __b17 +/// An 8-bit integral value used to initialize bits [143:136] of the result. +/// \param __b16 +/// An 8-bit integral value used to initialize bits [135:128] of the result. +/// \param __b15 +/// An 8-bit integral value used to initialize bits [127:120] of the result. +/// \param __b14 +/// An 8-bit integral value used to initialize bits [119:112] of the result. +/// \param __b13 +/// An 8-bit integral value used to initialize bits [111:104] of the result. +/// \param __b12 +/// An 8-bit integral value used to initialize bits [103:96] of the result. +/// \param __b11 +/// An 8-bit integral value used to initialize bits [95:88] of the result. +/// \param __b10 +/// An 8-bit integral value used to initialize bits [87:80] of the result. +/// \param __b09 +/// An 8-bit integral value used to initialize bits [79:72] of the result. +/// \param __b08 +/// An 8-bit integral value used to initialize bits [71:64] of the result. +/// \param __b07 +/// An 8-bit integral value used to initialize bits [63:56] of the result. +/// \param __b06 +/// An 8-bit integral value used to initialize bits [55:48] of the result. +/// \param __b05 +/// An 8-bit integral value used to initialize bits [47:40] of the result. +/// \param __b04 +/// An 8-bit integral value used to initialize bits [39:32] of the result. +/// \param __b03 +/// An 8-bit integral value used to initialize bits [31:24] of the result. +/// \param __b02 +/// An 8-bit integral value used to initialize bits [23:16] of the result. +/// \param __b01 +/// An 8-bit integral value used to initialize bits [15:8] of the result. +/// \param __b00 +/// An 8-bit integral value used to initialize bits [7:0] of the result. +/// \returns An initialized 256-bit integer vector. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_set_epi8(char __b31, char __b30, char __b29, char __b28, char __b27, char __b26, char __b25, char __b24, @@ -2581,6 +3712,23 @@ _mm256_set_epi8(char __b31, char __b30, char __b29, char __b28, }; } +/// \brief Constructs a 256-bit integer vector initialized with the specified +/// 64-bit integral values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VPUNPCKLQDQ+VINSERTF128 </c> +/// instruction. +/// +/// \param __a +/// A 64-bit integral value used to initialize bits [255:192] of the result. +/// \param __b +/// A 64-bit integral value used to initialize bits [191:128] of the result. +/// \param __c +/// A 64-bit integral value used to initialize bits [127:64] of the result. +/// \param __d +/// A 64-bit integral value used to initialize bits [63:0] of the result. +/// \returns An initialized 256-bit integer vector. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_set_epi64x(long long __a, long long __b, long long __c, long long __d) { @@ -2588,12 +3736,68 @@ _mm256_set_epi64x(long long __a, long long __b, long long __c, long long __d) } /* Create vectors with elements in reverse order */ +/// \brief Constructs a 256-bit floating-point vector of [4 x double], +/// initialized in reverse order with the specified double-precision +/// floating-point values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VUNPCKLPD+VINSERTF128 </c> +/// instruction. +/// +/// \param __a +/// A double-precision floating-point value used to initialize bits [63:0] +/// of the result. +/// \param __b +/// A double-precision floating-point value used to initialize bits [127:64] +/// of the result. +/// \param __c +/// A double-precision floating-point value used to initialize bits [191:128] +/// of the result. +/// \param __d +/// A double-precision floating-point value used to initialize bits [255:192] +/// of the result. +/// \returns An initialized 256-bit floating-point vector of [4 x double]. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_setr_pd(double __a, double __b, double __c, double __d) { return (__m256d){ __a, __b, __c, __d }; } +/// \brief Constructs a 256-bit floating-point vector of [8 x float], +/// initialized in reverse order with the specified single-precision +/// float-point values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic is a utility function and does not correspond to a specific +/// instruction. +/// +/// \param __a +/// A single-precision floating-point value used to initialize bits [31:0] +/// of the result. +/// \param __b +/// A single-precision floating-point value used to initialize bits [63:32] +/// of the result. +/// \param __c +/// A single-precision floating-point value used to initialize bits [95:64] +/// of the result. +/// \param __d +/// A single-precision floating-point value used to initialize bits [127:96] +/// of the result. +/// \param __e +/// A single-precision floating-point value used to initialize bits [159:128] +/// of the result. +/// \param __f +/// A single-precision floating-point value used to initialize bits [191:160] +/// of the result. +/// \param __g +/// A single-precision floating-point value used to initialize bits [223:192] +/// of the result. +/// \param __h +/// A single-precision floating-point value used to initialize bits [255:224] +/// of the result. +/// \returns An initialized 256-bit floating-point vector of [8 x float]. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_setr_ps(float __a, float __b, float __c, float __d, float __e, float __f, float __g, float __h) @@ -2601,6 +3805,31 @@ _mm256_setr_ps(float __a, float __b, float __c, float __d, return (__m256){ __a, __b, __c, __d, __e, __f, __g, __h }; } +/// \brief Constructs a 256-bit integer vector, initialized in reverse order +/// with the specified 32-bit integral values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic is a utility function and does not correspond to a specific +/// instruction. +/// +/// \param __i0 +/// A 32-bit integral value used to initialize bits [31:0] of the result. +/// \param __i1 +/// A 32-bit integral value used to initialize bits [63:32] of the result. +/// \param __i2 +/// A 32-bit integral value used to initialize bits [95:64] of the result. +/// \param __i3 +/// A 32-bit integral value used to initialize bits [127:96] of the result. +/// \param __i4 +/// A 32-bit integral value used to initialize bits [159:128] of the result. +/// \param __i5 +/// A 32-bit integral value used to initialize bits [191:160] of the result. +/// \param __i6 +/// A 32-bit integral value used to initialize bits [223:192] of the result. +/// \param __i7 +/// A 32-bit integral value used to initialize bits [255:224] of the result. +/// \returns An initialized 256-bit integer vector. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_setr_epi32(int __i0, int __i1, int __i2, int __i3, int __i4, int __i5, int __i6, int __i7) @@ -2608,6 +3837,47 @@ _mm256_setr_epi32(int __i0, int __i1, int __i2, int __i3, return (__m256i)(__v8si){ __i0, __i1, __i2, __i3, __i4, __i5, __i6, __i7 }; } +/// \brief Constructs a 256-bit integer vector, initialized in reverse order +/// with the specified 16-bit integral values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic is a utility function and does not correspond to a specific +/// instruction. +/// +/// \param __w15 +/// A 16-bit integral value used to initialize bits [15:0] of the result. +/// \param __w14 +/// A 16-bit integral value used to initialize bits [31:16] of the result. +/// \param __w13 +/// A 16-bit integral value used to initialize bits [47:32] of the result. +/// \param __w12 +/// A 16-bit integral value used to initialize bits [63:48] of the result. +/// \param __w11 +/// A 16-bit integral value used to initialize bits [79:64] of the result. +/// \param __w10 +/// A 16-bit integral value used to initialize bits [95:80] of the result. +/// \param __w09 +/// A 16-bit integral value used to initialize bits [111:96] of the result. +/// \param __w08 +/// A 16-bit integral value used to initialize bits [127:112] of the result. +/// \param __w07 +/// A 16-bit integral value used to initialize bits [143:128] of the result. +/// \param __w06 +/// A 16-bit integral value used to initialize bits [159:144] of the result. +/// \param __w05 +/// A 16-bit integral value used to initialize bits [175:160] of the result. +/// \param __w04 +/// A 16-bit integral value used to initialize bits [191:176] of the result. +/// \param __w03 +/// A 16-bit integral value used to initialize bits [207:192] of the result. +/// \param __w02 +/// A 16-bit integral value used to initialize bits [223:208] of the result. +/// \param __w01 +/// A 16-bit integral value used to initialize bits [239:224] of the result. +/// \param __w00 +/// A 16-bit integral value used to initialize bits [255:240] of the result. +/// \returns An initialized 256-bit integer vector. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_setr_epi16(short __w15, short __w14, short __w13, short __w12, short __w11, short __w10, short __w09, short __w08, @@ -2618,6 +3888,79 @@ _mm256_setr_epi16(short __w15, short __w14, short __w13, short __w12, __w08, __w07, __w06, __w05, __w04, __w03, __w02, __w01, __w00 }; } +/// \brief Constructs a 256-bit integer vector, initialized in reverse order +/// with the specified 8-bit integral values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic is a utility function and does not correspond to a specific +/// instruction. +/// +/// \param __b31 +/// An 8-bit integral value used to initialize bits [7:0] of the result. +/// \param __b30 +/// An 8-bit integral value used to initialize bits [15:8] of the result. +/// \param __b29 +/// An 8-bit integral value used to initialize bits [23:16] of the result. +/// \param __b28 +/// An 8-bit integral value used to initialize bits [31:24] of the result. +/// \param __b27 +/// An 8-bit integral value used to initialize bits [39:32] of the result. +/// \param __b26 +/// An 8-bit integral value used to initialize bits [47:40] of the result. +/// \param __b25 +/// An 8-bit integral value used to initialize bits [55:48] of the result. +/// \param __b24 +/// An 8-bit integral value used to initialize bits [63:56] of the result. +/// \param __b23 +/// An 8-bit integral value used to initialize bits [71:64] of the result. +/// \param __b22 +/// An 8-bit integral value used to initialize bits [79:72] of the result. +/// \param __b21 +/// An 8-bit integral value used to initialize bits [87:80] of the result. +/// \param __b20 +/// An 8-bit integral value used to initialize bits [95:88] of the result. +/// \param __b19 +/// An 8-bit integral value used to initialize bits [103:96] of the result. +/// \param __b18 +/// An 8-bit integral value used to initialize bits [111:104] of the result. +/// \param __b17 +/// An 8-bit integral value used to initialize bits [119:112] of the result. +/// \param __b16 +/// An 8-bit integral value used to initialize bits [127:120] of the result. +/// \param __b15 +/// An 8-bit integral value used to initialize bits [135:128] of the result. +/// \param __b14 +/// An 8-bit integral value used to initialize bits [143:136] of the result. +/// \param __b13 +/// An 8-bit integral value used to initialize bits [151:144] of the result. +/// \param __b12 +/// An 8-bit integral value used to initialize bits [159:152] of the result. +/// \param __b11 +/// An 8-bit integral value used to initialize bits [167:160] of the result. +/// \param __b10 +/// An 8-bit integral value used to initialize bits [175:168] of the result. +/// \param __b09 +/// An 8-bit integral value used to initialize bits [183:176] of the result. +/// \param __b08 +/// An 8-bit integral value used to initialize bits [191:184] of the result. +/// \param __b07 +/// An 8-bit integral value used to initialize bits [199:192] of the result. +/// \param __b06 +/// An 8-bit integral value used to initialize bits [207:200] of the result. +/// \param __b05 +/// An 8-bit integral value used to initialize bits [215:208] of the result. +/// \param __b04 +/// An 8-bit integral value used to initialize bits [223:216] of the result. +/// \param __b03 +/// An 8-bit integral value used to initialize bits [231:224] of the result. +/// \param __b02 +/// An 8-bit integral value used to initialize bits [239:232] of the result. +/// \param __b01 +/// An 8-bit integral value used to initialize bits [247:240] of the result. +/// \param __b00 +/// An 8-bit integral value used to initialize bits [255:248] of the result. +/// \returns An initialized 256-bit integer vector. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_setr_epi8(char __b31, char __b30, char __b29, char __b28, char __b27, char __b26, char __b25, char __b24, @@ -2635,6 +3978,23 @@ _mm256_setr_epi8(char __b31, char __b30, char __b29, char __b28, __b07, __b06, __b05, __b04, __b03, __b02, __b01, __b00 }; } +/// \brief Constructs a 256-bit integer vector, initialized in reverse order +/// with the specified 64-bit integral values. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VPUNPCKLQDQ+VINSERTF128 </c> +/// instruction. +/// +/// \param __a +/// A 64-bit integral value used to initialize bits [63:0] of the result. +/// \param __b +/// A 64-bit integral value used to initialize bits [127:64] of the result. +/// \param __c +/// A 64-bit integral value used to initialize bits [191:128] of the result. +/// \param __d +/// A 64-bit integral value used to initialize bits [255:192] of the result. +/// \returns An initialized 256-bit integer vector. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_setr_epi64x(long long __a, long long __b, long long __c, long long __d) { @@ -2642,24 +4002,74 @@ _mm256_setr_epi64x(long long __a, long long __b, long long __c, long long __d) } /* Create vectors with repeated elements */ +/// \brief Constructs a 256-bit floating-point vector of [4 x double], with each +/// of the four double-precision floating-point vector elements set to the +/// specified double-precision floating-point value. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVDDUP+VINSERTF128 </c> instruction. +/// +/// \param __w +/// A double-precision floating-point value used to initialize each vector +/// element of the result. +/// \returns An initialized 256-bit floating-point vector of [4 x double]. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_set1_pd(double __w) { return (__m256d){ __w, __w, __w, __w }; } +/// \brief Constructs a 256-bit floating-point vector of [8 x float], with each +/// of the eight single-precision floating-point vector elements set to the +/// specified single-precision floating-point value. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VPERMILPS+VINSERTF128 </c> +/// instruction. +/// +/// \param __w +/// A single-precision floating-point value used to initialize each vector +/// element of the result. +/// \returns An initialized 256-bit floating-point vector of [8 x float]. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_set1_ps(float __w) { return (__m256){ __w, __w, __w, __w, __w, __w, __w, __w }; } +/// \brief Constructs a 256-bit integer vector of [8 x i32], with each of the +/// 32-bit integral vector elements set to the specified 32-bit integral +/// value. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VPERMILPS+VINSERTF128 </c> +/// instruction. +/// +/// \param __i +/// A 32-bit integral value used to initialize each vector element of the +/// result. +/// \returns An initialized 256-bit integer vector of [8 x i32]. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_set1_epi32(int __i) { return (__m256i)(__v8si){ __i, __i, __i, __i, __i, __i, __i, __i }; } +/// \brief Constructs a 256-bit integer vector of [16 x i16], with each of the +/// 16-bit integral vector elements set to the specified 16-bit integral +/// value. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VPSHUFB+VINSERTF128 </c> instruction. +/// +/// \param __w +/// A 16-bit integral value used to initialize each vector element of the +/// result. +/// \returns An initialized 256-bit integer vector of [16 x i16]. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_set1_epi16(short __w) { @@ -2667,6 +4077,17 @@ _mm256_set1_epi16(short __w) __w, __w, __w, __w, __w, __w }; } +/// \brief Constructs a 256-bit integer vector of [32 x i8], with each of the +/// 8-bit integral vector elements set to the specified 8-bit integral value. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VPSHUFB+VINSERTF128 </c> instruction. +/// +/// \param __b +/// An 8-bit integral value used to initialize each vector element of the +/// result. +/// \returns An initialized 256-bit integer vector of [32 x i8]. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_set1_epi8(char __b) { @@ -2675,6 +4096,18 @@ _mm256_set1_epi8(char __b) __b, __b, __b, __b, __b, __b, __b }; } +/// \brief Constructs a 256-bit integer vector of [4 x i64], with each of the +/// 64-bit integral vector elements set to the specified 64-bit integral +/// value. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VMOVDDUP+VINSERTF128 </c> instruction. +/// +/// \param __q +/// A 64-bit integral value used to initialize each vector element of the +/// result. +/// \returns An initialized 256-bit integer vector of [4 x i64]. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_set1_epi64x(long long __q) { @@ -2682,18 +4115,41 @@ _mm256_set1_epi64x(long long __q) } /* Create __zeroed vectors */ +/// \brief Constructs a 256-bit floating-point vector of [4 x double] with all +/// vector elements initialized to zero. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VXORPS </c> instruction. +/// +/// \returns A 256-bit vector of [4 x double] with all elements set to zero. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_setzero_pd(void) { return (__m256d){ 0, 0, 0, 0 }; } +/// \brief Constructs a 256-bit floating-point vector of [8 x float] with all +/// vector elements initialized to zero. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VXORPS </c> instruction. +/// +/// \returns A 256-bit vector of [8 x float] with all elements set to zero. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_setzero_ps(void) { return (__m256){ 0, 0, 0, 0, 0, 0, 0, 0 }; } +/// \brief Constructs a 256-bit integer vector initialized to zero. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VXORPS </c> instruction. +/// +/// \returns A 256-bit integer vector initialized to zero. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_setzero_si256(void) { @@ -2701,72 +4157,210 @@ _mm256_setzero_si256(void) } /* Cast between vector types */ +/// \brief Casts a 256-bit floating-point vector of [4 x double] into a 256-bit +/// floating-point vector of [8 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 256-bit floating-point vector of [4 x double]. +/// \returns A 256-bit floating-point vector of [8 x float] containing the same +/// bitwise pattern as the parameter. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_castpd_ps(__m256d __a) { return (__m256)__a; } +/// \brief Casts a 256-bit floating-point vector of [4 x double] into a 256-bit +/// integer vector. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 256-bit floating-point vector of [4 x double]. +/// \returns A 256-bit integer vector containing the same bitwise pattern as the +/// parameter. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_castpd_si256(__m256d __a) { return (__m256i)__a; } +/// \brief Casts a 256-bit floating-point vector of [8 x float] into a 256-bit +/// floating-point vector of [4 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 256-bit floating-point vector of [8 x float]. +/// \returns A 256-bit floating-point vector of [4 x double] containing the same +/// bitwise pattern as the parameter. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_castps_pd(__m256 __a) { return (__m256d)__a; } +/// \brief Casts a 256-bit floating-point vector of [8 x float] into a 256-bit +/// integer vector. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 256-bit floating-point vector of [8 x float]. +/// \returns A 256-bit integer vector containing the same bitwise pattern as the +/// parameter. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_castps_si256(__m256 __a) { return (__m256i)__a; } +/// \brief Casts a 256-bit integer vector into a 256-bit floating-point vector +/// of [8 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 256-bit integer vector. +/// \returns A 256-bit floating-point vector of [8 x float] containing the same +/// bitwise pattern as the parameter. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_castsi256_ps(__m256i __a) { return (__m256)__a; } +/// \brief Casts a 256-bit integer vector into a 256-bit floating-point vector +/// of [4 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 256-bit integer vector. +/// \returns A 256-bit floating-point vector of [4 x double] containing the same +/// bitwise pattern as the parameter. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_castsi256_pd(__m256i __a) { return (__m256d)__a; } +/// \brief Returns the lower 128 bits of a 256-bit floating-point vector of +/// [4 x double] as a 128-bit floating-point vector of [2 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 256-bit floating-point vector of [4 x double]. +/// \returns A 128-bit floating-point vector of [2 x double] containing the +/// lower 128 bits of the parameter. static __inline __m128d __DEFAULT_FN_ATTRS _mm256_castpd256_pd128(__m256d __a) { return __builtin_shufflevector((__v4df)__a, (__v4df)__a, 0, 1); } +/// \brief Returns the lower 128 bits of a 256-bit floating-point vector of +/// [8 x float] as a 128-bit floating-point vector of [4 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 256-bit floating-point vector of [8 x float]. +/// \returns A 128-bit floating-point vector of [4 x float] containing the +/// lower 128 bits of the parameter. static __inline __m128 __DEFAULT_FN_ATTRS _mm256_castps256_ps128(__m256 __a) { return __builtin_shufflevector((__v8sf)__a, (__v8sf)__a, 0, 1, 2, 3); } +/// \brief Truncates a 256-bit integer vector into a 128-bit integer vector. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 256-bit integer vector. +/// \returns A 128-bit integer vector containing the lower 128 bits of the +/// parameter. static __inline __m128i __DEFAULT_FN_ATTRS _mm256_castsi256_si128(__m256i __a) { return __builtin_shufflevector((__v4di)__a, (__v4di)__a, 0, 1); } +/// \brief Constructs a 256-bit floating-point vector of [4 x double] from a +/// 128-bit floating-point vector of [2 x double]. The lower 128 bits +/// contain the value of the source vector. The contents of the upper 128 +/// bits are undefined. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 128-bit vector of [2 x double]. +/// \returns A 256-bit floating-point vector of [4 x double]. The lower 128 bits +/// contain the value of the parameter. The contents of the upper 128 bits +/// are undefined. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_castpd128_pd256(__m128d __a) { return __builtin_shufflevector((__v2df)__a, (__v2df)__a, 0, 1, -1, -1); } +/// \brief Constructs a 256-bit floating-point vector of [8 x float] from a +/// 128-bit floating-point vector of [4 x float]. The lower 128 bits contain +/// the value of the source vector. The contents of the upper 128 bits are +/// undefined. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 128-bit vector of [4 x float]. +/// \returns A 256-bit floating-point vector of [8 x float]. The lower 128 bits +/// contain the value of the parameter. The contents of the upper 128 bits +/// are undefined. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_castps128_ps256(__m128 __a) { return __builtin_shufflevector((__v4sf)__a, (__v4sf)__a, 0, 1, 2, 3, -1, -1, -1, -1); } +/// \brief Constructs a 256-bit integer vector from a 128-bit integer vector. +/// The lower 128 bits contain the value of the source vector. The contents +/// of the upper 128 bits are undefined. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic has no corresponding instruction. +/// +/// \param __a +/// A 128-bit integer vector. +/// \returns A 256-bit integer vector. The lower 128 bits contain the value of +/// the parameter. The contents of the upper 128 bits are undefined. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_castsi128_si256(__m128i __a) { @@ -2778,6 +4372,38 @@ _mm256_castsi128_si256(__m128i __a) We use macros rather than inlines because we only want to accept invocations where the immediate M is a constant expression. */ +/// \brief Constructs a new 256-bit vector of [8 x float] by first duplicating +/// a 256-bit vector of [8 x float] given in the first parameter, and then +/// replacing either the upper or the lower 128 bits with the contents of a +/// 128-bit vector of [4 x float] in the second parameter. The immediate +/// integer parameter determines between the upper or the lower 128 bits. +/// +/// \headerfile <x86intrin.h> +/// +/// \code +/// __m256 _mm256_insertf128_ps(__m256 V1, __m128 V2, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. +/// +/// \param V1 +/// A 256-bit vector of [8 x float]. This vector is copied to the result +/// first, and then either the upper or the lower 128 bits of the result will +/// be replaced by the contents of \a V2. +/// \param V2 +/// A 128-bit vector of [4 x float]. The contents of this parameter are +/// written to either the upper or the lower 128 bits of the result depending +/// on the value of parameter \a M. +/// \param M +/// An immediate integer. The least significant bit determines how the values +/// from the two parameters are interleaved: \n +/// If bit [0] of \a M is 0, \a V2 are copied to bits [127:0] of the result, +/// and bits [255:128] of \a V1 are copied to bits [255:128] of the +/// result. \n +/// If bit [0] of \a M is 1, \a V2 are copied to bits [255:128] of the +/// result, and bits [127:0] of \a V1 are copied to bits [127:0] of the +/// result. +/// \returns A 256-bit vector of [8 x float] containing the interleaved values. #define _mm256_insertf128_ps(V1, V2, M) __extension__ ({ \ (__m256)__builtin_shufflevector( \ (__v8sf)(__m256)(V1), \ @@ -2791,6 +4417,38 @@ _mm256_castsi128_si256(__m128i __a) (((M) & 1) ? 10 : 6), \ (((M) & 1) ? 11 : 7) );}) +/// \brief Constructs a new 256-bit vector of [4 x double] by first duplicating +/// a 256-bit vector of [4 x double] given in the first parameter, and then +/// replacing either the upper or the lower 128 bits with the contents of a +/// 128-bit vector of [2 x double] in the second parameter. The immediate +/// integer parameter determines between the upper or the lower 128 bits. +/// +/// \headerfile <x86intrin.h> +/// +/// \code +/// __m256d _mm256_insertf128_pd(__m256d V1, __m128d V2, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. +/// +/// \param V1 +/// A 256-bit vector of [4 x double]. This vector is copied to the result +/// first, and then either the upper or the lower 128 bits of the result will +/// be replaced by the contents of \a V2. +/// \param V2 +/// A 128-bit vector of [2 x double]. The contents of this parameter are +/// written to either the upper or the lower 128 bits of the result depending +/// on the value of parameter \a M. +/// \param M +/// An immediate integer. The least significant bit determines how the values +/// from the two parameters are interleaved: \n +/// If bit [0] of \a M is 0, \a V2 are copied to bits [127:0] of the result, +/// and bits [255:128] of \a V1 are copied to bits [255:128] of the +/// result. \n +/// If bit [0] of \a M is 1, \a V2 are copied to bits [255:128] of the +/// result, and bits [127:0] of \a V1 are copied to bits [127:0] of the +/// result. +/// \returns A 256-bit vector of [4 x double] containing the interleaved values. #define _mm256_insertf128_pd(V1, V2, M) __extension__ ({ \ (__m256d)__builtin_shufflevector( \ (__v4df)(__m256d)(V1), \ @@ -2800,6 +4458,38 @@ _mm256_castsi128_si256(__m128i __a) (((M) & 1) ? 4 : 2), \ (((M) & 1) ? 5 : 3) );}) +/// \brief Constructs a new 256-bit integer vector by first duplicating a +/// 256-bit integer vector given in the first parameter, and then replacing +/// either the upper or the lower 128 bits with the contents of a 128-bit +/// integer vector in the second parameter. The immediate integer parameter +/// determines between the upper or the lower 128 bits. +/// +/// \headerfile <x86intrin.h> +/// +/// \code +/// __m256i _mm256_insertf128_si256(__m256i V1, __m128i V2, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. +/// +/// \param V1 +/// A 256-bit integer vector. This vector is copied to the result first, and +/// then either the upper or the lower 128 bits of the result will be +/// replaced by the contents of \a V2. +/// \param V2 +/// A 128-bit integer vector. The contents of this parameter are written to +/// either the upper or the lower 128 bits of the result depending on the +/// value of parameter \a M. +/// \param M +/// An immediate integer. The least significant bit determines how the values +/// from the two parameters are interleaved: \n +/// If bit [0] of \a M is 0, \a V2 are copied to bits [127:0] of the result, +/// and bits [255:128] of \a V1 are copied to bits [255:128] of the +/// result. \n +/// If bit [0] of \a M is 1, \a V2 are copied to bits [255:128] of the +/// result, and bits [127:0] of \a V1 are copied to bits [127:0] of the +/// result. +/// \returns A 256-bit integer vector containing the interleaved values. #define _mm256_insertf128_si256(V1, V2, M) __extension__ ({ \ (__m256i)__builtin_shufflevector( \ (__v4di)(__m256i)(V1), \ @@ -2814,6 +4504,27 @@ _mm256_castsi128_si256(__m128i __a) We use macros rather than inlines because we only want to accept invocations where the immediate M is a constant expression. */ +/// \brief Extracts either the upper or the lower 128 bits from a 256-bit vector +/// of [8 x float], as determined by the immediate integer parameter, and +/// returns the extracted bits as a 128-bit vector of [4 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// \code +/// __m128 _mm256_extractf128_ps(__m256 V, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction. +/// +/// \param V +/// A 256-bit vector of [8 x float]. +/// \param M +/// An immediate integer. The least significant bit determines which bits are +/// extracted from the first parameter: \n +/// If bit [0] of \a M is 0, bits [127:0] of \a V are copied to the +/// result. \n +/// If bit [0] of \a M is 1, bits [255:128] of \a V are copied to the result. +/// \returns A 128-bit vector of [4 x float] containing the extracted bits. #define _mm256_extractf128_ps(V, M) __extension__ ({ \ (__m128)__builtin_shufflevector( \ (__v8sf)(__m256)(V), \ @@ -2823,6 +4534,27 @@ _mm256_castsi128_si256(__m128i __a) (((M) & 1) ? 6 : 2), \ (((M) & 1) ? 7 : 3) );}) +/// \brief Extracts either the upper or the lower 128 bits from a 256-bit vector +/// of [4 x double], as determined by the immediate integer parameter, and +/// returns the extracted bits as a 128-bit vector of [2 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// \code +/// __m128d _mm256_extractf128_pd(__m256d V, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction. +/// +/// \param V +/// A 256-bit vector of [4 x double]. +/// \param M +/// An immediate integer. The least significant bit determines which bits are +/// extracted from the first parameter: \n +/// If bit [0] of \a M is 0, bits [127:0] of \a V are copied to the +/// result. \n +/// If bit [0] of \a M is 1, bits [255:128] of \a V are copied to the result. +/// \returns A 128-bit vector of [2 x double] containing the extracted bits. #define _mm256_extractf128_pd(V, M) __extension__ ({ \ (__m128d)__builtin_shufflevector( \ (__v4df)(__m256d)(V), \ @@ -2830,6 +4562,27 @@ _mm256_castsi128_si256(__m128i __a) (((M) & 1) ? 2 : 0), \ (((M) & 1) ? 3 : 1) );}) +/// \brief Extracts either the upper or the lower 128 bits from a 256-bit +/// integer vector, as determined by the immediate integer parameter, and +/// returns the extracted bits as a 128-bit integer vector. +/// +/// \headerfile <x86intrin.h> +/// +/// \code +/// __m128i _mm256_extractf128_si256(__m256i V, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction. +/// +/// \param V +/// A 256-bit integer vector. +/// \param M +/// An immediate integer. The least significant bit determines which bits are +/// extracted from the first parameter: \n +/// If bit [0] of \a M is 0, bits [127:0] of \a V are copied to the +/// result. \n +/// If bit [0] of \a M is 1, bits [255:128] of \a V are copied to the result. +/// \returns A 128-bit integer vector containing the extracted bits. #define _mm256_extractf128_si256(V, M) __extension__ ({ \ (__m128i)__builtin_shufflevector( \ (__v4di)(__m256i)(V), \ @@ -2838,6 +4591,27 @@ _mm256_castsi128_si256(__m128i __a) (((M) & 1) ? 3 : 1) );}) /* SIMD load ops (unaligned) */ +/// \brief Loads two 128-bit floating-point vectors of [4 x float] from +/// unaligned memory locations and constructs a 256-bit floating-point vector +/// of [8 x float] by concatenating the two 128-bit vectors. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to load instructions followed by the +/// <c> VINSERTF128 </c> instruction. +/// +/// \param __addr_hi +/// A pointer to a 128-bit memory location containing 4 consecutive +/// single-precision floating-point values. These values are to be copied to +/// bits[255:128] of the result. The address of the memory location does not +/// have to be aligned. +/// \param __addr_lo +/// A pointer to a 128-bit memory location containing 4 consecutive +/// single-precision floating-point values. These values are to be copied to +/// bits[127:0] of the result. The address of the memory location does not +/// have to be aligned. +/// \returns A 256-bit floating-point vector of [8 x float] containing the +/// concatenated result. static __inline __m256 __DEFAULT_FN_ATTRS _mm256_loadu2_m128(float const *__addr_hi, float const *__addr_lo) { @@ -2845,6 +4619,27 @@ _mm256_loadu2_m128(float const *__addr_hi, float const *__addr_lo) return _mm256_insertf128_ps(__v256, _mm_loadu_ps(__addr_hi), 1); } +/// \brief Loads two 128-bit floating-point vectors of [2 x double] from +/// unaligned memory locations and constructs a 256-bit floating-point vector +/// of [4 x double] by concatenating the two 128-bit vectors. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to load instructions followed by the +/// <c> VINSERTF128 </c> instruction. +/// +/// \param __addr_hi +/// A pointer to a 128-bit memory location containing two consecutive +/// double-precision floating-point values. These values are to be copied to +/// bits[255:128] of the result. The address of the memory location does not +/// have to be aligned. +/// \param __addr_lo +/// A pointer to a 128-bit memory location containing two consecutive +/// double-precision floating-point values. These values are to be copied to +/// bits[127:0] of the result. The address of the memory location does not +/// have to be aligned. +/// \returns A 256-bit floating-point vector of [4 x double] containing the +/// concatenated result. static __inline __m256d __DEFAULT_FN_ATTRS _mm256_loadu2_m128d(double const *__addr_hi, double const *__addr_lo) { @@ -2852,6 +4647,24 @@ _mm256_loadu2_m128d(double const *__addr_hi, double const *__addr_lo) return _mm256_insertf128_pd(__v256, _mm_loadu_pd(__addr_hi), 1); } +/// \brief Loads two 128-bit integer vectors from unaligned memory locations and +/// constructs a 256-bit integer vector by concatenating the two 128-bit +/// vectors. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to load instructions followed by the +/// <c> VINSERTF128 </c> instruction. +/// +/// \param __addr_hi +/// A pointer to a 128-bit memory location containing a 128-bit integer +/// vector. This vector is to be copied to bits[255:128] of the result. The +/// address of the memory location does not have to be aligned. +/// \param __addr_lo +/// A pointer to a 128-bit memory location containing a 128-bit integer +/// vector. This vector is to be copied to bits[127:0] of the result. The +/// address of the memory location does not have to be aligned. +/// \returns A 256-bit integer vector containing the concatenated result. static __inline __m256i __DEFAULT_FN_ATTRS _mm256_loadu2_m128i(__m128i const *__addr_hi, __m128i const *__addr_lo) { @@ -2860,6 +4673,24 @@ _mm256_loadu2_m128i(__m128i const *__addr_hi, __m128i const *__addr_lo) } /* SIMD store ops (unaligned) */ +/// \brief Stores the upper and lower 128 bits of a 256-bit floating-point +/// vector of [8 x float] into two different unaligned memory locations. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction and the +/// store instructions. +/// +/// \param __addr_hi +/// A pointer to a 128-bit memory location. Bits[255:128] of \a __a are to be +/// copied to this memory location. The address of this memory location does +/// not have to be aligned. +/// \param __addr_lo +/// A pointer to a 128-bit memory location. Bits[127:0] of \a __a are to be +/// copied to this memory location. The address of this memory location does +/// not have to be aligned. +/// \param __a +/// A 256-bit floating-point vector of [8 x float]. static __inline void __DEFAULT_FN_ATTRS _mm256_storeu2_m128(float *__addr_hi, float *__addr_lo, __m256 __a) { @@ -2871,6 +4702,24 @@ _mm256_storeu2_m128(float *__addr_hi, float *__addr_lo, __m256 __a) _mm_storeu_ps(__addr_hi, __v128); } +/// \brief Stores the upper and lower 128 bits of a 256-bit floating-point +/// vector of [4 x double] into two different unaligned memory locations. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction and the +/// store instructions. +/// +/// \param __addr_hi +/// A pointer to a 128-bit memory location. Bits[255:128] of \a __a are to be +/// copied to this memory location. The address of this memory location does +/// not have to be aligned. +/// \param __addr_lo +/// A pointer to a 128-bit memory location. Bits[127:0] of \a __a are to be +/// copied to this memory location. The address of this memory location does +/// not have to be aligned. +/// \param __a +/// A 256-bit floating-point vector of [4 x double]. static __inline void __DEFAULT_FN_ATTRS _mm256_storeu2_m128d(double *__addr_hi, double *__addr_lo, __m256d __a) { @@ -2882,6 +4731,24 @@ _mm256_storeu2_m128d(double *__addr_hi, double *__addr_lo, __m256d __a) _mm_storeu_pd(__addr_hi, __v128); } +/// \brief Stores the upper and lower 128 bits of a 256-bit integer vector into +/// two different unaligned memory locations. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VEXTRACTF128 </c> instruction and the +/// store instructions. +/// +/// \param __addr_hi +/// A pointer to a 128-bit memory location. Bits[255:128] of \a __a are to be +/// copied to this memory location. The address of this memory location does +/// not have to be aligned. +/// \param __addr_lo +/// A pointer to a 128-bit memory location. Bits[127:0] of \a __a are to be +/// copied to this memory location. The address of this memory location does +/// not have to be aligned. +/// \param __a +/// A 256-bit integer vector. static __inline void __DEFAULT_FN_ATTRS _mm256_storeu2_m128i(__m128i *__addr_hi, __m128i *__addr_lo, __m256i __a) { @@ -2893,33 +4760,132 @@ _mm256_storeu2_m128i(__m128i *__addr_hi, __m128i *__addr_lo, __m256i __a) _mm_storeu_si128(__addr_hi, __v128); } +/// \brief Constructs a 256-bit floating-point vector of [8 x float] by +/// concatenating two 128-bit floating-point vectors of [4 x float]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. +/// +/// \param __hi +/// A 128-bit floating-point vector of [4 x float] to be copied to the upper +/// 128 bits of the result. +/// \param __lo +/// A 128-bit floating-point vector of [4 x float] to be copied to the lower +/// 128 bits of the result. +/// \returns A 256-bit floating-point vector of [8 x float] containing the +/// concatenated result. static __inline __m256 __DEFAULT_FN_ATTRS -_mm256_set_m128 (__m128 __hi, __m128 __lo) { +_mm256_set_m128 (__m128 __hi, __m128 __lo) +{ return (__m256) __builtin_shufflevector((__v4sf)__lo, (__v4sf)__hi, 0, 1, 2, 3, 4, 5, 6, 7); } +/// \brief Constructs a 256-bit floating-point vector of [4 x double] by +/// concatenating two 128-bit floating-point vectors of [2 x double]. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. +/// +/// \param __hi +/// A 128-bit floating-point vector of [2 x double] to be copied to the upper +/// 128 bits of the result. +/// \param __lo +/// A 128-bit floating-point vector of [2 x double] to be copied to the lower +/// 128 bits of the result. +/// \returns A 256-bit floating-point vector of [4 x double] containing the +/// concatenated result. static __inline __m256d __DEFAULT_FN_ATTRS -_mm256_set_m128d (__m128d __hi, __m128d __lo) { +_mm256_set_m128d (__m128d __hi, __m128d __lo) +{ return (__m256d)_mm256_set_m128((__m128)__hi, (__m128)__lo); } +/// \brief Constructs a 256-bit integer vector by concatenating two 128-bit +/// integer vectors. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. +/// +/// \param __hi +/// A 128-bit integer vector to be copied to the upper 128 bits of the +/// result. +/// \param __lo +/// A 128-bit integer vector to be copied to the lower 128 bits of the +/// result. +/// \returns A 256-bit integer vector containing the concatenated result. static __inline __m256i __DEFAULT_FN_ATTRS -_mm256_set_m128i (__m128i __hi, __m128i __lo) { +_mm256_set_m128i (__m128i __hi, __m128i __lo) +{ return (__m256i)_mm256_set_m128((__m128)__hi, (__m128)__lo); } +/// \brief Constructs a 256-bit floating-point vector of [8 x float] by +/// concatenating two 128-bit floating-point vectors of [4 x float]. This is +/// similar to _mm256_set_m128, but the order of the input parameters is +/// swapped. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. +/// +/// \param __lo +/// A 128-bit floating-point vector of [4 x float] to be copied to the lower +/// 128 bits of the result. +/// \param __hi +/// A 128-bit floating-point vector of [4 x float] to be copied to the upper +/// 128 bits of the result. +/// \returns A 256-bit floating-point vector of [8 x float] containing the +/// concatenated result. static __inline __m256 __DEFAULT_FN_ATTRS -_mm256_setr_m128 (__m128 __lo, __m128 __hi) { +_mm256_setr_m128 (__m128 __lo, __m128 __hi) +{ return _mm256_set_m128(__hi, __lo); } +/// \brief Constructs a 256-bit floating-point vector of [4 x double] by +/// concatenating two 128-bit floating-point vectors of [2 x double]. This is +/// similar to _mm256_set_m128d, but the order of the input parameters is +/// swapped. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. +/// +/// \param __lo +/// A 128-bit floating-point vector of [2 x double] to be copied to the lower +/// 128 bits of the result. +/// \param __hi +/// A 128-bit floating-point vector of [2 x double] to be copied to the upper +/// 128 bits of the result. +/// \returns A 256-bit floating-point vector of [4 x double] containing the +/// concatenated result. static __inline __m256d __DEFAULT_FN_ATTRS -_mm256_setr_m128d (__m128d __lo, __m128d __hi) { +_mm256_setr_m128d (__m128d __lo, __m128d __hi) +{ return (__m256d)_mm256_set_m128((__m128)__hi, (__m128)__lo); } +/// \brief Constructs a 256-bit integer vector by concatenating two 128-bit +/// integer vectors. This is similar to _mm256_set_m128i, but the order of +/// the input parameters is swapped. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the <c> VINSERTF128 </c> instruction. +/// +/// \param __lo +/// A 128-bit integer vector to be copied to the lower 128 bits of the +/// result. +/// \param __hi +/// A 128-bit integer vector to be copied to the upper 128 bits of the +/// result. +/// \returns A 256-bit integer vector containing the concatenated result. static __inline __m256i __DEFAULT_FN_ATTRS -_mm256_setr_m128i (__m128i __lo, __m128i __hi) { +_mm256_setr_m128i (__m128i __lo, __m128i __hi) +{ return (__m256i)_mm256_set_m128((__m128)__hi, (__m128)__lo); } |