diff options
Diffstat (limited to 'lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp')
| -rw-r--r-- | lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp b/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp index 8e7e740da6f6..2ba10d25e939 100644 --- a/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp +++ b/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp @@ -136,18 +136,21 @@ void AArch64DeadRegisterDefinitions::processMachineBasicBlock( // We need to skip this instruction because while it appears to have a // dead def it uses a frame index which might expand into a multi // instruction sequence during EPI. - DEBUG(dbgs() << " Ignoring, operand is frame index\n"); + LLVM_DEBUG(dbgs() << " Ignoring, operand is frame index\n"); continue; } if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) { // It is not allowed to write to the same register (not even the zero // register) twice in a single instruction. - DEBUG(dbgs() << " Ignoring, XZR or WZR already used by the instruction\n"); + LLVM_DEBUG( + dbgs() + << " Ignoring, XZR or WZR already used by the instruction\n"); continue; } if (shouldSkip(MI, MF)) { - DEBUG(dbgs() << " Ignoring, Atomic instruction with acquire semantics using WZR/XZR\n"); + LLVM_DEBUG(dbgs() << " Ignoring, Atomic instruction with acquire " + "semantics using WZR/XZR\n"); continue; } @@ -163,30 +166,30 @@ void AArch64DeadRegisterDefinitions::processMachineBasicBlock( (!MO.isDead() && !MRI->use_nodbg_empty(Reg))) continue; assert(!MO.isImplicit() && "Unexpected implicit def!"); - DEBUG(dbgs() << " Dead def operand #" << I << " in:\n "; - MI.print(dbgs())); + LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n "; + MI.print(dbgs())); // Be careful not to change the register if it's a tied operand. if (MI.isRegTiedToUseOperand(I)) { - DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); + LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); continue; } const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF); unsigned NewReg; if (RC == nullptr) { - DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); + LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); continue; } else if (RC->contains(AArch64::WZR)) NewReg = AArch64::WZR; else if (RC->contains(AArch64::XZR)) NewReg = AArch64::XZR; else { - DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); + LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); continue; } - DEBUG(dbgs() << " Replacing with zero register. New:\n "); + LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n "); MO.setReg(NewReg); MO.setIsDead(); - DEBUG(MI.print(dbgs())); + LLVM_DEBUG(MI.print(dbgs())); ++NumDeadDefsReplaced; Changed = true; // Only replace one dead register, see check for zero register above. @@ -204,7 +207,7 @@ bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { TRI = MF.getSubtarget().getRegisterInfo(); TII = MF.getSubtarget().getInstrInfo(); MRI = &MF.getRegInfo(); - DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); + LLVM_DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); Changed = false; for (auto &MBB : MF) processMachineBasicBlock(MBB); |