diff options
Diffstat (limited to 'lib/Target/AMDGPU/AMDGPUInstructionSelector.h')
| -rw-r--r-- | lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 55 |
1 files changed, 49 insertions, 6 deletions
diff --git a/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index 449431adc561..4f489ddfb23d 100644 --- a/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -1,9 +1,8 @@ //===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// /// \file @@ -18,7 +17,9 @@ #include "AMDGPUArgumentUsageInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/Register.h" #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" +#include "llvm/IR/InstrTypes.h" namespace { #define GET_GLOBALISEL_PREDICATE_BITSET @@ -58,24 +59,45 @@ private: GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { } }; + bool isInstrUniform(const MachineInstr &MI) const; + bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const; + /// tblgen-erated 'select' implementation. bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; - MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const; + MachineOperand getSubOperand64(MachineOperand &MO, + const TargetRegisterClass &SubRC, + unsigned SubIdx) const; bool selectCOPY(MachineInstr &I) const; + bool selectPHI(MachineInstr &I) const; + bool selectG_TRUNC(MachineInstr &I) const; + bool selectG_SZA_EXT(MachineInstr &I) const; bool selectG_CONSTANT(MachineInstr &I) const; - bool selectG_ADD(MachineInstr &I) const; + bool selectG_AND_OR_XOR(MachineInstr &I) const; + bool selectG_ADD_SUB(MachineInstr &I) const; + bool selectG_EXTRACT(MachineInstr &I) const; + bool selectG_MERGE_VALUES(MachineInstr &I) const; + bool selectG_UNMERGE_VALUES(MachineInstr &I) const; bool selectG_GEP(MachineInstr &I) const; bool selectG_IMPLICIT_DEF(MachineInstr &I) const; + bool selectG_INSERT(MachineInstr &I) const; bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I, CodeGenCoverage &CoverageInfo) const; + int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const; + bool selectG_ICMP(MachineInstr &I) const; bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const; void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const; bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const; bool selectG_LOAD(MachineInstr &I) const; + bool selectG_SELECT(MachineInstr &I) const; bool selectG_STORE(MachineInstr &I) const; + bool selectG_BRCOND(MachineInstr &I) const; + bool selectG_FRAME_INDEX(MachineInstr &I) const; + + std::pair<Register, unsigned> + selectVOP3ModsImpl(Register Src, const MachineRegisterInfo &MRI) const; InstructionSelector::ComplexRendererFns selectVCSRC(MachineOperand &Root) const; @@ -90,6 +112,27 @@ private: InstructionSelector::ComplexRendererFns selectVOP3Mods(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns + selectSmrdImm(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns + selectSmrdImm32(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns + selectSmrdSgpr(MachineOperand &Root) const; + + template <bool Signed> + InstructionSelector::ComplexRendererFns + selectFlatOffsetImpl(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns + selectFlatOffset(MachineOperand &Root) const; + + InstructionSelector::ComplexRendererFns + selectFlatOffsetSigned(MachineOperand &Root) const; + + InstructionSelector::ComplexRendererFns + selectMUBUFScratchOffen(MachineOperand &Root) const; + InstructionSelector::ComplexRendererFns + selectMUBUFScratchOffset(MachineOperand &Root) const; + const SIInstrInfo &TII; const SIRegisterInfo &TRI; const AMDGPURegisterBankInfo &RBI; |