diff options
Diffstat (limited to 'lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h')
| -rw-r--r-- | lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h | 32 |
1 files changed, 24 insertions, 8 deletions
diff --git a/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h index 75cfc5e11282..c5eaba615c2a 100644 --- a/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -1,9 +1,8 @@ //===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -42,15 +41,14 @@ class AMDGPUDisassembler : public MCDisassembler { private: std::unique_ptr<MCInstrInfo const> const MCII; const MCRegisterInfo &MRI; + const unsigned TargetMaxInstBytes; mutable ArrayRef<uint8_t> Bytes; mutable uint32_t Literal; mutable bool HasLiteral; public: AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, - MCInstrInfo const *MCII) : - MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()) {} - + MCInstrInfo const *MCII); ~AMDGPUDisassembler() override = default; DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, @@ -69,9 +67,12 @@ public: uint64_t Address) const; DecodeStatus convertSDWAInst(MCInst &MI) const; + DecodeStatus convertDPP8Inst(MCInst &MI) const; DecodeStatus convertMIMGInst(MCInst &MI) const; MCOperand decodeOperand_VGPR_32(unsigned Val) const; + MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const; + MCOperand decodeOperand_VS_32(unsigned Val) const; MCOperand decodeOperand_VS_64(unsigned Val) const; MCOperand decodeOperand_VS_128(unsigned Val) const; @@ -81,22 +82,33 @@ public: MCOperand decodeOperand_VReg_64(unsigned Val) const; MCOperand decodeOperand_VReg_96(unsigned Val) const; MCOperand decodeOperand_VReg_128(unsigned Val) const; + MCOperand decodeOperand_VReg_256(unsigned Val) const; + MCOperand decodeOperand_VReg_512(unsigned Val) const; MCOperand decodeOperand_SReg_32(unsigned Val) const; MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const; MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const; + MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const; MCOperand decodeOperand_SReg_64(unsigned Val) const; MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const; MCOperand decodeOperand_SReg_128(unsigned Val) const; MCOperand decodeOperand_SReg_256(unsigned Val) const; MCOperand decodeOperand_SReg_512(unsigned Val) const; + MCOperand decodeOperand_AGPR_32(unsigned Val) const; + MCOperand decodeOperand_AReg_128(unsigned Val) const; + MCOperand decodeOperand_AReg_512(unsigned Val) const; + MCOperand decodeOperand_AReg_1024(unsigned Val) const; + MCOperand decodeOperand_AV_32(unsigned Val) const; + MCOperand decodeOperand_AV_64(unsigned Val) const; + enum OpWidthTy { OPW32, OPW64, OPW128, OPW256, OPW512, + OPW1024, OPW16, OPWV216, OPW_LAST_, @@ -104,6 +116,7 @@ public: }; unsigned getVgprClassId(const OpWidthTy Width) const; + unsigned getAgprClassId(const OpWidthTy Width) const; unsigned getSgprClassId(const OpWidthTy Width) const; unsigned getTtmpClassId(const OpWidthTy Width) const; @@ -121,11 +134,14 @@ public: MCOperand decodeSDWASrc32(unsigned Val) const; MCOperand decodeSDWAVopcDst(unsigned Val) const; + MCOperand decodeBoolReg(unsigned Val) const; + int getTTmpIdx(unsigned Val) const; bool isVI() const; bool isGFX9() const; - }; + bool isGFX10() const; +}; //===----------------------------------------------------------------------===// // AMDGPUSymbolizer |