diff options
Diffstat (limited to 'lib/Target/AMDGPU/SIFixupVectorISel.cpp')
| -rw-r--r-- | lib/Target/AMDGPU/SIFixupVectorISel.cpp | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/lib/Target/AMDGPU/SIFixupVectorISel.cpp b/lib/Target/AMDGPU/SIFixupVectorISel.cpp index ee39eb04d831..5b834c8de13a 100644 --- a/lib/Target/AMDGPU/SIFixupVectorISel.cpp +++ b/lib/Target/AMDGPU/SIFixupVectorISel.cpp @@ -1,9 +1,8 @@ //===-- SIFixupVectorISel.cpp - Fixup post ISel vector issues -------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // /// \file /// SIFixupVectorISel pass cleans up post ISEL Vector issues. @@ -198,6 +197,11 @@ static bool fixupGlobalSaddr(MachineBasicBlock &MBB, // Atomics dont have a GLC, so omit the field if not there. if (Glc) NewGlob->addOperand(MF, *Glc); + + MachineOperand *DLC = TII->getNamedOperand(MI, AMDGPU::OpName::dlc); + if (DLC) + NewGlob->addOperand(MF, *DLC); + NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::slc)); // _D16 have an vdst_in operand, copy it in. MachineOperand *VDstInOp = TII->getNamedOperand(MI, |