summaryrefslogtreecommitdiff
path: root/lib/Target/ARM/ARMBaseRegisterInfo.h
diff options
context:
space:
mode:
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.h')
-rw-r--r--lib/Target/ARM/ARMBaseRegisterInfo.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h
index 2e91d9d4be24..5801e6bdbd0e 100644
--- a/lib/Target/ARM/ARMBaseRegisterInfo.h
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.h
@@ -17,9 +17,9 @@
#include "MCTargetDesc/ARMBaseInfo.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <cstdint>
#define GET_REGINFO_HEADER
@@ -27,6 +27,8 @@
namespace llvm {
+class LiveIntervals;
+
/// Register allocation hints.
namespace ARMRI {
@@ -143,7 +145,7 @@ public:
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const override;
- void getRegAllocationHints(unsigned VirtReg,
+ bool getRegAllocationHints(unsigned VirtReg,
ArrayRef<MCPhysReg> Order,
SmallVectorImpl<MCPhysReg> &Hints,
const MachineFunction &MF,
@@ -204,7 +206,8 @@ public:
unsigned SubReg,
const TargetRegisterClass *DstRC,
unsigned DstSubReg,
- const TargetRegisterClass *NewRC) const override;
+ const TargetRegisterClass *NewRC,
+ LiveIntervals &LIS) const override;
};
} // end namespace llvm