diff options
Diffstat (limited to 'lib/Target/ARM/Thumb1FrameLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb1FrameLowering.cpp | 10 | 
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/ARM/Thumb1FrameLowering.cpp b/lib/Target/ARM/Thumb1FrameLowering.cpp index 1a17d4e33e4f..f917c35b9ceb 100644 --- a/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -535,14 +535,14 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,    // Look for a temporary register to use.    // First, compute the liveness information. -  LivePhysRegs UsedRegs(STI.getRegisterInfo()); +  const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); +  LivePhysRegs UsedRegs(TRI);    UsedRegs.addLiveOuts(MBB);    // The semantic of pristines changed recently and now,    // the callee-saved registers that are touched in the function    // are not part of the pristines set anymore.    // Add those callee-saved now. -  const TargetRegisterInfo *TRI = STI.getRegisterInfo(); -  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF); +  const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);    for (unsigned i = 0; CSRegs[i]; ++i)      UsedRegs.addReg(CSRegs[i]); @@ -561,12 +561,12 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,    // And some temporary register, just in case.    unsigned TemporaryReg = 0;    BitVector PopFriendly = -      TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::tGPRRegClassID)); +      TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));    assert(PopFriendly.any() && "No allocatable pop-friendly register?!");    // Rebuild the GPRs from the high registers because they are removed    // form the GPR reg class for thumb1.    BitVector GPRsNoLRSP = -      TRI->getAllocatableSet(MF, TRI->getRegClass(ARM::hGPRRegClassID)); +      TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));    GPRsNoLRSP |= PopFriendly;    GPRsNoLRSP.reset(ARM::LR);    GPRsNoLRSP.reset(ARM::SP);  | 
