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-rw-r--r--lib/Target/Hexagon/HexagonBitSimplify.cpp120
1 files changed, 59 insertions, 61 deletions
diff --git a/lib/Target/Hexagon/HexagonBitSimplify.cpp b/lib/Target/Hexagon/HexagonBitSimplify.cpp
index d75d95a6baea..9e73766b6fdc 100644
--- a/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1,4 +1,4 @@
-//===--- HexagonBitSimplify.cpp -------------------------------------------===//
+//===- HexagonBitSimplify.cpp ---------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -7,10 +7,14 @@
//
//===----------------------------------------------------------------------===//
+#include "BitTracker.h"
#include "HexagonBitTracker.h"
-#include "HexagonTargetMachine.h"
+#include "HexagonInstrInfo.h"
+#include "HexagonRegisterInfo.h"
+#include "HexagonSubtarget.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
@@ -22,16 +26,16 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetRegisterInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
@@ -52,10 +56,10 @@ static cl::opt<bool> GenBitSplit("hexbit-bitsplit", cl::Hidden,
cl::init(true), cl::desc("Generate bitsplit instructions"));
static cl::opt<unsigned> MaxExtract("hexbit-max-extract", cl::Hidden,
- cl::init(UINT_MAX));
+ cl::init(std::numeric_limits<unsigned>::max()));
static unsigned CountExtract = 0;
static cl::opt<unsigned> MaxBitSplit("hexbit-max-bitsplit", cl::Hidden,
- cl::init(UINT_MAX));
+ cl::init(std::numeric_limits<unsigned>::max()));
static unsigned CountBitSplit = 0;
namespace llvm {
@@ -169,7 +173,7 @@ namespace {
raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) {
OS << '{';
for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))
- OS << ' ' << PrintReg(R, P.TRI);
+ OS << ' ' << printReg(R, P.TRI);
OS << " }";
return OS;
}
@@ -180,7 +184,7 @@ namespace {
public:
static char ID;
- HexagonBitSimplify() : MachineFunctionPass(ID), MDT(nullptr) {
+ HexagonBitSimplify() : MachineFunctionPass(ID) {
initializeHexagonBitSimplifyPass(*PassRegistry::getPassRegistry());
}
@@ -227,15 +231,14 @@ namespace {
const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI);
private:
- MachineDominatorTree *MDT;
+ MachineDominatorTree *MDT = nullptr;
bool visitBlock(MachineBasicBlock &B, Transformation &T, RegisterSet &AVs);
static bool hasTiedUse(unsigned Reg, MachineRegisterInfo &MRI,
unsigned NewSub = Hexagon::NoSubRegister);
};
- char HexagonBitSimplify::ID = 0;
- typedef HexagonBitSimplify HBS;
+ using HBS = HexagonBitSimplify;
// The purpose of this class is to provide a common facility to traverse
// the function top-down or bottom-up via the dominator tree, and keep
@@ -252,6 +255,8 @@ namespace {
} // end anonymous namespace
+char HexagonBitSimplify::ID = 0;
+
INITIALIZE_PASS_BEGIN(HexagonBitSimplify, "hexbit",
"Hexagon bit simplification", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
@@ -415,8 +420,7 @@ bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
switch (RC->getID()) {
case Hexagon::DoubleRegsRegClassID:
- case Hexagon::VecDblRegsRegClassID:
- case Hexagon::VecDblRegs128BRegClassID:
+ case Hexagon::HvxWRRegClassID:
Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 2;
if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
Begin = Width;
@@ -435,7 +439,7 @@ bool HexagonBitSimplify::parseRegSequence(const MachineInstr &I,
const MachineRegisterInfo &MRI) {
assert(I.getOpcode() == TargetOpcode::REG_SEQUENCE);
unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm();
- auto *DstRC = MRI.getRegClass(I.getOperand(0).getReg());
+ auto &DstRC = *MRI.getRegClass(I.getOperand(0).getReg());
auto &HRI = static_cast<const HexagonRegisterInfo&>(
*MRI.getTargetRegisterInfo());
unsigned SubLo = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_lo);
@@ -891,7 +895,7 @@ bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN,
}
// Calculate the register class that matches Reg:Sub. For example, if
-// vreg1 is a double register, then vreg1:isub_hi would match the "int"
+// %1 is a double register, then %1:isub_hi would match the "int"
// register class.
const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) {
@@ -905,20 +909,17 @@ const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void {
(void)HRI;
- assert(Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo) ||
- Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
+ assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) ||
+ Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_hi));
};
switch (RC->getID()) {
case Hexagon::DoubleRegsRegClassID:
VerifySR(RC, RR.Sub);
return &Hexagon::IntRegsRegClass;
- case Hexagon::VecDblRegsRegClassID:
- VerifySR(RC, RR.Sub);
- return &Hexagon::VectorRegsRegClass;
- case Hexagon::VecDblRegs128BRegClassID:
+ case Hexagon::HvxWRRegClassID:
VerifySR(RC, RR.Sub);
- return &Hexagon::VectorRegs128BRegClass;
+ return &Hexagon::HvxVRRegClass;
}
return nullptr;
}
@@ -1245,11 +1246,11 @@ bool RedundantInstrElimination::computeUsedBits(unsigned Reg, BitVector &Bits) {
// holds the bits for the entire register. To keep track of that, the
// argument Begin indicates where in Bits is the lowest-significant bit
// of the register used in operand OpN. For example, in instruction:
-// vreg1 = S2_lsr_i_r vreg2:isub_hi, 10
+// %1 = S2_lsr_i_r %2:isub_hi, 10
// the operand 1 is a 32-bit register, which happens to be a subregister
-// of the 64-bit register vreg2, and that subregister starts at position 32.
+// of the 64-bit register %2, and that subregister starts at position 32.
// In this case Begin=32, since Bits[32] would be the lowest-significant bit
-// of vreg2:isub_hi.
+// of %2:isub_hi.
bool RedundantInstrElimination::computeUsedBits(const MachineInstr &MI,
unsigned OpN, BitVector &Bits, uint16_t Begin) {
unsigned Opc = MI.getOpcode();
@@ -1314,7 +1315,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
if (MI->getOpcode() == TargetOpcode::COPY)
continue;
- if (MI->hasUnmodeledSideEffects() || MI->isInlineAsm())
+ if (MI->isPHI() || MI->hasUnmodeledSideEffects() || MI->isInlineAsm())
continue;
unsigned NumD = MI->getDesc().getNumDefs();
if (NumD != 1)
@@ -1324,8 +1325,7 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
if (!BT.has(RD.Reg))
continue;
const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg);
- auto At = MI->isPHI() ? B.getFirstNonPHI()
- : MachineBasicBlock::iterator(MI);
+ auto At = MachineBasicBlock::iterator(MI);
// Find a source operand that is equal to the result.
for (auto &Op : MI->uses()) {
@@ -1356,11 +1356,11 @@ bool RedundantInstrElimination::processBlock(MachineBasicBlock &B,
// This pass can create copies between registers that don't have the
// exact same values. Updating the tracker has to involve updating
// all dependent cells. Example:
- // vreg1 = inst vreg2 ; vreg1 != vreg2, but used bits are equal
+ // %1 = inst %2 ; %1 != %2, but used bits are equal
//
- // vreg3 = copy vreg2 ; <- inserted
- // ... = vreg3 ; <- replaced from vreg2
- // Indirectly, we can create a "copy" between vreg1 and vreg2 even
+ // %3 = copy %2 ; <- inserted
+ // ... = %3 ; <- replaced from %2
+ // Indirectly, we can create a "copy" between %1 and %2 even
// though their exact values do not match.
BT.visit(*CopyI);
Changed = true;
@@ -1622,11 +1622,10 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B,
}
if (FRC == &Hexagon::DoubleRegsRegClass ||
- FRC == &Hexagon::VecDblRegsRegClass ||
- FRC == &Hexagon::VecDblRegs128BRegClass) {
+ FRC == &Hexagon::HvxWRRegClass) {
// Try to generate REG_SEQUENCE.
- unsigned SubLo = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_lo);
- unsigned SubHi = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_hi);
+ unsigned SubLo = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_lo);
+ unsigned SubHi = HRI.getHexagonSubRegIndex(*FRC, Hexagon::ps_sub_hi);
BitTracker::RegisterRef TL = { R, SubLo };
BitTracker::RegisterRef TH = { R, SubHi };
BitTracker::RegisterRef ML, MH;
@@ -1660,7 +1659,6 @@ bool CopyPropagation::isCopyReg(unsigned Opc, bool NoConv) {
case Hexagon::A2_tfrp:
case Hexagon::A2_combinew:
case Hexagon::V6_vcombine:
- case Hexagon::V6_vcombine_128B:
return NoConv;
default:
break;
@@ -1690,7 +1688,7 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) {
case TargetOpcode::REG_SEQUENCE: {
BitTracker::RegisterRef SL, SH;
if (HBS::parseRegSequence(MI, SL, SH, MRI)) {
- const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
+ const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);
Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI);
@@ -1699,9 +1697,8 @@ bool CopyPropagation::propagateRegCopy(MachineInstr &MI) {
break;
}
case Hexagon::A2_combinew:
- case Hexagon::V6_vcombine:
- case Hexagon::V6_vcombine_128B: {
- const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
+ case Hexagon::V6_vcombine: {
+ const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);
BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
@@ -2316,10 +2313,10 @@ bool BitSimplification::genBitSplit(MachineInstr *MI,
// Check for tstbit simplification opportunity, where the bit being checked
// can be tracked back to another register. For example:
-// vreg2 = S2_lsr_i_r vreg1, 5
-// vreg3 = S2_tstbit_i vreg2, 0
+// %2 = S2_lsr_i_r %1, 5
+// %3 = S2_tstbit_i %2, 0
// =>
-// vreg3 = S2_tstbit_i vreg1, 5
+// %3 = S2_tstbit_i %1, 5
bool BitSimplification::simplifyTstbit(MachineInstr *MI,
BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) {
unsigned Opc = MI->getOpcode();
@@ -2456,7 +2453,7 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI,
return false;
DEBUG({
- dbgs() << __func__ << " on reg: " << PrintReg(RD.Reg, &HRI, RD.Sub)
+ dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub)
<< ", MI: " << *MI;
dbgs() << "Cell: " << RC << '\n';
dbgs() << "Expected bitfield size: " << Len << " bits, "
@@ -2634,7 +2631,7 @@ bool BitSimplification::processBlock(MachineBasicBlock &B,
}
bool HexagonBitSimplify::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(*MF.getFunction()))
+ if (skipFunction(MF.getFunction()))
return false;
auto &HST = MF.getSubtarget<HexagonSubtarget>();
@@ -2767,31 +2764,32 @@ namespace {
public:
static char ID;
- HexagonLoopRescheduling() : MachineFunctionPass(ID),
- HII(nullptr), HRI(nullptr), MRI(nullptr), BTP(nullptr) {
+ HexagonLoopRescheduling() : MachineFunctionPass(ID) {
initializeHexagonLoopReschedulingPass(*PassRegistry::getPassRegistry());
}
bool runOnMachineFunction(MachineFunction &MF) override;
private:
- const HexagonInstrInfo *HII;
- const HexagonRegisterInfo *HRI;
- MachineRegisterInfo *MRI;
- BitTracker *BTP;
+ const HexagonInstrInfo *HII = nullptr;
+ const HexagonRegisterInfo *HRI = nullptr;
+ MachineRegisterInfo *MRI = nullptr;
+ BitTracker *BTP = nullptr;
struct LoopCand {
LoopCand(MachineBasicBlock *lb, MachineBasicBlock *pb,
MachineBasicBlock *eb) : LB(lb), PB(pb), EB(eb) {}
+
MachineBasicBlock *LB, *PB, *EB;
};
- typedef std::vector<MachineInstr*> InstrList;
+ using InstrList = std::vector<MachineInstr *>;
struct InstrGroup {
BitTracker::RegisterRef Inp, Out;
InstrList Ins;
};
struct PhiInfo {
PhiInfo(MachineInstr &P, MachineBasicBlock &B);
+
unsigned DefR;
BitTracker::RegisterRef LR, PR; // Loop Register, Preheader Register
MachineBasicBlock *LB, *PB; // Loop Block, Preheader Block
@@ -2979,7 +2977,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB,
}
bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
- DEBUG(dbgs() << "Processing loop in BB#" << C.LB->getNumber() << "\n");
+ DEBUG(dbgs() << "Processing loop in " << printMBBReference(*C.LB) << "\n");
std::vector<PhiInfo> Phis;
for (auto &I : *C.LB) {
if (!I.isPHI())
@@ -3006,9 +3004,9 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
DEBUG({
dbgs() << "Phis: {";
for (auto &I : Phis) {
- dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi("
- << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
- << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
+ dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi("
+ << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
+ << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
<< I.LB->getNumber() << ')';
}
dbgs() << " }\n";
@@ -3079,7 +3077,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
// to the beginning of the loop, that input register would need to be
// the loop-carried register (through a phi node) instead of the (currently
// loop-carried) output register.
- typedef std::vector<InstrGroup> InstrGroupList;
+ using InstrGroupList = std::vector<InstrGroup>;
InstrGroupList Groups;
for (unsigned i = 0, n = ShufIns.size(); i < n; ++i) {
@@ -3128,8 +3126,8 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
for (unsigned i = 0, n = Groups.size(); i < n; ++i) {
InstrGroup &G = Groups[i];
dbgs() << "Group[" << i << "] inp: "
- << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub)
- << " out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
+ << printReg(G.Inp.Reg, HRI, G.Inp.Sub)
+ << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
for (unsigned j = 0, m = G.Ins.size(); j < m; ++j)
dbgs() << " " << *G.Ins[j];
}
@@ -3183,7 +3181,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
}
bool HexagonLoopRescheduling::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(*MF.getFunction()))
+ if (skipFunction(MF.getFunction()))
return false;
auto &HST = MF.getSubtarget<HexagonSubtarget>();
generated by cgit v1.3 (git 2.53.0) at 2026-07-28 02:10:35 +0000