aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/Mips/MCTargetDesc
diff options
context:
space:
mode:
Diffstat (limited to 'lib/Target/Mips/MCTargetDesc')
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp41
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h16
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp30
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp23
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h16
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp4
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp70
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h3
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h6
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp27
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h25
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp17
-rw-r--r--lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp6
13 files changed, 128 insertions, 156 deletions
diff --git a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
index a1ed0ea4d7f3..1ad524c06969 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
@@ -24,6 +24,7 @@
#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
#include "llvm/MC/MCValue.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
@@ -209,10 +210,9 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
return Value;
}
-MCObjectWriter *
+std::unique_ptr<MCObjectWriter>
MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
- return createMipsELFObjectWriter(OS,
- MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
+ return createMipsELFObjectWriter(OS, TheTriple, IsN32);
}
// Little-endian fixup data byte ordering:
@@ -475,34 +475,9 @@ bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
return true;
}
-// MCAsmBackend
-MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options) {
- return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
- /*Is64Bit*/ false);
-}
-
-MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options) {
- return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
- /*Is64Bit*/ false);
-}
-
-MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options) {
- return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
-}
-
-MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options) {
- return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
- /*Is64Bit*/ true);
+MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
+ const MCRegisterInfo &MRI,
+ const Triple &TT, StringRef CPU,
+ const MCTargetOptions &Options) {
+ return new MipsAsmBackend(T, MRI, TT, CPU, Options.ABIName == "n32");
}
diff --git a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
index 8ebde3b9b7a4..406b820edae5 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
@@ -23,20 +23,22 @@ namespace llvm {
class MCAssembler;
struct MCFixupKindInfo;
-class Target;
class MCObjectWriter;
+class MCRegisterInfo;
+class Target;
class MipsAsmBackend : public MCAsmBackend {
- Triple::OSType OSType;
+ Triple TheTriple;
bool IsLittle; // Big or little endian
- bool Is64Bit; // 32 or 64 bit words
+ bool IsN32;
public:
- MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle,
- bool Is64Bit)
- : MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {}
+ MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
+ StringRef CPU, bool N32)
+ : TheTriple(TT), IsLittle(TT.isLittleEndian()), IsN32(N32) {}
- MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override;
+ std::unique_ptr<MCObjectWriter>
+ createObjectWriter(raw_pwrite_stream &OS) const override;
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target, MutableArrayRef<char> Data,
diff --git a/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
index d116ac3471bc..6d2f098a6b32 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
@@ -13,6 +13,7 @@
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSymbolELF.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
@@ -55,7 +56,7 @@ raw_ostream &operator<<(raw_ostream &OS, const MipsRelocationEntry &RHS) {
class MipsELFObjectWriter : public MCELFObjectTargetWriter {
public:
- MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI, bool _isN64,
+ MipsELFObjectWriter(uint8_t OSABI, bool HasRelocationAddend, bool Is64,
bool IsLittleEndian);
~MipsELFObjectWriter() override = default;
@@ -209,11 +210,10 @@ static void dumpRelocs(const char *Prefix, const Container &Relocs) {
}
#endif
-MipsELFObjectWriter::MipsELFObjectWriter(bool _is64Bit, uint8_t OSABI,
- bool _isN64, bool IsLittleEndian)
- : MCELFObjectTargetWriter(_is64Bit, OSABI, ELF::EM_MIPS,
- /*HasRelocationAddend*/ _isN64,
- /*IsN64*/ _isN64) {}
+MipsELFObjectWriter::MipsELFObjectWriter(uint8_t OSABI,
+ bool HasRelocationAddend, bool Is64,
+ bool IsLittleEndian)
+ : MCELFObjectTargetWriter(Is64, OSABI, ELF::EM_MIPS, HasRelocationAddend) {}
unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
const MCValue &Target,
@@ -282,7 +282,7 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx,
case FK_TPRel_8:
return ELF::R_MIPS_TLS_TPREL64;
case FK_GPRel_4:
- if (isN64()) {
+ if (is64Bit()) {
unsigned Type = (unsigned)ELF::R_MIPS_NONE;
Type = setRType((unsigned)ELF::R_MIPS_GPREL32, Type);
Type = setRType2((unsigned)ELF::R_MIPS_64, Type);
@@ -656,11 +656,13 @@ bool MipsELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym,
}
}
-MCObjectWriter *llvm::createMipsELFObjectWriter(raw_pwrite_stream &OS,
- uint8_t OSABI,
- bool IsLittleEndian,
- bool Is64Bit) {
- MCELFObjectTargetWriter *MOTW =
- new MipsELFObjectWriter(Is64Bit, OSABI, Is64Bit, IsLittleEndian);
- return createELFObjectWriter(MOTW, OS, IsLittleEndian);
+std::unique_ptr<MCObjectWriter>
+llvm::createMipsELFObjectWriter(raw_pwrite_stream &OS, const Triple &TT,
+ bool IsN32) {
+ uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
+ bool IsN64 = TT.isArch64Bit() && !IsN32;
+ bool HasRelocationAddend = TT.isArch64Bit();
+ auto MOTW = llvm::make_unique<MipsELFObjectWriter>(
+ OSABI, HasRelocationAddend, IsN64, TT.isLittleEndian());
+ return createELFObjectWriter(std::move(MOTW), OS, TT.isLittleEndian());
}
diff --git a/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp
index f658aadff22f..4b8f9c7a680c 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp
@@ -11,7 +11,9 @@
#include "MipsOptionRecord.h"
#include "MipsTargetStreamer.h"
#include "llvm/BinaryFormat/ELF.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSymbolELF.h"
@@ -19,6 +21,16 @@
using namespace llvm;
+MipsELFStreamer::MipsELFStreamer(MCContext &Context,
+ std::unique_ptr<MCAsmBackend> MAB,
+ raw_pwrite_stream &OS,
+ std::unique_ptr<MCCodeEmitter> Emitter)
+ : MCELFStreamer(Context, std::move(MAB), OS, std::move(Emitter)) {
+ RegInfoRecord = new MipsRegInfoRecord(this, Context);
+ MipsOptionRecords.push_back(
+ std::unique_ptr<MipsRegInfoRecord>(RegInfoRecord));
+}
+
void MipsELFStreamer::EmitInstruction(const MCInst &Inst,
const MCSubtargetInfo &STI, bool) {
MCELFStreamer::EmitInstruction(Inst, STI);
@@ -77,10 +89,9 @@ void MipsELFStreamer::EmitMipsOptionRecords() {
I->EmitMipsOptionRecord();
}
-MCELFStreamer *llvm::createMipsELFStreamer(MCContext &Context,
- MCAsmBackend &MAB,
- raw_pwrite_stream &OS,
- MCCodeEmitter *Emitter,
- bool RelaxAll) {
- return new MipsELFStreamer(Context, MAB, OS, Emitter);
+MCELFStreamer *llvm::createMipsELFStreamer(
+ MCContext &Context, std::unique_ptr<MCAsmBackend> MAB,
+ raw_pwrite_stream &OS, std::unique_ptr<MCCodeEmitter> Emitter,
+ bool RelaxAll) {
+ return new MipsELFStreamer(Context, std::move(MAB), OS, std::move(Emitter));
}
diff --git a/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h b/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h
index f5eda112817e..2fe9b08b645a 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h
@@ -33,13 +33,9 @@ class MipsELFStreamer : public MCELFStreamer {
SmallVector<MCSymbol*, 4> Labels;
public:
- MipsELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS,
- MCCodeEmitter *Emitter)
- : MCELFStreamer(Context, MAB, OS, Emitter) {
- RegInfoRecord = new MipsRegInfoRecord(this, Context);
- MipsOptionRecords.push_back(
- std::unique_ptr<MipsRegInfoRecord>(RegInfoRecord));
- }
+ MipsELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> MAB,
+ raw_pwrite_stream &OS,
+ std::unique_ptr<MCCodeEmitter> Emitter);
/// Overriding this function allows us to add arbitrary behaviour before the
/// \p Inst is actually emitted. For example, we can inspect the operands and
@@ -69,9 +65,11 @@ public:
void createPendingLabelRelocs();
};
-MCELFStreamer *createMipsELFStreamer(MCContext &Context, MCAsmBackend &MAB,
+MCELFStreamer *createMipsELFStreamer(MCContext &Context,
+ std::unique_ptr<MCAsmBackend> MAB,
raw_pwrite_stream &OS,
- MCCodeEmitter *Emitter, bool RelaxAll);
+ std::unique_ptr<MCCodeEmitter> Emitter,
+ bool RelaxAll);
} // end namespace llvm
#endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSELFSTREAMER_H
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
index 11411d997bb3..e63304220ae5 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
@@ -61,4 +61,8 @@ MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) {
// Enable IAS by default for Debian mips64/mips64el.
if (TheTriple.getEnvironment() == Triple::GNUABI64)
UseIntegratedAssembler = true;
+
+ // Enable IAS by default for Android mips64el that uses N64 ABI.
+ if (TheTriple.getArch() == Triple::mips64el && TheTriple.isAndroid())
+ UseIntegratedAssembler = true;
}
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 0330824fd614..ac81e6207456 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -86,45 +86,6 @@ static void LowerLargeShift(MCInst& Inst) {
case Mips::DROTR:
Inst.setOpcode(Mips::DROTR32);
return;
- case Mips::DSLL_MM64R6:
- Inst.setOpcode(Mips::DSLL32_MM64R6);
- return;
- case Mips::DSRL_MM64R6:
- Inst.setOpcode(Mips::DSRL32_MM64R6);
- return;
- case Mips::DSRA_MM64R6:
- Inst.setOpcode(Mips::DSRA32_MM64R6);
- return;
- case Mips::DROTR_MM64R6:
- Inst.setOpcode(Mips::DROTR32_MM64R6);
- return;
- }
-}
-
-// Pick a DINS instruction variant based on the pos and size operands
-static void LowerDins(MCInst& InstIn) {
- assert(InstIn.getNumOperands() == 5 &&
- "Invalid no. of machine operands for DINS!");
-
- assert(InstIn.getOperand(2).isImm());
- int64_t pos = InstIn.getOperand(2).getImm();
- assert(InstIn.getOperand(3).isImm());
- int64_t size = InstIn.getOperand(3).getImm();
-
- assert((pos + size) <= 64 &&
- "DINS cannot have position plus size over 64");
- if (pos < 32) {
- if ((pos + size) > 0 && (pos + size) <= 32)
- return; // DINS, do nothing
- else if ((pos + size) > 32) {
- //DINSM
- InstIn.getOperand(3).setImm(size - 32);
- InstIn.setOpcode(Mips::DINSM);
- }
- } else if ((pos + size) > 32 && (pos + size) <= 64) {
- // DINSU
- InstIn.getOperand(2).setImm(pos - 32);
- InstIn.setOpcode(Mips::DINSU);
}
}
@@ -205,16 +166,8 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
case Mips::DSRL:
case Mips::DSRA:
case Mips::DROTR:
- case Mips::DSLL_MM64R6:
- case Mips::DSRL_MM64R6:
- case Mips::DSRA_MM64R6:
- case Mips::DROTR_MM64R6:
LowerLargeShift(TmpInst);
break;
- // Double extract instruction is chosen by pos and size operands
- case Mips::DINS:
- LowerDins(TmpInst);
- break;
// Compact branches, enforce encoding restrictions.
case Mips::BEQC:
case Mips::BNEC:
@@ -1146,6 +1099,29 @@ MipsMCCodeEmitter::getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
}
unsigned
+MipsMCCodeEmitter::getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ assert(((OpNo == 2) || (OpNo == 3)) &&
+ "Unexpected OpNo for movep operand encoding!");
+
+ MCOperand Op = MI.getOperand(OpNo);
+ assert(Op.isReg() && "Operand of movep is not a register!");
+ switch (Op.getReg()) {
+ default:
+ llvm_unreachable("Unknown register for movep!");
+ case Mips::ZERO: return 0;
+ case Mips::S1: return 1;
+ case Mips::V0: return 2;
+ case Mips::V1: return 3;
+ case Mips::S0: return 4;
+ case Mips::S2: return 5;
+ case Mips::S3: return 6;
+ case Mips::S4: return 7;
+ }
+}
+
+unsigned
MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
index d12d3195521a..1e840114b2b3 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
@@ -252,6 +252,9 @@ public:
unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+ unsigned getMovePRegSingleOpValue(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h b/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
index 687b800c2409..dfacf4354516 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
@@ -22,9 +22,11 @@ bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
bool baseRegNeedsLoadStoreMask(unsigned Reg);
// This function creates an MCELFStreamer for Mips NaCl.
-MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB,
+MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context,
+ std::unique_ptr<MCAsmBackend> TAB,
raw_pwrite_stream &OS,
- MCCodeEmitter *Emitter, bool RelaxAll);
+ std::unique_ptr<MCCodeEmitter> Emitter,
+ bool RelaxAll);
}
#endif
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
index 56fe18572118..8fcd8aa4c19b 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
@@ -13,11 +13,13 @@
#include "MipsMCTargetDesc.h"
#include "InstPrinter/MipsInstPrinter.h"
+#include "MipsAsmBackend.h"
#include "MipsELFStreamer.h"
#include "MipsMCAsmInfo.h"
#include "MipsMCNaCl.h"
#include "MipsTargetStreamer.h"
#include "llvm/ADT/Triple.h"
+#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrInfo.h"
@@ -90,13 +92,17 @@ static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
}
static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
- MCAsmBackend &MAB, raw_pwrite_stream &OS,
- MCCodeEmitter *Emitter, bool RelaxAll) {
+ std::unique_ptr<MCAsmBackend> &&MAB,
+ raw_pwrite_stream &OS,
+ std::unique_ptr<MCCodeEmitter> &&Emitter,
+ bool RelaxAll) {
MCStreamer *S;
if (!T.isOSNaCl())
- S = createMipsELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
+ S = createMipsELFStreamer(Context, std::move(MAB), OS, std::move(Emitter),
+ RelaxAll);
else
- S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
+ S = createMipsNaClELFStreamer(Context, std::move(MAB), OS,
+ std::move(Emitter), RelaxAll);
return S;
}
@@ -180,6 +186,9 @@ extern "C" void LLVMInitializeMipsTargetMC() {
TargetRegistry::RegisterObjectTargetStreamer(
*T, createMipsObjectTargetStreamer);
+
+ // Register the asm backend.
+ TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend);
}
// Register the MC Code Emitter
@@ -188,14 +197,4 @@ extern "C" void LLVMInitializeMipsTargetMC() {
for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
-
- // Register the asm backend.
- TargetRegistry::RegisterMCAsmBackend(getTheMipsTarget(),
- createMipsAsmBackendEB32);
- TargetRegistry::RegisterMCAsmBackend(getTheMipselTarget(),
- createMipsAsmBackendEL32);
- TargetRegistry::RegisterMCAsmBackend(getTheMips64Target(),
- createMipsAsmBackendEB64);
- TargetRegistry::RegisterMCAsmBackend(getTheMips64elTarget(),
- createMipsAsmBackendEL64);
}
diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
index b28681f42ebe..abbf08ed212f 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
+++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
@@ -16,6 +16,8 @@
#include "llvm/Support/DataTypes.h"
+#include <memory>
+
namespace llvm {
class MCAsmBackend;
class MCCodeEmitter;
@@ -43,25 +45,12 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI,
MCContext &Ctx);
-MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options);
-MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options);
-MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options);
-MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
- const MCRegisterInfo &MRI,
- const Triple &TT, StringRef CPU,
- const MCTargetOptions &Options);
+MCAsmBackend *createMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI,
+ const Triple &TT, StringRef CPU,
+ const MCTargetOptions &Options);
-MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
- bool IsLittleEndian, bool Is64Bit);
+std::unique_ptr<MCObjectWriter>
+createMipsELFObjectWriter(raw_pwrite_stream &OS, const Triple &TT, bool IsN32);
namespace MIPS_MC {
StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
diff --git a/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
index 9266f0e216d1..d878cf82e26d 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
@@ -20,7 +20,9 @@
#include "Mips.h"
#include "MipsELFStreamer.h"
#include "MipsMCNaCl.h"
+#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/ErrorHandling.h"
@@ -40,9 +42,10 @@ const unsigned LoadStoreStackMaskReg = Mips::T7;
class MipsNaClELFStreamer : public MipsELFStreamer {
public:
- MipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB,
- raw_pwrite_stream &OS, MCCodeEmitter *Emitter)
- : MipsELFStreamer(Context, TAB, OS, Emitter) {}
+ MipsNaClELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
+ raw_pwrite_stream &OS,
+ std::unique_ptr<MCCodeEmitter> Emitter)
+ : MipsELFStreamer(Context, std::move(TAB), OS, std::move(Emitter)) {}
~MipsNaClELFStreamer() override = default;
@@ -255,11 +258,13 @@ bool baseRegNeedsLoadStoreMask(unsigned Reg) {
return Reg != Mips::SP && Reg != Mips::T8;
}
-MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB,
+MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context,
+ std::unique_ptr<MCAsmBackend> TAB,
raw_pwrite_stream &OS,
- MCCodeEmitter *Emitter,
+ std::unique_ptr<MCCodeEmitter> Emitter,
bool RelaxAll) {
- MipsNaClELFStreamer *S = new MipsNaClELFStreamer(Context, TAB, OS, Emitter);
+ MipsNaClELFStreamer *S =
+ new MipsNaClELFStreamer(Context, std::move(TAB), OS, std::move(Emitter));
if (RelaxAll)
S->getAssembler().setRelaxAll(true);
diff --git a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index 7caeb08589af..fb4e1ba0ded9 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -98,6 +98,7 @@ void MipsTargetStreamer::emitDirectiveSetHardFloat() {
forbidModuleDirective();
}
void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
+void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); }
void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
bool MipsTargetStreamer::emitDirectiveCpRestore(
@@ -562,6 +563,11 @@ void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
MipsTargetStreamer::emitDirectiveSetDsp();
}
+void MipsTargetAsmStreamer::emitDirectiveSetDspr2() {
+ OS << "\t.set\tdspr2\n";
+ MipsTargetStreamer::emitDirectiveSetDspr2();
+}
+
void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
OS << "\t.set\tnodsp\n";
MipsTargetStreamer::emitDirectiveSetNoDsp();
generated by cgit v1.3 (git 2.53.0) at 2026-09-06 14:48:16 +0000