diff options
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 54 |
1 files changed, 26 insertions, 28 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index a943a0ad4094..8a6279da46b7 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -1,9 +1,8 @@ //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// @@ -259,6 +258,11 @@ let Namespace = "Mips" in { def MSARequest : MipsReg<5, "5">; def MSAMap : MipsReg<6, "6">; def MSAUnmap : MipsReg<7, "7">; + // MSA-ASE fake control registers. + // These registers do not exist, but instructions like `cfcmsa` + // and `ctcmsa` allows to specify them. + foreach I = 8-31 in + def MSA#I : MipsReg<#I, ""#I>; // Octeon multiplier and product registers def MPL0 : MipsReg<0, "mpl0">; @@ -383,10 +387,14 @@ def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; // 32bit fp: // * FGR32 - 16 32-bit even registers // * FGR32 - 32 32-bit registers (single float only mode) -def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; - -def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, - Unallocatable; +def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)> { + // Do not allocate odd registers when given -mattr=+nooddspreg. + let AltOrders = [(decimate FGR32, 2)]; + let AltOrderSelect = [{ + const auto & S = MF.getSubtarget<MipsSubtarget>(); + return S.isABI_O32() && !S.useOddSPReg(); + }]; +} def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Return Values and Arguments @@ -400,16 +408,14 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Callee save D10, D11, D12, D13, D14, D15)>; -def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; - -// Used to reserve odd registers when given -mattr=+nooddspreg -// FIXME: Remove double precision registers from this set. -def OddSP : RegisterClass<"Mips", [f32], 32, - (add (decimate (sequence "F%u", 1, 31), 2), - (decimate (sequence "F_HI%u", 1, 31), 2), - (decimate (sequence "D%u", 1, 15), 2), - (decimate (sequence "D%u_64", 1, 31), 2))>, - Unallocatable; +def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)> { + // Do not allocate odd registers when given -mattr=+nooddspreg. + let AltOrders = [(decimate FGR64, 2)]; + let AltOrderSelect = [{ + const auto & S = MF.getSubtarget<MipsSubtarget>(); + return S.isABI_O32() && !S.useOddSPReg(); + }]; +} // FP control registers. def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, @@ -437,7 +443,8 @@ def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128, (decimate (sequence "W%u", 0, 31), 2)>; def MSACtrl: RegisterClass<"Mips", [i32], 32, (add - MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; + MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap, + (sequence "MSA%u", 8, 31))>, Unallocatable; // Hi/Lo Registers def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; @@ -591,11 +598,6 @@ def StrictlyFGR32AsmOperand : MipsAsmRegOperand { let PredicateMethod = "isStrictlyFGRAsmReg"; } -def FGRH32AsmOperand : MipsAsmRegOperand { - let Name = "FGRH32AsmReg"; - let PredicateMethod = "isFGRAsmReg"; -} - def FCCRegsAsmOperand : MipsAsmRegOperand { let Name = "FCCAsmReg"; } @@ -703,10 +705,6 @@ def FGRCCOpnd : RegisterOperand<FGRCC> { let ParserMatchClass = FGR32AsmOperand; } -def FGRH32Opnd : RegisterOperand<FGRH32> { - let ParserMatchClass = FGRH32AsmOperand; -} - def FCCRegsOpnd : RegisterOperand<FCC> { let ParserMatchClass = FCCRegsAsmOperand; } |